adv7604.c 85.0 KB
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/*
 * adv7604 - Analog Devices ADV7604 video decoder driver
 *
 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
 *
 * This program is free software; you may redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 */

/*
 * References (c = chapter, p = page):
 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
 *		Revision 2.5, June 2010
 * REF_02 - Analog devices, Register map documentation, Documentation of
 *		the register maps, Software manual, Rev. F, June 2010
 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
 */

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#include <linux/delay.h>
#include <linux/i2c.h>
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#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
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#include <linux/v4l2-dv-timings.h>
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#include <linux/videodev2.h>
#include <linux/workqueue.h>
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#include <media/adv7604.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-dv-timings.h>
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static int debug;
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "debug level (0-2)");

MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
MODULE_LICENSE("GPL");

/* ADV7604 system clock frequency */
#define ADV7604_fsc (28636360)

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#define ADV7604_RGB_OUT					(1 << 1)

#define ADV7604_OP_FORMAT_SEL_8BIT			(0 << 0)
#define ADV7604_OP_FORMAT_SEL_10BIT			(1 << 0)
#define ADV7604_OP_FORMAT_SEL_12BIT			(2 << 0)

#define ADV7604_OP_MODE_SEL_SDR_422			(0 << 5)
#define ADV7604_OP_MODE_SEL_DDR_422			(1 << 5)
#define ADV7604_OP_MODE_SEL_SDR_444			(2 << 5)
#define ADV7604_OP_MODE_SEL_DDR_444			(3 << 5)
#define ADV7604_OP_MODE_SEL_SDR_422_2X			(4 << 5)
#define ADV7604_OP_MODE_SEL_ADI_CM			(5 << 5)

#define ADV7604_OP_CH_SEL_GBR				(0 << 5)
#define ADV7604_OP_CH_SEL_GRB				(1 << 5)
#define ADV7604_OP_CH_SEL_BGR				(2 << 5)
#define ADV7604_OP_CH_SEL_RGB				(3 << 5)
#define ADV7604_OP_CH_SEL_BRG				(4 << 5)
#define ADV7604_OP_CH_SEL_RBG				(5 << 5)

#define ADV7604_OP_SWAP_CB_CR				(1 << 0)

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enum adv7604_type {
	ADV7604,
	ADV7611,
};

struct adv7604_reg_seq {
	unsigned int reg;
	u8 val;
};

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struct adv7604_format_info {
	enum v4l2_mbus_pixelcode code;
	u8 op_ch_sel;
	bool rgb_out;
	bool swap_cb_cr;
	u8 op_format_sel;
};

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struct adv7604_chip_info {
	enum adv7604_type type;

	bool has_afe;
	unsigned int max_port;
	unsigned int num_dv_ports;

	unsigned int edid_enable_reg;
	unsigned int edid_status_reg;
	unsigned int lcf_reg;

	unsigned int cable_det_mask;
	unsigned int tdms_lock_mask;
	unsigned int fmt_change_digital_mask;

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	const struct adv7604_format_info *formats;
	unsigned int nformats;

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	void (*set_termination)(struct v4l2_subdev *sd, bool enable);
	void (*setup_irqs)(struct v4l2_subdev *sd);
	unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd);
	unsigned int (*read_cable_det)(struct v4l2_subdev *sd);

	/* 0 = AFE, 1 = HDMI */
	const struct adv7604_reg_seq *recommended_settings[2];
	unsigned int num_recommended_settings[2];

	unsigned long page_mask;
};

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/*
 **********************************************************************
 *
 *  Arrays with configuration parameters for the ADV7604
 *
 **********************************************************************
 */
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struct adv7604_state {
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	const struct adv7604_chip_info *info;
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	struct adv7604_platform_data pdata;
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	struct v4l2_subdev sd;
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	struct media_pad pads[ADV7604_PAD_MAX];
	unsigned int source_pad;
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	struct v4l2_ctrl_handler hdl;
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	enum adv7604_pad selected_input;
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	struct v4l2_dv_timings timings;
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	const struct adv7604_format_info *format;

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	struct {
		u8 edid[256];
		u32 present;
		unsigned blocks;
	} edid;
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	u16 spa_port_a[2];
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	struct v4l2_fract aspect_ratio;
	u32 rgb_quantization_range;
	struct workqueue_struct *work_queues;
	struct delayed_work delayed_work_enable_hotplug;
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	bool restart_stdi_once;
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	/* i2c clients */
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	struct i2c_client *i2c_clients[ADV7604_PAGE_MAX];
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	/* controls */
	struct v4l2_ctrl *detect_tx_5v_ctrl;
	struct v4l2_ctrl *analog_sampling_phase_ctrl;
	struct v4l2_ctrl *free_run_color_manual_ctrl;
	struct v4l2_ctrl *free_run_color_ctrl;
	struct v4l2_ctrl *rgb_quantization_range_ctrl;
};

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static bool adv7604_has_afe(struct adv7604_state *state)
{
	return state->info->has_afe;
}

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/* Supported CEA and DMT timings */
static const struct v4l2_dv_timings adv7604_timings[] = {
	V4L2_DV_BT_CEA_720X480P59_94,
	V4L2_DV_BT_CEA_720X576P50,
	V4L2_DV_BT_CEA_1280X720P24,
	V4L2_DV_BT_CEA_1280X720P25,
	V4L2_DV_BT_CEA_1280X720P50,
	V4L2_DV_BT_CEA_1280X720P60,
	V4L2_DV_BT_CEA_1920X1080P24,
	V4L2_DV_BT_CEA_1920X1080P25,
	V4L2_DV_BT_CEA_1920X1080P30,
	V4L2_DV_BT_CEA_1920X1080P50,
	V4L2_DV_BT_CEA_1920X1080P60,

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	/* sorted by DMT ID */
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	V4L2_DV_BT_DMT_640X350P85,
	V4L2_DV_BT_DMT_640X400P85,
	V4L2_DV_BT_DMT_720X400P85,
	V4L2_DV_BT_DMT_640X480P60,
	V4L2_DV_BT_DMT_640X480P72,
	V4L2_DV_BT_DMT_640X480P75,
	V4L2_DV_BT_DMT_640X480P85,
	V4L2_DV_BT_DMT_800X600P56,
	V4L2_DV_BT_DMT_800X600P60,
	V4L2_DV_BT_DMT_800X600P72,
	V4L2_DV_BT_DMT_800X600P75,
	V4L2_DV_BT_DMT_800X600P85,
	V4L2_DV_BT_DMT_848X480P60,
	V4L2_DV_BT_DMT_1024X768P60,
	V4L2_DV_BT_DMT_1024X768P70,
	V4L2_DV_BT_DMT_1024X768P75,
	V4L2_DV_BT_DMT_1024X768P85,
	V4L2_DV_BT_DMT_1152X864P75,
	V4L2_DV_BT_DMT_1280X768P60_RB,
	V4L2_DV_BT_DMT_1280X768P60,
	V4L2_DV_BT_DMT_1280X768P75,
	V4L2_DV_BT_DMT_1280X768P85,
	V4L2_DV_BT_DMT_1280X800P60_RB,
	V4L2_DV_BT_DMT_1280X800P60,
	V4L2_DV_BT_DMT_1280X800P75,
	V4L2_DV_BT_DMT_1280X800P85,
	V4L2_DV_BT_DMT_1280X960P60,
	V4L2_DV_BT_DMT_1280X960P85,
	V4L2_DV_BT_DMT_1280X1024P60,
	V4L2_DV_BT_DMT_1280X1024P75,
	V4L2_DV_BT_DMT_1280X1024P85,
	V4L2_DV_BT_DMT_1360X768P60,
	V4L2_DV_BT_DMT_1400X1050P60_RB,
	V4L2_DV_BT_DMT_1400X1050P60,
	V4L2_DV_BT_DMT_1400X1050P75,
	V4L2_DV_BT_DMT_1400X1050P85,
	V4L2_DV_BT_DMT_1440X900P60_RB,
	V4L2_DV_BT_DMT_1440X900P60,
	V4L2_DV_BT_DMT_1600X1200P60,
	V4L2_DV_BT_DMT_1680X1050P60_RB,
	V4L2_DV_BT_DMT_1680X1050P60,
	V4L2_DV_BT_DMT_1792X1344P60,
	V4L2_DV_BT_DMT_1856X1392P60,
	V4L2_DV_BT_DMT_1920X1200P60_RB,
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	V4L2_DV_BT_DMT_1366X768P60_RB,
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	V4L2_DV_BT_DMT_1366X768P60,
	V4L2_DV_BT_DMT_1920X1080P60,
	{ },
};

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struct adv7604_video_standards {
	struct v4l2_dv_timings timings;
	u8 vid_std;
	u8 v_freq;
};

/* sorted by number of lines */
static const struct adv7604_video_standards adv7604_prim_mode_comp[] = {
	/* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
	{ V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
	{ V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
	{ V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
	{ V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
	{ V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
	{ V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
	{ V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
	{ V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
	/* TODO add 1920x1080P60_RB (CVT timing) */
	{ },
};

/* sorted by number of lines */
static const struct adv7604_video_standards adv7604_prim_mode_gr[] = {
	{ V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
	{ V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
	{ V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
	{ V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
	{ V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
	{ V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
	{ V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
	{ V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
	{ V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
	{ V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
	{ V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
	{ V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
	{ V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
	{ V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
	{ V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
	{ V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
	{ V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
	{ V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
	{ V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
	{ V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
	/* TODO add 1600X1200P60_RB (not a DMT timing) */
	{ V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
	{ V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
	{ },
};

/* sorted by number of lines */
static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = {
	{ V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
	{ V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
	{ V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
	{ V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
	{ V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
	{ V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
	{ V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
	{ V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
	{ V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
	{ },
};

/* sorted by number of lines */
static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = {
	{ V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
	{ V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
	{ V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
	{ V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
	{ V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
	{ V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
	{ V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
	{ V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
	{ V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
	{ V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
	{ V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
	{ V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
	{ V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
	{ V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
	{ V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
	{ },
};

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/* ----------------------------------------------------------------------- */

static inline struct adv7604_state *to_state(struct v4l2_subdev *sd)
{
	return container_of(sd, struct adv7604_state, sd);
}

static inline unsigned hblanking(const struct v4l2_bt_timings *t)
{
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	return V4L2_DV_BT_BLANKING_WIDTH(t);
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}

static inline unsigned htotal(const struct v4l2_bt_timings *t)
{
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	return V4L2_DV_BT_FRAME_WIDTH(t);
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}

static inline unsigned vblanking(const struct v4l2_bt_timings *t)
{
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	return V4L2_DV_BT_BLANKING_HEIGHT(t);
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}

static inline unsigned vtotal(const struct v4l2_bt_timings *t)
{
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	return V4L2_DV_BT_FRAME_HEIGHT(t);
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}

/* ----------------------------------------------------------------------- */

static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
		u8 command, bool check)
{
	union i2c_smbus_data data;

	if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
			I2C_SMBUS_READ, command,
			I2C_SMBUS_BYTE_DATA, &data))
		return data.byte;
	if (check)
		v4l_err(client, "error reading %02x, %02x\n",
				client->addr, command);
	return -EIO;
}

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static s32 adv_smbus_read_byte_data(struct adv7604_state *state,
				    enum adv7604_page page, u8 command)
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{
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	return adv_smbus_read_byte_data_check(state->i2c_clients[page],
					      command, true);
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}

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static s32 adv_smbus_write_byte_data(struct adv7604_state *state,
				     enum adv7604_page page, u8 command,
				     u8 value)
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{
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	struct i2c_client *client = state->i2c_clients[page];
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	union i2c_smbus_data data;
	int err;
	int i;

	data.byte = value;
	for (i = 0; i < 3; i++) {
		err = i2c_smbus_xfer(client->adapter, client->addr,
				client->flags,
				I2C_SMBUS_WRITE, command,
				I2C_SMBUS_BYTE_DATA, &data);
		if (!err)
			break;
	}
	if (err < 0)
		v4l_err(client, "error writing %02x, %02x, %02x\n",
				client->addr, command, value);
	return err;
}

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static s32 adv_smbus_write_i2c_block_data(struct adv7604_state *state,
					  enum adv7604_page page, u8 command,
					  unsigned length, const u8 *values)
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{
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	struct i2c_client *client = state->i2c_clients[page];
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	union i2c_smbus_data data;

	if (length > I2C_SMBUS_BLOCK_MAX)
		length = I2C_SMBUS_BLOCK_MAX;
	data.block[0] = length;
	memcpy(data.block + 1, values, length);
	return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
			      I2C_SMBUS_WRITE, command,
			      I2C_SMBUS_I2C_BLOCK_DATA, &data);
}

/* ----------------------------------------------------------------------- */

static inline int io_read(struct v4l2_subdev *sd, u8 reg)
{
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	struct adv7604_state *state = to_state(sd);
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	return adv_smbus_read_byte_data(state, ADV7604_PAGE_IO, reg);
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}

static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
{
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	struct adv7604_state *state = to_state(sd);
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	return adv_smbus_write_byte_data(state, ADV7604_PAGE_IO, reg, val);
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}

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static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
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{
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	return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
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}

static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
{
	struct adv7604_state *state = to_state(sd);

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	return adv_smbus_read_byte_data(state, ADV7604_PAGE_AVLINK, reg);
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}

static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
{
	struct adv7604_state *state = to_state(sd);

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	return adv_smbus_write_byte_data(state, ADV7604_PAGE_AVLINK, reg, val);
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}

static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
{
	struct adv7604_state *state = to_state(sd);

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	return adv_smbus_read_byte_data(state, ADV7604_PAGE_CEC, reg);
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}

static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
{
	struct adv7604_state *state = to_state(sd);

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	return adv_smbus_write_byte_data(state, ADV7604_PAGE_CEC, reg, val);
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}

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static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
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{
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	return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val);
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}

static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
{
	struct adv7604_state *state = to_state(sd);

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	return adv_smbus_read_byte_data(state, ADV7604_PAGE_INFOFRAME, reg);
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}

static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
{
	struct adv7604_state *state = to_state(sd);

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	return adv_smbus_write_byte_data(state, ADV7604_PAGE_INFOFRAME,
					 reg, val);
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}

static inline int esdp_read(struct v4l2_subdev *sd, u8 reg)
{
	struct adv7604_state *state = to_state(sd);

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	return adv_smbus_read_byte_data(state, ADV7604_PAGE_ESDP, reg);
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}

static inline int esdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
{
	struct adv7604_state *state = to_state(sd);

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	return adv_smbus_write_byte_data(state, ADV7604_PAGE_ESDP, reg, val);
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}

static inline int dpp_read(struct v4l2_subdev *sd, u8 reg)
{
	struct adv7604_state *state = to_state(sd);

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	return adv_smbus_read_byte_data(state, ADV7604_PAGE_DPP, reg);
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}

static inline int dpp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
{
	struct adv7604_state *state = to_state(sd);

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	return adv_smbus_write_byte_data(state, ADV7604_PAGE_DPP, reg, val);
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}

static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
{
	struct adv7604_state *state = to_state(sd);

517
	return adv_smbus_read_byte_data(state, ADV7604_PAGE_AFE, reg);
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}

static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
{
	struct adv7604_state *state = to_state(sd);

524
	return adv_smbus_write_byte_data(state, ADV7604_PAGE_AFE, reg, val);
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}

static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
{
	struct adv7604_state *state = to_state(sd);

531
	return adv_smbus_read_byte_data(state, ADV7604_PAGE_REP, reg);
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}

static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
{
	struct adv7604_state *state = to_state(sd);

538
	return adv_smbus_write_byte_data(state, ADV7604_PAGE_REP, reg, val);
539 540
}

541
static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
542
{
543
	return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val);
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}

static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
{
	struct adv7604_state *state = to_state(sd);

550
	return adv_smbus_read_byte_data(state, ADV7604_PAGE_EDID, reg);
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}

static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
{
	struct adv7604_state *state = to_state(sd);

557
	return adv_smbus_write_byte_data(state, ADV7604_PAGE_EDID, reg, val);
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}

static inline int edid_read_block(struct v4l2_subdev *sd, unsigned len, u8 *val)
{
	struct adv7604_state *state = to_state(sd);
563
	struct i2c_client *client = state->i2c_clients[ADV7604_PAGE_EDID];
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	u8 msgbuf0[1] = { 0 };
	u8 msgbuf1[256];
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	struct i2c_msg msg[2] = {
		{
			.addr = client->addr,
			.len = 1,
			.buf = msgbuf0
		},
		{
			.addr = client->addr,
			.flags = I2C_M_RD,
			.len = len,
			.buf = msgbuf1
		},
	};
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	if (i2c_transfer(client->adapter, msg, 2) < 0)
		return -EIO;
	memcpy(val, msgbuf1, len);
	return 0;
}

static inline int edid_write_block(struct v4l2_subdev *sd,
					unsigned len, const u8 *val)
{
	struct adv7604_state *state = to_state(sd);
	int err = 0;
	int i;

	v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len);

	for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
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		err = adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_EDID,
				i, I2C_SMBUS_BLOCK_MAX, val + i);
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	return err;
}
600

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static void adv7604_delayed_work_enable_hotplug(struct work_struct *work)
{
	struct delayed_work *dwork = to_delayed_work(work);
	struct adv7604_state *state = container_of(dwork, struct adv7604_state,
						delayed_work_enable_hotplug);
	struct v4l2_subdev *sd = &state->sd;
607

608
	v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
609

610
	v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present);
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}

static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
{
	struct adv7604_state *state = to_state(sd);

617
	return adv_smbus_read_byte_data(state, ADV7604_PAGE_HDMI, reg);
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}

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static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
{
	return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask;
}

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static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
{
	struct adv7604_state *state = to_state(sd);

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	return adv_smbus_write_byte_data(state, ADV7604_PAGE_HDMI, reg, val);
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}

632
static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
633
{
634
	return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val);
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}

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static inline int test_read(struct v4l2_subdev *sd, u8 reg)
{
	struct adv7604_state *state = to_state(sd);

641
	return adv_smbus_read_byte_data(state, ADV7604_PAGE_TEST, reg);
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}

static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
{
	struct adv7604_state *state = to_state(sd);

648
	return adv_smbus_write_byte_data(state, ADV7604_PAGE_TEST, reg, val);
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}

static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
{
	struct adv7604_state *state = to_state(sd);

655
	return adv_smbus_read_byte_data(state, ADV7604_PAGE_CP, reg);
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}

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static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
{
	return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask;
}

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static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
{
	struct adv7604_state *state = to_state(sd);

667
	return adv_smbus_write_byte_data(state, ADV7604_PAGE_CP, reg, val);
668 669
}

670
static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
671
{
672
	return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);
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}

static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
{
	struct adv7604_state *state = to_state(sd);

679
	return adv_smbus_read_byte_data(state, ADV7604_PAGE_VDP, reg);
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}

static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
{
	struct adv7604_state *state = to_state(sd);

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	return adv_smbus_write_byte_data(state, ADV7604_PAGE_VDP, reg, val);
}
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#define ADV7604_REG(page, offset)	(((page) << 8) | (offset))
#define ADV7604_REG_SEQ_TERM		0xffff

#ifdef CONFIG_VIDEO_ADV_DEBUG
static int adv7604_read_reg(struct v4l2_subdev *sd, unsigned int reg)
{
	struct adv7604_state *state = to_state(sd);
	unsigned int page = reg >> 8;

	if (!(BIT(page) & state->info->page_mask))
		return -EINVAL;

	reg &= 0xff;

703
	return adv_smbus_read_byte_data(state, page, reg);
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}
#endif

static int adv7604_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
{
	struct adv7604_state *state = to_state(sd);
	unsigned int page = reg >> 8;

	if (!(BIT(page) & state->info->page_mask))
		return -EINVAL;

	reg &= 0xff;

717
	return adv_smbus_write_byte_data(state, page, reg, val);
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}

static void adv7604_write_reg_seq(struct v4l2_subdev *sd,
				  const struct adv7604_reg_seq *reg_seq)
{
	unsigned int i;

	for (i = 0; reg_seq[i].reg != ADV7604_REG_SEQ_TERM; i++)
		adv7604_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
}

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/* -----------------------------------------------------------------------------
 * Format helpers
 */

static const struct adv7604_format_info adv7604_formats[] = {
	{ V4L2_MBUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false,
	  ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT },
	{ V4L2_MBUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false,
	  ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT },
	{ V4L2_MBUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true,
	  ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT },
	{ V4L2_MBUS_FMT_YUYV10_2X10, ADV7604_OP_CH_SEL_RGB, false, false,
	  ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
	{ V4L2_MBUS_FMT_YVYU10_2X10, ADV7604_OP_CH_SEL_RGB, false, true,
	  ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
	{ V4L2_MBUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false,
	  ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT },
	{ V4L2_MBUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true,
	  ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT },
	{ V4L2_MBUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false,
	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
	{ V4L2_MBUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true,
	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
	{ V4L2_MBUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false,
	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
	{ V4L2_MBUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true,
	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
	{ V4L2_MBUS_FMT_UYVY10_1X20, ADV7604_OP_CH_SEL_RBG, false, false,
	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
	{ V4L2_MBUS_FMT_VYUY10_1X20, ADV7604_OP_CH_SEL_RBG, false, true,
	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
	{ V4L2_MBUS_FMT_YUYV10_1X20, ADV7604_OP_CH_SEL_RGB, false, false,
	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
	{ V4L2_MBUS_FMT_YVYU10_1X20, ADV7604_OP_CH_SEL_RGB, false, true,
	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
	{ V4L2_MBUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false,
	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
	{ V4L2_MBUS_FMT_VYUY12_1X24, ADV7604_OP_CH_SEL_RBG, false, true,
	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
	{ V4L2_MBUS_FMT_YUYV12_1X24, ADV7604_OP_CH_SEL_RGB, false, false,
	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
	{ V4L2_MBUS_FMT_YVYU12_1X24, ADV7604_OP_CH_SEL_RGB, false, true,
	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
};

static const struct adv7604_format_info adv7611_formats[] = {
	{ V4L2_MBUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false,
	  ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT },
	{ V4L2_MBUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false,
	  ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT },
	{ V4L2_MBUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true,
	  ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT },
	{ V4L2_MBUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false,
	  ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT },
	{ V4L2_MBUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true,
	  ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT },
	{ V4L2_MBUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false,
	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
	{ V4L2_MBUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true,
	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
	{ V4L2_MBUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false,
	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
	{ V4L2_MBUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true,
	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
	{ V4L2_MBUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false,
	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
	{ V4L2_MBUS_FMT_VYUY12_1X24, ADV7604_OP_CH_SEL_RBG, false, true,
	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
	{ V4L2_MBUS_FMT_YUYV12_1X24, ADV7604_OP_CH_SEL_RGB, false, false,
	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
	{ V4L2_MBUS_FMT_YVYU12_1X24, ADV7604_OP_CH_SEL_RGB, false, true,
	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
};

static const struct adv7604_format_info *
adv7604_format_info(struct adv7604_state *state, enum v4l2_mbus_pixelcode code)
{
	unsigned int i;

	for (i = 0; i < state->info->nformats; ++i) {
		if (state->info->formats[i].code == code)
			return &state->info->formats[i];
	}

	return NULL;
}

816 817
/* ----------------------------------------------------------------------- */

818 819 820 821
static inline bool is_analog_input(struct v4l2_subdev *sd)
{
	struct adv7604_state *state = to_state(sd);

822 823
	return state->selected_input == ADV7604_PAD_VGA_RGB ||
	       state->selected_input == ADV7604_PAD_VGA_COMP;
824 825 826 827 828 829
}

static inline bool is_digital_input(struct v4l2_subdev *sd)
{
	struct adv7604_state *state = to_state(sd);

830 831 832 833
	return state->selected_input == ADV7604_PAD_HDMI_PORT_A ||
	       state->selected_input == ADV7604_PAD_HDMI_PORT_B ||
	       state->selected_input == ADV7604_PAD_HDMI_PORT_C ||
	       state->selected_input == ADV7604_PAD_HDMI_PORT_D;
834 835 836 837
}

/* ----------------------------------------------------------------------- */

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#ifdef CONFIG_VIDEO_ADV_DEBUG
static void adv7604_inv_register(struct v4l2_subdev *sd)
{
	v4l2_info(sd, "0x000-0x0ff: IO Map\n");
	v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
	v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
	v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
	v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
	v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
	v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
	v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
	v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
	v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
	v4l2_info(sd, "0xa00-0xaff: Test Map\n");
	v4l2_info(sd, "0xb00-0xbff: CP Map\n");
	v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
}

static int adv7604_g_register(struct v4l2_subdev *sd,
					struct v4l2_dbg_register *reg)
{
859 860 861 862
	int ret;

	ret = adv7604_read_reg(sd, reg->reg);
	if (ret < 0) {
863 864
		v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
		adv7604_inv_register(sd);
865
		return ret;
866
	}
867 868 869 870

	reg->size = 1;
	reg->val = ret;

871 872 873 874
	return 0;
}

static int adv7604_s_register(struct v4l2_subdev *sd,
875
					const struct v4l2_dbg_register *reg)
876
{
877
	int ret;
878

879 880
	ret = adv7604_write_reg(sd, reg->reg, reg->val);
	if (ret < 0) {
881 882
		v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
		adv7604_inv_register(sd);
883
		return ret;
884
	}
885

886 887 888 889
	return 0;
}
#endif

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static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd)
{
	u8 value = io_read(sd, 0x6f);

	return ((value & 0x10) >> 4)
	     | ((value & 0x08) >> 2)
	     | ((value & 0x04) << 0)
	     | ((value & 0x02) << 2);
}

static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
{
	u8 value = io_read(sd, 0x6f);

	return value & 1;
}

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static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
{
	struct adv7604_state *state = to_state(sd);
910
	const struct adv7604_chip_info *info = state->info;
911 912

	return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
913
				info->read_cable_det(sd));
914 915
}

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static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
		u8 prim_mode,
		const struct adv7604_video_standards *predef_vid_timings,
		const struct v4l2_dv_timings *timings)
{
	int i;

	for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
924
		if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
925
					is_digital_input(sd) ? 250000 : 1000000))
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			continue;
		io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
		io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
				prim_mode); /* v_freq and prim mode */
		return 0;
	}

	return -1;
}

static int configure_predefined_video_timings(struct v4l2_subdev *sd,
		struct v4l2_dv_timings *timings)
938
{
939 940 941 942 943
	struct adv7604_state *state = to_state(sd);
	int err;

	v4l2_dbg(1, debug, sd, "%s", __func__);

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	if (adv7604_has_afe(state)) {
		/* reset to default values */
		io_write(sd, 0x16, 0x43);
		io_write(sd, 0x17, 0x5a);
	}
949
	/* disable embedded syncs for auto graphics mode */
950
	cp_write_clr_set(sd, 0x81, 0x10, 0x00);
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	cp_write(sd, 0x8f, 0x00);
	cp_write(sd, 0x90, 0x00);
	cp_write(sd, 0xa2, 0x00);
	cp_write(sd, 0xa3, 0x00);
	cp_write(sd, 0xa4, 0x00);
	cp_write(sd, 0xa5, 0x00);
	cp_write(sd, 0xa6, 0x00);
	cp_write(sd, 0xa7, 0x00);
	cp_write(sd, 0xab, 0x00);
	cp_write(sd, 0xac, 0x00);

962
	if (is_analog_input(sd)) {
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		err = find_and_set_predefined_video_timings(sd,
				0x01, adv7604_prim_mode_comp, timings);
		if (err)
			err = find_and_set_predefined_video_timings(sd,
					0x02, adv7604_prim_mode_gr, timings);
968
	} else if (is_digital_input(sd)) {
969 970 971 972 973
		err = find_and_set_predefined_video_timings(sd,
				0x05, adv7604_prim_mode_hdmi_comp, timings);
		if (err)
			err = find_and_set_predefined_video_timings(sd,
					0x06, adv7604_prim_mode_hdmi_gr, timings);
974 975 976
	} else {
		v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
				__func__, state->selected_input);
977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999
		err = -1;
	}


	return err;
}

static void configure_custom_video_timings(struct v4l2_subdev *sd,
		const struct v4l2_bt_timings *bt)
{
	struct adv7604_state *state = to_state(sd);
	u32 width = htotal(bt);
	u32 height = vtotal(bt);
	u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
	u16 cp_start_eav = width - bt->hfrontporch;
	u16 cp_start_vbi = height - bt->vfrontporch;
	u16 cp_end_vbi = bt->vsync + bt->vbackporch;
	u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
		((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
	const u8 pll[2] = {
		0xc0 | ((width >> 8) & 0x1f),
		width & 0xff
	};
1000 1001 1002

	v4l2_dbg(2, debug, sd, "%s\n", __func__);

1003
	if (is_analog_input(sd)) {
1004 1005 1006 1007
		/* auto graphics */
		io_write(sd, 0x00, 0x07); /* video std */
		io_write(sd, 0x01, 0x02); /* prim mode */
		/* enable embedded syncs for auto graphics mode */
1008
		cp_write_clr_set(sd, 0x81, 0x10, 0x10);
1009

1010
		/* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
1011 1012
		/* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
		/* IO-map reg. 0x16 and 0x17 should be written in sequence */
1013 1014
		if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_IO,
						   0x16, 2, pll))
1015 1016 1017 1018
			v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");

		/* active video - horizontal timing */
		cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
1019
		cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
1020
				   ((cp_start_eav >> 8) & 0x0f));
1021 1022 1023 1024
		cp_write(sd, 0xa4, cp_start_eav & 0xff);

		/* active video - vertical timing */
		cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1025
		cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1026
				   ((cp_end_vbi >> 8) & 0xf));
1027
		cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1028
	} else if (is_digital_input(sd)) {
1029
		/* set default prim_mode/vid_std for HDMI
1030
		   according to [REF_03, c. 4.2] */
1031 1032
		io_write(sd, 0x00, 0x02); /* video std */
		io_write(sd, 0x01, 0x06); /* prim mode */
1033 1034 1035
	} else {
		v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
				__func__, state->selected_input);
1036 1037
	}

1038 1039 1040 1041 1042
	cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
	cp_write(sd, 0x90, ch1_fr_ll & 0xff);
	cp_write(sd, 0xab, (height >> 4) & 0xff);
	cp_write(sd, 0xac, (height & 0x0f) << 4);
}
1043

1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064
static void adv7604_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
{
	struct adv7604_state *state = to_state(sd);
	u8 offset_buf[4];

	if (auto_offset) {
		offset_a = 0x3ff;
		offset_b = 0x3ff;
		offset_c = 0x3ff;
	}

	v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
			__func__, auto_offset ? "Auto" : "Manual",
			offset_a, offset_b, offset_c);

	offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
	offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
	offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
	offset_buf[3] = offset_c & 0x0ff;

	/* Registers must be written in this order with no i2c access in between */
1065 1066
	if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_CP,
					   0x77, 4, offset_buf))
1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094
		v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
}

static void adv7604_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
{
	struct adv7604_state *state = to_state(sd);
	u8 gain_buf[4];
	u8 gain_man = 1;
	u8 agc_mode_man = 1;

	if (auto_gain) {
		gain_man = 0;
		agc_mode_man = 0;
		gain_a = 0x100;
		gain_b = 0x100;
		gain_c = 0x100;
	}

	v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
			__func__, auto_gain ? "Auto" : "Manual",
			gain_a, gain_b, gain_c);

	gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
	gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
	gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
	gain_buf[3] = ((gain_c & 0x0ff));

	/* Registers must be written in this order with no i2c access in between */
1095 1096
	if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_CP,
					   0x73, 4, gain_buf))
1097 1098 1099
		v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
}

1100 1101 1102
static void set_rgb_quantization_range(struct v4l2_subdev *sd)
{
	struct adv7604_state *state = to_state(sd);
1103 1104 1105 1106 1107 1108
	bool rgb_output = io_read(sd, 0x02) & 0x02;
	bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;

	v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
			__func__, state->rgb_quantization_range,
			rgb_output, hdmi_signal);
1109

1110 1111
	adv7604_set_gain(sd, true, 0x0, 0x0, 0x0);
	adv7604_set_offset(sd, true, 0x0, 0x0, 0x0);
1112

1113 1114
	switch (state->rgb_quantization_range) {
	case V4L2_DV_RGB_RANGE_AUTO:
1115
		if (state->selected_input == ADV7604_PAD_VGA_RGB) {
1116 1117
			/* Receiving analog RGB signal
			 * Set RGB full range (0-255) */
1118
			io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1119 1120 1121
			break;
		}

1122
		if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1123 1124
			/* Receiving analog YPbPr signal
			 * Set automode */
1125
			io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1126 1127 1128
			break;
		}

1129
		if (hdmi_signal) {
1130 1131
			/* Receiving HDMI signal
			 * Set automode */
1132
			io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1133 1134 1135 1136 1137 1138 1139 1140
			break;
		}

		/* Receiving DVI-D signal
		 * ADV7604 selects RGB limited range regardless of
		 * input format (CE/IT) in automatic mode */
		if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
			/* RGB limited range (16-235) */
1141
			io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1142 1143
		} else {
			/* RGB full range (0-255) */
1144
			io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1145 1146 1147 1148 1149 1150 1151

			if (is_digital_input(sd) && rgb_output) {
				adv7604_set_offset(sd, false, 0x40, 0x40, 0x40);
			} else {
				adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
				adv7604_set_offset(sd, false, 0x70, 0x70, 0x70);
			}
1152 1153 1154
		}
		break;
	case V4L2_DV_RGB_RANGE_LIMITED:
1155
		if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1156
			/* YCrCb limited range (16-235) */
1157
			io_write_clr_set(sd, 0x02, 0xf0, 0x20);
1158
			break;
1159
		}
1160 1161

		/* RGB limited range (16-235) */
1162
		io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1163

1164 1165
		break;
	case V4L2_DV_RGB_RANGE_FULL:
1166
		if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1167
			/* YCrCb full range (0-255) */
1168
			io_write_clr_set(sd, 0x02, 0xf0, 0x60);
1169 1170 1171 1172
			break;
		}

		/* RGB full range (0-255) */
1173
		io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1174 1175 1176 1177 1178 1179 1180

		if (is_analog_input(sd) || hdmi_signal)
			break;

		/* Adjust gain/offset for DVI-D signals only */
		if (rgb_output) {
			adv7604_set_offset(sd, false, 0x40, 0x40, 0x40);
1181
		} else {
1182 1183
			adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
			adv7604_set_offset(sd, false, 0x70, 0x70, 0x70);
1184
		}
1185 1186 1187 1188 1189 1190
		break;
	}
}

static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl)
{
1191 1192 1193
	struct v4l2_subdev *sd =
		&container_of(ctrl->handler, struct adv7604_state, hdl)->sd;

1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213
	struct adv7604_state *state = to_state(sd);

	switch (ctrl->id) {
	case V4L2_CID_BRIGHTNESS:
		cp_write(sd, 0x3c, ctrl->val);
		return 0;
	case V4L2_CID_CONTRAST:
		cp_write(sd, 0x3a, ctrl->val);
		return 0;
	case V4L2_CID_SATURATION:
		cp_write(sd, 0x3b, ctrl->val);
		return 0;
	case V4L2_CID_HUE:
		cp_write(sd, 0x3d, ctrl->val);
		return 0;
	case  V4L2_CID_DV_RX_RGB_RANGE:
		state->rgb_quantization_range = ctrl->val;
		set_rgb_quantization_range(sd);
		return 0;
	case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1214 1215
		if (!adv7604_has_afe(state))
			return -EINVAL;
1216 1217 1218 1219 1220 1221 1222 1223 1224
		/* Set the analog sampling phase. This is needed to find the
		   best sampling phase for analog video: an application or
		   driver has to try a number of phases and analyze the picture
		   quality before settling on the best performing phase. */
		afe_write(sd, 0xc8, ctrl->val);
		return 0;
	case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
		/* Use the default blue color for free running mode,
		   or supply your own. */
1225
		cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2);
1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245
		return 0;
	case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
		cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
		cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
		cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
		return 0;
	}
	return -EINVAL;
}

/* ----------------------------------------------------------------------- */

static inline bool no_power(struct v4l2_subdev *sd)
{
	/* Entire chip or CP powered off */
	return io_read(sd, 0x0c) & 0x24;
}

static inline bool no_signal_tmds(struct v4l2_subdev *sd)
{
1246 1247 1248
	struct adv7604_state *state = to_state(sd);

	return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
1249 1250 1251 1252
}

static inline bool no_lock_tmds(struct v4l2_subdev *sd)
{
1253 1254 1255 1256
	struct adv7604_state *state = to_state(sd);
	const struct adv7604_chip_info *info = state->info;

	return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
1257 1258
}

1259 1260 1261 1262 1263
static inline bool is_hdmi(struct v4l2_subdev *sd)
{
	return hdmi_read(sd, 0x05) & 0x80;
}

1264 1265
static inline bool no_lock_sspd(struct v4l2_subdev *sd)
{
1266 1267 1268 1269 1270 1271 1272 1273 1274
	struct adv7604_state *state = to_state(sd);

	/*
	 * Chips without a AFE don't expose registers for the SSPD, so just assume
	 * that we have a lock.
	 */
	if (adv7604_has_afe(state))
		return false;

1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293
	/* TODO channel 2 */
	return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
}

static inline bool no_lock_stdi(struct v4l2_subdev *sd)
{
	/* TODO channel 2 */
	return !(cp_read(sd, 0xb1) & 0x80);
}

static inline bool no_signal(struct v4l2_subdev *sd)
{
	bool ret;

	ret = no_power(sd);

	ret |= no_lock_stdi(sd);
	ret |= no_lock_sspd(sd);

1294
	if (is_digital_input(sd)) {
1295 1296 1297 1298 1299 1300 1301 1302 1303
		ret |= no_lock_tmds(sd);
		ret |= no_signal_tmds(sd);
	}

	return ret;
}

static inline bool no_lock_cp(struct v4l2_subdev *sd)
{
1304 1305 1306 1307 1308
	struct adv7604_state *state = to_state(sd);

	if (!adv7604_has_afe(state))
		return false;

1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319
	/* CP has detected a non standard number of lines on the incoming
	   video compared to what it is configured to receive by s_dv_timings */
	return io_read(sd, 0x12) & 0x01;
}

static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status)
{
	*status = 0;
	*status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
	*status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
	if (no_lock_cp(sd))
1320
		*status |= is_digital_input(sd) ? V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369

	v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);

	return 0;
}

/* ----------------------------------------------------------------------- */

struct stdi_readback {
	u16 bl, lcf, lcvs;
	u8 hs_pol, vs_pol;
	bool interlaced;
};

static int stdi2dv_timings(struct v4l2_subdev *sd,
		struct stdi_readback *stdi,
		struct v4l2_dv_timings *timings)
{
	struct adv7604_state *state = to_state(sd);
	u32 hfreq = (ADV7604_fsc * 8) / stdi->bl;
	u32 pix_clk;
	int i;

	for (i = 0; adv7604_timings[i].bt.height; i++) {
		if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1)
			continue;
		if (adv7604_timings[i].bt.vsync != stdi->lcvs)
			continue;

		pix_clk = hfreq * htotal(&adv7604_timings[i].bt);

		if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) &&
		    (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) {
			*timings = adv7604_timings[i];
			return 0;
		}
	}

	if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
			(stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
			(stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
			timings))
		return 0;
	if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
			(stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
			(stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
			state->aspect_ratio, timings))
		return 0;

1370 1371 1372 1373
	v4l2_dbg(2, debug, sd,
		"%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
		__func__, stdi->lcvs, stdi->lcf, stdi->bl,
		stdi->hs_pol, stdi->vs_pol);
1374 1375 1376
	return -1;
}

1377

1378 1379
static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
{
1380 1381
	struct adv7604_state *state = to_state(sd);
	const struct adv7604_chip_info *info = state->info;
1382 1383
	u8 polarity;

1384 1385 1386 1387 1388 1389
	if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
		v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
		return -1;
	}

	/* read STDI */
1390
	stdi->bl = cp_read16(sd, 0xb1, 0x3fff);
1391
	stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff);
1392 1393 1394
	stdi->lcvs = cp_read(sd, 0xb3) >> 3;
	stdi->interlaced = io_read(sd, 0x12) & 0x10;

1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406
	if (adv7604_has_afe(state)) {
		/* read SSPD */
		polarity = cp_read(sd, 0xb5);
		if ((polarity & 0x03) == 0x01) {
			stdi->hs_pol = polarity & 0x10
				     ? (polarity & 0x08 ? '+' : '-') : 'x';
			stdi->vs_pol = polarity & 0x40
				     ? (polarity & 0x20 ? '+' : '-') : 'x';
		} else {
			stdi->hs_pol = 'x';
			stdi->vs_pol = 'x';
		}
1407
	} else {
1408 1409 1410
		polarity = hdmi_read(sd, 0x05);
		stdi->hs_pol = polarity & 0x20 ? '+' : '-';
		stdi->vs_pol = polarity & 0x10 ? '+' : '-';
1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436
	}

	if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
		v4l2_dbg(2, debug, sd,
			"%s: signal lost during readout of STDI/SSPD\n", __func__);
		return -1;
	}

	if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
		v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
		memset(stdi, 0, sizeof(struct stdi_readback));
		return -1;
	}

	v4l2_dbg(2, debug, sd,
		"%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
		__func__, stdi->lcf, stdi->bl, stdi->lcvs,
		stdi->hs_pol, stdi->vs_pol,
		stdi->interlaced ? "interlaced" : "progressive");

	return 0;
}

static int adv7604_enum_dv_timings(struct v4l2_subdev *sd,
			struct v4l2_enum_dv_timings *timings)
{
1437 1438
	struct adv7604_state *state = to_state(sd);

1439 1440
	if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1)
		return -EINVAL;
1441 1442 1443 1444

	if (timings->pad >= state->source_pad)
		return -EINVAL;

1445 1446 1447 1448 1449
	memset(timings->reserved, 0, sizeof(timings->reserved));
	timings->timings = adv7604_timings[timings->index];
	return 0;
}

1450 1451
static int adv7604_dv_timings_cap(struct v4l2_subdev *sd,
			struct v4l2_dv_timings_cap *cap)
1452
{
1453 1454 1455 1456 1457
	struct adv7604_state *state = to_state(sd);

	if (cap->pad >= state->source_pad)
		return -EINVAL;

1458 1459 1460
	cap->type = V4L2_DV_BT_656_1120;
	cap->bt.max_width = 1920;
	cap->bt.max_height = 1200;
1461
	cap->bt.min_pixelclock = 25000000;
1462

1463
	switch (cap->pad) {
1464 1465 1466 1467
	case ADV7604_PAD_HDMI_PORT_A:
	case ADV7604_PAD_HDMI_PORT_B:
	case ADV7604_PAD_HDMI_PORT_C:
	case ADV7604_PAD_HDMI_PORT_D:
1468
		cap->bt.max_pixelclock = 225000000;
1469 1470 1471 1472
		break;
	case ADV7604_PAD_VGA_RGB:
	case ADV7604_PAD_VGA_COMP:
	default:
1473
		cap->bt.max_pixelclock = 170000000;
1474 1475 1476
		break;
	}

1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491
	cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
			 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
	cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
		V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
	return 0;
}

/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
   if the format is listed in adv7604_timings[] */
static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
		struct v4l2_dv_timings *timings)
{
	int i;

	for (i = 0; adv7604_timings[i].bt.width; i++) {
1492
		if (v4l2_match_dv_timings(timings, &adv7604_timings[i],
1493
					is_digital_input(sd) ? 250000 : 1000000)) {
1494 1495 1496 1497 1498 1499
			*timings = adv7604_timings[i];
			break;
		}
	}
}

1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531
static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd)
{
	unsigned int freq;
	int a, b;

	a = hdmi_read(sd, 0x06);
	b = hdmi_read(sd, 0x3b);
	if (a < 0 || b < 0)
		return 0;
	freq =  a * 1000000 + ((b & 0x30) >> 4) * 250000;

	if (is_hdmi(sd)) {
		/* adjust for deep color mode */
		unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;

		freq = freq * 8 / bits_per_channel;
	}

	return freq;
}

static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
{
	int a, b;

	a = hdmi_read(sd, 0x51);
	b = hdmi_read(sd, 0x52);
	if (a < 0 || b < 0)
		return 0;
	return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
}

1532 1533 1534 1535
static int adv7604_query_dv_timings(struct v4l2_subdev *sd,
			struct v4l2_dv_timings *timings)
{
	struct adv7604_state *state = to_state(sd);
1536
	const struct adv7604_chip_info *info = state->info;
1537 1538 1539 1540 1541 1542 1543 1544 1545
	struct v4l2_bt_timings *bt = &timings->bt;
	struct stdi_readback stdi;

	if (!timings)
		return -EINVAL;

	memset(timings, 0, sizeof(struct v4l2_dv_timings));

	if (no_signal(sd)) {
1546
		state->restart_stdi_once = true;
1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558
		v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
		return -ENOLINK;
	}

	/* read STDI */
	if (read_stdi(sd, &stdi)) {
		v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
		return -ENOLINK;
	}
	bt->interlaced = stdi.interlaced ?
		V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;

1559
	if (is_digital_input(sd)) {
1560 1561
		timings->type = V4L2_DV_BT_656_1120;

1562
		/* FIXME: All masks are incorrect for ADV7611 */
1563 1564
		bt->width = hdmi_read16(sd, 0x07, 0xfff);
		bt->height = hdmi_read16(sd, 0x09, 0xfff);
1565
		bt->pixelclock = info->read_hdmi_pixelclock(sd);
1566 1567 1568 1569 1570 1571
		bt->hfrontporch = hdmi_read16(sd, 0x20, 0x3ff);
		bt->hsync = hdmi_read16(sd, 0x22, 0x3ff);
		bt->hbackporch = hdmi_read16(sd, 0x24, 0x3ff);
		bt->vfrontporch = hdmi_read16(sd, 0x2a, 0x1fff) / 2;
		bt->vsync = hdmi_read16(sd, 0x2e, 0x1fff) / 2;
		bt->vbackporch = hdmi_read16(sd, 0x32, 0x1fff) / 2;
1572 1573 1574
		bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
			((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
		if (bt->interlaced == V4L2_DV_INTERLACED) {
1575 1576 1577 1578
			bt->height += hdmi_read16(sd, 0x0b, 0xfff);
			bt->il_vfrontporch = hdmi_read16(sd, 0x2c, 0x1fff) / 2;
			bt->il_vsync = hdmi_read16(sd, 0x30, 0x1fff) / 2;
			bt->vbackporch = hdmi_read16(sd, 0x34, 0x1fff) / 2;
1579 1580 1581 1582
		}
		adv7604_fill_optional_dv_timings_fields(sd, timings);
	} else {
		/* find format
H
Hans Verkuil 已提交
1583
		 * Since LCVS values are inaccurate [REF_03, p. 275-276],
1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594
		 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
		 */
		if (!stdi2dv_timings(sd, &stdi, timings))
			goto found;
		stdi.lcvs += 1;
		v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
		if (!stdi2dv_timings(sd, &stdi, timings))
			goto found;
		stdi.lcvs -= 2;
		v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
		if (stdi2dv_timings(sd, &stdi, timings)) {
1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607
			/*
			 * The STDI block may measure wrong values, especially
			 * for lcvs and lcf. If the driver can not find any
			 * valid timing, the STDI block is restarted to measure
			 * the video timings again. The function will return an
			 * error, but the restart of STDI will generate a new
			 * STDI interrupt and the format detection process will
			 * restart.
			 */
			if (state->restart_stdi_once) {
				v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
				/* TODO restart STDI for Sync Channel 2 */
				/* enter one-shot mode */
1608
				cp_write_clr_set(sd, 0x86, 0x06, 0x00);
1609
				/* trigger STDI restart */
1610
				cp_write_clr_set(sd, 0x86, 0x06, 0x04);
1611
				/* reset to continuous mode */
1612
				cp_write_clr_set(sd, 0x86, 0x06, 0x02);
1613 1614 1615
				state->restart_stdi_once = false;
				return -ENOLINK;
			}
1616 1617 1618
			v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
			return -ERANGE;
		}
1619
		state->restart_stdi_once = true;
1620 1621 1622 1623 1624 1625 1626 1627 1628
	}
found:

	if (no_signal(sd)) {
		v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
		memset(timings, 0, sizeof(struct v4l2_dv_timings));
		return -ENOLINK;
	}

1629 1630
	if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
			(is_digital_input(sd) && bt->pixelclock > 225000000)) {
1631 1632 1633 1634 1635 1636
		v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
				__func__, (u32)bt->pixelclock);
		return -ERANGE;
	}

	if (debug > 1)
1637 1638
		v4l2_print_dv_timings(sd->name, "adv7604_query_dv_timings: ",
				      timings, true);
1639 1640 1641 1642 1643 1644 1645 1646 1647

	return 0;
}

static int adv7604_s_dv_timings(struct v4l2_subdev *sd,
		struct v4l2_dv_timings *timings)
{
	struct adv7604_state *state = to_state(sd);
	struct v4l2_bt_timings *bt;
1648
	int err;
1649 1650 1651 1652

	if (!timings)
		return -EINVAL;

1653 1654 1655 1656 1657
	if (v4l2_match_dv_timings(&state->timings, timings, 0)) {
		v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
		return 0;
	}

1658 1659
	bt = &timings->bt;

1660 1661
	if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
			(is_digital_input(sd) && bt->pixelclock > 225000000)) {
1662 1663 1664 1665
		v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
				__func__, (u32)bt->pixelclock);
		return -ERANGE;
	}
1666

1667 1668 1669 1670
	adv7604_fill_optional_dv_timings_fields(sd, timings);

	state->timings = *timings;

1671
	cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);
1672 1673 1674 1675 1676 1677 1678 1679

	/* Use prim_mode and vid_std when available */
	err = configure_predefined_video_timings(sd, timings);
	if (err) {
		/* custom settings when the video format
		 does not have prim_mode/vid_std */
		configure_custom_video_timings(sd, bt);
	}
1680 1681 1682 1683

	set_rgb_quantization_range(sd);

	if (debug > 1)
1684 1685
		v4l2_print_dv_timings(sd->name, "adv7604_s_dv_timings: ",
				      timings, true);
1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697
	return 0;
}

static int adv7604_g_dv_timings(struct v4l2_subdev *sd,
		struct v4l2_dv_timings *timings)
{
	struct adv7604_state *state = to_state(sd);

	*timings = state->timings;
	return 0;
}

1698 1699 1700 1701 1702 1703 1704 1705 1706 1707
static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable)
{
	hdmi_write(sd, 0x01, enable ? 0x00 : 0x78);
}

static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
{
	hdmi_write(sd, 0x83, enable ? 0xfe : 0xff);
}

1708
static void enable_input(struct v4l2_subdev *sd)
1709
{
1710 1711
	struct adv7604_state *state = to_state(sd);

1712
	if (is_analog_input(sd)) {
1713
		io_write(sd, 0x15, 0xb0);   /* Disable Tristate of Pins (no audio) */
1714
	} else if (is_digital_input(sd)) {
1715
		hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input);
1716
		state->info->set_termination(sd, true);
1717
		io_write(sd, 0x15, 0xa0);   /* Disable Tristate of Pins */
1718
		hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */
1719 1720 1721
	} else {
		v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
				__func__, state->selected_input);
1722 1723 1724 1725 1726
	}
}

static void disable_input(struct v4l2_subdev *sd)
{
1727 1728
	struct adv7604_state *state = to_state(sd);

1729
	hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
1730
	msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
1731
	io_write(sd, 0x15, 0xbe);   /* Tristate all outputs from video core */
1732
	state->info->set_termination(sd, false);
1733 1734
}

1735
static void select_input(struct v4l2_subdev *sd)
1736
{
1737
	struct adv7604_state *state = to_state(sd);
1738
	const struct adv7604_chip_info *info = state->info;
1739

1740
	if (is_analog_input(sd)) {
1741
		adv7604_write_reg_seq(sd, info->recommended_settings[0]);
1742 1743 1744 1745

		afe_write(sd, 0x00, 0x08); /* power up ADC */
		afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
		afe_write(sd, 0xc8, 0x00); /* phase control */
1746 1747
	} else if (is_digital_input(sd)) {
		hdmi_write(sd, 0x00, state->selected_input & 0x03);
1748

1749 1750 1751 1752 1753 1754 1755 1756
		adv7604_write_reg_seq(sd, info->recommended_settings[1]);

		if (adv7604_has_afe(state)) {
			afe_write(sd, 0x00, 0xff); /* power down ADC */
			afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
			afe_write(sd, 0xc8, 0x40); /* phase control */
		}

1757 1758 1759
		cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
		cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
		cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
1760 1761 1762
	} else {
		v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
				__func__, state->selected_input);
1763 1764 1765 1766 1767 1768 1769 1770
	}
}

static int adv7604_s_routing(struct v4l2_subdev *sd,
		u32 input, u32 output, u32 config)
{
	struct adv7604_state *state = to_state(sd);

1771 1772 1773 1774 1775
	v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
			__func__, input, state->selected_input);

	if (input == state->selected_input)
		return 0;
1776

1777 1778 1779
	if (input > state->info->max_port)
		return -EINVAL;

1780
	state->selected_input = input;
1781 1782 1783

	disable_input(sd);

1784
	select_input(sd);
1785

1786
	enable_input(sd);
1787 1788 1789 1790

	return 0;
}

1791 1792 1793
static int adv7604_enum_mbus_code(struct v4l2_subdev *sd,
				  struct v4l2_subdev_fh *fh,
				  struct v4l2_subdev_mbus_code_enum *code)
1794
{
1795 1796 1797
	struct adv7604_state *state = to_state(sd);

	if (code->index >= state->info->nformats)
1798
		return -EINVAL;
1799 1800 1801

	code->code = state->info->formats[code->index].code;

1802 1803 1804
	return 0;
}

1805 1806
static void adv7604_fill_format(struct adv7604_state *state,
				struct v4l2_mbus_framefmt *format)
1807
{
1808
	memset(format, 0, sizeof(*format));
1809

1810 1811 1812 1813 1814 1815
	format->width = state->timings.bt.width;
	format->height = state->timings.bt.height;
	format->field = V4L2_FIELD_NONE;

	if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861)
		format->colorspace = (state->timings.bt.height <= 576) ?
1816
			V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859
}

/*
 * Compute the op_ch_sel value required to obtain on the bus the component order
 * corresponding to the selected format taking into account bus reordering
 * applied by the board at the output of the device.
 *
 * The following table gives the op_ch_value from the format component order
 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
 * adv7604_bus_order value in row).
 *
 *           |	GBR(0)	GRB(1)	BGR(2)	RGB(3)	BRG(4)	RBG(5)
 * ----------+-------------------------------------------------
 * RGB (NOP) |	GBR	GRB	BGR	RGB	BRG	RBG
 * GRB (1-2) |	BGR	RGB	GBR	GRB	RBG	BRG
 * RBG (2-3) |	GRB	GBR	BRG	RBG	BGR	RGB
 * BGR (1-3) |	RBG	BRG	RGB	BGR	GRB	GBR
 * BRG (ROR) |	BRG	RBG	GRB	GBR	RGB	BGR
 * GBR (ROL) |	RGB	BGR	RBG	BRG	GBR	GRB
 */
static unsigned int adv7604_op_ch_sel(struct adv7604_state *state)
{
#define _SEL(a,b,c,d,e,f)	{ \
	ADV7604_OP_CH_SEL_##a, ADV7604_OP_CH_SEL_##b, ADV7604_OP_CH_SEL_##c, \
	ADV7604_OP_CH_SEL_##d, ADV7604_OP_CH_SEL_##e, ADV7604_OP_CH_SEL_##f }
#define _BUS(x)			[ADV7604_BUS_ORDER_##x]

	static const unsigned int op_ch_sel[6][6] = {
		_BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
		_BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
		_BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
		_BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
		_BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
		_BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
	};

	return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
}

static void adv7604_setup_format(struct adv7604_state *state)
{
	struct v4l2_subdev *sd = &state->sd;

1860
	io_write_clr_set(sd, 0x02, 0x02,
1861 1862 1863
			state->format->rgb_out ? ADV7604_RGB_OUT : 0);
	io_write(sd, 0x03, state->format->op_format_sel |
		 state->pdata.op_format_mode_sel);
1864 1865
	io_write_clr_set(sd, 0x04, 0xe0, adv7604_op_ch_sel(state));
	io_write_clr_set(sd, 0x05, 0x01,
1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885
			state->format->swap_cb_cr ? ADV7604_OP_SWAP_CB_CR : 0);
}

static int adv7604_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
			      struct v4l2_subdev_format *format)
{
	struct adv7604_state *state = to_state(sd);

	if (format->pad != state->source_pad)
		return -EINVAL;

	adv7604_fill_format(state, &format->format);

	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
		struct v4l2_mbus_framefmt *fmt;

		fmt = v4l2_subdev_get_try_format(fh, format->pad);
		format->format.code = fmt->code;
	} else {
		format->format.code = state->format->code;
1886
	}
1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916

	return 0;
}

static int adv7604_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
			      struct v4l2_subdev_format *format)
{
	struct adv7604_state *state = to_state(sd);
	const struct adv7604_format_info *info;

	if (format->pad != state->source_pad)
		return -EINVAL;

	info = adv7604_format_info(state, format->format.code);
	if (info == NULL)
		info = adv7604_format_info(state, V4L2_MBUS_FMT_YUYV8_2X8);

	adv7604_fill_format(state, &format->format);
	format->format.code = info->code;

	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
		struct v4l2_mbus_framefmt *fmt;

		fmt = v4l2_subdev_get_try_format(fh, format->pad);
		fmt->code = format->format.code;
	} else {
		state->format = info;
		adv7604_setup_format(state);
	}

1917 1918 1919 1920 1921
	return 0;
}

static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
{
1922 1923
	struct adv7604_state *state = to_state(sd);
	const struct adv7604_chip_info *info = state->info;
1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936
	const u8 irq_reg_0x43 = io_read(sd, 0x43);
	const u8 irq_reg_0x6b = io_read(sd, 0x6b);
	const u8 irq_reg_0x70 = io_read(sd, 0x70);
	u8 fmt_change_digital;
	u8 fmt_change;
	u8 tx_5v;

	if (irq_reg_0x43)
		io_write(sd, 0x44, irq_reg_0x43);
	if (irq_reg_0x70)
		io_write(sd, 0x71, irq_reg_0x70);
	if (irq_reg_0x6b)
		io_write(sd, 0x6c, irq_reg_0x6b);
1937

1938 1939
	v4l2_dbg(2, debug, sd, "%s: ", __func__);

1940
	/* format change */
1941
	fmt_change = irq_reg_0x43 & 0x98;
1942 1943 1944
	fmt_change_digital = is_digital_input(sd)
			   ? irq_reg_0x6b & info->fmt_change_digital_mask
			   : 0;
1945

1946 1947
	if (fmt_change || fmt_change_digital) {
		v4l2_dbg(1, debug, sd,
1948
			"%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
1949
			__func__, fmt_change, fmt_change_digital);
1950

1951
		v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL);
1952

1953 1954 1955
		if (handled)
			*handled = true;
	}
1956 1957 1958 1959 1960 1961 1962 1963 1964
	/* HDMI/DVI mode */
	if (irq_reg_0x6b & 0x01) {
		v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
			(io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
		set_rgb_quantization_range(sd);
		if (handled)
			*handled = true;
	}

1965
	/* tx 5v detect */
1966
	tx_5v = io_read(sd, 0x70) & info->cable_det_mask;
1967 1968 1969 1970 1971 1972 1973 1974 1975 1976
	if (tx_5v) {
		v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
		io_write(sd, 0x71, tx_5v);
		adv7604_s_detect_tx_5v_ctrl(sd);
		if (handled)
			*handled = true;
	}
	return 0;
}

1977
static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
1978 1979
{
	struct adv7604_state *state = to_state(sd);
1980
	u8 *data = NULL;
1981

1982
	if (edid->pad > ADV7604_PAD_HDMI_PORT_D)
1983 1984 1985
		return -EINVAL;
	if (edid->blocks == 0)
		return -EINVAL;
1986
	if (edid->blocks > 2)
1987
		return -EINVAL;
1988 1989 1990 1991 1992 1993 1994 1995 1996
	if (edid->start_block > 1)
		return -EINVAL;
	if (edid->start_block == 1)
		edid->blocks = 1;

	if (edid->blocks > state->edid.blocks)
		edid->blocks = state->edid.blocks;

	switch (edid->pad) {
1997 1998 1999 2000
	case ADV7604_PAD_HDMI_PORT_A:
	case ADV7604_PAD_HDMI_PORT_B:
	case ADV7604_PAD_HDMI_PORT_C:
	case ADV7604_PAD_HDMI_PORT_D:
2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012
		if (state->edid.present & (1 << edid->pad))
			data = state->edid.edid;
		break;
	default:
		return -EINVAL;
		break;
	}
	if (!data)
		return -ENODATA;

	memcpy(edid->edid,
	       data + edid->start_block * 128,
2013 2014 2015 2016
	       edid->blocks * 128);
	return 0;
}

2017
static int get_edid_spa_location(const u8 *edid)
2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044
{
	u8 d;

	if ((edid[0x7e] != 1) ||
	    (edid[0x80] != 0x02) ||
	    (edid[0x81] != 0x03)) {
		return -1;
	}

	/* search Vendor Specific Data Block (tag 3) */
	d = edid[0x82] & 0x7f;
	if (d > 4) {
		int i = 0x84;
		int end = 0x80 + d;

		do {
			u8 tag = edid[i] >> 5;
			u8 len = edid[i] & 0x1f;

			if ((tag == 3) && (len >= 5))
				return i + 4;
			i += len + 1;
		} while (i < end);
	}
	return -1;
}

2045
static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2046 2047
{
	struct adv7604_state *state = to_state(sd);
2048
	const struct adv7604_chip_info *info = state->info;
2049
	int spa_loc;
2050
	int tmp = 0;
2051
	int err;
2052
	int i;
2053

2054
	if (edid->pad > ADV7604_PAD_HDMI_PORT_D)
2055 2056 2057 2058
		return -EINVAL;
	if (edid->start_block != 0)
		return -EINVAL;
	if (edid->blocks == 0) {
2059
		/* Disable hotplug and I2C access to EDID RAM from DDC port */
2060 2061
		state->edid.present &= ~(1 << edid->pad);
		v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present);
2062
		rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2063

2064 2065 2066
		/* Fall back to a 16:9 aspect ratio */
		state->aspect_ratio.numerator = 16;
		state->aspect_ratio.denominator = 9;
2067 2068 2069 2070 2071 2072

		if (!state->edid.present)
			state->edid.blocks = 0;

		v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
				__func__, edid->pad, state->edid.present);
2073 2074
		return 0;
	}
2075 2076
	if (edid->blocks > 2) {
		edid->blocks = 2;
2077
		return -E2BIG;
2078 2079
	}

2080 2081 2082
	v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
			__func__, edid->pad, state->edid.present);

2083
	/* Disable hotplug and I2C access to EDID RAM from DDC port */
2084
	cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
2085
	v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&tmp);
2086
	rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
2087

2088 2089 2090 2091
	spa_loc = get_edid_spa_location(edid->edid);
	if (spa_loc < 0)
		spa_loc = 0xc0; /* Default value [REF_02, p. 116] */

2092
	switch (edid->pad) {
2093
	case ADV7604_PAD_HDMI_PORT_A:
2094 2095
		state->spa_port_a[0] = edid->edid[spa_loc];
		state->spa_port_a[1] = edid->edid[spa_loc + 1];
2096
		break;
2097
	case ADV7604_PAD_HDMI_PORT_B:
2098 2099
		rep_write(sd, 0x70, edid->edid[spa_loc]);
		rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
2100
		break;
2101
	case ADV7604_PAD_HDMI_PORT_C:
2102 2103
		rep_write(sd, 0x72, edid->edid[spa_loc]);
		rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
2104
		break;
2105
	case ADV7604_PAD_HDMI_PORT_D:
2106 2107
		rep_write(sd, 0x74, edid->edid[spa_loc]);
		rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
2108
		break;
2109 2110
	default:
		return -EINVAL;
2111
	}
2112 2113 2114

	if (info->type == ADV7604) {
		rep_write(sd, 0x76, spa_loc & 0xff);
2115
		rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2);
2116 2117
	} else {
		/* FIXME: Where is the SPA location LSB register ? */
2118
		rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8);
2119
	}
2120

2121 2122
	edid->edid[spa_loc] = state->spa_port_a[0];
	edid->edid[spa_loc + 1] = state->spa_port_a[1];
2123 2124 2125

	memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
	state->edid.blocks = edid->blocks;
2126 2127
	state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
			edid->edid[0x16]);
2128
	state->edid.present |= 1 << edid->pad;
2129 2130 2131

	err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
	if (err < 0) {
2132
		v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
2133 2134 2135
		return err;
	}

2136 2137
	/* adv7604 calculates the checksums and enables I2C access to internal
	   EDID RAM from DDC port. */
2138
	rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2139 2140

	for (i = 0; i < 1000; i++) {
2141
		if (rep_read(sd, info->edid_status_reg) & state->edid.present)
2142 2143 2144 2145 2146 2147 2148 2149 2150
			break;
		mdelay(1);
	}
	if (i == 1000) {
		v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
		return -EIO;
	}


2151 2152 2153 2154
	/* enable hotplug after 100 ms */
	queue_delayed_work(state->work_queues,
			&state->delayed_work_enable_hotplug, HZ / 10);
	return 0;
2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165
}

/*********** avi info frame CEA-861-E **************/

static void print_avi_infoframe(struct v4l2_subdev *sd)
{
	int i;
	u8 buf[14];
	u8 avi_len;
	u8 avi_ver;

2166
	if (!is_hdmi(sd)) {
2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203
		v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
		return;
	}
	if (!(io_read(sd, 0x60) & 0x01)) {
		v4l2_info(sd, "AVI infoframe not received\n");
		return;
	}

	if (io_read(sd, 0x83) & 0x01) {
		v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n");
		io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
		if (io_read(sd, 0x83) & 0x01) {
			v4l2_info(sd, "AVI infoframe checksum error still present\n");
			io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
		}
	}

	avi_len = infoframe_read(sd, 0xe2);
	avi_ver = infoframe_read(sd, 0xe1);
	v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
			avi_ver, avi_len);

	if (avi_ver != 0x02)
		return;

	for (i = 0; i < 14; i++)
		buf[i] = infoframe_read(sd, i);

	v4l2_info(sd,
		"\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
		buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
		buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
}

static int adv7604_log_status(struct v4l2_subdev *sd)
{
	struct adv7604_state *state = to_state(sd);
2204
	const struct adv7604_chip_info *info = state->info;
2205 2206 2207
	struct v4l2_dv_timings timings;
	struct stdi_readback stdi;
	u8 reg_io_0x02 = io_read(sd, 0x02);
2208 2209
	u8 edid_enabled;
	u8 cable_det;
2210

2211
	static const char * const csc_coeff_sel_rb[16] = {
2212 2213 2214 2215 2216
		"bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
		"reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
		"reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
		"reserved", "reserved", "reserved", "reserved", "manual"
	};
2217
	static const char * const input_color_space_txt[16] = {
2218 2219
		"RGB limited range (16-235)", "RGB full range (0-255)",
		"YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2220
		"xvYCC Bt.601", "xvYCC Bt.709",
2221 2222 2223 2224
		"YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
		"invalid", "invalid", "invalid", "invalid", "invalid",
		"invalid", "invalid", "automatic"
	};
2225
	static const char * const rgb_quantization_range_txt[] = {
2226 2227 2228 2229
		"Automatic",
		"RGB limited range (16-235)",
		"RGB full range (0-255)",
	};
2230
	static const char * const deep_color_mode_txt[4] = {
2231 2232 2233 2234 2235
		"8-bits per channel",
		"10-bits per channel",
		"12-bits per channel",
		"16-bits per channel (not supported)"
	};
2236 2237 2238

	v4l2_info(sd, "-----Chip status-----\n");
	v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2239
	edid_enabled = rep_read(sd, info->edid_status_reg);
2240
	v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
2241 2242 2243 2244
			((edid_enabled & 0x01) ? "Yes" : "No"),
			((edid_enabled & 0x02) ? "Yes" : "No"),
			((edid_enabled & 0x04) ? "Yes" : "No"),
			((edid_enabled & 0x08) ? "Yes" : "No"));
2245 2246 2247 2248
	v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
			"enabled" : "disabled");

	v4l2_info(sd, "-----Signal status-----\n");
2249
	cable_det = info->read_cable_det(sd);
2250
	v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
2251 2252
			((cable_det & 0x01) ? "Yes" : "No"),
			((cable_det & 0x02) ? "Yes" : "No"),
2253
			((cable_det & 0x04) ? "Yes" : "No"),
2254
			((cable_det & 0x08) ? "Yes" : "No"));
2255 2256 2257 2258 2259 2260 2261 2262 2263
	v4l2_info(sd, "TMDS signal detected: %s\n",
			no_signal_tmds(sd) ? "false" : "true");
	v4l2_info(sd, "TMDS signal locked: %s\n",
			no_lock_tmds(sd) ? "false" : "true");
	v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
	v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
	v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
	v4l2_info(sd, "CP free run: %s\n",
			(!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
2264 2265 2266
	v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
			io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
			(io_read(sd, 0x01) & 0x70) >> 4);
2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278

	v4l2_info(sd, "-----Video Timings-----\n");
	if (read_stdi(sd, &stdi))
		v4l2_info(sd, "STDI: not locked\n");
	else
		v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
				stdi.lcf, stdi.bl, stdi.lcvs,
				stdi.interlaced ? "interlaced" : "progressive",
				stdi.hs_pol, stdi.vs_pol);
	if (adv7604_query_dv_timings(sd, &timings))
		v4l2_info(sd, "No video detected\n");
	else
2279 2280 2281 2282
		v4l2_print_dv_timings(sd->name, "Detected format: ",
				      &timings, true);
	v4l2_print_dv_timings(sd->name, "Configured format: ",
			      &state->timings, true);
2283

2284 2285 2286
	if (no_signal(sd))
		return 0;

2287 2288 2289 2290 2291 2292 2293 2294 2295
	v4l2_info(sd, "-----Color space-----\n");
	v4l2_info(sd, "RGB quantization range ctrl: %s\n",
			rgb_quantization_range_txt[state->rgb_quantization_range]);
	v4l2_info(sd, "Input color space: %s\n",
			input_color_space_txt[reg_io_0x02 >> 4]);
	v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
			(reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
			(reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
			((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
2296
				"enabled" : "disabled");
2297 2298 2299
	v4l2_info(sd, "Color space conversion: %s\n",
			csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]);

2300
	if (!is_digital_input(sd))
2301 2302 2303
		return 0;

	v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2304 2305 2306 2307
	v4l2_info(sd, "Digital video port selected: %c\n",
			(hdmi_read(sd, 0x00) & 0x03) + 'A');
	v4l2_info(sd, "HDCP encrypted content: %s\n",
			(hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333
	v4l2_info(sd, "HDCP keys read: %s%s\n",
			(hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
			(hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
	if (!is_hdmi(sd)) {
		bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
		bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
		bool audio_mute = io_read(sd, 0x65) & 0x40;

		v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
				audio_pll_locked ? "locked" : "not locked",
				audio_sample_packet_detect ? "detected" : "not detected",
				audio_mute ? "muted" : "enabled");
		if (audio_pll_locked && audio_sample_packet_detect) {
			v4l2_info(sd, "Audio format: %s\n",
					(hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
		}
		v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
				(hdmi_read(sd, 0x5c) << 8) +
				(hdmi_read(sd, 0x5d) & 0xf0));
		v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
				(hdmi_read(sd, 0x5e) << 8) +
				hdmi_read(sd, 0x5f));
		v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");

		v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);

2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363
		print_avi_infoframe(sd);
	}

	return 0;
}

/* ----------------------------------------------------------------------- */

static const struct v4l2_ctrl_ops adv7604_ctrl_ops = {
	.s_ctrl = adv7604_s_ctrl,
};

static const struct v4l2_subdev_core_ops adv7604_core_ops = {
	.log_status = adv7604_log_status,
	.interrupt_service_routine = adv7604_isr,
#ifdef CONFIG_VIDEO_ADV_DEBUG
	.g_register = adv7604_g_register,
	.s_register = adv7604_s_register,
#endif
};

static const struct v4l2_subdev_video_ops adv7604_video_ops = {
	.s_routing = adv7604_s_routing,
	.g_input_status = adv7604_g_input_status,
	.s_dv_timings = adv7604_s_dv_timings,
	.g_dv_timings = adv7604_g_dv_timings,
	.query_dv_timings = adv7604_query_dv_timings,
};

static const struct v4l2_subdev_pad_ops adv7604_pad_ops = {
2364 2365 2366
	.enum_mbus_code = adv7604_enum_mbus_code,
	.get_fmt = adv7604_get_format,
	.set_fmt = adv7604_set_format,
2367 2368
	.get_edid = adv7604_get_edid,
	.set_edid = adv7604_set_edid,
2369
	.dv_timings_cap = adv7604_dv_timings_cap,
2370
	.enum_dv_timings = adv7604_enum_dv_timings,
2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418
};

static const struct v4l2_subdev_ops adv7604_ops = {
	.core = &adv7604_core_ops,
	.video = &adv7604_video_ops,
	.pad = &adv7604_pad_ops,
};

/* -------------------------- custom ctrls ---------------------------------- */

static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
	.ops = &adv7604_ctrl_ops,
	.id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
	.name = "Analog Sampling Phase",
	.type = V4L2_CTRL_TYPE_INTEGER,
	.min = 0,
	.max = 0x1f,
	.step = 1,
	.def = 0,
};

static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = {
	.ops = &adv7604_ctrl_ops,
	.id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
	.name = "Free Running Color, Manual",
	.type = V4L2_CTRL_TYPE_BOOLEAN,
	.min = false,
	.max = true,
	.step = 1,
	.def = false,
};

static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = {
	.ops = &adv7604_ctrl_ops,
	.id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
	.name = "Free Running Color",
	.type = V4L2_CTRL_TYPE_INTEGER,
	.min = 0x0,
	.max = 0xffffff,
	.step = 0x1,
	.def = 0x0,
};

/* ----------------------------------------------------------------------- */

static int adv7604_core_init(struct v4l2_subdev *sd)
{
	struct adv7604_state *state = to_state(sd);
2419
	const struct adv7604_chip_info *info = state->info;
2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433
	struct adv7604_platform_data *pdata = &state->pdata;

	hdmi_write(sd, 0x48,
		(pdata->disable_pwrdnb ? 0x80 : 0) |
		(pdata->disable_cable_det_rst ? 0x40 : 0));

	disable_input(sd);

	/* power */
	io_write(sd, 0x0c, 0x42);   /* Power up part and power down VDP */
	io_write(sd, 0x0b, 0x44);   /* Power down ESDP block */
	cp_write(sd, 0xcf, 0x01);   /* Power down macrovision */

	/* video format */
2434
	io_write_clr_set(sd, 0x02, 0x0f,
2435 2436 2437
			pdata->alt_gamma << 3 |
			pdata->op_656_range << 2 |
			pdata->alt_data_sat << 0);
2438
	io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
2439 2440 2441
			pdata->insert_av_codes << 2 |
			pdata->replicate_av_codes << 1);
	adv7604_setup_format(state);
2442 2443

	cp_write(sd, 0x69, 0x30);   /* Enable CP CSC */
2444 2445 2446

	/* VS, HS polarities */
	io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 | pdata->inv_hs_pol << 1);
2447 2448 2449 2450 2451 2452

	/* Adjust drive strength */
	io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
				pdata->dr_str_clk << 2 |
				pdata->dr_str_sync);

2453 2454 2455
	cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
	cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
	cp_write(sd, 0xf9, 0x23); /*  STDI ch. 1 - LCVS change threshold -
H
Hans Verkuil 已提交
2456
				      ADI recommended setting [REF_01, c. 2.3.3] */
2457
	cp_write(sd, 0x45, 0x23); /*  STDI ch. 2 - LCVS change threshold -
H
Hans Verkuil 已提交
2458
				      ADI recommended setting [REF_01, c. 2.3.3] */
2459 2460 2461
	cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
				     for digital formats */

2462
	/* HDMI audio */
2463 2464 2465
	hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
	hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */
	hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
2466

2467 2468 2469
	/* TODO from platform data */
	afe_write(sd, 0xb5, 0x01);  /* Setting MCLK to 256Fs */

2470 2471
	if (adv7604_has_afe(state)) {
		afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2472
		io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
2473
	}
2474 2475

	/* interrupts */
2476
	io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */
2477
	io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
2478 2479 2480
	io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
	io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */
	info->setup_irqs(sd);
2481 2482 2483 2484

	return v4l2_ctrl_handler_setup(sd->ctrl_handler);
}

2485 2486 2487 2488 2489 2490 2491 2492 2493 2494
static void adv7604_setup_irqs(struct v4l2_subdev *sd)
{
	io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
}

static void adv7611_setup_irqs(struct v4l2_subdev *sd)
{
	io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
}

2495 2496
static void adv7604_unregister_clients(struct adv7604_state *state)
{
2497 2498 2499 2500 2501 2502
	unsigned int i;

	for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) {
		if (state->i2c_clients[i])
			i2c_unregister_device(state->i2c_clients[i]);
	}
2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514
}

static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd,
							u8 addr, u8 io_reg)
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);

	if (addr)
		io_write(sd, io_reg, addr << 1);
	return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
}

2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582
static const struct adv7604_reg_seq adv7604_recommended_settings_afe[] = {
	/* reset ADI recommended settings for HDMI: */
	/* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */

	/* set ADI recommended settings for digitizer */
	/* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
	{ ADV7604_REG(ADV7604_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
	{ ADV7604_REG(ADV7604_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
	{ ADV7604_REG(ADV7604_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
	{ ADV7604_REG(ADV7604_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
	{ ADV7604_REG(ADV7604_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */

	{ ADV7604_REG_SEQ_TERM, 0 },
};

static const struct adv7604_reg_seq adv7604_recommended_settings_hdmi[] = {
	/* set ADI recommended settings for HDMI: */
	/* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */

	/* reset ADI recommended settings for digitizer */
	/* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
	{ ADV7604_REG(ADV7604_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
	{ ADV7604_REG(ADV7604_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */

	{ ADV7604_REG_SEQ_TERM, 0 },
};

static const struct adv7604_reg_seq adv7611_recommended_settings_hdmi[] = {
	{ ADV7604_REG(ADV7604_PAGE_CP, 0x6c), 0x00 },
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x6f), 0x0c },
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x87), 0x70 },
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0xda },
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x01 },
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x03), 0x98 },
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x4c), 0x44 },
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x04 },
	{ ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x1e },

	{ ADV7604_REG_SEQ_TERM, 0 },
};

static const struct adv7604_chip_info adv7604_chip_info[] = {
	[ADV7604] = {
		.type = ADV7604,
		.has_afe = true,
2583
		.max_port = ADV7604_PAD_VGA_COMP,
2584 2585 2586 2587 2588 2589 2590
		.num_dv_ports = 4,
		.edid_enable_reg = 0x77,
		.edid_status_reg = 0x7d,
		.lcf_reg = 0xb3,
		.tdms_lock_mask = 0xe0,
		.cable_det_mask = 0x1e,
		.fmt_change_digital_mask = 0xc1,
2591 2592
		.formats = adv7604_formats,
		.nformats = ARRAY_SIZE(adv7604_formats),
2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615
		.set_termination = adv7604_set_termination,
		.setup_irqs = adv7604_setup_irqs,
		.read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock,
		.read_cable_det = adv7604_read_cable_det,
		.recommended_settings = {
		    [0] = adv7604_recommended_settings_afe,
		    [1] = adv7604_recommended_settings_hdmi,
		},
		.num_recommended_settings = {
		    [0] = ARRAY_SIZE(adv7604_recommended_settings_afe),
		    [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
		},
		.page_mask = BIT(ADV7604_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) |
			BIT(ADV7604_PAGE_CEC) | BIT(ADV7604_PAGE_INFOFRAME) |
			BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) |
			BIT(ADV7604_PAGE_AFE) | BIT(ADV7604_PAGE_REP) |
			BIT(ADV7604_PAGE_EDID) | BIT(ADV7604_PAGE_HDMI) |
			BIT(ADV7604_PAGE_TEST) | BIT(ADV7604_PAGE_CP) |
			BIT(ADV7604_PAGE_VDP),
	},
	[ADV7611] = {
		.type = ADV7611,
		.has_afe = false,
2616
		.max_port = ADV7604_PAD_HDMI_PORT_A,
2617 2618 2619 2620 2621 2622 2623
		.num_dv_ports = 1,
		.edid_enable_reg = 0x74,
		.edid_status_reg = 0x76,
		.lcf_reg = 0xa3,
		.tdms_lock_mask = 0x43,
		.cable_det_mask = 0x01,
		.fmt_change_digital_mask = 0x03,
2624 2625
		.formats = adv7611_formats,
		.nformats = ARRAY_SIZE(adv7611_formats),
2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642
		.set_termination = adv7611_set_termination,
		.setup_irqs = adv7611_setup_irqs,
		.read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
		.read_cable_det = adv7611_read_cable_det,
		.recommended_settings = {
		    [1] = adv7611_recommended_settings_hdmi,
		},
		.num_recommended_settings = {
		    [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
		},
		.page_mask = BIT(ADV7604_PAGE_IO) | BIT(ADV7604_PAGE_CEC) |
			BIT(ADV7604_PAGE_INFOFRAME) | BIT(ADV7604_PAGE_AFE) |
			BIT(ADV7604_PAGE_REP) |  BIT(ADV7604_PAGE_EDID) |
			BIT(ADV7604_PAGE_HDMI) | BIT(ADV7604_PAGE_CP),
	},
};

2643 2644 2645
static int adv7604_probe(struct i2c_client *client,
			 const struct i2c_device_id *id)
{
2646 2647
	static const struct v4l2_dv_timings cea640x480 =
		V4L2_DV_BT_CEA_640X480P59_94;
2648 2649 2650 2651
	struct adv7604_state *state;
	struct adv7604_platform_data *pdata = client->dev.platform_data;
	struct v4l2_ctrl_handler *hdl;
	struct v4l2_subdev *sd;
2652
	unsigned int i;
2653
	u16 val;
2654 2655 2656 2657 2658 2659 2660 2661
	int err;

	/* Check if the adapter supports the needed features */
	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
		return -EIO;
	v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n",
			client->addr << 1);

2662
	state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
2663 2664 2665 2666 2667
	if (!state) {
		v4l_err(client, "Could not allocate adv7604_state memory!\n");
		return -ENOMEM;
	}

2668
	state->info = &adv7604_chip_info[id->driver_data];
2669
	state->i2c_clients[ADV7604_PAGE_IO] = client;
2670

2671 2672
	/* initialize variables */
	state->restart_stdi_once = true;
2673
	state->selected_input = ~0;
2674

2675 2676 2677
	/* platform data */
	if (!pdata) {
		v4l_err(client, "No platform data!\n");
2678
		return -ENODEV;
2679
	}
2680 2681
	state->pdata = *pdata;
	state->timings = cea640x480;
2682
	state->format = adv7604_format_info(state, V4L2_MBUS_FMT_YUYV8_2X8);
2683 2684 2685

	sd = &state->sd;
	v4l2_i2c_subdev_init(sd, client, &adv7604_ops);
2686 2687 2688
	snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
		id->name, i2c_adapter_id(client->adapter),
		client->addr);
2689 2690
	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;

2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710
	/*
	 * Verify that the chip is present. On ADV7604 the RD_INFO register only
	 * identifies the revision, while on ADV7611 it identifies the model as
	 * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611.
	 */
	if (state->info->type == ADV7604) {
		val = adv_smbus_read_byte_data_check(client, 0xfb, false);
		if (val != 0x68) {
			v4l2_info(sd, "not an adv7604 on address 0x%x\n",
					client->addr << 1);
			return -ENODEV;
		}
	} else {
		val = (adv_smbus_read_byte_data_check(client, 0xea, false) << 8)
		    | (adv_smbus_read_byte_data_check(client, 0xeb, false) << 0);
		if (val != 0x2051) {
			v4l2_info(sd, "not an adv7611 on address 0x%x\n",
					client->addr << 1);
			return -ENODEV;
		}
2711 2712 2713 2714
	}

	/* control handlers */
	hdl = &state->hdl;
2715
	v4l2_ctrl_handler_init(hdl, adv7604_has_afe(state) ? 9 : 8);
2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727

	v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
			V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
	v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
			V4L2_CID_CONTRAST, 0, 255, 1, 128);
	v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
			V4L2_CID_SATURATION, 0, 255, 1, 128);
	v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
			V4L2_CID_HUE, 0, 128, 1, 0);

	/* private controls */
	state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
2728 2729
			V4L2_CID_DV_RX_POWER_PRESENT, 0,
			(1 << state->info->num_dv_ports) - 1, 0, 0);
2730 2731 2732 2733 2734 2735
	state->rgb_quantization_range_ctrl =
		v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops,
			V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
			0, V4L2_DV_RGB_RANGE_AUTO);

	/* custom controls */
2736 2737 2738
	if (adv7604_has_afe(state))
		state->analog_sampling_phase_ctrl =
			v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
2739 2740 2741 2742 2743 2744 2745 2746 2747 2748
	state->free_run_color_manual_ctrl =
		v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL);
	state->free_run_color_ctrl =
		v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL);

	sd->ctrl_handler = hdl;
	if (hdl->error) {
		err = hdl->error;
		goto err_hdl;
	}
2749 2750
	state->detect_tx_5v_ctrl->is_private = true;
	state->rgb_quantization_range_ctrl->is_private = true;
2751 2752
	if (adv7604_has_afe(state))
		state->analog_sampling_phase_ctrl->is_private = true;
2753 2754 2755
	state->free_run_color_manual_ctrl->is_private = true;
	state->free_run_color_ctrl->is_private = true;

2756 2757 2758 2759 2760
	if (adv7604_s_detect_tx_5v_ctrl(sd)) {
		err = -ENODEV;
		goto err_hdl;
	}

2761 2762 2763
	for (i = 1; i < ADV7604_PAGE_MAX; ++i) {
		if (!(BIT(i) & state->info->page_mask))
			continue;
2764

2765 2766 2767 2768
		state->i2c_clients[i] =
			adv7604_dummy_client(sd, pdata->i2c_addresses[i],
					     0xf2 + i);
		if (state->i2c_clients[i] == NULL) {
2769
			err = -ENOMEM;
2770
			v4l2_err(sd, "failed to create i2c client %u\n", i);
2771 2772 2773
			goto err_i2c;
		}
	}
2774

2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785
	/* work queues */
	state->work_queues = create_singlethread_workqueue(client->name);
	if (!state->work_queues) {
		v4l2_err(sd, "Could not create work queue\n");
		err = -ENOMEM;
		goto err_i2c;
	}

	INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
			adv7604_delayed_work_enable_hotplug);

2786 2787 2788 2789 2790 2791 2792 2793
	state->source_pad = state->info->num_dv_ports
			  + (state->info->has_afe ? 2 : 0);
	for (i = 0; i < state->source_pad; ++i)
		state->pads[i].flags = MEDIA_PAD_FL_SINK;
	state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE;

	err = media_entity_init(&sd->entity, state->source_pad + 1,
				state->pads, 0);
2794 2795 2796 2797 2798 2799 2800 2801
	if (err)
		goto err_work_queues;

	err = adv7604_core_init(sd);
	if (err)
		goto err_entity;
	v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
			client->addr << 1, client->adapter->name);
2802 2803 2804 2805 2806

	err = v4l2_async_register_subdev(sd);
	if (err)
		goto err_entity;

2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829
	return 0;

err_entity:
	media_entity_cleanup(&sd->entity);
err_work_queues:
	cancel_delayed_work(&state->delayed_work_enable_hotplug);
	destroy_workqueue(state->work_queues);
err_i2c:
	adv7604_unregister_clients(state);
err_hdl:
	v4l2_ctrl_handler_free(hdl);
	return err;
}

/* ----------------------------------------------------------------------- */

static int adv7604_remove(struct i2c_client *client)
{
	struct v4l2_subdev *sd = i2c_get_clientdata(client);
	struct adv7604_state *state = to_state(sd);

	cancel_delayed_work(&state->delayed_work_enable_hotplug);
	destroy_workqueue(state->work_queues);
2830
	v4l2_async_unregister_subdev(sd);
2831 2832 2833 2834 2835 2836 2837 2838 2839 2840
	v4l2_device_unregister_subdev(sd);
	media_entity_cleanup(&sd->entity);
	adv7604_unregister_clients(to_state(sd));
	v4l2_ctrl_handler_free(sd->ctrl_handler);
	return 0;
}

/* ----------------------------------------------------------------------- */

static struct i2c_device_id adv7604_id[] = {
2841 2842
	{ "adv7604", ADV7604 },
	{ "adv7611", ADV7611 },
2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857
	{ }
};
MODULE_DEVICE_TABLE(i2c, adv7604_id);

static struct i2c_driver adv7604_driver = {
	.driver = {
		.owner = THIS_MODULE,
		.name = "adv7604",
	},
	.probe = adv7604_probe,
	.remove = adv7604_remove,
	.id_table = adv7604_id,
};

module_i2c_driver(adv7604_driver);