intel_ddi.c 81.7 KB
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/*
 * Copyright © 2012 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eugeni Dodonov <eugeni.dodonov@intel.com>
 *
 */

#include "i915_drv.h"
#include "intel_drv.h"

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struct ddi_buf_trans {
	u32 trans1;	/* balance leg enable, de-emph level */
	u32 trans2;	/* vref sel, vswing */
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	u8 i_boost;	/* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
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};

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static const u8 index_to_dp_signal_levels[] = {
	[0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
	[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
	[2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
	[3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
	[4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
	[5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
	[6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
	[7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
	[8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
	[9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
};

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/* HDMI/DVI modes ignore everything but the last 2 items. So we share
 * them for both DP and FDI transports, allowing those ports to
 * automatically adapt to HDMI connections as well
 */
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static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
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	{ 0x00FFFFFF, 0x0006000E, 0x0 },
	{ 0x00D75FFF, 0x0005000A, 0x0 },
	{ 0x00C30FFF, 0x00040006, 0x0 },
	{ 0x80AAAFFF, 0x000B0000, 0x0 },
	{ 0x00FFFFFF, 0x0005000A, 0x0 },
	{ 0x00D75FFF, 0x000C0004, 0x0 },
	{ 0x80C30FFF, 0x000B0000, 0x0 },
	{ 0x00FFFFFF, 0x00040006, 0x0 },
	{ 0x80D75FFF, 0x000B0000, 0x0 },
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};

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static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
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	{ 0x00FFFFFF, 0x0007000E, 0x0 },
	{ 0x00D75FFF, 0x000F000A, 0x0 },
	{ 0x00C30FFF, 0x00060006, 0x0 },
	{ 0x00AAAFFF, 0x001E0000, 0x0 },
	{ 0x00FFFFFF, 0x000F000A, 0x0 },
	{ 0x00D75FFF, 0x00160004, 0x0 },
	{ 0x00C30FFF, 0x001E0000, 0x0 },
	{ 0x00FFFFFF, 0x00060006, 0x0 },
	{ 0x00D75FFF, 0x001E0000, 0x0 },
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};

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static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
					/* Idx	NT mV d	T mV d	db	*/
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	{ 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:	400	400	0	*/
	{ 0x00E79FFF, 0x000E000C, 0x0 },/* 1:	400	500	2	*/
	{ 0x00D75FFF, 0x0005000A, 0x0 },/* 2:	400	600	3.5	*/
	{ 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:	600	600	0	*/
	{ 0x00E79FFF, 0x001D0007, 0x0 },/* 4:	600	750	2	*/
	{ 0x00D75FFF, 0x000C0004, 0x0 },/* 5:	600	900	3.5	*/
	{ 0x00FFFFFF, 0x00040006, 0x0 },/* 6:	800	800	0	*/
	{ 0x80E79FFF, 0x00030002, 0x0 },/* 7:	800	1000	2	*/
	{ 0x00FFFFFF, 0x00140005, 0x0 },/* 8:	850	850	0	*/
	{ 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:	900	900	0	*/
	{ 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:	950	950	0	*/
	{ 0x80FFFFFF, 0x00030002, 0x0 },/* 11:	1000	1000	0	*/
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};

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static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
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	{ 0x00FFFFFF, 0x00000012, 0x0 },
	{ 0x00EBAFFF, 0x00020011, 0x0 },
	{ 0x00C71FFF, 0x0006000F, 0x0 },
	{ 0x00AAAFFF, 0x000E000A, 0x0 },
	{ 0x00FFFFFF, 0x00020011, 0x0 },
	{ 0x00DB6FFF, 0x0005000F, 0x0 },
	{ 0x00BEEFFF, 0x000A000C, 0x0 },
	{ 0x00FFFFFF, 0x0005000F, 0x0 },
	{ 0x00DB6FFF, 0x000A000C, 0x0 },
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};

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static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
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	{ 0x00FFFFFF, 0x0007000E, 0x0 },
	{ 0x00D75FFF, 0x000E000A, 0x0 },
	{ 0x00BEFFFF, 0x00140006, 0x0 },
	{ 0x80B2CFFF, 0x001B0002, 0x0 },
	{ 0x00FFFFFF, 0x000E000A, 0x0 },
	{ 0x00DB6FFF, 0x00160005, 0x0 },
	{ 0x80C71FFF, 0x001A0002, 0x0 },
	{ 0x00F7DFFF, 0x00180004, 0x0 },
	{ 0x80D75FFF, 0x001B0002, 0x0 },
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};

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static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
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	{ 0x00FFFFFF, 0x0001000E, 0x0 },
	{ 0x00D75FFF, 0x0004000A, 0x0 },
	{ 0x00C30FFF, 0x00070006, 0x0 },
	{ 0x00AAAFFF, 0x000C0000, 0x0 },
	{ 0x00FFFFFF, 0x0004000A, 0x0 },
	{ 0x00D75FFF, 0x00090004, 0x0 },
	{ 0x00C30FFF, 0x000C0000, 0x0 },
	{ 0x00FFFFFF, 0x00070006, 0x0 },
	{ 0x00D75FFF, 0x000C0000, 0x0 },
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};

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static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
					/* Idx	NT mV d	T mV df	db	*/
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	{ 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:	400	400	0	*/
	{ 0x00D75FFF, 0x000E000A, 0x0 },/* 1:	400	600	3.5	*/
	{ 0x00BEFFFF, 0x00140006, 0x0 },/* 2:	400	800	6	*/
	{ 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:	450	450	0	*/
	{ 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:	600	600	0	*/
	{ 0x00D7FFFF, 0x00140006, 0x0 },/* 5:	600	800	2.5	*/
	{ 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:	600	1000	4.5	*/
	{ 0x00FFFFFF, 0x00140006, 0x0 },/* 7:	800	800	0	*/
	{ 0x80E79FFF, 0x001B0002, 0x0 },/* 8:	800	1000	2	*/
	{ 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:	1000	1000	0	*/
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};

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/* Skylake H and S */
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static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
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	{ 0x00002016, 0x000000A0, 0x0 },
	{ 0x00005012, 0x0000009B, 0x0 },
	{ 0x00007011, 0x00000088, 0x0 },
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	{ 0x80009010, 0x000000C0, 0x1 },
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	{ 0x00002016, 0x0000009B, 0x0 },
	{ 0x00005012, 0x00000088, 0x0 },
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	{ 0x80007011, 0x000000C0, 0x1 },
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	{ 0x00002016, 0x000000DF, 0x0 },
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	{ 0x80005012, 0x000000C0, 0x1 },
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};

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/* Skylake U */
static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
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	{ 0x0000201B, 0x000000A2, 0x0 },
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	{ 0x00005012, 0x00000088, 0x0 },
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	{ 0x80007011, 0x000000CD, 0x1 },
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	{ 0x80009010, 0x000000C0, 0x1 },
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	{ 0x0000201B, 0x0000009D, 0x0 },
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	{ 0x80005012, 0x000000C0, 0x1 },
	{ 0x80007011, 0x000000C0, 0x1 },
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	{ 0x00002016, 0x00000088, 0x0 },
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	{ 0x80005012, 0x000000C0, 0x1 },
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};

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/* Skylake Y */
static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
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	{ 0x00000018, 0x000000A2, 0x0 },
	{ 0x00005012, 0x00000088, 0x0 },
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	{ 0x80007011, 0x000000CD, 0x3 },
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	{ 0x80009010, 0x000000C0, 0x3 },
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	{ 0x00000018, 0x0000009D, 0x0 },
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	{ 0x80005012, 0x000000C0, 0x3 },
	{ 0x80007011, 0x000000C0, 0x3 },
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	{ 0x00000018, 0x00000088, 0x0 },
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	{ 0x80005012, 0x000000C0, 0x3 },
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};

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/* Kabylake H and S */
static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
	{ 0x00002016, 0x000000A0, 0x0 },
	{ 0x00005012, 0x0000009B, 0x0 },
	{ 0x00007011, 0x00000088, 0x0 },
	{ 0x80009010, 0x000000C0, 0x1 },
	{ 0x00002016, 0x0000009B, 0x0 },
	{ 0x00005012, 0x00000088, 0x0 },
	{ 0x80007011, 0x000000C0, 0x1 },
	{ 0x00002016, 0x00000097, 0x0 },
	{ 0x80005012, 0x000000C0, 0x1 },
};

/* Kabylake U */
static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
	{ 0x0000201B, 0x000000A1, 0x0 },
	{ 0x00005012, 0x00000088, 0x0 },
	{ 0x80007011, 0x000000CD, 0x3 },
	{ 0x80009010, 0x000000C0, 0x3 },
	{ 0x0000201B, 0x0000009D, 0x0 },
	{ 0x80005012, 0x000000C0, 0x3 },
	{ 0x80007011, 0x000000C0, 0x3 },
	{ 0x00002016, 0x0000004F, 0x0 },
	{ 0x80005012, 0x000000C0, 0x3 },
};

/* Kabylake Y */
static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
	{ 0x00001017, 0x000000A1, 0x0 },
	{ 0x00005012, 0x00000088, 0x0 },
	{ 0x80007011, 0x000000CD, 0x3 },
	{ 0x8000800F, 0x000000C0, 0x3 },
	{ 0x00001017, 0x0000009D, 0x0 },
	{ 0x80005012, 0x000000C0, 0x3 },
	{ 0x80007011, 0x000000C0, 0x3 },
	{ 0x00001017, 0x0000004C, 0x0 },
	{ 0x80005012, 0x000000C0, 0x3 },
};

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/*
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 * Skylake/Kabylake H and S
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 * eDP 1.4 low vswing translation parameters
 */
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static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
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	{ 0x00000018, 0x000000A8, 0x0 },
	{ 0x00004013, 0x000000A9, 0x0 },
	{ 0x00007011, 0x000000A2, 0x0 },
	{ 0x00009010, 0x0000009C, 0x0 },
	{ 0x00000018, 0x000000A9, 0x0 },
	{ 0x00006013, 0x000000A2, 0x0 },
	{ 0x00007011, 0x000000A6, 0x0 },
	{ 0x00000018, 0x000000AB, 0x0 },
	{ 0x00007013, 0x0000009F, 0x0 },
	{ 0x00000018, 0x000000DF, 0x0 },
};

/*
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 * Skylake/Kabylake U
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 * eDP 1.4 low vswing translation parameters
 */
static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
	{ 0x00000018, 0x000000A8, 0x0 },
	{ 0x00004013, 0x000000A9, 0x0 },
	{ 0x00007011, 0x000000A2, 0x0 },
	{ 0x00009010, 0x0000009C, 0x0 },
	{ 0x00000018, 0x000000A9, 0x0 },
	{ 0x00006013, 0x000000A2, 0x0 },
	{ 0x00007011, 0x000000A6, 0x0 },
	{ 0x00002016, 0x000000AB, 0x0 },
	{ 0x00005013, 0x0000009F, 0x0 },
	{ 0x00000018, 0x000000DF, 0x0 },
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};

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/*
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 * Skylake/Kabylake Y
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 * eDP 1.4 low vswing translation parameters
 */
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static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
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	{ 0x00000018, 0x000000A8, 0x0 },
	{ 0x00004013, 0x000000AB, 0x0 },
	{ 0x00007011, 0x000000A4, 0x0 },
	{ 0x00009010, 0x000000DF, 0x0 },
	{ 0x00000018, 0x000000AA, 0x0 },
	{ 0x00006013, 0x000000A4, 0x0 },
	{ 0x00007011, 0x0000009D, 0x0 },
	{ 0x00000018, 0x000000A0, 0x0 },
	{ 0x00006012, 0x000000DF, 0x0 },
	{ 0x00000018, 0x0000008A, 0x0 },
};
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/* Skylake/Kabylake U, H and S */
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static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
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	{ 0x00000018, 0x000000AC, 0x0 },
	{ 0x00005012, 0x0000009D, 0x0 },
	{ 0x00007011, 0x00000088, 0x0 },
	{ 0x00000018, 0x000000A1, 0x0 },
	{ 0x00000018, 0x00000098, 0x0 },
	{ 0x00004013, 0x00000088, 0x0 },
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	{ 0x80006012, 0x000000CD, 0x1 },
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	{ 0x00000018, 0x000000DF, 0x0 },
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	{ 0x80003015, 0x000000CD, 0x1 },	/* Default */
	{ 0x80003015, 0x000000C0, 0x1 },
	{ 0x80000018, 0x000000C0, 0x1 },
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};

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/* Skylake/Kabylake Y */
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static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
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	{ 0x00000018, 0x000000A1, 0x0 },
	{ 0x00005012, 0x000000DF, 0x0 },
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	{ 0x80007011, 0x000000CB, 0x3 },
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	{ 0x00000018, 0x000000A4, 0x0 },
	{ 0x00000018, 0x0000009D, 0x0 },
	{ 0x00004013, 0x00000080, 0x0 },
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	{ 0x80006013, 0x000000C0, 0x3 },
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	{ 0x00000018, 0x0000008A, 0x0 },
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	{ 0x80003015, 0x000000C0, 0x3 },	/* Default */
	{ 0x80003015, 0x000000C0, 0x3 },
	{ 0x80000018, 0x000000C0, 0x3 },
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};

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struct bxt_ddi_buf_trans {
	u32 margin;	/* swing value */
	u32 scale;	/* scale value */
	u32 enable;	/* scale enable */
	u32 deemphasis;
	bool default_index; /* true if the entry represents default value */
};

static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
					/* Idx	NT mV diff	db  */
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	{ 52,  0x9A, 0, 128, true  },	/* 0:	400		0   */
	{ 78,  0x9A, 0, 85,  false },	/* 1:	400		3.5 */
	{ 104, 0x9A, 0, 64,  false },	/* 2:	400		6   */
	{ 154, 0x9A, 0, 43,  false },	/* 3:	400		9.5 */
	{ 77,  0x9A, 0, 128, false },	/* 4:	600		0   */
	{ 116, 0x9A, 0, 85,  false },	/* 5:	600		3.5 */
	{ 154, 0x9A, 0, 64,  false },	/* 6:	600		6   */
	{ 102, 0x9A, 0, 128, false },	/* 7:	800		0   */
	{ 154, 0x9A, 0, 85,  false },	/* 8:	800		3.5 */
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	{ 154, 0x9A, 1, 128, false },	/* 9:	1200		0   */
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};

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static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
					/* Idx	NT mV diff	db  */
	{ 26, 0, 0, 128, false },	/* 0:	200		0   */
	{ 38, 0, 0, 112, false },	/* 1:	200		1.5 */
	{ 48, 0, 0, 96,  false },	/* 2:	200		4   */
	{ 54, 0, 0, 69,  false },	/* 3:	200		6   */
	{ 32, 0, 0, 128, false },	/* 4:	250		0   */
	{ 48, 0, 0, 104, false },	/* 5:	250		1.5 */
	{ 54, 0, 0, 85,  false },	/* 6:	250		4   */
	{ 43, 0, 0, 128, false },	/* 7:	300		0   */
	{ 54, 0, 0, 101, false },	/* 8:	300		1.5 */
	{ 48, 0, 0, 128, false },	/* 9:	300		0   */
};

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/* BSpec has 2 recommended values - entries 0 and 8.
 * Using the entry with higher vswing.
 */
static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
					/* Idx	NT mV diff	db  */
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	{ 52,  0x9A, 0, 128, false },	/* 0:	400		0   */
	{ 52,  0x9A, 0, 85,  false },	/* 1:	400		3.5 */
	{ 52,  0x9A, 0, 64,  false },	/* 2:	400		6   */
	{ 42,  0x9A, 0, 43,  false },	/* 3:	400		9.5 */
	{ 77,  0x9A, 0, 128, false },	/* 4:	600		0   */
	{ 77,  0x9A, 0, 85,  false },	/* 5:	600		3.5 */
	{ 77,  0x9A, 0, 64,  false },	/* 6:	600		6   */
	{ 102, 0x9A, 0, 128, false },	/* 7:	800		0   */
	{ 102, 0x9A, 0, 85,  false },	/* 8:	800		3.5 */
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	{ 154, 0x9A, 1, 128, true },	/* 9:	1200		0   */
};

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struct cnl_ddi_buf_trans {
	u32 dw2_swing_sel;
	u32 dw7_n_scalar;
	u32 dw4_cursor_coeff;
	u32 dw4_post_cursor_2;
	u32 dw4_post_cursor_1;
};

/* Voltage Swing Programming for VccIO 0.85V for DP */
static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
						/* NT mV Trans mV db    */
	{ 0xA, 0x5D, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
	{ 0xA, 0x6A, 0x38, 0x00, 0x07 },	/* 350   500      3.1   */
	{ 0xB, 0x7A, 0x32, 0x00, 0x0D },	/* 350   700      6.0   */
	{ 0x6, 0x7C, 0x2D, 0x00, 0x12 },	/* 350   900      8.2   */
	{ 0xA, 0x69, 0x3F, 0x00, 0x00 },	/* 500   500      0.0   */
	{ 0xB, 0x7A, 0x36, 0x00, 0x09 },	/* 500   700      2.9   */
	{ 0x6, 0x7C, 0x30, 0x00, 0x0F },	/* 500   900      5.1   */
	{ 0xB, 0x7D, 0x3C, 0x00, 0x03 },	/* 650   725      0.9   */
	{ 0x6, 0x7C, 0x34, 0x00, 0x0B },	/* 600   900      3.5   */
	{ 0x6, 0x7B, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
};

/* Voltage Swing Programming for VccIO 0.85V for HDMI */
static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
						/* NT mV Trans mV db    */
	{ 0xA, 0x60, 0x3F, 0x00, 0x00 },	/* 450   450      0.0   */
	{ 0xB, 0x73, 0x36, 0x00, 0x09 },	/* 450   650      3.2   */
	{ 0x6, 0x7F, 0x31, 0x00, 0x0E },	/* 450   850      5.5   */
	{ 0xB, 0x73, 0x3F, 0x00, 0x00 },	/* 650   650      0.0   */
	{ 0x6, 0x7F, 0x37, 0x00, 0x08 },	/* 650   850      2.3   */
	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 850   850      0.0   */
	{ 0x6, 0x7F, 0x35, 0x00, 0x0A },	/* 600   850      3.0   */
};

/* Voltage Swing Programming for VccIO 0.85V for eDP */
static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
						/* NT mV Trans mV db    */
	{ 0xA, 0x66, 0x3A, 0x00, 0x05 },	/* 384   500      2.3   */
	{ 0x0, 0x7F, 0x38, 0x00, 0x07 },	/* 153   200      2.3   */
	{ 0x8, 0x7F, 0x38, 0x00, 0x07 },	/* 192   250      2.3   */
	{ 0x1, 0x7F, 0x38, 0x00, 0x07 },	/* 230   300      2.3   */
	{ 0x9, 0x7F, 0x38, 0x00, 0x07 },	/* 269   350      2.3   */
	{ 0xA, 0x66, 0x3C, 0x00, 0x03 },	/* 446   500      1.0   */
	{ 0xB, 0x70, 0x3C, 0x00, 0x03 },	/* 460   600      2.3   */
	{ 0xC, 0x75, 0x3C, 0x00, 0x03 },	/* 537   700      2.3   */
	{ 0x2, 0x7F, 0x3F, 0x00, 0x00 },	/* 400   400      0.0   */
};

/* Voltage Swing Programming for VccIO 0.95V for DP */
static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
						/* NT mV Trans mV db    */
	{ 0xA, 0x5D, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
	{ 0xA, 0x6A, 0x38, 0x00, 0x07 },	/* 350   500      3.1   */
	{ 0xB, 0x7A, 0x32, 0x00, 0x0D },	/* 350   700      6.0   */
	{ 0x6, 0x7C, 0x2D, 0x00, 0x12 },	/* 350   900      8.2   */
	{ 0xA, 0x69, 0x3F, 0x00, 0x00 },	/* 500   500      0.0   */
	{ 0xB, 0x7A, 0x36, 0x00, 0x09 },	/* 500   700      2.9   */
	{ 0x6, 0x7C, 0x30, 0x00, 0x0F },	/* 500   900      5.1   */
	{ 0xB, 0x7D, 0x3C, 0x00, 0x03 },	/* 650   725      0.9   */
	{ 0x6, 0x7C, 0x34, 0x00, 0x0B },	/* 600   900      3.5   */
	{ 0x6, 0x7B, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
};

/* Voltage Swing Programming for VccIO 0.95V for HDMI */
static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
						/* NT mV Trans mV db    */
	{ 0xA, 0x5C, 0x3F, 0x00, 0x00 },	/* 400   400      0.0   */
	{ 0xB, 0x69, 0x37, 0x00, 0x08 },	/* 400   600      3.5   */
	{ 0x5, 0x76, 0x31, 0x00, 0x0E },	/* 400   800      6.0   */
	{ 0xA, 0x5E, 0x3F, 0x00, 0x00 },	/* 450   450      0.0   */
	{ 0xB, 0x69, 0x3F, 0x00, 0x00 },	/* 600   600      0.0   */
	{ 0xB, 0x79, 0x35, 0x00, 0x0A },	/* 600   850      3.0   */
	{ 0x6, 0x7D, 0x32, 0x00, 0x0D },	/* 600   1000     4.4   */
	{ 0x5, 0x76, 0x3F, 0x00, 0x00 },	/* 800   800      0.0   */
	{ 0x6, 0x7D, 0x39, 0x00, 0x06 },	/* 800   1000     1.9   */
	{ 0x6, 0x7F, 0x39, 0x00, 0x06 },	/* 850   1050     1.8   */
	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 1050  1050     0.0   */
};

/* Voltage Swing Programming for VccIO 0.95V for eDP */
static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
						/* NT mV Trans mV db    */
	{ 0xA, 0x61, 0x3A, 0x00, 0x05 },	/* 384   500      2.3   */
	{ 0x0, 0x7F, 0x38, 0x00, 0x07 },	/* 153   200      2.3   */
	{ 0x8, 0x7F, 0x38, 0x00, 0x07 },	/* 192   250      2.3   */
	{ 0x1, 0x7F, 0x38, 0x00, 0x07 },	/* 230   300      2.3   */
	{ 0x9, 0x7F, 0x38, 0x00, 0x07 },	/* 269   350      2.3   */
	{ 0xA, 0x61, 0x3C, 0x00, 0x03 },	/* 446   500      1.0   */
	{ 0xB, 0x68, 0x39, 0x00, 0x06 },	/* 460   600      2.3   */
	{ 0xC, 0x6E, 0x39, 0x00, 0x06 },	/* 537   700      2.3   */
	{ 0x4, 0x7F, 0x3A, 0x00, 0x05 },	/* 460   600      2.3   */
	{ 0x2, 0x7F, 0x3F, 0x00, 0x00 },	/* 400   400      0.0   */
};

/* Voltage Swing Programming for VccIO 1.05V for DP */
static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
						/* NT mV Trans mV db    */
	{ 0xA, 0x58, 0x3F, 0x00, 0x00 },	/* 400   400      0.0   */
	{ 0xB, 0x64, 0x37, 0x00, 0x08 },	/* 400   600      3.5   */
	{ 0x5, 0x70, 0x31, 0x00, 0x0E },	/* 400   800      6.0   */
	{ 0x6, 0x7F, 0x2C, 0x00, 0x13 },	/* 400   1050     8.4   */
	{ 0xB, 0x64, 0x3F, 0x00, 0x00 },	/* 600   600      0.0   */
	{ 0x5, 0x73, 0x35, 0x00, 0x0A },	/* 600   850      3.0   */
	{ 0x6, 0x7F, 0x30, 0x00, 0x0F },	/* 550   1050     5.6   */
	{ 0x5, 0x76, 0x3E, 0x00, 0x01 },	/* 850   900      0.5   */
	{ 0x6, 0x7F, 0x36, 0x00, 0x09 },	/* 750   1050     2.9   */
	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 1050  1050     0.0   */
};

/* Voltage Swing Programming for VccIO 1.05V for HDMI */
static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
						/* NT mV Trans mV db    */
	{ 0xA, 0x58, 0x3F, 0x00, 0x00 },	/* 400   400      0.0   */
	{ 0xB, 0x64, 0x37, 0x00, 0x08 },	/* 400   600      3.5   */
	{ 0x5, 0x70, 0x31, 0x00, 0x0E },	/* 400   800      6.0   */
	{ 0xA, 0x5B, 0x3F, 0x00, 0x00 },	/* 450   450      0.0   */
	{ 0xB, 0x64, 0x3F, 0x00, 0x00 },	/* 600   600      0.0   */
	{ 0x5, 0x73, 0x35, 0x00, 0x0A },	/* 600   850      3.0   */
	{ 0x6, 0x7C, 0x32, 0x00, 0x0D },	/* 600   1000     4.4   */
	{ 0x5, 0x70, 0x3F, 0x00, 0x00 },	/* 800   800      0.0   */
	{ 0x6, 0x7C, 0x39, 0x00, 0x06 },	/* 800   1000     1.9   */
	{ 0x6, 0x7F, 0x39, 0x00, 0x06 },	/* 850   1050     1.8   */
	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 1050  1050     0.0   */
};

/* Voltage Swing Programming for VccIO 1.05V for eDP */
static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
						/* NT mV Trans mV db    */
	{ 0xA, 0x5E, 0x3A, 0x00, 0x05 },	/* 384   500      2.3   */
	{ 0x0, 0x7F, 0x38, 0x00, 0x07 },	/* 153   200      2.3   */
	{ 0x8, 0x7F, 0x38, 0x00, 0x07 },	/* 192   250      2.3   */
	{ 0x1, 0x7F, 0x38, 0x00, 0x07 },	/* 230   300      2.3   */
	{ 0x9, 0x7F, 0x38, 0x00, 0x07 },	/* 269   350      2.3   */
	{ 0xA, 0x5E, 0x3C, 0x00, 0x03 },	/* 446   500      1.0   */
	{ 0xB, 0x64, 0x39, 0x00, 0x06 },	/* 460   600      2.3   */
	{ 0xE, 0x6A, 0x39, 0x00, 0x06 },	/* 537   700      2.3   */
	{ 0x2, 0x7F, 0x3F, 0x00, 0x00 },	/* 400   400      0.0   */
};

496
enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
497
{
498
	switch (encoder->type) {
499
	case INTEL_OUTPUT_DP_MST:
500
		return enc_to_mst(&encoder->base)->primary->port;
501
	case INTEL_OUTPUT_DP:
502 503 504
	case INTEL_OUTPUT_EDP:
	case INTEL_OUTPUT_HDMI:
	case INTEL_OUTPUT_UNKNOWN:
505
		return enc_to_dig_port(&encoder->base)->port;
506
	case INTEL_OUTPUT_ANALOG:
507 508 509 510
		return PORT_E;
	default:
		MISSING_CASE(encoder->type);
		return PORT_A;
511 512 513
	}
}

514 515 516 517 518 519 520 521 522 523 524 525
static const struct ddi_buf_trans *
bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
{
	if (dev_priv->vbt.edp.low_vswing) {
		*n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
		return bdw_ddi_translations_edp;
	} else {
		*n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
		return bdw_ddi_translations_dp;
	}
}

526
static const struct ddi_buf_trans *
527
skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
528
{
529
	if (IS_SKL_ULX(dev_priv)) {
530
		*n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
531
		return skl_y_ddi_translations_dp;
532
	} else if (IS_SKL_ULT(dev_priv)) {
533
		*n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
534
		return skl_u_ddi_translations_dp;
535 536
	} else {
		*n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
537
		return skl_ddi_translations_dp;
538 539 540
	}
}

541 542 543 544 545 546
static const struct ddi_buf_trans *
kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
{
	if (IS_KBL_ULX(dev_priv)) {
		*n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
		return kbl_y_ddi_translations_dp;
547
	} else if (IS_KBL_ULT(dev_priv) || IS_CFL_ULT(dev_priv)) {
548 549 550 551 552 553 554 555
		*n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
		return kbl_u_ddi_translations_dp;
	} else {
		*n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
		return kbl_ddi_translations_dp;
	}
}

556
static const struct ddi_buf_trans *
557
skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
558
{
559
	if (dev_priv->vbt.edp.low_vswing) {
560
		if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
561
			*n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
562
			return skl_y_ddi_translations_edp;
563 564
		} else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv) ||
			   IS_CFL_ULT(dev_priv)) {
565
			*n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
566
			return skl_u_ddi_translations_edp;
567 568
		} else {
			*n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
569
			return skl_ddi_translations_edp;
570 571
		}
	}
572

573
	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
574 575 576
		return kbl_get_buf_trans_dp(dev_priv, n_entries);
	else
		return skl_get_buf_trans_dp(dev_priv, n_entries);
577 578 579
}

static const struct ddi_buf_trans *
580
skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
581
{
582
	if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
583
		*n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
584
		return skl_y_ddi_translations_hdmi;
585 586
	} else {
		*n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
587
		return skl_ddi_translations_hdmi;
588 589 590
	}
}

591 592 593 594 595 596 597 598
static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
{
	int n_hdmi_entries;
	int hdmi_level;
	int hdmi_default_entry;

	hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;

599
	if (IS_GEN9_LP(dev_priv))
600 601
		return hdmi_level;

602
	if (IS_GEN9_BC(dev_priv)) {
603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624
		skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
		hdmi_default_entry = 8;
	} else if (IS_BROADWELL(dev_priv)) {
		n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
		hdmi_default_entry = 7;
	} else if (IS_HASWELL(dev_priv)) {
		n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
		hdmi_default_entry = 6;
	} else {
		WARN(1, "ddi translation table missing\n");
		n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
		hdmi_default_entry = 7;
	}

	/* Choose a good default if VBT is badly populated */
	if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
	    hdmi_level >= n_hdmi_entries)
		hdmi_level = hdmi_default_entry;

	return hdmi_level;
}

625 626 627 628
static const struct ddi_buf_trans *
intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
			   int *n_entries)
{
629
	if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648
		return kbl_get_buf_trans_dp(dev_priv, n_entries);
	} else if (IS_SKYLAKE(dev_priv)) {
		return skl_get_buf_trans_dp(dev_priv, n_entries);
	} else if (IS_BROADWELL(dev_priv)) {
		*n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
		return  bdw_ddi_translations_dp;
	} else if (IS_HASWELL(dev_priv)) {
		*n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
		return hsw_ddi_translations_dp;
	}

	*n_entries = 0;
	return NULL;
}

static const struct ddi_buf_trans *
intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
			    int *n_entries)
{
649
	if (IS_GEN9_BC(dev_priv)) {
650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677
		return skl_get_buf_trans_edp(dev_priv, n_entries);
	} else if (IS_BROADWELL(dev_priv)) {
		return bdw_get_buf_trans_edp(dev_priv, n_entries);
	} else if (IS_HASWELL(dev_priv)) {
		*n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
		return hsw_ddi_translations_dp;
	}

	*n_entries = 0;
	return NULL;
}

static const struct ddi_buf_trans *
intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
			    int *n_entries)
{
	if (IS_BROADWELL(dev_priv)) {
		*n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
		return hsw_ddi_translations_fdi;
	} else if (IS_HASWELL(dev_priv)) {
		*n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
		return hsw_ddi_translations_fdi;
	}

	*n_entries = 0;
	return NULL;
}

678 679
/*
 * Starting with Haswell, DDI port buffers must be programmed with correct
680 681
 * values in advance. This function programs the correct values for
 * DP/eDP/FDI use cases.
682
 */
683
static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
684
{
685
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
686
	u32 iboost_bit = 0;
687
	int i, n_entries;
688
	enum port port = intel_ddi_get_encoder_port(encoder);
689
	const struct ddi_buf_trans *ddi_translations;
690

691
	if (IS_GEN9_LP(dev_priv))
692
		return;
693

694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709
	switch (encoder->type) {
	case INTEL_OUTPUT_EDP:
		ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv,
							       &n_entries);
		break;
	case INTEL_OUTPUT_DP:
		ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv,
							      &n_entries);
		break;
	case INTEL_OUTPUT_ANALOG:
		ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
							       &n_entries);
		break;
	default:
		MISSING_CASE(encoder->type);
		return;
710 711
	}

712
	if (IS_GEN9_BC(dev_priv)) {
713 714 715 716 717 718
		/* If we're boosting the current, set bit 31 of trans1 */
		if (dev_priv->vbt.ddi_port_info[port].dp_boost_level)
			iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;

		if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
			    port != PORT_A && port != PORT_E &&
719 720
			    n_entries > 9))
			n_entries = 9;
721
	}
722

723
	for (i = 0; i < n_entries; i++) {
724 725 726 727
		I915_WRITE(DDI_BUF_TRANS_LO(port, i),
			   ddi_translations[i].trans1 | iboost_bit);
		I915_WRITE(DDI_BUF_TRANS_HI(port, i),
			   ddi_translations[i].trans2);
728
	}
729 730 731 732 733 734 735 736 737 738 739 740 741 742
}

/*
 * Starting with Haswell, DDI port buffers must be programmed with correct
 * values in advance. This function programs the correct values for
 * HDMI/DVI use cases.
 */
static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	u32 iboost_bit = 0;
	int n_hdmi_entries, hdmi_level;
	enum port port = intel_ddi_get_encoder_port(encoder);
	const struct ddi_buf_trans *ddi_translations_hdmi;
743

744
	if (IS_GEN9_LP(dev_priv))
745 746
		return;

747 748
	hdmi_level = intel_ddi_hdmi_level(dev_priv, port);

749
	if (IS_GEN9_BC(dev_priv)) {
750
		ddi_translations_hdmi = skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
751

752
		/* If we're boosting the current, set bit 31 of trans1 */
753
		if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
754 755 756 757 758 759 760 761 762 763 764 765 766
			iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
	} else if (IS_BROADWELL(dev_priv)) {
		ddi_translations_hdmi = bdw_ddi_translations_hdmi;
		n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
	} else if (IS_HASWELL(dev_priv)) {
		ddi_translations_hdmi = hsw_ddi_translations_hdmi;
		n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
	} else {
		WARN(1, "ddi translation table missing\n");
		ddi_translations_hdmi = bdw_ddi_translations_hdmi;
		n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
	}

767
	/* Entry 9 is for HDMI: */
768
	I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
769
		   ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
770
	I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
771
		   ddi_translations_hdmi[hdmi_level].trans2);
772 773
}

774 775 776
static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
				    enum port port)
{
777
	i915_reg_t reg = DDI_BUF_CTL(port);
778 779
	int i;

780
	for (i = 0; i < 16; i++) {
781 782 783 784 785 786
		udelay(1);
		if (I915_READ(reg) & DDI_BUF_IS_IDLE)
			return;
	}
	DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
}
787

788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808
static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll *pll)
{
	switch (pll->id) {
	case DPLL_ID_WRPLL1:
		return PORT_CLK_SEL_WRPLL1;
	case DPLL_ID_WRPLL2:
		return PORT_CLK_SEL_WRPLL2;
	case DPLL_ID_SPLL:
		return PORT_CLK_SEL_SPLL;
	case DPLL_ID_LCPLL_810:
		return PORT_CLK_SEL_LCPLL_810;
	case DPLL_ID_LCPLL_1350:
		return PORT_CLK_SEL_LCPLL_1350;
	case DPLL_ID_LCPLL_2700:
		return PORT_CLK_SEL_LCPLL_2700;
	default:
		MISSING_CASE(pll->id);
		return PORT_CLK_SEL_NONE;
	}
}

809 810 811 812 813 814 815 816 817
/* Starting with Haswell, different DDI ports can work in FDI mode for
 * connection to the PCH-located connectors. For this, it is necessary to train
 * both the DDI port and PCH receiver for the desired DDI buffer settings.
 *
 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
 * please note that when FDI mode is active on DDI E, it shares 2 lines with
 * DDI A (which is used for eDP)
 */

818 819
void hsw_fdi_link_train(struct intel_crtc *crtc,
			const struct intel_crtc_state *crtc_state)
820
{
821
	struct drm_device *dev = crtc->base.dev;
822
	struct drm_i915_private *dev_priv = to_i915(dev);
823
	struct intel_encoder *encoder;
824
	u32 temp, i, rx_ctl_val, ddi_pll_sel;
825

826
	for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
827
		WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
828
		intel_prepare_dp_ddi_buffers(encoder);
829 830
	}

831 832 833 834
	/* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
	 * mode set "sequence for CRT port" document:
	 * - TP1 to TP2 time with the default value
	 * - FDI delay to 90h
835 836
	 *
	 * WaFDIAutoLinkSetTimingOverrride:hsw
837
	 */
838
	I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
839 840 841 842
				  FDI_RX_PWRDN_LANE0_VAL(2) |
				  FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);

	/* Enable the PCH Receiver FDI PLL */
843
	rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
844
		     FDI_RX_PLL_ENABLE |
845
		     FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
846 847
	I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
	POSTING_READ(FDI_RX_CTL(PIPE_A));
848 849 850 851
	udelay(220);

	/* Switch from Rawclk to PCDclk */
	rx_ctl_val |= FDI_PCDCLK;
852
	I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
853 854

	/* Configure Port Clock Select */
855
	ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
856 857
	I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
	WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
858 859 860

	/* Start the training iterating through available voltages and emphasis,
	 * testing each value twice. */
861
	for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
862 863 864 865 866 867 868
		/* Configure DP_TP_CTL with auto-training */
		I915_WRITE(DP_TP_CTL(PORT_E),
					DP_TP_CTL_FDI_AUTOTRAIN |
					DP_TP_CTL_ENHANCED_FRAME_ENABLE |
					DP_TP_CTL_LINK_TRAIN_PAT1 |
					DP_TP_CTL_ENABLE);

869 870 871 872
		/* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
		 * DDI E does not support port reversal, the functionality is
		 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
		 * port reversal bit */
873
		I915_WRITE(DDI_BUF_CTL(PORT_E),
874
			   DDI_BUF_CTL_ENABLE |
875
			   ((crtc_state->fdi_lanes - 1) << 1) |
876
			   DDI_BUF_TRANS_SELECT(i / 2));
877
		POSTING_READ(DDI_BUF_CTL(PORT_E));
878 879 880

		udelay(600);

881
		/* Program PCH FDI Receiver TU */
882
		I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
883 884 885

		/* Enable PCH FDI Receiver with auto-training */
		rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
886 887
		I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
		POSTING_READ(FDI_RX_CTL(PIPE_A));
888 889 890 891 892

		/* Wait for FDI receiver lane calibration */
		udelay(30);

		/* Unset FDI_RX_MISC pwrdn lanes */
893
		temp = I915_READ(FDI_RX_MISC(PIPE_A));
894
		temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
895 896
		I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
		POSTING_READ(FDI_RX_MISC(PIPE_A));
897 898 899

		/* Wait for FDI auto training time */
		udelay(5);
900 901 902

		temp = I915_READ(DP_TP_STATUS(PORT_E));
		if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
903
			DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
904 905
			break;
		}
906

907 908 909 910 911 912 913
		/*
		 * Leave things enabled even if we failed to train FDI.
		 * Results in less fireworks from the state checker.
		 */
		if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
			DRM_ERROR("FDI link training failed!\n");
			break;
914
		}
915

916 917 918 919
		rx_ctl_val &= ~FDI_RX_ENABLE;
		I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
		POSTING_READ(FDI_RX_CTL(PIPE_A));

920 921 922 923 924
		temp = I915_READ(DDI_BUF_CTL(PORT_E));
		temp &= ~DDI_BUF_CTL_ENABLE;
		I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
		POSTING_READ(DDI_BUF_CTL(PORT_E));

925
		/* Disable DP_TP_CTL and FDI_RX_CTL and retry */
926 927 928 929 930 931 932
		temp = I915_READ(DP_TP_CTL(PORT_E));
		temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
		temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
		I915_WRITE(DP_TP_CTL(PORT_E), temp);
		POSTING_READ(DP_TP_CTL(PORT_E));

		intel_wait_ddi_buf_idle(dev_priv, PORT_E);
933 934

		/* Reset FDI_RX_MISC pwrdn lanes */
935
		temp = I915_READ(FDI_RX_MISC(PIPE_A));
936 937
		temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
		temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
938 939
		I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
		POSTING_READ(FDI_RX_MISC(PIPE_A));
940 941
	}

942 943 944 945 946 947
	/* Enable normal pixel sending for FDI */
	I915_WRITE(DP_TP_CTL(PORT_E),
		   DP_TP_CTL_FDI_AUTOTRAIN |
		   DP_TP_CTL_LINK_TRAIN_NORMAL |
		   DP_TP_CTL_ENHANCED_FRAME_ENABLE |
		   DP_TP_CTL_ENABLE);
948
}
949

950
static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
951 952 953 954 955 956
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct intel_digital_port *intel_dig_port =
		enc_to_dig_port(&encoder->base);

	intel_dp->DP = intel_dig_port->saved_port_bits |
957
		DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
958
	intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
959 960
}

961
static struct intel_encoder *
962
intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
963
{
964
	struct drm_device *dev = crtc->base.dev;
965
	struct intel_encoder *encoder, *ret = NULL;
966 967
	int num_encoders = 0;

968 969
	for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
		ret = encoder;
970 971 972 973
		num_encoders++;
	}

	if (num_encoders != 1)
974
		WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
975
		     pipe_name(crtc->pipe));
976 977 978 979 980

	BUG_ON(ret == NULL);
	return ret;
}

981 982
/* Finds the only possible encoder associated with the given CRTC. */
struct intel_encoder *
983
intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
984
{
985 986 987
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
	struct intel_encoder *ret = NULL;
	struct drm_atomic_state *state;
988 989
	struct drm_connector *connector;
	struct drm_connector_state *connector_state;
990
	int num_encoders = 0;
991
	int i;
992

993 994
	state = crtc_state->base.state;

995
	for_each_new_connector_in_state(state, connector, connector_state, i) {
996
		if (connector_state->crtc != crtc_state->base.crtc)
997 998
			continue;

999
		ret = to_intel_encoder(connector_state->best_encoder);
1000
		num_encoders++;
1001 1002 1003 1004 1005 1006 1007 1008 1009
	}

	WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
	     pipe_name(crtc->pipe));

	BUG_ON(ret == NULL);
	return ret;
}

1010 1011
#define LC_FREQ 2700

1012 1013
static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
				   i915_reg_t reg)
1014 1015 1016 1017 1018 1019
{
	int refclk = LC_FREQ;
	int n, p, r;
	u32 wrpll;

	wrpll = I915_READ(reg);
1020 1021 1022
	switch (wrpll & WRPLL_PLL_REF_MASK) {
	case WRPLL_PLL_SSC:
	case WRPLL_PLL_NON_SSC:
1023 1024 1025 1026 1027 1028 1029
		/*
		 * We could calculate spread here, but our checking
		 * code only cares about 5% accuracy, and spread is a max of
		 * 0.5% downspread.
		 */
		refclk = 135;
		break;
1030
	case WRPLL_PLL_LCPLL:
1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041
		refclk = LC_FREQ;
		break;
	default:
		WARN(1, "bad wrpll refclk\n");
		return 0;
	}

	r = wrpll & WRPLL_DIVIDER_REF_MASK;
	p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
	n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;

1042 1043
	/* Convert to KHz, p & r have a fixed point portion */
	return (refclk * n * 100) / (p * r);
1044 1045
}

1046 1047 1048
static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
			       uint32_t dpll)
{
1049
	i915_reg_t cfgcr1_reg, cfgcr2_reg;
1050 1051 1052
	uint32_t cfgcr1_val, cfgcr2_val;
	uint32_t p0, p1, p2, dco_freq;

1053 1054
	cfgcr1_reg = DPLL_CFGCR1(dpll);
	cfgcr2_reg = DPLL_CFGCR2(dpll);
1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105

	cfgcr1_val = I915_READ(cfgcr1_reg);
	cfgcr2_val = I915_READ(cfgcr2_reg);

	p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
	p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;

	if (cfgcr2_val &  DPLL_CFGCR2_QDIV_MODE(1))
		p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
	else
		p1 = 1;


	switch (p0) {
	case DPLL_CFGCR2_PDIV_1:
		p0 = 1;
		break;
	case DPLL_CFGCR2_PDIV_2:
		p0 = 2;
		break;
	case DPLL_CFGCR2_PDIV_3:
		p0 = 3;
		break;
	case DPLL_CFGCR2_PDIV_7:
		p0 = 7;
		break;
	}

	switch (p2) {
	case DPLL_CFGCR2_KDIV_5:
		p2 = 5;
		break;
	case DPLL_CFGCR2_KDIV_2:
		p2 = 2;
		break;
	case DPLL_CFGCR2_KDIV_3:
		p2 = 3;
		break;
	case DPLL_CFGCR2_KDIV_1:
		p2 = 1;
		break;
	}

	dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;

	dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
		1000) / 0x8000;

	return dco_freq / (p0 * p1 * p2 * 5);
}

1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161
static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
			       uint32_t pll_id)
{
	uint32_t cfgcr0, cfgcr1;
	uint32_t p0, p1, p2, dco_freq, ref_clock;

	cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
	cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));

	p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
	p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;

	if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
		p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
			DPLL_CFGCR1_QDIV_RATIO_SHIFT;
	else
		p1 = 1;


	switch (p0) {
	case DPLL_CFGCR1_PDIV_2:
		p0 = 2;
		break;
	case DPLL_CFGCR1_PDIV_3:
		p0 = 3;
		break;
	case DPLL_CFGCR1_PDIV_5:
		p0 = 5;
		break;
	case DPLL_CFGCR1_PDIV_7:
		p0 = 7;
		break;
	}

	switch (p2) {
	case DPLL_CFGCR1_KDIV_1:
		p2 = 1;
		break;
	case DPLL_CFGCR1_KDIV_2:
		p2 = 2;
		break;
	case DPLL_CFGCR1_KDIV_4:
		p2 = 4;
		break;
	}

	ref_clock = dev_priv->cdclk.hw.ref;

	dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;

	dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
		      DPLL_CFGCR0_DCO_FRAC_SHIFT) * ref_clock) / 0x8000;

	return dco_freq / (p0 * p1 * p2 * 5);
}

1162 1163 1164 1165 1166 1167 1168
static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
{
	int dotclock;

	if (pipe_config->has_pch_encoder)
		dotclock = intel_dotclock_calculate(pipe_config->port_clock,
						    &pipe_config->fdi_m_n);
1169
	else if (intel_crtc_has_dp_encoder(pipe_config))
1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181
		dotclock = intel_dotclock_calculate(pipe_config->port_clock,
						    &pipe_config->dp_m_n);
	else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
		dotclock = pipe_config->port_clock * 2 / 3;
	else
		dotclock = pipe_config->port_clock;

	if (pipe_config->pixel_multiplier)
		dotclock /= pipe_config->pixel_multiplier;

	pipe_config->base.adjusted_mode.crtc_clock = dotclock;
}
1182

1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235
static void cnl_ddi_clock_get(struct intel_encoder *encoder,
			      struct intel_crtc_state *pipe_config)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	int link_clock = 0;
	uint32_t cfgcr0, pll_id;

	pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);

	cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));

	if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {
		link_clock = cnl_calc_wrpll_link(dev_priv, pll_id);
	} else {
		link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;

		switch (link_clock) {
		case DPLL_CFGCR0_LINK_RATE_810:
			link_clock = 81000;
			break;
		case DPLL_CFGCR0_LINK_RATE_1080:
			link_clock = 108000;
			break;
		case DPLL_CFGCR0_LINK_RATE_1350:
			link_clock = 135000;
			break;
		case DPLL_CFGCR0_LINK_RATE_1620:
			link_clock = 162000;
			break;
		case DPLL_CFGCR0_LINK_RATE_2160:
			link_clock = 216000;
			break;
		case DPLL_CFGCR0_LINK_RATE_2700:
			link_clock = 270000;
			break;
		case DPLL_CFGCR0_LINK_RATE_3240:
			link_clock = 324000;
			break;
		case DPLL_CFGCR0_LINK_RATE_4050:
			link_clock = 405000;
			break;
		default:
			WARN(1, "Unsupported link rate\n");
			break;
		}
		link_clock *= 2;
	}

	pipe_config->port_clock = link_clock;

	ddi_dotclock_get(pipe_config);
}

1236
static void skl_ddi_clock_get(struct intel_encoder *encoder,
1237
				struct intel_crtc_state *pipe_config)
1238
{
1239
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1240 1241 1242
	int link_clock = 0;
	uint32_t dpll_ctl1, dpll;

1243
	dpll = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
1244 1245 1246 1247 1248 1249

	dpll_ctl1 = I915_READ(DPLL_CTRL1);

	if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
		link_clock = skl_calc_wrpll_link(dev_priv, dpll);
	} else {
1250 1251
		link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
		link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
1252 1253

		switch (link_clock) {
1254
		case DPLL_CTRL1_LINK_RATE_810:
1255 1256
			link_clock = 81000;
			break;
1257
		case DPLL_CTRL1_LINK_RATE_1080:
1258 1259
			link_clock = 108000;
			break;
1260
		case DPLL_CTRL1_LINK_RATE_1350:
1261 1262
			link_clock = 135000;
			break;
1263
		case DPLL_CTRL1_LINK_RATE_1620:
1264 1265
			link_clock = 162000;
			break;
1266
		case DPLL_CTRL1_LINK_RATE_2160:
1267 1268
			link_clock = 216000;
			break;
1269
		case DPLL_CTRL1_LINK_RATE_2700:
1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280
			link_clock = 270000;
			break;
		default:
			WARN(1, "Unsupported link rate\n");
			break;
		}
		link_clock *= 2;
	}

	pipe_config->port_clock = link_clock;

1281
	ddi_dotclock_get(pipe_config);
1282 1283
}

1284
static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1285
			      struct intel_crtc_state *pipe_config)
1286
{
1287
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1288 1289 1290
	int link_clock = 0;
	u32 val, pll;

1291
	val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302
	switch (val & PORT_CLK_SEL_MASK) {
	case PORT_CLK_SEL_LCPLL_810:
		link_clock = 81000;
		break;
	case PORT_CLK_SEL_LCPLL_1350:
		link_clock = 135000;
		break;
	case PORT_CLK_SEL_LCPLL_2700:
		link_clock = 270000;
		break;
	case PORT_CLK_SEL_WRPLL1:
1303
		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1304 1305
		break;
	case PORT_CLK_SEL_WRPLL2:
1306
		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327
		break;
	case PORT_CLK_SEL_SPLL:
		pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
		if (pll == SPLL_PLL_FREQ_810MHz)
			link_clock = 81000;
		else if (pll == SPLL_PLL_FREQ_1350MHz)
			link_clock = 135000;
		else if (pll == SPLL_PLL_FREQ_2700MHz)
			link_clock = 270000;
		else {
			WARN(1, "bad spll freq\n");
			return;
		}
		break;
	default:
		WARN(1, "bad port clock sel\n");
		return;
	}

	pipe_config->port_clock = link_clock * 2;

1328
	ddi_dotclock_get(pipe_config);
1329 1330
}

1331 1332 1333
static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
				enum intel_dpll_id dpll)
{
1334 1335
	struct intel_shared_dpll *pll;
	struct intel_dpll_hw_state *state;
1336
	struct dpll clock;
1337 1338 1339 1340 1341 1342

	/* For DDI ports we always use a shared PLL. */
	if (WARN_ON(dpll == DPLL_ID_PRIVATE))
		return 0;

	pll = &dev_priv->shared_dplls[dpll];
1343
	state = &pll->state.hw_state;
1344 1345 1346 1347 1348 1349 1350 1351 1352 1353

	clock.m1 = 2;
	clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
	if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
		clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
	clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
	clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
	clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;

	return chv_calc_dpll_params(100000, &clock);
1354 1355 1356 1357 1358
}

static void bxt_ddi_clock_get(struct intel_encoder *encoder,
				struct intel_crtc_state *pipe_config)
{
1359
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1360 1361 1362
	enum port port = intel_ddi_get_encoder_port(encoder);
	uint32_t dpll = port;

1363
	pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
1364

1365
	ddi_dotclock_get(pipe_config);
1366 1367
}

1368
void intel_ddi_clock_get(struct intel_encoder *encoder,
1369
			 struct intel_crtc_state *pipe_config)
1370
{
1371
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1372

1373
	if (INTEL_GEN(dev_priv) <= 8)
1374
		hsw_ddi_clock_get(encoder, pipe_config);
1375
	else if (IS_GEN9_BC(dev_priv))
1376
		skl_ddi_clock_get(encoder, pipe_config);
1377
	else if (IS_GEN9_LP(dev_priv))
1378
		bxt_ddi_clock_get(encoder, pipe_config);
1379 1380
	else if (IS_CANNONLAKE(dev_priv))
		cnl_ddi_clock_get(encoder, pipe_config);
1381 1382
}

1383
void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1384
{
1385
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1386
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1387
	struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1388
	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1389
	int type = encoder->type;
1390 1391
	uint32_t temp;

1392
	if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
J
Jani Nikula 已提交
1393 1394
		WARN_ON(transcoder_is_dsi(cpu_transcoder));

1395
		temp = TRANS_MSA_SYNC_CLK;
1396
		switch (crtc_state->pipe_bpp) {
1397
		case 18:
1398
			temp |= TRANS_MSA_6_BPC;
1399 1400
			break;
		case 24:
1401
			temp |= TRANS_MSA_8_BPC;
1402 1403
			break;
		case 30:
1404
			temp |= TRANS_MSA_10_BPC;
1405 1406
			break;
		case 36:
1407
			temp |= TRANS_MSA_12_BPC;
1408 1409
			break;
		default:
1410
			BUG();
1411
		}
1412
		I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1413 1414 1415
	}
}

1416 1417
void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
				    bool state)
1418
{
1419
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1420
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1421
	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1422 1423 1424 1425 1426 1427 1428 1429 1430
	uint32_t temp;
	temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
	if (state == true)
		temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
	else
		temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
	I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
}

1431
void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1432
{
1433
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1434
	struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1435 1436
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	enum pipe pipe = crtc->pipe;
1437
	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1438 1439
	enum port port = intel_ddi_get_encoder_port(encoder);
	int type = encoder->type;
1440 1441
	uint32_t temp;

1442 1443
	/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
	temp = TRANS_DDI_FUNC_ENABLE;
1444
	temp |= TRANS_DDI_SELECT_PORT(port);
1445

1446
	switch (crtc_state->pipe_bpp) {
1447
	case 18:
1448
		temp |= TRANS_DDI_BPC_6;
1449 1450
		break;
	case 24:
1451
		temp |= TRANS_DDI_BPC_8;
1452 1453
		break;
	case 30:
1454
		temp |= TRANS_DDI_BPC_10;
1455 1456
		break;
	case 36:
1457
		temp |= TRANS_DDI_BPC_12;
1458 1459
		break;
	default:
1460
		BUG();
1461
	}
1462

1463
	if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1464
		temp |= TRANS_DDI_PVSYNC;
1465
	if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1466
		temp |= TRANS_DDI_PHSYNC;
1467

1468 1469 1470
	if (cpu_transcoder == TRANSCODER_EDP) {
		switch (pipe) {
		case PIPE_A:
1471 1472 1473 1474
			/* On Haswell, can only use the always-on power well for
			 * eDP when not using the panel fitter, and when not
			 * using motion blur mitigation (which we don't
			 * support). */
1475
			if (IS_HASWELL(dev_priv) &&
1476 1477
			    (crtc_state->pch_pfit.enabled ||
			     crtc_state->pch_pfit.force_thru))
1478 1479 1480
				temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
			else
				temp |= TRANS_DDI_EDP_INPUT_A_ON;
1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493
			break;
		case PIPE_B:
			temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
			break;
		case PIPE_C:
			temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
			break;
		default:
			BUG();
			break;
		}
	}

1494
	if (type == INTEL_OUTPUT_HDMI) {
1495
		if (crtc_state->has_hdmi_sink)
1496
			temp |= TRANS_DDI_MODE_SELECT_HDMI;
1497
		else
1498
			temp |= TRANS_DDI_MODE_SELECT_DVI;
S
Shashank Sharma 已提交
1499 1500 1501 1502 1503

		if (crtc_state->hdmi_scrambling)
			temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
		if (crtc_state->hdmi_high_tmds_clock_ratio)
			temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1504
	} else if (type == INTEL_OUTPUT_ANALOG) {
1505
		temp |= TRANS_DDI_MODE_SELECT_FDI;
1506
		temp |= (crtc_state->fdi_lanes - 1) << 1;
1507
	} else if (type == INTEL_OUTPUT_DP ||
1508
		   type == INTEL_OUTPUT_EDP) {
1509
		temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1510
		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1511
	} else if (type == INTEL_OUTPUT_DP_MST) {
1512
		temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1513
		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1514
	} else {
1515
		WARN(1, "Invalid encoder type %d for pipe %c\n",
1516
		     encoder->type, pipe_name(pipe));
1517 1518
	}

1519
	I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1520
}
1521

1522 1523
void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
				       enum transcoder cpu_transcoder)
1524
{
1525
	i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1526 1527
	uint32_t val = I915_READ(reg);

1528
	val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1529
	val |= TRANS_DDI_PORT_NONE;
1530
	I915_WRITE(reg, val);
1531 1532
}

1533 1534 1535
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
{
	struct drm_device *dev = intel_connector->base.dev;
1536
	struct drm_i915_private *dev_priv = to_i915(dev);
1537
	struct intel_encoder *encoder = intel_connector->encoder;
1538
	int type = intel_connector->base.connector_type;
1539
	enum port port = intel_ddi_get_encoder_port(encoder);
1540 1541 1542
	enum pipe pipe = 0;
	enum transcoder cpu_transcoder;
	uint32_t tmp;
1543
	bool ret;
1544

1545
	if (!intel_display_power_get_if_enabled(dev_priv,
1546
						encoder->power_domain))
1547 1548
		return false;

1549
	if (!encoder->get_hw_state(encoder, &pipe)) {
1550 1551 1552
		ret = false;
		goto out;
	}
1553 1554 1555 1556

	if (port == PORT_A)
		cpu_transcoder = TRANSCODER_EDP;
	else
D
Daniel Vetter 已提交
1557
		cpu_transcoder = (enum transcoder) pipe;
1558 1559 1560 1561 1562 1563

	tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));

	switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
	case TRANS_DDI_MODE_SELECT_HDMI:
	case TRANS_DDI_MODE_SELECT_DVI:
1564 1565
		ret = type == DRM_MODE_CONNECTOR_HDMIA;
		break;
1566 1567

	case TRANS_DDI_MODE_SELECT_DP_SST:
1568 1569 1570 1571
		ret = type == DRM_MODE_CONNECTOR_eDP ||
		      type == DRM_MODE_CONNECTOR_DisplayPort;
		break;

1572 1573 1574
	case TRANS_DDI_MODE_SELECT_DP_MST:
		/* if the transcoder is in MST state then
		 * connector isn't connected */
1575 1576
		ret = false;
		break;
1577 1578

	case TRANS_DDI_MODE_SELECT_FDI:
1579 1580
		ret = type == DRM_MODE_CONNECTOR_VGA;
		break;
1581 1582

	default:
1583 1584
		ret = false;
		break;
1585
	}
1586 1587

out:
1588
	intel_display_power_put(dev_priv, encoder->power_domain);
1589 1590

	return ret;
1591 1592
}

1593 1594 1595 1596
bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
			    enum pipe *pipe)
{
	struct drm_device *dev = encoder->base.dev;
1597
	struct drm_i915_private *dev_priv = to_i915(dev);
1598
	enum port port = intel_ddi_get_encoder_port(encoder);
1599 1600
	u32 tmp;
	int i;
1601
	bool ret;
1602

1603 1604
	if (!intel_display_power_get_if_enabled(dev_priv,
						encoder->power_domain))
1605 1606
		return false;

1607 1608
	ret = false;

1609
	tmp = I915_READ(DDI_BUF_CTL(port));
1610 1611

	if (!(tmp & DDI_BUF_CTL_ENABLE))
1612
		goto out;
1613

1614 1615
	if (port == PORT_A) {
		tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1616

1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629
		switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
		case TRANS_DDI_EDP_INPUT_A_ON:
		case TRANS_DDI_EDP_INPUT_A_ONOFF:
			*pipe = PIPE_A;
			break;
		case TRANS_DDI_EDP_INPUT_B_ONOFF:
			*pipe = PIPE_B;
			break;
		case TRANS_DDI_EDP_INPUT_C_ONOFF:
			*pipe = PIPE_C;
			break;
		}

1630
		ret = true;
1631

1632 1633
		goto out;
	}
1634

1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646
	for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
		tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));

		if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
			if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
			    TRANS_DDI_MODE_SELECT_DP_MST)
				goto out;

			*pipe = i;
			ret = true;

			goto out;
1647 1648 1649
		}
	}

1650
	DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1651

1652
out:
1653
	if (ret && IS_GEN9_LP(dev_priv)) {
1654 1655 1656 1657 1658 1659 1660
		tmp = I915_READ(BXT_PHY_CTL(port));
		if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
			    BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
			DRM_ERROR("Port %c enabled but PHY powered down? "
				  "(PHY_CTL %08x)\n", port_name(port), tmp);
	}

1661
	intel_display_power_put(dev_priv, encoder->power_domain);
1662 1663

	return ret;
1664 1665
}

1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676
static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder)
{
	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
	enum pipe pipe;

	if (intel_ddi_get_hw_state(encoder, &pipe))
		return BIT_ULL(dig_port->ddi_io_power_domain);

	return 0;
}

1677
void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
1678
{
1679
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1680
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1681 1682
	struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
	enum port port = intel_ddi_get_encoder_port(encoder);
1683
	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1684

1685 1686 1687
	if (cpu_transcoder != TRANSCODER_EDP)
		I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
			   TRANS_CLK_SEL_PORT(port));
1688 1689
}

1690
void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
1691
{
1692 1693
	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1694

1695 1696 1697
	if (cpu_transcoder != TRANSCODER_EDP)
		I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
			   TRANS_CLK_SEL_DISABLED);
1698 1699
}

1700 1701
static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
				enum port port, uint8_t iboost)
1702
{
1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719
	u32 tmp;

	tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
	tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
	if (iboost)
		tmp |= iboost << BALANCE_LEG_SHIFT(port);
	else
		tmp |= BALANCE_LEG_DISABLE(port);
	I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
}

static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
{
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
	struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
	enum port port = intel_dig_port->port;
	int type = encoder->type;
1720 1721
	const struct ddi_buf_trans *ddi_translations;
	uint8_t iboost;
1722
	uint8_t dp_iboost, hdmi_iboost;
1723 1724
	int n_entries;

1725 1726 1727 1728
	/* VBT may override standard boost values */
	dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
	hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;

1729
	if (type == INTEL_OUTPUT_DP) {
1730 1731 1732
		if (dp_iboost) {
			iboost = dp_iboost;
		} else {
1733
			if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
1734 1735 1736 1737 1738
				ddi_translations = kbl_get_buf_trans_dp(dev_priv,
									&n_entries);
			else
				ddi_translations = skl_get_buf_trans_dp(dev_priv,
									&n_entries);
1739
			iboost = ddi_translations[level].i_boost;
1740
		}
1741
	} else if (type == INTEL_OUTPUT_EDP) {
1742 1743 1744
		if (dp_iboost) {
			iboost = dp_iboost;
		} else {
1745
			ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
1746 1747 1748 1749 1750

			if (WARN_ON(port != PORT_A &&
				    port != PORT_E && n_entries > 9))
				n_entries = 9;

1751
			iboost = ddi_translations[level].i_boost;
1752
		}
1753
	} else if (type == INTEL_OUTPUT_HDMI) {
1754 1755 1756
		if (hdmi_iboost) {
			iboost = hdmi_iboost;
		} else {
1757
			ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
1758
			iboost = ddi_translations[level].i_boost;
1759
		}
1760 1761 1762 1763 1764 1765 1766 1767 1768 1769
	} else {
		return;
	}

	/* Make sure that the requested I_boost is valid */
	if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
		DRM_ERROR("Invalid I_boost value %u\n", iboost);
		return;
	}

1770
	_skl_ddi_set_iboost(dev_priv, port, iboost);
1771

1772 1773
	if (port == PORT_A && intel_dig_port->max_lanes == 4)
		_skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
1774 1775
}

1776 1777
static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
				    u32 level, enum port port, int type)
1778 1779 1780 1781
{
	const struct bxt_ddi_buf_trans *ddi_translations;
	u32 n_entries, i;

1782
	if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
1783 1784
		n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
		ddi_translations = bxt_ddi_translations_edp;
1785
	} else if (type == INTEL_OUTPUT_DP
1786
			|| type == INTEL_OUTPUT_EDP) {
1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808
		n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
		ddi_translations = bxt_ddi_translations_dp;
	} else if (type == INTEL_OUTPUT_HDMI) {
		n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
		ddi_translations = bxt_ddi_translations_hdmi;
	} else {
		DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
				type);
		return;
	}

	/* Check if default value has to be used */
	if (level >= n_entries ||
	    (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
		for (i = 0; i < n_entries; i++) {
			if (ddi_translations[i].default_index) {
				level = i;
				break;
			}
		}
	}

1809 1810 1811 1812 1813
	bxt_ddi_phy_set_signal_level(dev_priv, port,
				     ddi_translations[level].margin,
				     ddi_translations[level].scale,
				     ddi_translations[level].enable,
				     ddi_translations[level].deemphasis);
1814 1815
}

1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834
u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	int n_entries;

	if (encoder->type == INTEL_OUTPUT_EDP)
		intel_ddi_get_buf_trans_edp(dev_priv, &n_entries);
	else
		intel_ddi_get_buf_trans_dp(dev_priv, &n_entries);

	if (WARN_ON(n_entries < 1))
		n_entries = 1;
	if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
		n_entries = ARRAY_SIZE(index_to_dp_signal_levels);

	return index_to_dp_signal_levels[n_entries - 1] &
		DP_TRAIN_VOLTAGE_SWING_MASK;
}

1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926
static const struct cnl_ddi_buf_trans *
cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv,
		       u32 voltage, int *n_entries)
{
	if (voltage == VOLTAGE_INFO_0_85V) {
		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
		return cnl_ddi_translations_hdmi_0_85V;
	} else if (voltage == VOLTAGE_INFO_0_95V) {
		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
		return cnl_ddi_translations_hdmi_0_95V;
	} else if (voltage == VOLTAGE_INFO_1_05V) {
		*n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
		return cnl_ddi_translations_hdmi_1_05V;
	}
	return NULL;
}

static const struct cnl_ddi_buf_trans *
cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv,
		     u32 voltage, int *n_entries)
{
	if (voltage == VOLTAGE_INFO_0_85V) {
		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
		return cnl_ddi_translations_dp_0_85V;
	} else if (voltage == VOLTAGE_INFO_0_95V) {
		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
		return cnl_ddi_translations_dp_0_95V;
	} else if (voltage == VOLTAGE_INFO_1_05V) {
		*n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
		return cnl_ddi_translations_dp_1_05V;
	}
	return NULL;
}

static const struct cnl_ddi_buf_trans *
cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv,
		      u32 voltage, int *n_entries)
{
	if (dev_priv->vbt.edp.low_vswing) {
		if (voltage == VOLTAGE_INFO_0_85V) {
			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
			return cnl_ddi_translations_dp_0_85V;
		} else if (voltage == VOLTAGE_INFO_0_95V) {
			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
			return cnl_ddi_translations_edp_0_95V;
		} else if (voltage == VOLTAGE_INFO_1_05V) {
			*n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
			return cnl_ddi_translations_edp_1_05V;
		}
		return NULL;
	} else {
		return cnl_get_buf_trans_dp(dev_priv, voltage, n_entries);
	}
}

static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv,
				    u32 level, enum port port, int type)
{
	const struct cnl_ddi_buf_trans *ddi_translations = NULL;
	u32 n_entries, val, voltage;
	int ln;

	/*
	 * Values for each port type are listed in
	 * voltage swing programming tables.
	 * Vccio voltage found in PORT_COMP_DW3.
	 */
	voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;

	if (type == INTEL_OUTPUT_HDMI) {
		ddi_translations = cnl_get_buf_trans_hdmi(dev_priv,
							  voltage, &n_entries);
	} else if (type == INTEL_OUTPUT_DP) {
		ddi_translations = cnl_get_buf_trans_dp(dev_priv,
							voltage, &n_entries);
	} else if (type == INTEL_OUTPUT_EDP) {
		ddi_translations = cnl_get_buf_trans_edp(dev_priv,
							 voltage, &n_entries);
	}

	if (ddi_translations == NULL) {
		MISSING_CASE(voltage);
		return;
	}

	if (level >= n_entries) {
		DRM_DEBUG_KMS("DDI translation not found for level %d. Using %d instead.", level, n_entries - 1);
		level = n_entries - 1;
	}

	/* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1927
	val &= ~SCALING_MODE_SEL_MASK;
1928 1929 1930 1931 1932
	val |= SCALING_MODE_SEL(2);
	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);

	/* Program PORT_TX_DW2 */
	val = I915_READ(CNL_PORT_TX_DW2_LN0(port));
1933 1934
	val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
		 RCOMP_SCALAR_MASK);
1935 1936 1937 1938 1939 1940 1941 1942 1943 1944
	val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
	val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
	/* Rcomp scalar is fixed as 0x98 for every table entry */
	val |= RCOMP_SCALAR(0x98);
	I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val);

        /* Program PORT_TX_DW4 */
	/* We cannot write to GRP. It would overrite individual loadgen */
	for (ln = 0; ln < 4; ln++) {
		val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
1945 1946
		val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
			 CURSOR_COEFF_MASK);
1947 1948 1949 1950 1951 1952 1953 1954 1955
		val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
		val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
		val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
		I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
	}

        /* Program PORT_TX_DW5 */
	/* All DW5 values are fixed for every table entry */
	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
1956
	val &= ~RTERM_SELECT_MASK;
1957 1958 1959 1960 1961 1962
	val |= RTERM_SELECT(6);
	val |= TAP3_DISABLE;
	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);

        /* Program PORT_TX_DW7 */
	val = I915_READ(CNL_PORT_TX_DW7_LN0(port));
1963
	val &= ~N_SCALAR_MASK;
1964 1965 1966 1967
	val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
	I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val);
}

1968
static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level)
1969
{
1970 1971 1972 1973 1974 1975
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	enum port port = intel_ddi_get_encoder_port(encoder);
	int type = encoder->type;
	int width = 0;
	int rate = 0;
1976
	u32 val;
1977 1978 1979 1980 1981 1982 1983 1984 1985
	int ln = 0;

	if ((intel_dp) && (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)) {
		width = intel_dp->lane_count;
		rate = intel_dp->link_rate;
	} else {
		width = 4;
		/* Rate is always < than 6GHz for HDMI */
	}
1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000

	/*
	 * 1. If port type is eDP or DP,
	 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
	 * else clear to 0b.
	 */
	val = I915_READ(CNL_PORT_PCS_DW1_LN0(port));
	if (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP)
		val |= COMMON_KEEPER_EN;
	else
		val &= ~COMMON_KEEPER_EN;
	I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val);

	/* 2. Program loadgen select */
	/*
2001 2002 2003 2004
	 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
	 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
	 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
	 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2005
	 */
2006 2007 2008 2009 2010 2011 2012 2013 2014 2015
	for (ln = 0; ln <= 3; ln++) {
		val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
		val &= ~LOADGEN_SELECT;

		if (((rate < 600000) && (width == 4) && (ln >= 1))  ||
		    ((rate < 600000) && (width < 4) && ((ln == 1) || (ln == 2)))) {
			val |= LOADGEN_SELECT;
		}
		I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
	}
2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035

	/* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
	val = I915_READ(CNL_PORT_CL1CM_DW5);
	val |= SUS_CLOCK_CONFIG;
	I915_WRITE(CNL_PORT_CL1CM_DW5, val);

	/* 4. Clear training enable to change swing values */
	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
	val &= ~TX_TRAINING_EN;
	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);

	/* 5. Program swing and de-emphasis */
	cnl_ddi_vswing_program(dev_priv, level, port, type);

	/* 6. Set training enable to trigger update */
	val = I915_READ(CNL_PORT_TX_DW5_LN0(port));
	val |= TX_TRAINING_EN;
	I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val);
}

2036 2037
static uint32_t translate_signal_level(int signal_levels)
{
2038
	int i;
2039

2040 2041 2042
	for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
		if (index_to_dp_signal_levels[i] == signal_levels)
			return i;
2043 2044
	}

2045 2046 2047 2048
	WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
	     signal_levels);

	return 0;
2049 2050 2051 2052 2053
}

uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
{
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2054
	struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2055 2056 2057 2058 2059 2060 2061 2062 2063
	struct intel_encoder *encoder = &dport->base;
	uint8_t train_set = intel_dp->train_set[0];
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	enum port port = dport->port;
	uint32_t level;

	level = translate_signal_level(signal_levels);

2064
	if (IS_GEN9_BC(dev_priv))
2065
		skl_ddi_set_iboost(encoder, level);
2066
	else if (IS_GEN9_LP(dev_priv))
2067
		bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
2068
	else if (IS_CANNONLAKE(dev_priv)) {
2069
		cnl_ddi_vswing_sequence(encoder, level);
2070 2071 2072
		/* DDI_BUF_CTL bits 27:24 are reserved on CNL */
		return 0;
	}
2073 2074 2075
	return DDI_BUF_TRANS_SELECT(level);
}

2076 2077
static void intel_ddi_clk_select(struct intel_encoder *encoder,
				 struct intel_shared_dpll *pll)
2078
{
2079 2080
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	enum port port = intel_ddi_get_encoder_port(encoder);
R
Rodrigo Vivi 已提交
2081
	uint32_t val;
2082

2083 2084 2085
	if (WARN_ON(!pll))
		return;

R
Rodrigo Vivi 已提交
2086 2087 2088 2089 2090
	if (IS_CANNONLAKE(dev_priv)) {
		/* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
		val = I915_READ(DPCLKA_CFGCR0);
		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
		I915_WRITE(DPCLKA_CFGCR0, val);
2091

R
Rodrigo Vivi 已提交
2092 2093 2094 2095 2096 2097 2098 2099 2100 2101
		/*
		 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
		 * This step and the step before must be done with separate
		 * register writes.
		 */
		val = I915_READ(DPCLKA_CFGCR0);
		val &= ~(DPCLKA_CFGCR0_DDI_CLK_OFF(port) |
			 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port));
		I915_WRITE(DPCLKA_CFGCR0, val);
	} else if (IS_GEN9_BC(dev_priv)) {
2102
		/* DDI -> PLL mapping  */
2103 2104 2105 2106
		val = I915_READ(DPLL_CTRL2);

		val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
			DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
2107
		val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
2108 2109 2110
			DPLL_CTRL2_DDI_SEL_OVERRIDE(port));

		I915_WRITE(DPLL_CTRL2, val);
2111

2112
	} else if (INTEL_INFO(dev_priv)->gen < 9) {
2113
		I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
2114
	}
2115 2116
}

2117 2118 2119 2120
static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
				    int link_rate, uint32_t lane_count,
				    struct intel_shared_dpll *pll,
				    bool link_mst)
2121
{
2122 2123 2124
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	enum port port = intel_ddi_get_encoder_port(encoder);
2125
	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2126

2127 2128
	WARN_ON(link_mst && (port == PORT_A || port == PORT_E));

2129 2130 2131
	intel_dp_set_link_params(intel_dp, link_rate, lane_count,
				 link_mst);
	if (encoder->type == INTEL_OUTPUT_EDP)
2132
		intel_edp_panel_on(intel_dp);
2133

2134
	intel_ddi_clk_select(encoder, pll);
2135 2136 2137

	intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);

2138 2139 2140 2141 2142 2143 2144
	intel_prepare_dp_ddi_buffers(encoder);
	intel_ddi_init_dp_buf_reg(encoder);
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
	intel_dp_start_link_train(intel_dp);
	if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
		intel_dp_stop_link_train(intel_dp);
}
2145

2146 2147
static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
				      bool has_hdmi_sink,
2148 2149
				      const struct intel_crtc_state *crtc_state,
				      const struct drm_connector_state *conn_state,
2150 2151 2152 2153 2154 2155 2156
				      struct intel_shared_dpll *pll)
{
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	struct drm_encoder *drm_encoder = &encoder->base;
	enum port port = intel_ddi_get_encoder_port(encoder);
	int level = intel_ddi_hdmi_level(dev_priv, port);
2157
	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
2158

2159 2160
	intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
	intel_ddi_clk_select(encoder, pll);
2161 2162 2163

	intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);

2164
	intel_prepare_hdmi_ddi_buffers(encoder);
2165
	if (IS_GEN9_BC(dev_priv))
2166
		skl_ddi_set_iboost(encoder, level);
2167
	else if (IS_GEN9_LP(dev_priv))
2168 2169
		bxt_ddi_vswing_sequence(dev_priv, level, port,
					INTEL_OUTPUT_HDMI);
2170
	else if (IS_CANNONLAKE(dev_priv))
2171
		cnl_ddi_vswing_sequence(encoder, level);
2172

2173 2174
	intel_hdmi->set_infoframes(drm_encoder,
				   has_hdmi_sink,
2175
				   crtc_state, conn_state);
2176
}
2177

2178
static void intel_ddi_pre_enable(struct intel_encoder *encoder,
2179 2180 2181
				 struct intel_crtc_state *pipe_config,
				 struct drm_connector_state *conn_state)
{
2182
	int type = encoder->type;
2183

2184
	if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
2185
		intel_ddi_pre_enable_dp(encoder,
2186 2187 2188 2189
					pipe_config->port_clock,
					pipe_config->lane_count,
					pipe_config->shared_dpll,
					intel_crtc_has_type(pipe_config,
2190 2191 2192
							    INTEL_OUTPUT_DP_MST));
	}
	if (type == INTEL_OUTPUT_HDMI) {
2193
		intel_ddi_pre_enable_hdmi(encoder,
2194 2195
					  pipe_config->has_hdmi_sink,
					  pipe_config, conn_state,
2196
					  pipe_config->shared_dpll);
2197
	}
2198 2199
}

2200 2201 2202
static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
				   struct intel_crtc_state *old_crtc_state,
				   struct drm_connector_state *old_conn_state)
2203 2204
{
	struct drm_encoder *encoder = &intel_encoder->base;
2205
	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
2206
	enum port port = intel_ddi_get_encoder_port(intel_encoder);
2207
	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2208
	struct intel_dp *intel_dp = NULL;
2209
	int type = intel_encoder->type;
2210
	uint32_t val;
2211
	bool wait = false;
2212

2213 2214
	/* old_crtc_state and old_conn_state are NULL when called from DP_MST */

2215 2216 2217 2218 2219
	if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
		intel_dp = enc_to_intel_dp(encoder);
		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
	}

2220 2221 2222 2223
	val = I915_READ(DDI_BUF_CTL(port));
	if (val & DDI_BUF_CTL_ENABLE) {
		val &= ~DDI_BUF_CTL_ENABLE;
		I915_WRITE(DDI_BUF_CTL(port), val);
2224
		wait = true;
2225
	}
2226

2227 2228 2229 2230 2231 2232 2233 2234
	val = I915_READ(DP_TP_CTL(port));
	val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
	val |= DP_TP_CTL_LINK_TRAIN_PAT1;
	I915_WRITE(DP_TP_CTL(port), val);

	if (wait)
		intel_wait_ddi_buf_idle(dev_priv, port);

2235
	if (intel_dp) {
2236
		intel_edp_panel_vdd_on(intel_dp);
2237
		intel_edp_panel_off(intel_dp);
2238 2239
	}

2240 2241 2242
	if (dig_port)
		intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);

R
Rodrigo Vivi 已提交
2243 2244 2245 2246
	if (IS_CANNONLAKE(dev_priv))
		I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
			   DPCLKA_CFGCR0_DDI_CLK_OFF(port));
	else if (IS_GEN9_BC(dev_priv))
2247 2248
		I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
					DPLL_CTRL2_DDI_CLK_OFF(port)));
2249
	else if (INTEL_GEN(dev_priv) < 9)
2250
		I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2251 2252 2253 2254 2255 2256

	if (type == INTEL_OUTPUT_HDMI) {
		struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);

		intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
	}
2257 2258
}

2259
void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
2260 2261 2262
				struct intel_crtc_state *old_crtc_state,
				struct drm_connector_state *old_conn_state)
{
2263
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275
	uint32_t val;

	/*
	 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
	 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
	 * step 13 is the correct place for it. Step 18 is where it was
	 * originally before the BUN.
	 */
	val = I915_READ(FDI_RX_CTL(PIPE_A));
	val &= ~FDI_RX_ENABLE;
	I915_WRITE(FDI_RX_CTL(PIPE_A), val);

2276
	intel_ddi_post_disable(encoder, old_crtc_state, old_conn_state);
2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291

	val = I915_READ(FDI_RX_MISC(PIPE_A));
	val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
	val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
	I915_WRITE(FDI_RX_MISC(PIPE_A), val);

	val = I915_READ(FDI_RX_CTL(PIPE_A));
	val &= ~FDI_PCDCLK;
	I915_WRITE(FDI_RX_CTL(PIPE_A), val);

	val = I915_READ(FDI_RX_CTL(PIPE_A));
	val &= ~FDI_RX_PLL_ENABLE;
	I915_WRITE(FDI_RX_CTL(PIPE_A), val);
}

2292 2293 2294
static void intel_enable_ddi(struct intel_encoder *intel_encoder,
			     struct intel_crtc_state *pipe_config,
			     struct drm_connector_state *conn_state)
2295
{
2296
	struct drm_encoder *encoder = &intel_encoder->base;
2297
	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
2298 2299
	enum port port = intel_ddi_get_encoder_port(intel_encoder);
	int type = intel_encoder->type;
2300

2301
	if (type == INTEL_OUTPUT_HDMI) {
2302 2303
		struct intel_digital_port *intel_dig_port =
			enc_to_dig_port(encoder);
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2304 2305 2306 2307 2308 2309
		bool clock_ratio = pipe_config->hdmi_high_tmds_clock_ratio;
		bool scrambling = pipe_config->hdmi_scrambling;

		intel_hdmi_handle_sink_scrambling(intel_encoder,
						  conn_state->connector,
						  clock_ratio, scrambling);
2310

2311 2312 2313 2314
		/* In HDMI/DVI mode, the port width, and swing/emphasis values
		 * are ignored so nothing special needs to be done besides
		 * enabling the port.
		 */
2315
		I915_WRITE(DDI_BUF_CTL(port),
2316 2317
			   intel_dig_port->saved_port_bits |
			   DDI_BUF_CTL_ENABLE);
2318 2319 2320
	} else if (type == INTEL_OUTPUT_EDP) {
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

2321
		if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
2322 2323
			intel_dp_stop_link_train(intel_dp);

2324
		intel_edp_backlight_on(pipe_config, conn_state);
R
Rodrigo Vivi 已提交
2325
		intel_psr_enable(intel_dp);
2326
		intel_edp_drrs_enable(intel_dp, pipe_config);
2327
	}
2328

2329
	if (pipe_config->has_audio)
2330
		intel_audio_codec_enable(intel_encoder, pipe_config, conn_state);
2331 2332
}

2333 2334 2335
static void intel_disable_ddi(struct intel_encoder *intel_encoder,
			      struct intel_crtc_state *old_crtc_state,
			      struct drm_connector_state *old_conn_state)
2336
{
2337 2338 2339
	struct drm_encoder *encoder = &intel_encoder->base;
	int type = intel_encoder->type;

2340
	if (old_crtc_state->has_audio)
2341
		intel_audio_codec_disable(intel_encoder);
2342

S
Shashank Sharma 已提交
2343 2344 2345 2346 2347 2348
	if (type == INTEL_OUTPUT_HDMI) {
		intel_hdmi_handle_sink_scrambling(intel_encoder,
						  old_conn_state->connector,
						  false, false);
	}

2349 2350 2351
	if (type == INTEL_OUTPUT_EDP) {
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

2352
		intel_edp_drrs_disable(intel_dp, old_crtc_state);
R
Rodrigo Vivi 已提交
2353
		intel_psr_disable(intel_dp);
2354
		intel_edp_backlight_off(old_conn_state);
2355
	}
2356
}
P
Paulo Zanoni 已提交
2357

2358 2359 2360
static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
				   struct intel_crtc_state *pipe_config,
				   struct drm_connector_state *conn_state)
2361
{
2362
	uint8_t mask = pipe_config->lane_lat_optim_mask;
2363

2364
	bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
2365 2366
}

2367
void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
2368
{
2369 2370 2371
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_i915_private *dev_priv =
		to_i915(intel_dig_port->base.base.dev);
2372
	enum port port = intel_dig_port->port;
2373
	uint32_t val;
2374
	bool wait = false;
2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393

	if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
		val = I915_READ(DDI_BUF_CTL(port));
		if (val & DDI_BUF_CTL_ENABLE) {
			val &= ~DDI_BUF_CTL_ENABLE;
			I915_WRITE(DDI_BUF_CTL(port), val);
			wait = true;
		}

		val = I915_READ(DP_TP_CTL(port));
		val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
		val |= DP_TP_CTL_LINK_TRAIN_PAT1;
		I915_WRITE(DP_TP_CTL(port), val);
		POSTING_READ(DP_TP_CTL(port));

		if (wait)
			intel_wait_ddi_buf_idle(dev_priv, port);
	}

2394
	val = DP_TP_CTL_ENABLE |
2395
	      DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
2396
	if (intel_dp->link_mst)
2397 2398 2399 2400 2401 2402
		val |= DP_TP_CTL_MODE_MST;
	else {
		val |= DP_TP_CTL_MODE_SST;
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
			val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
	}
2403 2404 2405 2406 2407 2408 2409 2410 2411
	I915_WRITE(DP_TP_CTL(port), val);
	POSTING_READ(DP_TP_CTL(port));

	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
	I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
	POSTING_READ(DDI_BUF_CTL(port));

	udelay(600);
}
P
Paulo Zanoni 已提交
2412

2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425
bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
				 struct intel_crtc *intel_crtc)
{
	u32 temp;

	if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
		temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
		if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
			return true;
	}
	return false;
}

2426
void intel_ddi_get_config(struct intel_encoder *encoder,
2427
			  struct intel_crtc_state *pipe_config)
2428
{
2429
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2430
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2431
	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2432
	struct intel_hdmi *intel_hdmi;
2433 2434
	u32 temp, flags = 0;

J
Jani Nikula 已提交
2435 2436 2437 2438
	/* XXX: DSI transcoder paranoia */
	if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
		return;

2439 2440 2441 2442 2443 2444 2445 2446 2447 2448
	temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
	if (temp & TRANS_DDI_PHSYNC)
		flags |= DRM_MODE_FLAG_PHSYNC;
	else
		flags |= DRM_MODE_FLAG_NHSYNC;
	if (temp & TRANS_DDI_PVSYNC)
		flags |= DRM_MODE_FLAG_PVSYNC;
	else
		flags |= DRM_MODE_FLAG_NVSYNC;

2449
	pipe_config->base.adjusted_mode.flags |= flags;
2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466

	switch (temp & TRANS_DDI_BPC_MASK) {
	case TRANS_DDI_BPC_6:
		pipe_config->pipe_bpp = 18;
		break;
	case TRANS_DDI_BPC_8:
		pipe_config->pipe_bpp = 24;
		break;
	case TRANS_DDI_BPC_10:
		pipe_config->pipe_bpp = 30;
		break;
	case TRANS_DDI_BPC_12:
		pipe_config->pipe_bpp = 36;
		break;
	default:
		break;
	}
2467 2468 2469

	switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
	case TRANS_DDI_MODE_SELECT_HDMI:
2470
		pipe_config->has_hdmi_sink = true;
2471 2472
		intel_hdmi = enc_to_intel_hdmi(&encoder->base);

2473
		if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
2474
			pipe_config->has_infoframe = true;
S
Shashank Sharma 已提交
2475 2476 2477 2478 2479 2480

		if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
			TRANS_DDI_HDMI_SCRAMBLING_MASK)
			pipe_config->hdmi_scrambling = true;
		if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
			pipe_config->hdmi_high_tmds_clock_ratio = true;
2481
		/* fall through */
2482
	case TRANS_DDI_MODE_SELECT_DVI:
2483 2484
		pipe_config->lane_count = 4;
		break;
2485 2486 2487 2488
	case TRANS_DDI_MODE_SELECT_FDI:
		break;
	case TRANS_DDI_MODE_SELECT_DP_SST:
	case TRANS_DDI_MODE_SELECT_DP_MST:
2489 2490
		pipe_config->lane_count =
			((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
2491 2492 2493 2494 2495
		intel_dp_get_m_n(intel_crtc, pipe_config);
		break;
	default:
		break;
	}
2496

2497 2498
	pipe_config->has_audio =
		intel_ddi_is_audio_enabled(dev_priv, intel_crtc);
2499

2500 2501
	if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
	    pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515
		/*
		 * This is a big fat ugly hack.
		 *
		 * Some machines in UEFI boot mode provide us a VBT that has 18
		 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
		 * unknown we fail to light up. Yet the same BIOS boots up with
		 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
		 * max, not what it tells us to use.
		 *
		 * Note: This will still be broken if the eDP panel is not lit
		 * up by the BIOS, and thus we can't get the mode at module
		 * load.
		 */
		DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2516 2517
			      pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
		dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2518
	}
2519

2520
	intel_ddi_clock_get(encoder, pipe_config);
2521

2522
	if (IS_GEN9_LP(dev_priv))
2523 2524
		pipe_config->lane_lat_optim_mask =
			bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
2525 2526
}

2527
static bool intel_ddi_compute_config(struct intel_encoder *encoder,
2528 2529
				     struct intel_crtc_state *pipe_config,
				     struct drm_connector_state *conn_state)
P
Paulo Zanoni 已提交
2530
{
2531
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2532
	int type = encoder->type;
2533
	int port = intel_ddi_get_encoder_port(encoder);
2534
	int ret;
P
Paulo Zanoni 已提交
2535

2536
	WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
P
Paulo Zanoni 已提交
2537

2538 2539 2540
	if (port == PORT_A)
		pipe_config->cpu_transcoder = TRANSCODER_EDP;

P
Paulo Zanoni 已提交
2541
	if (type == INTEL_OUTPUT_HDMI)
2542
		ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
P
Paulo Zanoni 已提交
2543
	else
2544
		ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
2545

2546
	if (IS_GEN9_LP(dev_priv) && ret)
2547 2548
		pipe_config->lane_lat_optim_mask =
			bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
2549
							     pipe_config->lane_count);
2550 2551 2552

	return ret;

P
Paulo Zanoni 已提交
2553 2554 2555
}

static const struct drm_encoder_funcs intel_ddi_funcs = {
2556 2557
	.reset = intel_dp_encoder_reset,
	.destroy = intel_dp_encoder_destroy,
P
Paulo Zanoni 已提交
2558 2559
};

2560 2561 2562 2563 2564 2565
static struct intel_connector *
intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
{
	struct intel_connector *connector;
	enum port port = intel_dig_port->port;

2566
	connector = intel_connector_alloc();
2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584
	if (!connector)
		return NULL;

	intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
	if (!intel_dp_init_connector(intel_dig_port, connector)) {
		kfree(connector);
		return NULL;
	}

	return connector;
}

static struct intel_connector *
intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
{
	struct intel_connector *connector;
	enum port port = intel_dig_port->port;

2585
	connector = intel_connector_alloc();
2586 2587 2588 2589 2590 2591 2592 2593 2594
	if (!connector)
		return NULL;

	intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
	intel_hdmi_init_connector(intel_dig_port, connector);

	return connector;
}

2595
void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
P
Paulo Zanoni 已提交
2596 2597 2598 2599
{
	struct intel_digital_port *intel_dig_port;
	struct intel_encoder *intel_encoder;
	struct drm_encoder *encoder;
2600
	bool init_hdmi, init_dp, init_lspcon = false;
2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627
	int max_lanes;

	if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
		switch (port) {
		case PORT_A:
			max_lanes = 4;
			break;
		case PORT_E:
			max_lanes = 0;
			break;
		default:
			max_lanes = 4;
			break;
		}
	} else {
		switch (port) {
		case PORT_A:
			max_lanes = 2;
			break;
		case PORT_E:
			max_lanes = 2;
			break;
		default:
			max_lanes = 4;
			break;
		}
	}
2628 2629 2630 2631

	init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
		     dev_priv->vbt.ddi_port_info[port].supports_hdmi);
	init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644

	if (intel_bios_is_lspcon_present(dev_priv, port)) {
		/*
		 * Lspcon device needs to be driven with DP connector
		 * with special detection sequence. So make sure DP
		 * is initialized before lspcon.
		 */
		init_dp = true;
		init_lspcon = true;
		init_hdmi = false;
		DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
	}

2645
	if (!init_dp && !init_hdmi) {
2646
		DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
2647
			      port_name(port));
2648
		return;
2649
	}
P
Paulo Zanoni 已提交
2650

2651
	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
P
Paulo Zanoni 已提交
2652 2653 2654 2655 2656 2657
	if (!intel_dig_port)
		return;

	intel_encoder = &intel_dig_port->base;
	encoder = &intel_encoder->base;

2658
	drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
2659
			 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
P
Paulo Zanoni 已提交
2660

2661
	intel_encoder->compute_config = intel_ddi_compute_config;
P
Paulo Zanoni 已提交
2662
	intel_encoder->enable = intel_enable_ddi;
2663
	if (IS_GEN9_LP(dev_priv))
2664
		intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
P
Paulo Zanoni 已提交
2665 2666 2667 2668
	intel_encoder->pre_enable = intel_ddi_pre_enable;
	intel_encoder->disable = intel_disable_ddi;
	intel_encoder->post_disable = intel_ddi_post_disable;
	intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2669
	intel_encoder->get_config = intel_ddi_get_config;
2670
	intel_encoder->suspend = intel_dp_encoder_suspend;
2671
	intel_encoder->get_power_domains = intel_ddi_get_power_domains;
P
Paulo Zanoni 已提交
2672 2673

	intel_dig_port->port = port;
2674 2675 2676
	intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
					  (DDI_BUF_PORT_REVERSAL |
					   DDI_A_4_LANES);
P
Paulo Zanoni 已提交
2677

2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702
	switch (port) {
	case PORT_A:
		intel_dig_port->ddi_io_power_domain =
			POWER_DOMAIN_PORT_DDI_A_IO;
		break;
	case PORT_B:
		intel_dig_port->ddi_io_power_domain =
			POWER_DOMAIN_PORT_DDI_B_IO;
		break;
	case PORT_C:
		intel_dig_port->ddi_io_power_domain =
			POWER_DOMAIN_PORT_DDI_C_IO;
		break;
	case PORT_D:
		intel_dig_port->ddi_io_power_domain =
			POWER_DOMAIN_PORT_DDI_D_IO;
		break;
	case PORT_E:
		intel_dig_port->ddi_io_power_domain =
			POWER_DOMAIN_PORT_DDI_E_IO;
		break;
	default:
		MISSING_CASE(port);
	}

2703 2704 2705 2706 2707 2708 2709
	/*
	 * Bspec says that DDI_A_4_LANES is the only supported configuration
	 * for Broxton.  Yet some BIOS fail to set this bit on port A if eDP
	 * wasn't lit up at boot.  Force this bit on in our internal
	 * configuration so that we use the proper lane count for our
	 * calculations.
	 */
2710
	if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
2711 2712 2713
		if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
			DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
			intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
2714
			max_lanes = 4;
2715 2716 2717
		}
	}

2718 2719
	intel_dig_port->max_lanes = max_lanes;

P
Paulo Zanoni 已提交
2720
	intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
2721
	intel_encoder->power_domain = intel_port_to_power_domain(port);
2722
	intel_encoder->port = port;
2723
	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2724
	intel_encoder->cloneable = 0;
P
Paulo Zanoni 已提交
2725

2726 2727 2728
	if (init_dp) {
		if (!intel_ddi_init_dp_connector(intel_dig_port))
			goto err;
2729

2730
		intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2731
		dev_priv->hotplug.irq_port[port] = intel_dig_port;
2732
	}
2733

2734 2735
	/* In theory we don't need the encoder->type check, but leave it just in
	 * case we have some really bad VBTs... */
2736 2737 2738
	if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
		if (!intel_ddi_init_hdmi_connector(intel_dig_port))
			goto err;
2739
	}
2740

2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754
	if (init_lspcon) {
		if (lspcon_init(intel_dig_port))
			/* TODO: handle hdmi info frame part */
			DRM_DEBUG_KMS("LSPCON init success on port %c\n",
				port_name(port));
		else
			/*
			 * LSPCON init faied, but DP init was success, so
			 * lets try to drive as DP++ port.
			 */
			DRM_ERROR("LSPCON init failed on port %c\n",
				port_name(port));
	}

2755 2756 2757 2758 2759
	return;

err:
	drm_encoder_cleanup(encoder);
	kfree(intel_dig_port);
P
Paulo Zanoni 已提交
2760
}