intel_ddi.c 65.8 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
/*
 * Copyright © 2012 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eugeni Dodonov <eugeni.dodonov@intel.com>
 *
 */

#include "i915_drv.h"
#include "intel_drv.h"

31 32 33
struct ddi_buf_trans {
	u32 trans1;	/* balance leg enable, de-emph level */
	u32 trans2;	/* vref sel, vswing */
34
	u8 i_boost;	/* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
35 36
};

37 38 39 40 41 42 43 44 45 46 47 48 49
static const u8 index_to_dp_signal_levels[] = {
	[0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
	[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
	[2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
	[3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
	[4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
	[5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
	[6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
	[7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
	[8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
	[9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
};

50 51 52 53
/* HDMI/DVI modes ignore everything but the last 2 items. So we share
 * them for both DP and FDI transports, allowing those ports to
 * automatically adapt to HDMI connections as well
 */
54
static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
55 56 57 58 59 60 61 62 63
	{ 0x00FFFFFF, 0x0006000E, 0x0 },
	{ 0x00D75FFF, 0x0005000A, 0x0 },
	{ 0x00C30FFF, 0x00040006, 0x0 },
	{ 0x80AAAFFF, 0x000B0000, 0x0 },
	{ 0x00FFFFFF, 0x0005000A, 0x0 },
	{ 0x00D75FFF, 0x000C0004, 0x0 },
	{ 0x80C30FFF, 0x000B0000, 0x0 },
	{ 0x00FFFFFF, 0x00040006, 0x0 },
	{ 0x80D75FFF, 0x000B0000, 0x0 },
64 65
};

66
static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
67 68 69 70 71 72 73 74 75
	{ 0x00FFFFFF, 0x0007000E, 0x0 },
	{ 0x00D75FFF, 0x000F000A, 0x0 },
	{ 0x00C30FFF, 0x00060006, 0x0 },
	{ 0x00AAAFFF, 0x001E0000, 0x0 },
	{ 0x00FFFFFF, 0x000F000A, 0x0 },
	{ 0x00D75FFF, 0x00160004, 0x0 },
	{ 0x00C30FFF, 0x001E0000, 0x0 },
	{ 0x00FFFFFF, 0x00060006, 0x0 },
	{ 0x00D75FFF, 0x001E0000, 0x0 },
76 77
};

78 79
static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
					/* Idx	NT mV d	T mV d	db	*/
80 81 82 83 84 85 86 87 88 89 90 91
	{ 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:	400	400	0	*/
	{ 0x00E79FFF, 0x000E000C, 0x0 },/* 1:	400	500	2	*/
	{ 0x00D75FFF, 0x0005000A, 0x0 },/* 2:	400	600	3.5	*/
	{ 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:	600	600	0	*/
	{ 0x00E79FFF, 0x001D0007, 0x0 },/* 4:	600	750	2	*/
	{ 0x00D75FFF, 0x000C0004, 0x0 },/* 5:	600	900	3.5	*/
	{ 0x00FFFFFF, 0x00040006, 0x0 },/* 6:	800	800	0	*/
	{ 0x80E79FFF, 0x00030002, 0x0 },/* 7:	800	1000	2	*/
	{ 0x00FFFFFF, 0x00140005, 0x0 },/* 8:	850	850	0	*/
	{ 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:	900	900	0	*/
	{ 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:	950	950	0	*/
	{ 0x80FFFFFF, 0x00030002, 0x0 },/* 11:	1000	1000	0	*/
92 93
};

94
static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
95 96 97 98 99 100 101 102 103
	{ 0x00FFFFFF, 0x00000012, 0x0 },
	{ 0x00EBAFFF, 0x00020011, 0x0 },
	{ 0x00C71FFF, 0x0006000F, 0x0 },
	{ 0x00AAAFFF, 0x000E000A, 0x0 },
	{ 0x00FFFFFF, 0x00020011, 0x0 },
	{ 0x00DB6FFF, 0x0005000F, 0x0 },
	{ 0x00BEEFFF, 0x000A000C, 0x0 },
	{ 0x00FFFFFF, 0x0005000F, 0x0 },
	{ 0x00DB6FFF, 0x000A000C, 0x0 },
104 105
};

106
static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
107 108 109 110 111 112 113 114 115
	{ 0x00FFFFFF, 0x0007000E, 0x0 },
	{ 0x00D75FFF, 0x000E000A, 0x0 },
	{ 0x00BEFFFF, 0x00140006, 0x0 },
	{ 0x80B2CFFF, 0x001B0002, 0x0 },
	{ 0x00FFFFFF, 0x000E000A, 0x0 },
	{ 0x00DB6FFF, 0x00160005, 0x0 },
	{ 0x80C71FFF, 0x001A0002, 0x0 },
	{ 0x00F7DFFF, 0x00180004, 0x0 },
	{ 0x80D75FFF, 0x001B0002, 0x0 },
116 117
};

118
static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
119 120 121 122 123 124 125 126 127
	{ 0x00FFFFFF, 0x0001000E, 0x0 },
	{ 0x00D75FFF, 0x0004000A, 0x0 },
	{ 0x00C30FFF, 0x00070006, 0x0 },
	{ 0x00AAAFFF, 0x000C0000, 0x0 },
	{ 0x00FFFFFF, 0x0004000A, 0x0 },
	{ 0x00D75FFF, 0x00090004, 0x0 },
	{ 0x00C30FFF, 0x000C0000, 0x0 },
	{ 0x00FFFFFF, 0x00070006, 0x0 },
	{ 0x00D75FFF, 0x000C0000, 0x0 },
128 129
};

130 131
static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
					/* Idx	NT mV d	T mV df	db	*/
132 133 134 135 136 137 138 139 140 141
	{ 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:	400	400	0	*/
	{ 0x00D75FFF, 0x000E000A, 0x0 },/* 1:	400	600	3.5	*/
	{ 0x00BEFFFF, 0x00140006, 0x0 },/* 2:	400	800	6	*/
	{ 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:	450	450	0	*/
	{ 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:	600	600	0	*/
	{ 0x00D7FFFF, 0x00140006, 0x0 },/* 5:	600	800	2.5	*/
	{ 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:	600	1000	4.5	*/
	{ 0x00FFFFFF, 0x00140006, 0x0 },/* 7:	800	800	0	*/
	{ 0x80E79FFF, 0x001B0002, 0x0 },/* 8:	800	1000	2	*/
	{ 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:	1000	1000	0	*/
142 143
};

144
/* Skylake H and S */
145
static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
146 147 148
	{ 0x00002016, 0x000000A0, 0x0 },
	{ 0x00005012, 0x0000009B, 0x0 },
	{ 0x00007011, 0x00000088, 0x0 },
149
	{ 0x80009010, 0x000000C0, 0x1 },
150 151
	{ 0x00002016, 0x0000009B, 0x0 },
	{ 0x00005012, 0x00000088, 0x0 },
152
	{ 0x80007011, 0x000000C0, 0x1 },
153
	{ 0x00002016, 0x000000DF, 0x0 },
154
	{ 0x80005012, 0x000000C0, 0x1 },
155 156
};

157 158
/* Skylake U */
static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
159
	{ 0x0000201B, 0x000000A2, 0x0 },
160
	{ 0x00005012, 0x00000088, 0x0 },
161
	{ 0x80007011, 0x000000CD, 0x1 },
162
	{ 0x80009010, 0x000000C0, 0x1 },
163
	{ 0x0000201B, 0x0000009D, 0x0 },
164 165
	{ 0x80005012, 0x000000C0, 0x1 },
	{ 0x80007011, 0x000000C0, 0x1 },
166
	{ 0x00002016, 0x00000088, 0x0 },
167
	{ 0x80005012, 0x000000C0, 0x1 },
168 169
};

170 171
/* Skylake Y */
static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
172 173
	{ 0x00000018, 0x000000A2, 0x0 },
	{ 0x00005012, 0x00000088, 0x0 },
174
	{ 0x80007011, 0x000000CD, 0x3 },
175
	{ 0x80009010, 0x000000C0, 0x3 },
176
	{ 0x00000018, 0x0000009D, 0x0 },
177 178
	{ 0x80005012, 0x000000C0, 0x3 },
	{ 0x80007011, 0x000000C0, 0x3 },
179
	{ 0x00000018, 0x00000088, 0x0 },
180
	{ 0x80005012, 0x000000C0, 0x3 },
181 182
};

183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221
/* Kabylake H and S */
static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
	{ 0x00002016, 0x000000A0, 0x0 },
	{ 0x00005012, 0x0000009B, 0x0 },
	{ 0x00007011, 0x00000088, 0x0 },
	{ 0x80009010, 0x000000C0, 0x1 },
	{ 0x00002016, 0x0000009B, 0x0 },
	{ 0x00005012, 0x00000088, 0x0 },
	{ 0x80007011, 0x000000C0, 0x1 },
	{ 0x00002016, 0x00000097, 0x0 },
	{ 0x80005012, 0x000000C0, 0x1 },
};

/* Kabylake U */
static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
	{ 0x0000201B, 0x000000A1, 0x0 },
	{ 0x00005012, 0x00000088, 0x0 },
	{ 0x80007011, 0x000000CD, 0x3 },
	{ 0x80009010, 0x000000C0, 0x3 },
	{ 0x0000201B, 0x0000009D, 0x0 },
	{ 0x80005012, 0x000000C0, 0x3 },
	{ 0x80007011, 0x000000C0, 0x3 },
	{ 0x00002016, 0x0000004F, 0x0 },
	{ 0x80005012, 0x000000C0, 0x3 },
};

/* Kabylake Y */
static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
	{ 0x00001017, 0x000000A1, 0x0 },
	{ 0x00005012, 0x00000088, 0x0 },
	{ 0x80007011, 0x000000CD, 0x3 },
	{ 0x8000800F, 0x000000C0, 0x3 },
	{ 0x00001017, 0x0000009D, 0x0 },
	{ 0x80005012, 0x000000C0, 0x3 },
	{ 0x80007011, 0x000000C0, 0x3 },
	{ 0x00001017, 0x0000004C, 0x0 },
	{ 0x80005012, 0x000000C0, 0x3 },
};

222
/*
223
 * Skylake/Kabylake H and S
224 225
 * eDP 1.4 low vswing translation parameters
 */
226
static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
227 228 229 230 231 232 233 234 235 236 237 238 239
	{ 0x00000018, 0x000000A8, 0x0 },
	{ 0x00004013, 0x000000A9, 0x0 },
	{ 0x00007011, 0x000000A2, 0x0 },
	{ 0x00009010, 0x0000009C, 0x0 },
	{ 0x00000018, 0x000000A9, 0x0 },
	{ 0x00006013, 0x000000A2, 0x0 },
	{ 0x00007011, 0x000000A6, 0x0 },
	{ 0x00000018, 0x000000AB, 0x0 },
	{ 0x00007013, 0x0000009F, 0x0 },
	{ 0x00000018, 0x000000DF, 0x0 },
};

/*
240
 * Skylake/Kabylake U
241 242 243 244 245 246 247 248 249 250 251 252 253
 * eDP 1.4 low vswing translation parameters
 */
static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
	{ 0x00000018, 0x000000A8, 0x0 },
	{ 0x00004013, 0x000000A9, 0x0 },
	{ 0x00007011, 0x000000A2, 0x0 },
	{ 0x00009010, 0x0000009C, 0x0 },
	{ 0x00000018, 0x000000A9, 0x0 },
	{ 0x00006013, 0x000000A2, 0x0 },
	{ 0x00007011, 0x000000A6, 0x0 },
	{ 0x00002016, 0x000000AB, 0x0 },
	{ 0x00005013, 0x0000009F, 0x0 },
	{ 0x00000018, 0x000000DF, 0x0 },
254 255
};

256
/*
257
 * Skylake/Kabylake Y
258 259
 * eDP 1.4 low vswing translation parameters
 */
260
static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
261 262 263 264 265 266 267 268 269 270 271
	{ 0x00000018, 0x000000A8, 0x0 },
	{ 0x00004013, 0x000000AB, 0x0 },
	{ 0x00007011, 0x000000A4, 0x0 },
	{ 0x00009010, 0x000000DF, 0x0 },
	{ 0x00000018, 0x000000AA, 0x0 },
	{ 0x00006013, 0x000000A4, 0x0 },
	{ 0x00007011, 0x0000009D, 0x0 },
	{ 0x00000018, 0x000000A0, 0x0 },
	{ 0x00006012, 0x000000DF, 0x0 },
	{ 0x00000018, 0x0000008A, 0x0 },
};
272

273
/* Skylake/Kabylake U, H and S */
274
static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
275 276 277 278 279 280
	{ 0x00000018, 0x000000AC, 0x0 },
	{ 0x00005012, 0x0000009D, 0x0 },
	{ 0x00007011, 0x00000088, 0x0 },
	{ 0x00000018, 0x000000A1, 0x0 },
	{ 0x00000018, 0x00000098, 0x0 },
	{ 0x00004013, 0x00000088, 0x0 },
281
	{ 0x80006012, 0x000000CD, 0x1 },
282
	{ 0x00000018, 0x000000DF, 0x0 },
283 284 285
	{ 0x80003015, 0x000000CD, 0x1 },	/* Default */
	{ 0x80003015, 0x000000C0, 0x1 },
	{ 0x80000018, 0x000000C0, 0x1 },
286 287
};

288
/* Skylake/Kabylake Y */
289
static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
290 291
	{ 0x00000018, 0x000000A1, 0x0 },
	{ 0x00005012, 0x000000DF, 0x0 },
292
	{ 0x80007011, 0x000000CB, 0x3 },
293 294 295
	{ 0x00000018, 0x000000A4, 0x0 },
	{ 0x00000018, 0x0000009D, 0x0 },
	{ 0x00004013, 0x00000080, 0x0 },
296
	{ 0x80006013, 0x000000C0, 0x3 },
297
	{ 0x00000018, 0x0000008A, 0x0 },
298 299 300
	{ 0x80003015, 0x000000C0, 0x3 },	/* Default */
	{ 0x80003015, 0x000000C0, 0x3 },
	{ 0x80000018, 0x000000C0, 0x3 },
301 302
};

303 304 305 306 307 308 309 310 311 312
struct bxt_ddi_buf_trans {
	u32 margin;	/* swing value */
	u32 scale;	/* scale value */
	u32 enable;	/* scale enable */
	u32 deemphasis;
	bool default_index; /* true if the entry represents default value */
};

static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
					/* Idx	NT mV diff	db  */
313 314 315 316 317 318 319 320 321
	{ 52,  0x9A, 0, 128, true  },	/* 0:	400		0   */
	{ 78,  0x9A, 0, 85,  false },	/* 1:	400		3.5 */
	{ 104, 0x9A, 0, 64,  false },	/* 2:	400		6   */
	{ 154, 0x9A, 0, 43,  false },	/* 3:	400		9.5 */
	{ 77,  0x9A, 0, 128, false },	/* 4:	600		0   */
	{ 116, 0x9A, 0, 85,  false },	/* 5:	600		3.5 */
	{ 154, 0x9A, 0, 64,  false },	/* 6:	600		6   */
	{ 102, 0x9A, 0, 128, false },	/* 7:	800		0   */
	{ 154, 0x9A, 0, 85,  false },	/* 8:	800		3.5 */
322
	{ 154, 0x9A, 1, 128, false },	/* 9:	1200		0   */
323 324
};

325 326 327 328 329 330 331 332 333 334 335 336 337 338
static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
					/* Idx	NT mV diff	db  */
	{ 26, 0, 0, 128, false },	/* 0:	200		0   */
	{ 38, 0, 0, 112, false },	/* 1:	200		1.5 */
	{ 48, 0, 0, 96,  false },	/* 2:	200		4   */
	{ 54, 0, 0, 69,  false },	/* 3:	200		6   */
	{ 32, 0, 0, 128, false },	/* 4:	250		0   */
	{ 48, 0, 0, 104, false },	/* 5:	250		1.5 */
	{ 54, 0, 0, 85,  false },	/* 6:	250		4   */
	{ 43, 0, 0, 128, false },	/* 7:	300		0   */
	{ 54, 0, 0, 101, false },	/* 8:	300		1.5 */
	{ 48, 0, 0, 128, false },	/* 9:	300		0   */
};

339 340 341 342 343
/* BSpec has 2 recommended values - entries 0 and 8.
 * Using the entry with higher vswing.
 */
static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
					/* Idx	NT mV diff	db  */
344 345 346 347 348 349 350 351 352
	{ 52,  0x9A, 0, 128, false },	/* 0:	400		0   */
	{ 52,  0x9A, 0, 85,  false },	/* 1:	400		3.5 */
	{ 52,  0x9A, 0, 64,  false },	/* 2:	400		6   */
	{ 42,  0x9A, 0, 43,  false },	/* 3:	400		9.5 */
	{ 77,  0x9A, 0, 128, false },	/* 4:	600		0   */
	{ 77,  0x9A, 0, 85,  false },	/* 5:	600		3.5 */
	{ 77,  0x9A, 0, 64,  false },	/* 6:	600		6   */
	{ 102, 0x9A, 0, 128, false },	/* 7:	800		0   */
	{ 102, 0x9A, 0, 85,  false },	/* 8:	800		3.5 */
353 354 355
	{ 154, 0x9A, 1, 128, true },	/* 9:	1200		0   */
};

356
enum port intel_ddi_get_encoder_port(struct intel_encoder *encoder)
357
{
358
	switch (encoder->type) {
359
	case INTEL_OUTPUT_DP_MST:
360
		return enc_to_mst(&encoder->base)->primary->port;
361
	case INTEL_OUTPUT_DP:
362 363 364
	case INTEL_OUTPUT_EDP:
	case INTEL_OUTPUT_HDMI:
	case INTEL_OUTPUT_UNKNOWN:
365
		return enc_to_dig_port(&encoder->base)->port;
366
	case INTEL_OUTPUT_ANALOG:
367 368 369 370
		return PORT_E;
	default:
		MISSING_CASE(encoder->type);
		return PORT_A;
371 372 373
	}
}

374 375 376 377 378 379 380 381 382 383 384 385
static const struct ddi_buf_trans *
bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
{
	if (dev_priv->vbt.edp.low_vswing) {
		*n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
		return bdw_ddi_translations_edp;
	} else {
		*n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
		return bdw_ddi_translations_dp;
	}
}

386
static const struct ddi_buf_trans *
387
skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
388
{
389
	if (IS_SKL_ULX(dev_priv)) {
390
		*n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
391
		return skl_y_ddi_translations_dp;
392
	} else if (IS_SKL_ULT(dev_priv)) {
393
		*n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
394
		return skl_u_ddi_translations_dp;
395 396
	} else {
		*n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
397
		return skl_ddi_translations_dp;
398 399 400
	}
}

401 402 403 404 405 406 407 408 409 410 411 412 413 414 415
static const struct ddi_buf_trans *
kbl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
{
	if (IS_KBL_ULX(dev_priv)) {
		*n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
		return kbl_y_ddi_translations_dp;
	} else if (IS_KBL_ULT(dev_priv)) {
		*n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
		return kbl_u_ddi_translations_dp;
	} else {
		*n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
		return kbl_ddi_translations_dp;
	}
}

416
static const struct ddi_buf_trans *
417
skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
418
{
419
	if (dev_priv->vbt.edp.low_vswing) {
420
		if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
421
			*n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
422
			return skl_y_ddi_translations_edp;
423
		} else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
424
			*n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
425
			return skl_u_ddi_translations_edp;
426 427
		} else {
			*n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
428
			return skl_ddi_translations_edp;
429 430
		}
	}
431

432 433 434 435
	if (IS_KABYLAKE(dev_priv))
		return kbl_get_buf_trans_dp(dev_priv, n_entries);
	else
		return skl_get_buf_trans_dp(dev_priv, n_entries);
436 437 438
}

static const struct ddi_buf_trans *
439
skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
440
{
441
	if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
442
		*n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
443
		return skl_y_ddi_translations_hdmi;
444 445
	} else {
		*n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
446
		return skl_ddi_translations_hdmi;
447 448 449
	}
}

450 451 452 453 454 455 456 457
static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
{
	int n_hdmi_entries;
	int hdmi_level;
	int hdmi_default_entry;

	hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;

458
	if (IS_GEN9_LP(dev_priv))
459 460
		return hdmi_level;

461
	if (IS_GEN9_BC(dev_priv)) {
462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483
		skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
		hdmi_default_entry = 8;
	} else if (IS_BROADWELL(dev_priv)) {
		n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
		hdmi_default_entry = 7;
	} else if (IS_HASWELL(dev_priv)) {
		n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
		hdmi_default_entry = 6;
	} else {
		WARN(1, "ddi translation table missing\n");
		n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
		hdmi_default_entry = 7;
	}

	/* Choose a good default if VBT is badly populated */
	if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
	    hdmi_level >= n_hdmi_entries)
		hdmi_level = hdmi_default_entry;

	return hdmi_level;
}

484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536
static const struct ddi_buf_trans *
intel_ddi_get_buf_trans_dp(struct drm_i915_private *dev_priv,
			   int *n_entries)
{
	if (IS_KABYLAKE(dev_priv)) {
		return kbl_get_buf_trans_dp(dev_priv, n_entries);
	} else if (IS_SKYLAKE(dev_priv)) {
		return skl_get_buf_trans_dp(dev_priv, n_entries);
	} else if (IS_BROADWELL(dev_priv)) {
		*n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
		return  bdw_ddi_translations_dp;
	} else if (IS_HASWELL(dev_priv)) {
		*n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
		return hsw_ddi_translations_dp;
	}

	*n_entries = 0;
	return NULL;
}

static const struct ddi_buf_trans *
intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv,
			    int *n_entries)
{
	if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv)) {
		return skl_get_buf_trans_edp(dev_priv, n_entries);
	} else if (IS_BROADWELL(dev_priv)) {
		return bdw_get_buf_trans_edp(dev_priv, n_entries);
	} else if (IS_HASWELL(dev_priv)) {
		*n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
		return hsw_ddi_translations_dp;
	}

	*n_entries = 0;
	return NULL;
}

static const struct ddi_buf_trans *
intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
			    int *n_entries)
{
	if (IS_BROADWELL(dev_priv)) {
		*n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
		return hsw_ddi_translations_fdi;
	} else if (IS_HASWELL(dev_priv)) {
		*n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
		return hsw_ddi_translations_fdi;
	}

	*n_entries = 0;
	return NULL;
}

537 538
/*
 * Starting with Haswell, DDI port buffers must be programmed with correct
539 540
 * values in advance. This function programs the correct values for
 * DP/eDP/FDI use cases.
541
 */
542
static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder)
543
{
544
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
545
	u32 iboost_bit = 0;
546
	int i, n_entries;
547
	enum port port = intel_ddi_get_encoder_port(encoder);
548
	const struct ddi_buf_trans *ddi_translations;
549

550
	if (IS_GEN9_LP(dev_priv))
551
		return;
552

553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568
	switch (encoder->type) {
	case INTEL_OUTPUT_EDP:
		ddi_translations = intel_ddi_get_buf_trans_edp(dev_priv,
							       &n_entries);
		break;
	case INTEL_OUTPUT_DP:
		ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv,
							      &n_entries);
		break;
	case INTEL_OUTPUT_ANALOG:
		ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
							       &n_entries);
		break;
	default:
		MISSING_CASE(encoder->type);
		return;
569 570
	}

571
	if (IS_GEN9_BC(dev_priv)) {
572 573 574 575 576 577
		/* If we're boosting the current, set bit 31 of trans1 */
		if (dev_priv->vbt.ddi_port_info[port].dp_boost_level)
			iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;

		if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
			    port != PORT_A && port != PORT_E &&
578 579
			    n_entries > 9))
			n_entries = 9;
580
	}
581

582
	for (i = 0; i < n_entries; i++) {
583 584 585 586
		I915_WRITE(DDI_BUF_TRANS_LO(port, i),
			   ddi_translations[i].trans1 | iboost_bit);
		I915_WRITE(DDI_BUF_TRANS_HI(port, i),
			   ddi_translations[i].trans2);
587
	}
588 589 590 591 592 593 594 595 596 597 598 599 600 601
}

/*
 * Starting with Haswell, DDI port buffers must be programmed with correct
 * values in advance. This function programs the correct values for
 * HDMI/DVI use cases.
 */
static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	u32 iboost_bit = 0;
	int n_hdmi_entries, hdmi_level;
	enum port port = intel_ddi_get_encoder_port(encoder);
	const struct ddi_buf_trans *ddi_translations_hdmi;
602

603
	if (IS_GEN9_LP(dev_priv))
604 605
		return;

606 607
	hdmi_level = intel_ddi_hdmi_level(dev_priv, port);

608
	if (IS_GEN9_BC(dev_priv)) {
609
		ddi_translations_hdmi = skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
610

611
		/* If we're boosting the current, set bit 31 of trans1 */
612
		if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level)
613 614 615 616 617 618 619 620 621 622 623 624 625
			iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
	} else if (IS_BROADWELL(dev_priv)) {
		ddi_translations_hdmi = bdw_ddi_translations_hdmi;
		n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
	} else if (IS_HASWELL(dev_priv)) {
		ddi_translations_hdmi = hsw_ddi_translations_hdmi;
		n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
	} else {
		WARN(1, "ddi translation table missing\n");
		ddi_translations_hdmi = bdw_ddi_translations_hdmi;
		n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
	}

626
	/* Entry 9 is for HDMI: */
627
	I915_WRITE(DDI_BUF_TRANS_LO(port, 9),
628
		   ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
629
	I915_WRITE(DDI_BUF_TRANS_HI(port, 9),
630
		   ddi_translations_hdmi[hdmi_level].trans2);
631 632
}

633 634 635
static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
				    enum port port)
{
636
	i915_reg_t reg = DDI_BUF_CTL(port);
637 638
	int i;

639
	for (i = 0; i < 16; i++) {
640 641 642 643 644 645
		udelay(1);
		if (I915_READ(reg) & DDI_BUF_IS_IDLE)
			return;
	}
	DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
}
646

647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667
static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll *pll)
{
	switch (pll->id) {
	case DPLL_ID_WRPLL1:
		return PORT_CLK_SEL_WRPLL1;
	case DPLL_ID_WRPLL2:
		return PORT_CLK_SEL_WRPLL2;
	case DPLL_ID_SPLL:
		return PORT_CLK_SEL_SPLL;
	case DPLL_ID_LCPLL_810:
		return PORT_CLK_SEL_LCPLL_810;
	case DPLL_ID_LCPLL_1350:
		return PORT_CLK_SEL_LCPLL_1350;
	case DPLL_ID_LCPLL_2700:
		return PORT_CLK_SEL_LCPLL_2700;
	default:
		MISSING_CASE(pll->id);
		return PORT_CLK_SEL_NONE;
	}
}

668 669 670 671 672 673 674 675 676
/* Starting with Haswell, different DDI ports can work in FDI mode for
 * connection to the PCH-located connectors. For this, it is necessary to train
 * both the DDI port and PCH receiver for the desired DDI buffer settings.
 *
 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
 * please note that when FDI mode is active on DDI E, it shares 2 lines with
 * DDI A (which is used for eDP)
 */

677 678
void hsw_fdi_link_train(struct intel_crtc *crtc,
			const struct intel_crtc_state *crtc_state)
679
{
680
	struct drm_device *dev = crtc->base.dev;
681
	struct drm_i915_private *dev_priv = to_i915(dev);
682
	struct intel_encoder *encoder;
683
	u32 temp, i, rx_ctl_val, ddi_pll_sel;
684

685
	for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
686
		WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
687
		intel_prepare_dp_ddi_buffers(encoder);
688 689
	}

690 691 692 693
	/* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
	 * mode set "sequence for CRT port" document:
	 * - TP1 to TP2 time with the default value
	 * - FDI delay to 90h
694 695
	 *
	 * WaFDIAutoLinkSetTimingOverrride:hsw
696
	 */
697
	I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
698 699 700 701
				  FDI_RX_PWRDN_LANE0_VAL(2) |
				  FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);

	/* Enable the PCH Receiver FDI PLL */
702
	rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
703
		     FDI_RX_PLL_ENABLE |
704
		     FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
705 706
	I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
	POSTING_READ(FDI_RX_CTL(PIPE_A));
707 708 709 710
	udelay(220);

	/* Switch from Rawclk to PCDclk */
	rx_ctl_val |= FDI_PCDCLK;
711
	I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
712 713

	/* Configure Port Clock Select */
714
	ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
715 716
	I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
	WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
717 718 719

	/* Start the training iterating through available voltages and emphasis,
	 * testing each value twice. */
720
	for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
721 722 723 724 725 726 727
		/* Configure DP_TP_CTL with auto-training */
		I915_WRITE(DP_TP_CTL(PORT_E),
					DP_TP_CTL_FDI_AUTOTRAIN |
					DP_TP_CTL_ENHANCED_FRAME_ENABLE |
					DP_TP_CTL_LINK_TRAIN_PAT1 |
					DP_TP_CTL_ENABLE);

728 729 730 731
		/* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
		 * DDI E does not support port reversal, the functionality is
		 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
		 * port reversal bit */
732
		I915_WRITE(DDI_BUF_CTL(PORT_E),
733
			   DDI_BUF_CTL_ENABLE |
734
			   ((crtc_state->fdi_lanes - 1) << 1) |
735
			   DDI_BUF_TRANS_SELECT(i / 2));
736
		POSTING_READ(DDI_BUF_CTL(PORT_E));
737 738 739

		udelay(600);

740
		/* Program PCH FDI Receiver TU */
741
		I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
742 743 744

		/* Enable PCH FDI Receiver with auto-training */
		rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
745 746
		I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
		POSTING_READ(FDI_RX_CTL(PIPE_A));
747 748 749 750 751

		/* Wait for FDI receiver lane calibration */
		udelay(30);

		/* Unset FDI_RX_MISC pwrdn lanes */
752
		temp = I915_READ(FDI_RX_MISC(PIPE_A));
753
		temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
754 755
		I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
		POSTING_READ(FDI_RX_MISC(PIPE_A));
756 757 758

		/* Wait for FDI auto training time */
		udelay(5);
759 760 761

		temp = I915_READ(DP_TP_STATUS(PORT_E));
		if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
762
			DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
763 764
			break;
		}
765

766 767 768 769 770 771 772
		/*
		 * Leave things enabled even if we failed to train FDI.
		 * Results in less fireworks from the state checker.
		 */
		if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
			DRM_ERROR("FDI link training failed!\n");
			break;
773
		}
774

775 776 777 778
		rx_ctl_val &= ~FDI_RX_ENABLE;
		I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
		POSTING_READ(FDI_RX_CTL(PIPE_A));

779 780 781 782 783
		temp = I915_READ(DDI_BUF_CTL(PORT_E));
		temp &= ~DDI_BUF_CTL_ENABLE;
		I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
		POSTING_READ(DDI_BUF_CTL(PORT_E));

784
		/* Disable DP_TP_CTL and FDI_RX_CTL and retry */
785 786 787 788 789 790 791
		temp = I915_READ(DP_TP_CTL(PORT_E));
		temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
		temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
		I915_WRITE(DP_TP_CTL(PORT_E), temp);
		POSTING_READ(DP_TP_CTL(PORT_E));

		intel_wait_ddi_buf_idle(dev_priv, PORT_E);
792 793

		/* Reset FDI_RX_MISC pwrdn lanes */
794
		temp = I915_READ(FDI_RX_MISC(PIPE_A));
795 796
		temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
		temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
797 798
		I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
		POSTING_READ(FDI_RX_MISC(PIPE_A));
799 800
	}

801 802 803 804 805 806
	/* Enable normal pixel sending for FDI */
	I915_WRITE(DP_TP_CTL(PORT_E),
		   DP_TP_CTL_FDI_AUTOTRAIN |
		   DP_TP_CTL_LINK_TRAIN_NORMAL |
		   DP_TP_CTL_ENHANCED_FRAME_ENABLE |
		   DP_TP_CTL_ENABLE);
807
}
808

809
static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
810 811 812 813 814 815
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct intel_digital_port *intel_dig_port =
		enc_to_dig_port(&encoder->base);

	intel_dp->DP = intel_dig_port->saved_port_bits |
816
		DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
817
	intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
818 819
}

820
static struct intel_encoder *
821
intel_ddi_get_crtc_encoder(struct intel_crtc *crtc)
822
{
823
	struct drm_device *dev = crtc->base.dev;
824
	struct intel_encoder *encoder, *ret = NULL;
825 826
	int num_encoders = 0;

827 828
	for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
		ret = encoder;
829 830 831 832
		num_encoders++;
	}

	if (num_encoders != 1)
833
		WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
834
		     pipe_name(crtc->pipe));
835 836 837 838 839

	BUG_ON(ret == NULL);
	return ret;
}

840 841
/* Finds the only possible encoder associated with the given CRTC. */
struct intel_encoder *
842
intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
843
{
844 845 846
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
	struct intel_encoder *ret = NULL;
	struct drm_atomic_state *state;
847 848
	struct drm_connector *connector;
	struct drm_connector_state *connector_state;
849
	int num_encoders = 0;
850
	int i;
851

852 853
	state = crtc_state->base.state;

854
	for_each_new_connector_in_state(state, connector, connector_state, i) {
855
		if (connector_state->crtc != crtc_state->base.crtc)
856 857
			continue;

858
		ret = to_intel_encoder(connector_state->best_encoder);
859
		num_encoders++;
860 861 862 863 864 865 866 867 868
	}

	WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
	     pipe_name(crtc->pipe));

	BUG_ON(ret == NULL);
	return ret;
}

869 870
#define LC_FREQ 2700

871 872
static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
				   i915_reg_t reg)
873 874 875 876 877 878
{
	int refclk = LC_FREQ;
	int n, p, r;
	u32 wrpll;

	wrpll = I915_READ(reg);
879 880 881
	switch (wrpll & WRPLL_PLL_REF_MASK) {
	case WRPLL_PLL_SSC:
	case WRPLL_PLL_NON_SSC:
882 883 884 885 886 887 888
		/*
		 * We could calculate spread here, but our checking
		 * code only cares about 5% accuracy, and spread is a max of
		 * 0.5% downspread.
		 */
		refclk = 135;
		break;
889
	case WRPLL_PLL_LCPLL:
890 891 892 893 894 895 896 897 898 899 900
		refclk = LC_FREQ;
		break;
	default:
		WARN(1, "bad wrpll refclk\n");
		return 0;
	}

	r = wrpll & WRPLL_DIVIDER_REF_MASK;
	p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
	n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;

901 902
	/* Convert to KHz, p & r have a fixed point portion */
	return (refclk * n * 100) / (p * r);
903 904
}

905 906 907
static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
			       uint32_t dpll)
{
908
	i915_reg_t cfgcr1_reg, cfgcr2_reg;
909 910 911
	uint32_t cfgcr1_val, cfgcr2_val;
	uint32_t p0, p1, p2, dco_freq;

912 913
	cfgcr1_reg = DPLL_CFGCR1(dpll);
	cfgcr2_reg = DPLL_CFGCR2(dpll);
914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964

	cfgcr1_val = I915_READ(cfgcr1_reg);
	cfgcr2_val = I915_READ(cfgcr2_reg);

	p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
	p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;

	if (cfgcr2_val &  DPLL_CFGCR2_QDIV_MODE(1))
		p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
	else
		p1 = 1;


	switch (p0) {
	case DPLL_CFGCR2_PDIV_1:
		p0 = 1;
		break;
	case DPLL_CFGCR2_PDIV_2:
		p0 = 2;
		break;
	case DPLL_CFGCR2_PDIV_3:
		p0 = 3;
		break;
	case DPLL_CFGCR2_PDIV_7:
		p0 = 7;
		break;
	}

	switch (p2) {
	case DPLL_CFGCR2_KDIV_5:
		p2 = 5;
		break;
	case DPLL_CFGCR2_KDIV_2:
		p2 = 2;
		break;
	case DPLL_CFGCR2_KDIV_3:
		p2 = 3;
		break;
	case DPLL_CFGCR2_KDIV_1:
		p2 = 1;
		break;
	}

	dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;

	dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
		1000) / 0x8000;

	return dco_freq / (p0 * p1 * p2 * 5);
}

965 966 967 968 969 970 971
static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
{
	int dotclock;

	if (pipe_config->has_pch_encoder)
		dotclock = intel_dotclock_calculate(pipe_config->port_clock,
						    &pipe_config->fdi_m_n);
972
	else if (intel_crtc_has_dp_encoder(pipe_config))
973 974 975 976 977 978 979 980 981 982 983 984
		dotclock = intel_dotclock_calculate(pipe_config->port_clock,
						    &pipe_config->dp_m_n);
	else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
		dotclock = pipe_config->port_clock * 2 / 3;
	else
		dotclock = pipe_config->port_clock;

	if (pipe_config->pixel_multiplier)
		dotclock /= pipe_config->pixel_multiplier;

	pipe_config->base.adjusted_mode.crtc_clock = dotclock;
}
985 986

static void skl_ddi_clock_get(struct intel_encoder *encoder,
987
				struct intel_crtc_state *pipe_config)
988
{
989
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
990 991 992
	int link_clock = 0;
	uint32_t dpll_ctl1, dpll;

993
	dpll = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
994 995 996 997 998 999

	dpll_ctl1 = I915_READ(DPLL_CTRL1);

	if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
		link_clock = skl_calc_wrpll_link(dev_priv, dpll);
	} else {
1000 1001
		link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
		link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
1002 1003

		switch (link_clock) {
1004
		case DPLL_CTRL1_LINK_RATE_810:
1005 1006
			link_clock = 81000;
			break;
1007
		case DPLL_CTRL1_LINK_RATE_1080:
1008 1009
			link_clock = 108000;
			break;
1010
		case DPLL_CTRL1_LINK_RATE_1350:
1011 1012
			link_clock = 135000;
			break;
1013
		case DPLL_CTRL1_LINK_RATE_1620:
1014 1015
			link_clock = 162000;
			break;
1016
		case DPLL_CTRL1_LINK_RATE_2160:
1017 1018
			link_clock = 216000;
			break;
1019
		case DPLL_CTRL1_LINK_RATE_2700:
1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030
			link_clock = 270000;
			break;
		default:
			WARN(1, "Unsupported link rate\n");
			break;
		}
		link_clock *= 2;
	}

	pipe_config->port_clock = link_clock;

1031
	ddi_dotclock_get(pipe_config);
1032 1033
}

1034
static void hsw_ddi_clock_get(struct intel_encoder *encoder,
1035
			      struct intel_crtc_state *pipe_config)
1036
{
1037
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1038 1039 1040
	int link_clock = 0;
	u32 val, pll;

1041
	val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052
	switch (val & PORT_CLK_SEL_MASK) {
	case PORT_CLK_SEL_LCPLL_810:
		link_clock = 81000;
		break;
	case PORT_CLK_SEL_LCPLL_1350:
		link_clock = 135000;
		break;
	case PORT_CLK_SEL_LCPLL_2700:
		link_clock = 270000;
		break;
	case PORT_CLK_SEL_WRPLL1:
1053
		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
1054 1055
		break;
	case PORT_CLK_SEL_WRPLL2:
1056
		link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077
		break;
	case PORT_CLK_SEL_SPLL:
		pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
		if (pll == SPLL_PLL_FREQ_810MHz)
			link_clock = 81000;
		else if (pll == SPLL_PLL_FREQ_1350MHz)
			link_clock = 135000;
		else if (pll == SPLL_PLL_FREQ_2700MHz)
			link_clock = 270000;
		else {
			WARN(1, "bad spll freq\n");
			return;
		}
		break;
	default:
		WARN(1, "bad port clock sel\n");
		return;
	}

	pipe_config->port_clock = link_clock * 2;

1078
	ddi_dotclock_get(pipe_config);
1079 1080
}

1081 1082 1083
static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
				enum intel_dpll_id dpll)
{
1084 1085
	struct intel_shared_dpll *pll;
	struct intel_dpll_hw_state *state;
1086
	struct dpll clock;
1087 1088 1089 1090 1091 1092

	/* For DDI ports we always use a shared PLL. */
	if (WARN_ON(dpll == DPLL_ID_PRIVATE))
		return 0;

	pll = &dev_priv->shared_dplls[dpll];
1093
	state = &pll->state.hw_state;
1094 1095 1096 1097 1098 1099 1100 1101 1102 1103

	clock.m1 = 2;
	clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
	if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
		clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
	clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
	clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
	clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;

	return chv_calc_dpll_params(100000, &clock);
1104 1105 1106 1107 1108
}

static void bxt_ddi_clock_get(struct intel_encoder *encoder,
				struct intel_crtc_state *pipe_config)
{
1109
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1110 1111 1112
	enum port port = intel_ddi_get_encoder_port(encoder);
	uint32_t dpll = port;

1113
	pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
1114

1115
	ddi_dotclock_get(pipe_config);
1116 1117
}

1118
void intel_ddi_clock_get(struct intel_encoder *encoder,
1119
			 struct intel_crtc_state *pipe_config)
1120
{
1121
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1122

1123
	if (INTEL_GEN(dev_priv) <= 8)
1124
		hsw_ddi_clock_get(encoder, pipe_config);
1125
	else if (IS_GEN9_BC(dev_priv))
1126
		skl_ddi_clock_get(encoder, pipe_config);
1127
	else if (IS_GEN9_LP(dev_priv))
1128
		bxt_ddi_clock_get(encoder, pipe_config);
1129 1130
}

1131
void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
1132
{
1133
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1134
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1135
	struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1136
	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1137
	int type = encoder->type;
1138 1139
	uint32_t temp;

1140
	if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
J
Jani Nikula 已提交
1141 1142
		WARN_ON(transcoder_is_dsi(cpu_transcoder));

1143
		temp = TRANS_MSA_SYNC_CLK;
1144
		switch (crtc_state->pipe_bpp) {
1145
		case 18:
1146
			temp |= TRANS_MSA_6_BPC;
1147 1148
			break;
		case 24:
1149
			temp |= TRANS_MSA_8_BPC;
1150 1151
			break;
		case 30:
1152
			temp |= TRANS_MSA_10_BPC;
1153 1154
			break;
		case 36:
1155
			temp |= TRANS_MSA_12_BPC;
1156 1157
			break;
		default:
1158
			BUG();
1159
		}
1160
		I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
1161 1162 1163
	}
}

1164 1165
void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
				    bool state)
1166
{
1167
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1168
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1169
	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1170 1171 1172 1173 1174 1175 1176 1177 1178
	uint32_t temp;
	temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
	if (state == true)
		temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
	else
		temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
	I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
}

1179
void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
1180
{
1181
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1182
	struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
1183 1184
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
	enum pipe pipe = crtc->pipe;
1185
	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1186 1187
	enum port port = intel_ddi_get_encoder_port(encoder);
	int type = encoder->type;
1188 1189
	uint32_t temp;

1190 1191
	/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
	temp = TRANS_DDI_FUNC_ENABLE;
1192
	temp |= TRANS_DDI_SELECT_PORT(port);
1193

1194
	switch (crtc_state->pipe_bpp) {
1195
	case 18:
1196
		temp |= TRANS_DDI_BPC_6;
1197 1198
		break;
	case 24:
1199
		temp |= TRANS_DDI_BPC_8;
1200 1201
		break;
	case 30:
1202
		temp |= TRANS_DDI_BPC_10;
1203 1204
		break;
	case 36:
1205
		temp |= TRANS_DDI_BPC_12;
1206 1207
		break;
	default:
1208
		BUG();
1209
	}
1210

1211
	if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1212
		temp |= TRANS_DDI_PVSYNC;
1213
	if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1214
		temp |= TRANS_DDI_PHSYNC;
1215

1216 1217 1218
	if (cpu_transcoder == TRANSCODER_EDP) {
		switch (pipe) {
		case PIPE_A:
1219 1220 1221 1222
			/* On Haswell, can only use the always-on power well for
			 * eDP when not using the panel fitter, and when not
			 * using motion blur mitigation (which we don't
			 * support). */
1223
			if (IS_HASWELL(dev_priv) &&
1224 1225
			    (crtc_state->pch_pfit.enabled ||
			     crtc_state->pch_pfit.force_thru))
1226 1227 1228
				temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
			else
				temp |= TRANS_DDI_EDP_INPUT_A_ON;
1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241
			break;
		case PIPE_B:
			temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
			break;
		case PIPE_C:
			temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
			break;
		default:
			BUG();
			break;
		}
	}

1242
	if (type == INTEL_OUTPUT_HDMI) {
1243
		if (crtc_state->has_hdmi_sink)
1244
			temp |= TRANS_DDI_MODE_SELECT_HDMI;
1245
		else
1246
			temp |= TRANS_DDI_MODE_SELECT_DVI;
S
Shashank Sharma 已提交
1247 1248 1249 1250 1251

		if (crtc_state->hdmi_scrambling)
			temp |= TRANS_DDI_HDMI_SCRAMBLING_MASK;
		if (crtc_state->hdmi_high_tmds_clock_ratio)
			temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1252
	} else if (type == INTEL_OUTPUT_ANALOG) {
1253
		temp |= TRANS_DDI_MODE_SELECT_FDI;
1254
		temp |= (crtc_state->fdi_lanes - 1) << 1;
1255
	} else if (type == INTEL_OUTPUT_DP ||
1256
		   type == INTEL_OUTPUT_EDP) {
1257
		temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1258
		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1259
	} else if (type == INTEL_OUTPUT_DP_MST) {
1260
		temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1261
		temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1262
	} else {
1263
		WARN(1, "Invalid encoder type %d for pipe %c\n",
1264
		     encoder->type, pipe_name(pipe));
1265 1266
	}

1267
	I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1268
}
1269

1270 1271
void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
				       enum transcoder cpu_transcoder)
1272
{
1273
	i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1274 1275
	uint32_t val = I915_READ(reg);

1276
	val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1277
	val |= TRANS_DDI_PORT_NONE;
1278
	I915_WRITE(reg, val);
1279 1280
}

1281 1282 1283
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
{
	struct drm_device *dev = intel_connector->base.dev;
1284
	struct drm_i915_private *dev_priv = to_i915(dev);
1285
	struct intel_encoder *encoder = intel_connector->encoder;
1286
	int type = intel_connector->base.connector_type;
1287
	enum port port = intel_ddi_get_encoder_port(encoder);
1288 1289 1290
	enum pipe pipe = 0;
	enum transcoder cpu_transcoder;
	uint32_t tmp;
1291
	bool ret;
1292

1293
	if (!intel_display_power_get_if_enabled(dev_priv,
1294
						encoder->power_domain))
1295 1296
		return false;

1297
	if (!encoder->get_hw_state(encoder, &pipe)) {
1298 1299 1300
		ret = false;
		goto out;
	}
1301 1302 1303 1304

	if (port == PORT_A)
		cpu_transcoder = TRANSCODER_EDP;
	else
D
Daniel Vetter 已提交
1305
		cpu_transcoder = (enum transcoder) pipe;
1306 1307 1308 1309 1310 1311

	tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));

	switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
	case TRANS_DDI_MODE_SELECT_HDMI:
	case TRANS_DDI_MODE_SELECT_DVI:
1312 1313
		ret = type == DRM_MODE_CONNECTOR_HDMIA;
		break;
1314 1315

	case TRANS_DDI_MODE_SELECT_DP_SST:
1316 1317 1318 1319
		ret = type == DRM_MODE_CONNECTOR_eDP ||
		      type == DRM_MODE_CONNECTOR_DisplayPort;
		break;

1320 1321 1322
	case TRANS_DDI_MODE_SELECT_DP_MST:
		/* if the transcoder is in MST state then
		 * connector isn't connected */
1323 1324
		ret = false;
		break;
1325 1326

	case TRANS_DDI_MODE_SELECT_FDI:
1327 1328
		ret = type == DRM_MODE_CONNECTOR_VGA;
		break;
1329 1330

	default:
1331 1332
		ret = false;
		break;
1333
	}
1334 1335

out:
1336
	intel_display_power_put(dev_priv, encoder->power_domain);
1337 1338

	return ret;
1339 1340
}

1341 1342 1343 1344
bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
			    enum pipe *pipe)
{
	struct drm_device *dev = encoder->base.dev;
1345
	struct drm_i915_private *dev_priv = to_i915(dev);
1346
	enum port port = intel_ddi_get_encoder_port(encoder);
1347 1348
	u32 tmp;
	int i;
1349
	bool ret;
1350

1351 1352
	if (!intel_display_power_get_if_enabled(dev_priv,
						encoder->power_domain))
1353 1354
		return false;

1355 1356
	ret = false;

1357
	tmp = I915_READ(DDI_BUF_CTL(port));
1358 1359

	if (!(tmp & DDI_BUF_CTL_ENABLE))
1360
		goto out;
1361

1362 1363
	if (port == PORT_A) {
		tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1364

1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377
		switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
		case TRANS_DDI_EDP_INPUT_A_ON:
		case TRANS_DDI_EDP_INPUT_A_ONOFF:
			*pipe = PIPE_A;
			break;
		case TRANS_DDI_EDP_INPUT_B_ONOFF:
			*pipe = PIPE_B;
			break;
		case TRANS_DDI_EDP_INPUT_C_ONOFF:
			*pipe = PIPE_C;
			break;
		}

1378
		ret = true;
1379

1380 1381
		goto out;
	}
1382

1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394
	for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
		tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));

		if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
			if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
			    TRANS_DDI_MODE_SELECT_DP_MST)
				goto out;

			*pipe = i;
			ret = true;

			goto out;
1395 1396 1397
		}
	}

1398
	DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
1399

1400
out:
1401
	if (ret && IS_GEN9_LP(dev_priv)) {
1402 1403 1404 1405 1406 1407 1408
		tmp = I915_READ(BXT_PHY_CTL(port));
		if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
			    BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
			DRM_ERROR("Port %c enabled but PHY powered down? "
				  "(PHY_CTL %08x)\n", port_name(port), tmp);
	}

1409
	intel_display_power_put(dev_priv, encoder->power_domain);
1410 1411

	return ret;
1412 1413
}

1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424
static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder)
{
	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
	enum pipe pipe;

	if (intel_ddi_get_hw_state(encoder, &pipe))
		return BIT_ULL(dig_port->ddi_io_power_domain);

	return 0;
}

1425
void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
1426
{
1427
	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1428
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1429 1430
	struct intel_encoder *encoder = intel_ddi_get_crtc_encoder(crtc);
	enum port port = intel_ddi_get_encoder_port(encoder);
1431
	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1432

1433 1434 1435
	if (cpu_transcoder != TRANSCODER_EDP)
		I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
			   TRANS_CLK_SEL_PORT(port));
1436 1437
}

1438
void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
1439
{
1440 1441
	struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1442

1443 1444 1445
	if (cpu_transcoder != TRANSCODER_EDP)
		I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
			   TRANS_CLK_SEL_DISABLED);
1446 1447
}

1448 1449
static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
				enum port port, uint8_t iboost)
1450
{
1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467
	u32 tmp;

	tmp = I915_READ(DISPIO_CR_TX_BMU_CR0);
	tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
	if (iboost)
		tmp |= iboost << BALANCE_LEG_SHIFT(port);
	else
		tmp |= BALANCE_LEG_DISABLE(port);
	I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp);
}

static void skl_ddi_set_iboost(struct intel_encoder *encoder, u32 level)
{
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
	struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
	enum port port = intel_dig_port->port;
	int type = encoder->type;
1468 1469
	const struct ddi_buf_trans *ddi_translations;
	uint8_t iboost;
1470
	uint8_t dp_iboost, hdmi_iboost;
1471 1472
	int n_entries;

1473 1474 1475 1476
	/* VBT may override standard boost values */
	dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
	hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;

1477
	if (type == INTEL_OUTPUT_DP) {
1478 1479 1480
		if (dp_iboost) {
			iboost = dp_iboost;
		} else {
1481 1482 1483 1484 1485 1486
			if (IS_KABYLAKE(dev_priv))
				ddi_translations = kbl_get_buf_trans_dp(dev_priv,
									&n_entries);
			else
				ddi_translations = skl_get_buf_trans_dp(dev_priv,
									&n_entries);
1487
			iboost = ddi_translations[level].i_boost;
1488
		}
1489
	} else if (type == INTEL_OUTPUT_EDP) {
1490 1491 1492
		if (dp_iboost) {
			iboost = dp_iboost;
		} else {
1493
			ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
1494 1495 1496 1497 1498

			if (WARN_ON(port != PORT_A &&
				    port != PORT_E && n_entries > 9))
				n_entries = 9;

1499
			iboost = ddi_translations[level].i_boost;
1500
		}
1501
	} else if (type == INTEL_OUTPUT_HDMI) {
1502 1503 1504
		if (hdmi_iboost) {
			iboost = hdmi_iboost;
		} else {
1505
			ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
1506
			iboost = ddi_translations[level].i_boost;
1507
		}
1508 1509 1510 1511 1512 1513 1514 1515 1516 1517
	} else {
		return;
	}

	/* Make sure that the requested I_boost is valid */
	if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
		DRM_ERROR("Invalid I_boost value %u\n", iboost);
		return;
	}

1518
	_skl_ddi_set_iboost(dev_priv, port, iboost);
1519

1520 1521
	if (port == PORT_A && intel_dig_port->max_lanes == 4)
		_skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
1522 1523
}

1524 1525
static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
				    u32 level, enum port port, int type)
1526 1527 1528 1529
{
	const struct bxt_ddi_buf_trans *ddi_translations;
	u32 n_entries, i;

1530
	if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
1531 1532
		n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
		ddi_translations = bxt_ddi_translations_edp;
1533
	} else if (type == INTEL_OUTPUT_DP
1534
			|| type == INTEL_OUTPUT_EDP) {
1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556
		n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
		ddi_translations = bxt_ddi_translations_dp;
	} else if (type == INTEL_OUTPUT_HDMI) {
		n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
		ddi_translations = bxt_ddi_translations_hdmi;
	} else {
		DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
				type);
		return;
	}

	/* Check if default value has to be used */
	if (level >= n_entries ||
	    (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
		for (i = 0; i < n_entries; i++) {
			if (ddi_translations[i].default_index) {
				level = i;
				break;
			}
		}
	}

1557 1558 1559 1560 1561
	bxt_ddi_phy_set_signal_level(dev_priv, port,
				     ddi_translations[level].margin,
				     ddi_translations[level].scale,
				     ddi_translations[level].enable,
				     ddi_translations[level].deemphasis);
1562 1563
}

1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582
u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	int n_entries;

	if (encoder->type == INTEL_OUTPUT_EDP)
		intel_ddi_get_buf_trans_edp(dev_priv, &n_entries);
	else
		intel_ddi_get_buf_trans_dp(dev_priv, &n_entries);

	if (WARN_ON(n_entries < 1))
		n_entries = 1;
	if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
		n_entries = ARRAY_SIZE(index_to_dp_signal_levels);

	return index_to_dp_signal_levels[n_entries - 1] &
		DP_TRAIN_VOLTAGE_SWING_MASK;
}

1583 1584
static uint32_t translate_signal_level(int signal_levels)
{
1585
	int i;
1586

1587 1588 1589
	for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
		if (index_to_dp_signal_levels[i] == signal_levels)
			return i;
1590 1591
	}

1592 1593 1594 1595
	WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
	     signal_levels);

	return 0;
1596 1597 1598 1599 1600
}

uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
{
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1601
	struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
1602 1603 1604 1605 1606 1607 1608 1609 1610
	struct intel_encoder *encoder = &dport->base;
	uint8_t train_set = intel_dp->train_set[0];
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	enum port port = dport->port;
	uint32_t level;

	level = translate_signal_level(signal_levels);

1611
	if (IS_GEN9_BC(dev_priv))
1612
		skl_ddi_set_iboost(encoder, level);
1613
	else if (IS_GEN9_LP(dev_priv))
1614
		bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
1615 1616 1617 1618

	return DDI_BUF_TRANS_SELECT(level);
}

1619 1620
static void intel_ddi_clk_select(struct intel_encoder *encoder,
				 struct intel_shared_dpll *pll)
1621
{
1622 1623
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	enum port port = intel_ddi_get_encoder_port(encoder);
R
Rodrigo Vivi 已提交
1624
	uint32_t val;
1625

1626 1627 1628
	if (WARN_ON(!pll))
		return;

R
Rodrigo Vivi 已提交
1629 1630 1631 1632 1633
	if (IS_CANNONLAKE(dev_priv)) {
		/* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
		val = I915_READ(DPCLKA_CFGCR0);
		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->id, port);
		I915_WRITE(DPCLKA_CFGCR0, val);
1634

R
Rodrigo Vivi 已提交
1635 1636 1637 1638 1639 1640 1641 1642 1643 1644
		/*
		 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
		 * This step and the step before must be done with separate
		 * register writes.
		 */
		val = I915_READ(DPCLKA_CFGCR0);
		val &= ~(DPCLKA_CFGCR0_DDI_CLK_OFF(port) |
			 DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port));
		I915_WRITE(DPCLKA_CFGCR0, val);
	} else if (IS_GEN9_BC(dev_priv)) {
1645
		/* DDI -> PLL mapping  */
1646 1647 1648 1649
		val = I915_READ(DPLL_CTRL2);

		val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
			DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1650
		val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
1651 1652 1653
			DPLL_CTRL2_DDI_SEL_OVERRIDE(port));

		I915_WRITE(DPLL_CTRL2, val);
1654

1655
	} else if (INTEL_INFO(dev_priv)->gen < 9) {
1656
		I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
1657
	}
1658 1659
}

1660 1661 1662 1663
static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
				    int link_rate, uint32_t lane_count,
				    struct intel_shared_dpll *pll,
				    bool link_mst)
1664
{
1665 1666 1667
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	enum port port = intel_ddi_get_encoder_port(encoder);
1668
	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
1669

1670 1671
	WARN_ON(link_mst && (port == PORT_A || port == PORT_E));

1672 1673 1674
	intel_dp_set_link_params(intel_dp, link_rate, lane_count,
				 link_mst);
	if (encoder->type == INTEL_OUTPUT_EDP)
1675
		intel_edp_panel_on(intel_dp);
1676

1677
	intel_ddi_clk_select(encoder, pll);
1678 1679 1680

	intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);

1681 1682 1683 1684 1685 1686 1687
	intel_prepare_dp_ddi_buffers(encoder);
	intel_ddi_init_dp_buf_reg(encoder);
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
	intel_dp_start_link_train(intel_dp);
	if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
		intel_dp_stop_link_train(intel_dp);
}
1688

1689 1690
static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder,
				      bool has_hdmi_sink,
1691 1692
				      const struct intel_crtc_state *crtc_state,
				      const struct drm_connector_state *conn_state,
1693 1694 1695 1696 1697 1698 1699
				      struct intel_shared_dpll *pll)
{
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	struct drm_encoder *drm_encoder = &encoder->base;
	enum port port = intel_ddi_get_encoder_port(encoder);
	int level = intel_ddi_hdmi_level(dev_priv, port);
1700
	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
1701

1702 1703
	intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
	intel_ddi_clk_select(encoder, pll);
1704 1705 1706

	intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);

1707
	intel_prepare_hdmi_ddi_buffers(encoder);
1708
	if (IS_GEN9_BC(dev_priv))
1709
		skl_ddi_set_iboost(encoder, level);
1710
	else if (IS_GEN9_LP(dev_priv))
1711 1712
		bxt_ddi_vswing_sequence(dev_priv, level, port,
					INTEL_OUTPUT_HDMI);
1713

1714 1715
	intel_hdmi->set_infoframes(drm_encoder,
				   has_hdmi_sink,
1716
				   crtc_state, conn_state);
1717
}
1718

1719
static void intel_ddi_pre_enable(struct intel_encoder *encoder,
1720 1721 1722
				 struct intel_crtc_state *pipe_config,
				 struct drm_connector_state *conn_state)
{
1723
	int type = encoder->type;
1724

1725
	if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
1726
		intel_ddi_pre_enable_dp(encoder,
1727 1728 1729 1730
					pipe_config->port_clock,
					pipe_config->lane_count,
					pipe_config->shared_dpll,
					intel_crtc_has_type(pipe_config,
1731 1732 1733
							    INTEL_OUTPUT_DP_MST));
	}
	if (type == INTEL_OUTPUT_HDMI) {
1734
		intel_ddi_pre_enable_hdmi(encoder,
1735 1736
					  pipe_config->has_hdmi_sink,
					  pipe_config, conn_state,
1737
					  pipe_config->shared_dpll);
1738
	}
1739 1740
}

1741 1742 1743
static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
				   struct intel_crtc_state *old_crtc_state,
				   struct drm_connector_state *old_conn_state)
1744 1745
{
	struct drm_encoder *encoder = &intel_encoder->base;
1746
	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
1747
	enum port port = intel_ddi_get_encoder_port(intel_encoder);
1748
	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1749
	struct intel_dp *intel_dp = NULL;
1750
	int type = intel_encoder->type;
1751
	uint32_t val;
1752
	bool wait = false;
1753

1754 1755
	/* old_crtc_state and old_conn_state are NULL when called from DP_MST */

1756 1757 1758 1759 1760
	if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
		intel_dp = enc_to_intel_dp(encoder);
		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
	}

1761 1762 1763 1764
	val = I915_READ(DDI_BUF_CTL(port));
	if (val & DDI_BUF_CTL_ENABLE) {
		val &= ~DDI_BUF_CTL_ENABLE;
		I915_WRITE(DDI_BUF_CTL(port), val);
1765
		wait = true;
1766
	}
1767

1768 1769 1770 1771 1772 1773 1774 1775
	val = I915_READ(DP_TP_CTL(port));
	val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
	val |= DP_TP_CTL_LINK_TRAIN_PAT1;
	I915_WRITE(DP_TP_CTL(port), val);

	if (wait)
		intel_wait_ddi_buf_idle(dev_priv, port);

1776
	if (intel_dp) {
1777
		intel_edp_panel_vdd_on(intel_dp);
1778
		intel_edp_panel_off(intel_dp);
1779 1780
	}

1781 1782 1783
	if (dig_port)
		intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);

R
Rodrigo Vivi 已提交
1784 1785 1786 1787
	if (IS_CANNONLAKE(dev_priv))
		I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
			   DPCLKA_CFGCR0_DDI_CLK_OFF(port));
	else if (IS_GEN9_BC(dev_priv))
1788 1789
		I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
					DPLL_CTRL2_DDI_CLK_OFF(port)));
1790
	else if (INTEL_GEN(dev_priv) < 9)
1791
		I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1792 1793 1794 1795 1796 1797

	if (type == INTEL_OUTPUT_HDMI) {
		struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);

		intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
	}
1798 1799
}

1800
void intel_ddi_fdi_post_disable(struct intel_encoder *encoder,
1801 1802 1803
				struct intel_crtc_state *old_crtc_state,
				struct drm_connector_state *old_conn_state)
{
1804
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816
	uint32_t val;

	/*
	 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
	 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
	 * step 13 is the correct place for it. Step 18 is where it was
	 * originally before the BUN.
	 */
	val = I915_READ(FDI_RX_CTL(PIPE_A));
	val &= ~FDI_RX_ENABLE;
	I915_WRITE(FDI_RX_CTL(PIPE_A), val);

1817
	intel_ddi_post_disable(encoder, old_crtc_state, old_conn_state);
1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832

	val = I915_READ(FDI_RX_MISC(PIPE_A));
	val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
	val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
	I915_WRITE(FDI_RX_MISC(PIPE_A), val);

	val = I915_READ(FDI_RX_CTL(PIPE_A));
	val &= ~FDI_PCDCLK;
	I915_WRITE(FDI_RX_CTL(PIPE_A), val);

	val = I915_READ(FDI_RX_CTL(PIPE_A));
	val &= ~FDI_RX_PLL_ENABLE;
	I915_WRITE(FDI_RX_CTL(PIPE_A), val);
}

1833 1834 1835
static void intel_enable_ddi(struct intel_encoder *intel_encoder,
			     struct intel_crtc_state *pipe_config,
			     struct drm_connector_state *conn_state)
1836
{
1837
	struct drm_encoder *encoder = &intel_encoder->base;
1838
	struct drm_i915_private *dev_priv = to_i915(encoder->dev);
1839 1840
	enum port port = intel_ddi_get_encoder_port(intel_encoder);
	int type = intel_encoder->type;
1841

1842
	if (type == INTEL_OUTPUT_HDMI) {
1843 1844
		struct intel_digital_port *intel_dig_port =
			enc_to_dig_port(encoder);
S
Shashank Sharma 已提交
1845 1846 1847 1848 1849 1850
		bool clock_ratio = pipe_config->hdmi_high_tmds_clock_ratio;
		bool scrambling = pipe_config->hdmi_scrambling;

		intel_hdmi_handle_sink_scrambling(intel_encoder,
						  conn_state->connector,
						  clock_ratio, scrambling);
1851

1852 1853 1854 1855
		/* In HDMI/DVI mode, the port width, and swing/emphasis values
		 * are ignored so nothing special needs to be done besides
		 * enabling the port.
		 */
1856
		I915_WRITE(DDI_BUF_CTL(port),
1857 1858
			   intel_dig_port->saved_port_bits |
			   DDI_BUF_CTL_ENABLE);
1859 1860 1861
	} else if (type == INTEL_OUTPUT_EDP) {
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

1862
		if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
1863 1864
			intel_dp_stop_link_train(intel_dp);

1865
		intel_edp_backlight_on(pipe_config, conn_state);
R
Rodrigo Vivi 已提交
1866
		intel_psr_enable(intel_dp);
1867
		intel_edp_drrs_enable(intel_dp, pipe_config);
1868
	}
1869

1870
	if (pipe_config->has_audio)
1871
		intel_audio_codec_enable(intel_encoder, pipe_config, conn_state);
1872 1873
}

1874 1875 1876
static void intel_disable_ddi(struct intel_encoder *intel_encoder,
			      struct intel_crtc_state *old_crtc_state,
			      struct drm_connector_state *old_conn_state)
1877
{
1878 1879 1880
	struct drm_encoder *encoder = &intel_encoder->base;
	int type = intel_encoder->type;

1881
	if (old_crtc_state->has_audio)
1882
		intel_audio_codec_disable(intel_encoder);
1883

S
Shashank Sharma 已提交
1884 1885 1886 1887 1888 1889
	if (type == INTEL_OUTPUT_HDMI) {
		intel_hdmi_handle_sink_scrambling(intel_encoder,
						  old_conn_state->connector,
						  false, false);
	}

1890 1891 1892
	if (type == INTEL_OUTPUT_EDP) {
		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

1893
		intel_edp_drrs_disable(intel_dp, old_crtc_state);
R
Rodrigo Vivi 已提交
1894
		intel_psr_disable(intel_dp);
1895
		intel_edp_backlight_off(old_conn_state);
1896
	}
1897
}
P
Paulo Zanoni 已提交
1898

1899 1900 1901
static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
				   struct intel_crtc_state *pipe_config,
				   struct drm_connector_state *conn_state)
1902
{
1903
	uint8_t mask = pipe_config->lane_lat_optim_mask;
1904

1905
	bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
1906 1907
}

1908
void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
1909
{
1910 1911 1912
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_i915_private *dev_priv =
		to_i915(intel_dig_port->base.base.dev);
1913
	enum port port = intel_dig_port->port;
1914
	uint32_t val;
1915
	bool wait = false;
1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934

	if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
		val = I915_READ(DDI_BUF_CTL(port));
		if (val & DDI_BUF_CTL_ENABLE) {
			val &= ~DDI_BUF_CTL_ENABLE;
			I915_WRITE(DDI_BUF_CTL(port), val);
			wait = true;
		}

		val = I915_READ(DP_TP_CTL(port));
		val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
		val |= DP_TP_CTL_LINK_TRAIN_PAT1;
		I915_WRITE(DP_TP_CTL(port), val);
		POSTING_READ(DP_TP_CTL(port));

		if (wait)
			intel_wait_ddi_buf_idle(dev_priv, port);
	}

1935
	val = DP_TP_CTL_ENABLE |
1936
	      DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
1937
	if (intel_dp->link_mst)
1938 1939 1940 1941 1942 1943
		val |= DP_TP_CTL_MODE_MST;
	else {
		val |= DP_TP_CTL_MODE_SST;
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
			val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
	}
1944 1945 1946 1947 1948 1949 1950 1951 1952
	I915_WRITE(DP_TP_CTL(port), val);
	POSTING_READ(DP_TP_CTL(port));

	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
	I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
	POSTING_READ(DDI_BUF_CTL(port));

	udelay(600);
}
P
Paulo Zanoni 已提交
1953

1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966
bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
				 struct intel_crtc *intel_crtc)
{
	u32 temp;

	if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
		temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
		if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
			return true;
	}
	return false;
}

1967
void intel_ddi_get_config(struct intel_encoder *encoder,
1968
			  struct intel_crtc_state *pipe_config)
1969
{
1970
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1971
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1972
	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
1973
	struct intel_hdmi *intel_hdmi;
1974 1975
	u32 temp, flags = 0;

J
Jani Nikula 已提交
1976 1977 1978 1979
	/* XXX: DSI transcoder paranoia */
	if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
		return;

1980 1981 1982 1983 1984 1985 1986 1987 1988 1989
	temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
	if (temp & TRANS_DDI_PHSYNC)
		flags |= DRM_MODE_FLAG_PHSYNC;
	else
		flags |= DRM_MODE_FLAG_NHSYNC;
	if (temp & TRANS_DDI_PVSYNC)
		flags |= DRM_MODE_FLAG_PVSYNC;
	else
		flags |= DRM_MODE_FLAG_NVSYNC;

1990
	pipe_config->base.adjusted_mode.flags |= flags;
1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007

	switch (temp & TRANS_DDI_BPC_MASK) {
	case TRANS_DDI_BPC_6:
		pipe_config->pipe_bpp = 18;
		break;
	case TRANS_DDI_BPC_8:
		pipe_config->pipe_bpp = 24;
		break;
	case TRANS_DDI_BPC_10:
		pipe_config->pipe_bpp = 30;
		break;
	case TRANS_DDI_BPC_12:
		pipe_config->pipe_bpp = 36;
		break;
	default:
		break;
	}
2008 2009 2010

	switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
	case TRANS_DDI_MODE_SELECT_HDMI:
2011
		pipe_config->has_hdmi_sink = true;
2012 2013
		intel_hdmi = enc_to_intel_hdmi(&encoder->base);

2014
		if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
2015
			pipe_config->has_infoframe = true;
S
Shashank Sharma 已提交
2016 2017 2018 2019 2020 2021

		if ((temp & TRANS_DDI_HDMI_SCRAMBLING_MASK) ==
			TRANS_DDI_HDMI_SCRAMBLING_MASK)
			pipe_config->hdmi_scrambling = true;
		if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
			pipe_config->hdmi_high_tmds_clock_ratio = true;
2022
		/* fall through */
2023
	case TRANS_DDI_MODE_SELECT_DVI:
2024 2025
		pipe_config->lane_count = 4;
		break;
2026 2027 2028 2029
	case TRANS_DDI_MODE_SELECT_FDI:
		break;
	case TRANS_DDI_MODE_SELECT_DP_SST:
	case TRANS_DDI_MODE_SELECT_DP_MST:
2030 2031
		pipe_config->lane_count =
			((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
2032 2033 2034 2035 2036
		intel_dp_get_m_n(intel_crtc, pipe_config);
		break;
	default:
		break;
	}
2037

2038 2039
	pipe_config->has_audio =
		intel_ddi_is_audio_enabled(dev_priv, intel_crtc);
2040

2041 2042
	if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
	    pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056
		/*
		 * This is a big fat ugly hack.
		 *
		 * Some machines in UEFI boot mode provide us a VBT that has 18
		 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
		 * unknown we fail to light up. Yet the same BIOS boots up with
		 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
		 * max, not what it tells us to use.
		 *
		 * Note: This will still be broken if the eDP panel is not lit
		 * up by the BIOS, and thus we can't get the mode at module
		 * load.
		 */
		DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2057 2058
			      pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
		dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2059
	}
2060

2061
	intel_ddi_clock_get(encoder, pipe_config);
2062

2063
	if (IS_GEN9_LP(dev_priv))
2064 2065
		pipe_config->lane_lat_optim_mask =
			bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
2066 2067
}

2068
static bool intel_ddi_compute_config(struct intel_encoder *encoder,
2069 2070
				     struct intel_crtc_state *pipe_config,
				     struct drm_connector_state *conn_state)
P
Paulo Zanoni 已提交
2071
{
2072
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2073
	int type = encoder->type;
2074
	int port = intel_ddi_get_encoder_port(encoder);
2075
	int ret;
P
Paulo Zanoni 已提交
2076

2077
	WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
P
Paulo Zanoni 已提交
2078

2079 2080 2081
	if (port == PORT_A)
		pipe_config->cpu_transcoder = TRANSCODER_EDP;

P
Paulo Zanoni 已提交
2082
	if (type == INTEL_OUTPUT_HDMI)
2083
		ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
P
Paulo Zanoni 已提交
2084
	else
2085
		ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
2086

2087
	if (IS_GEN9_LP(dev_priv) && ret)
2088 2089
		pipe_config->lane_lat_optim_mask =
			bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
2090
							     pipe_config->lane_count);
2091 2092 2093

	return ret;

P
Paulo Zanoni 已提交
2094 2095 2096
}

static const struct drm_encoder_funcs intel_ddi_funcs = {
2097 2098
	.reset = intel_dp_encoder_reset,
	.destroy = intel_dp_encoder_destroy,
P
Paulo Zanoni 已提交
2099 2100
};

2101 2102 2103 2104 2105 2106
static struct intel_connector *
intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
{
	struct intel_connector *connector;
	enum port port = intel_dig_port->port;

2107
	connector = intel_connector_alloc();
2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125
	if (!connector)
		return NULL;

	intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
	if (!intel_dp_init_connector(intel_dig_port, connector)) {
		kfree(connector);
		return NULL;
	}

	return connector;
}

static struct intel_connector *
intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
{
	struct intel_connector *connector;
	enum port port = intel_dig_port->port;

2126
	connector = intel_connector_alloc();
2127 2128 2129 2130 2131 2132 2133 2134 2135
	if (!connector)
		return NULL;

	intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
	intel_hdmi_init_connector(intel_dig_port, connector);

	return connector;
}

2136
void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
P
Paulo Zanoni 已提交
2137 2138 2139 2140
{
	struct intel_digital_port *intel_dig_port;
	struct intel_encoder *intel_encoder;
	struct drm_encoder *encoder;
2141
	bool init_hdmi, init_dp, init_lspcon = false;
2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168
	int max_lanes;

	if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
		switch (port) {
		case PORT_A:
			max_lanes = 4;
			break;
		case PORT_E:
			max_lanes = 0;
			break;
		default:
			max_lanes = 4;
			break;
		}
	} else {
		switch (port) {
		case PORT_A:
			max_lanes = 2;
			break;
		case PORT_E:
			max_lanes = 2;
			break;
		default:
			max_lanes = 4;
			break;
		}
	}
2169 2170 2171 2172

	init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
		     dev_priv->vbt.ddi_port_info[port].supports_hdmi);
	init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185

	if (intel_bios_is_lspcon_present(dev_priv, port)) {
		/*
		 * Lspcon device needs to be driven with DP connector
		 * with special detection sequence. So make sure DP
		 * is initialized before lspcon.
		 */
		init_dp = true;
		init_lspcon = true;
		init_hdmi = false;
		DRM_DEBUG_KMS("VBT says port %c has lspcon\n", port_name(port));
	}

2186
	if (!init_dp && !init_hdmi) {
2187
		DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
2188
			      port_name(port));
2189
		return;
2190
	}
P
Paulo Zanoni 已提交
2191

2192
	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
P
Paulo Zanoni 已提交
2193 2194 2195 2196 2197 2198
	if (!intel_dig_port)
		return;

	intel_encoder = &intel_dig_port->base;
	encoder = &intel_encoder->base;

2199
	drm_encoder_init(&dev_priv->drm, encoder, &intel_ddi_funcs,
2200
			 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
P
Paulo Zanoni 已提交
2201

2202
	intel_encoder->compute_config = intel_ddi_compute_config;
P
Paulo Zanoni 已提交
2203
	intel_encoder->enable = intel_enable_ddi;
2204
	if (IS_GEN9_LP(dev_priv))
2205
		intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
P
Paulo Zanoni 已提交
2206 2207 2208 2209
	intel_encoder->pre_enable = intel_ddi_pre_enable;
	intel_encoder->disable = intel_disable_ddi;
	intel_encoder->post_disable = intel_ddi_post_disable;
	intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2210
	intel_encoder->get_config = intel_ddi_get_config;
2211
	intel_encoder->suspend = intel_dp_encoder_suspend;
2212
	intel_encoder->get_power_domains = intel_ddi_get_power_domains;
P
Paulo Zanoni 已提交
2213 2214

	intel_dig_port->port = port;
2215 2216 2217
	intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
					  (DDI_BUF_PORT_REVERSAL |
					   DDI_A_4_LANES);
P
Paulo Zanoni 已提交
2218

2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243
	switch (port) {
	case PORT_A:
		intel_dig_port->ddi_io_power_domain =
			POWER_DOMAIN_PORT_DDI_A_IO;
		break;
	case PORT_B:
		intel_dig_port->ddi_io_power_domain =
			POWER_DOMAIN_PORT_DDI_B_IO;
		break;
	case PORT_C:
		intel_dig_port->ddi_io_power_domain =
			POWER_DOMAIN_PORT_DDI_C_IO;
		break;
	case PORT_D:
		intel_dig_port->ddi_io_power_domain =
			POWER_DOMAIN_PORT_DDI_D_IO;
		break;
	case PORT_E:
		intel_dig_port->ddi_io_power_domain =
			POWER_DOMAIN_PORT_DDI_E_IO;
		break;
	default:
		MISSING_CASE(port);
	}

2244 2245 2246 2247 2248 2249 2250
	/*
	 * Bspec says that DDI_A_4_LANES is the only supported configuration
	 * for Broxton.  Yet some BIOS fail to set this bit on port A if eDP
	 * wasn't lit up at boot.  Force this bit on in our internal
	 * configuration so that we use the proper lane count for our
	 * calculations.
	 */
2251
	if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
2252 2253 2254
		if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
			DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
			intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
2255
			max_lanes = 4;
2256 2257 2258
		}
	}

2259 2260
	intel_dig_port->max_lanes = max_lanes;

P
Paulo Zanoni 已提交
2261
	intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
2262
	intel_encoder->power_domain = intel_port_to_power_domain(port);
2263
	intel_encoder->port = port;
2264
	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2265
	intel_encoder->cloneable = 0;
P
Paulo Zanoni 已提交
2266

2267 2268 2269
	if (init_dp) {
		if (!intel_ddi_init_dp_connector(intel_dig_port))
			goto err;
2270

2271
		intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
2272
		dev_priv->hotplug.irq_port[port] = intel_dig_port;
2273
	}
2274

2275 2276
	/* In theory we don't need the encoder->type check, but leave it just in
	 * case we have some really bad VBTs... */
2277 2278 2279
	if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
		if (!intel_ddi_init_hdmi_connector(intel_dig_port))
			goto err;
2280
	}
2281

2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295
	if (init_lspcon) {
		if (lspcon_init(intel_dig_port))
			/* TODO: handle hdmi info frame part */
			DRM_DEBUG_KMS("LSPCON init success on port %c\n",
				port_name(port));
		else
			/*
			 * LSPCON init faied, but DP init was success, so
			 * lets try to drive as DP++ port.
			 */
			DRM_ERROR("LSPCON init failed on port %c\n",
				port_name(port));
	}

2296 2297 2298 2299 2300
	return;

err:
	drm_encoder_cleanup(encoder);
	kfree(intel_dig_port);
P
Paulo Zanoni 已提交
2301
}