mpic.c 46.9 KB
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/*
 *  arch/powerpc/kernel/mpic.c
 *
 *  Driver for interrupt controllers following the OpenPIC standard, the
 *  common implementation beeing IBM's MPIC. This driver also can deal
 *  with various broken implementations of this HW.
 *
 *  Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
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 *  Copyright 2010-2011 Freescale Semiconductor, Inc.
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 *
 *  This file is subject to the terms and conditions of the GNU General Public
 *  License.  See the file COPYING in the main directory of this archive
 *  for more details.
 */

#undef DEBUG
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#undef DEBUG_IPI
#undef DEBUG_IRQ
#undef DEBUG_LOW
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#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/smp.h>
#include <linux/interrupt.h>
#include <linux/bootmem.h>
#include <linux/spinlock.h>
#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/syscore_ops.h>
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#include <linux/ratelimit.h>
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#include <asm/ptrace.h>
#include <asm/signal.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/irq.h>
#include <asm/machdep.h>
#include <asm/mpic.h>
#include <asm/smp.h>

M
Michael Ellerman 已提交
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#include "mpic.h"

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#ifdef DEBUG
#define DBG(fmt...) printk(fmt)
#else
#define DBG(fmt...)
#endif

static struct mpic *mpics;
static struct mpic *mpic_primary;
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static DEFINE_RAW_SPINLOCK(mpic_lock);
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#ifdef CONFIG_PPC32	/* XXX for now */
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#ifdef CONFIG_IRQ_ALL_CPUS
#define distribute_irqs	(1)
#else
#define distribute_irqs	(0)
#endif
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#endif
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#ifdef CONFIG_MPIC_WEIRD
static u32 mpic_infos[][MPIC_IDX_END] = {
	[0] = {	/* Original OpenPIC compatible MPIC */
		MPIC_GREG_BASE,
		MPIC_GREG_FEATURE_0,
		MPIC_GREG_GLOBAL_CONF_0,
		MPIC_GREG_VENDOR_ID,
		MPIC_GREG_IPI_VECTOR_PRI_0,
		MPIC_GREG_IPI_STRIDE,
		MPIC_GREG_SPURIOUS,
		MPIC_GREG_TIMER_FREQ,

		MPIC_TIMER_BASE,
		MPIC_TIMER_STRIDE,
		MPIC_TIMER_CURRENT_CNT,
		MPIC_TIMER_BASE_CNT,
		MPIC_TIMER_VECTOR_PRI,
		MPIC_TIMER_DESTINATION,

		MPIC_CPU_BASE,
		MPIC_CPU_STRIDE,
		MPIC_CPU_IPI_DISPATCH_0,
		MPIC_CPU_IPI_DISPATCH_STRIDE,
		MPIC_CPU_CURRENT_TASK_PRI,
		MPIC_CPU_WHOAMI,
		MPIC_CPU_INTACK,
		MPIC_CPU_EOI,
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		MPIC_CPU_MCACK,
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		MPIC_IRQ_BASE,
		MPIC_IRQ_STRIDE,
		MPIC_IRQ_VECTOR_PRI,
		MPIC_VECPRI_VECTOR_MASK,
		MPIC_VECPRI_POLARITY_POSITIVE,
		MPIC_VECPRI_POLARITY_NEGATIVE,
		MPIC_VECPRI_SENSE_LEVEL,
		MPIC_VECPRI_SENSE_EDGE,
		MPIC_VECPRI_POLARITY_MASK,
		MPIC_VECPRI_SENSE_MASK,
		MPIC_IRQ_DESTINATION
	},
	[1] = {	/* Tsi108/109 PIC */
		TSI108_GREG_BASE,
		TSI108_GREG_FEATURE_0,
		TSI108_GREG_GLOBAL_CONF_0,
		TSI108_GREG_VENDOR_ID,
		TSI108_GREG_IPI_VECTOR_PRI_0,
		TSI108_GREG_IPI_STRIDE,
		TSI108_GREG_SPURIOUS,
		TSI108_GREG_TIMER_FREQ,

		TSI108_TIMER_BASE,
		TSI108_TIMER_STRIDE,
		TSI108_TIMER_CURRENT_CNT,
		TSI108_TIMER_BASE_CNT,
		TSI108_TIMER_VECTOR_PRI,
		TSI108_TIMER_DESTINATION,

		TSI108_CPU_BASE,
		TSI108_CPU_STRIDE,
		TSI108_CPU_IPI_DISPATCH_0,
		TSI108_CPU_IPI_DISPATCH_STRIDE,
		TSI108_CPU_CURRENT_TASK_PRI,
		TSI108_CPU_WHOAMI,
		TSI108_CPU_INTACK,
		TSI108_CPU_EOI,
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		TSI108_CPU_MCACK,
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		TSI108_IRQ_BASE,
		TSI108_IRQ_STRIDE,
		TSI108_IRQ_VECTOR_PRI,
		TSI108_VECPRI_VECTOR_MASK,
		TSI108_VECPRI_POLARITY_POSITIVE,
		TSI108_VECPRI_POLARITY_NEGATIVE,
		TSI108_VECPRI_SENSE_LEVEL,
		TSI108_VECPRI_SENSE_EDGE,
		TSI108_VECPRI_POLARITY_MASK,
		TSI108_VECPRI_SENSE_MASK,
		TSI108_IRQ_DESTINATION
	},
};

#define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]

#else /* CONFIG_MPIC_WEIRD */

#define MPIC_INFO(name) MPIC_##name

#endif /* CONFIG_MPIC_WEIRD */

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static inline unsigned int mpic_processor_id(struct mpic *mpic)
{
	unsigned int cpu = 0;

	if (mpic->flags & MPIC_PRIMARY)
		cpu = hard_smp_processor_id();

	return cpu;
}

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/*
 * Register accessor functions
 */


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static inline u32 _mpic_read(enum mpic_reg_type type,
			     struct mpic_reg_bank *rb,
			     unsigned int reg)
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{
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	switch(type) {
#ifdef CONFIG_PPC_DCR
	case mpic_access_dcr:
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		return dcr_read(rb->dhost, reg);
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#endif
	case mpic_access_mmio_be:
		return in_be32(rb->base + (reg >> 2));
	case mpic_access_mmio_le:
	default:
		return in_le32(rb->base + (reg >> 2));
	}
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}

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static inline void _mpic_write(enum mpic_reg_type type,
			       struct mpic_reg_bank *rb,
 			       unsigned int reg, u32 value)
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{
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	switch(type) {
#ifdef CONFIG_PPC_DCR
	case mpic_access_dcr:
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		dcr_write(rb->dhost, reg, value);
		break;
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#endif
	case mpic_access_mmio_be:
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		out_be32(rb->base + (reg >> 2), value);
		break;
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	case mpic_access_mmio_le:
	default:
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		out_le32(rb->base + (reg >> 2), value);
		break;
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	}
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}

static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
{
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	enum mpic_reg_type type = mpic->reg_type;
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	unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
			      (ipi * MPIC_INFO(GREG_IPI_STRIDE));
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	if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
		type = mpic_access_mmio_be;
	return _mpic_read(type, &mpic->gregs, offset);
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}

static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
{
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	unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
			      (ipi * MPIC_INFO(GREG_IPI_STRIDE));
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	_mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
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}

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static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
{
	unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
			      ((tm & 3) * MPIC_INFO(TIMER_STRIDE));

	if (tm >= 4)
		offset += 0x1000 / 4;

	return _mpic_read(mpic->reg_type, &mpic->tmregs, offset);
}

static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value)
{
	unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
			      ((tm & 3) * MPIC_INFO(TIMER_STRIDE));

	if (tm >= 4)
		offset += 0x1000 / 4;

	_mpic_write(mpic->reg_type, &mpic->tmregs, offset, value);
}

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static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
{
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	unsigned int cpu = mpic_processor_id(mpic);
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	return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
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}

static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
{
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	unsigned int cpu = mpic_processor_id(mpic);
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	_mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
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}

static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
{
	unsigned int	isu = src_no >> mpic->isu_shift;
	unsigned int	idx = src_no & mpic->isu_mask;
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	unsigned int	val;
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	val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
			 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
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#ifdef CONFIG_MPIC_BROKEN_REGREAD
	if (reg == 0)
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		val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
			mpic->isu_reg0_shadow[src_no];
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#endif
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	return val;
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}

static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
				   unsigned int reg, u32 value)
{
	unsigned int	isu = src_no >> mpic->isu_shift;
	unsigned int	idx = src_no & mpic->isu_mask;

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	_mpic_write(mpic->reg_type, &mpic->isus[isu],
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		    reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
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#ifdef CONFIG_MPIC_BROKEN_REGREAD
	if (reg == 0)
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		mpic->isu_reg0_shadow[src_no] =
			value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
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#endif
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}

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#define mpic_read(b,r)		_mpic_read(mpic->reg_type,&(b),(r))
#define mpic_write(b,r,v)	_mpic_write(mpic->reg_type,&(b),(r),(v))
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#define mpic_ipi_read(i)	_mpic_ipi_read(mpic,(i))
#define mpic_ipi_write(i,v)	_mpic_ipi_write(mpic,(i),(v))
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#define mpic_tm_read(i)		_mpic_tm_read(mpic,(i))
#define mpic_tm_write(i,v)	_mpic_tm_write(mpic,(i),(v))
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#define mpic_cpu_read(i)	_mpic_cpu_read(mpic,(i))
#define mpic_cpu_write(i,v)	_mpic_cpu_write(mpic,(i),(v))
#define mpic_irq_read(s,r)	_mpic_irq_read(mpic,(s),(r))
#define mpic_irq_write(s,r,v)	_mpic_irq_write(mpic,(s),(r),(v))


/*
 * Low level utility functions
 */


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static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
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			   struct mpic_reg_bank *rb, unsigned int offset,
			   unsigned int size)
{
	rb->base = ioremap(phys_addr + offset, size);
	BUG_ON(rb->base == NULL);
}

#ifdef CONFIG_PPC_DCR
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static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node,
			  struct mpic_reg_bank *rb,
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			  unsigned int offset, unsigned int size)
{
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	const u32 *dbasep;

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	dbasep = of_get_property(node, "dcr-reg", NULL);
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	rb->dhost = dcr_map(node, *dbasep + offset, size);
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	BUG_ON(!DCR_MAP_OK(rb->dhost));
}

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static inline void mpic_map(struct mpic *mpic, struct device_node *node,
			    phys_addr_t phys_addr, struct mpic_reg_bank *rb,
			    unsigned int offset, unsigned int size)
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{
	if (mpic->flags & MPIC_USES_DCR)
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		_mpic_map_dcr(mpic, node, rb, offset, size);
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	else
		_mpic_map_mmio(mpic, phys_addr, rb, offset, size);
}
#else /* CONFIG_PPC_DCR */
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#define mpic_map(m,n,p,b,o,s)	_mpic_map_mmio(m,p,b,o,s)
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#endif /* !CONFIG_PPC_DCR */


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/* Check if we have one of those nice broken MPICs with a flipped endian on
 * reads from IPI registers
 */
static void __init mpic_test_broken_ipi(struct mpic *mpic)
{
	u32 r;

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	mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
	r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
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	if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
		printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
		mpic->flags |= MPIC_BROKEN_IPI;
	}
}

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#ifdef CONFIG_MPIC_U3_HT_IRQS
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/* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
 * to force the edge setting on the MPIC and do the ack workaround.
 */
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static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
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{
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	if (source >= 128 || !mpic->fixups)
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		return 0;
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	return mpic->fixups[source].base != NULL;
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}

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static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
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{
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	struct mpic_irq_fixup *fixup = &mpic->fixups[source];
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	if (fixup->applebase) {
		unsigned int soff = (fixup->index >> 3) & ~3;
		unsigned int mask = 1U << (fixup->index & 0x1f);
		writel(mask, fixup->applebase + soff);
	} else {
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		raw_spin_lock(&mpic->fixup_lock);
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		writeb(0x11 + 2 * fixup->index, fixup->base + 2);
		writel(fixup->data, fixup->base + 4);
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		raw_spin_unlock(&mpic->fixup_lock);
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	}
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}

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static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
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				      bool level)
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{
	struct mpic_irq_fixup *fixup = &mpic->fixups[source];
	unsigned long flags;
	u32 tmp;

	if (fixup->base == NULL)
		return;

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	DBG("startup_ht_interrupt(0x%x) index: %d\n",
	    source, fixup->index);
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	raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
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	/* Enable and configure */
	writeb(0x10 + 2 * fixup->index, fixup->base + 2);
	tmp = readl(fixup->base + 4);
	tmp &= ~(0x23U);
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	if (level)
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		tmp |= 0x22;
	writel(tmp, fixup->base + 4);
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	raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
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#ifdef CONFIG_PM
	/* use the lowest bit inverted to the actual HW,
	 * set if this fixup was enabled, clear otherwise */
	mpic->save_data[source].fixup_data = tmp | 1;
#endif
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}

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static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
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{
	struct mpic_irq_fixup *fixup = &mpic->fixups[source];
	unsigned long flags;
	u32 tmp;

	if (fixup->base == NULL)
		return;

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	DBG("shutdown_ht_interrupt(0x%x)\n", source);
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	/* Disable */
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	raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
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	writeb(0x10 + 2 * fixup->index, fixup->base + 2);
	tmp = readl(fixup->base + 4);
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	tmp |= 1;
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	writel(tmp, fixup->base + 4);
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	raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
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#ifdef CONFIG_PM
	/* use the lowest bit inverted to the actual HW,
	 * set if this fixup was enabled, clear otherwise */
	mpic->save_data[source].fixup_data = tmp & ~1;
#endif
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}
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#ifdef CONFIG_PCI_MSI
static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
				    unsigned int devfn)
{
	u8 __iomem *base;
	u8 pos, flags;
	u64 addr = 0;

	for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
	     pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
		u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
		if (id == PCI_CAP_ID_HT) {
			id = readb(devbase + pos + 3);
			if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
				break;
		}
	}

	if (pos == 0)
		return;

	base = devbase + pos;

	flags = readb(base + HT_MSI_FLAGS);
	if (!(flags & HT_MSI_FLAGS_FIXED)) {
		addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
		addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
	}

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	printk(KERN_DEBUG "mpic:   - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
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		PCI_SLOT(devfn), PCI_FUNC(devfn),
		flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);

	if (!(flags & HT_MSI_FLAGS_ENABLE))
		writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
}
#else
static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
				    unsigned int devfn)
{
	return;
}
#endif

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static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
				    unsigned int devfn, u32 vdid)
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{
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	int i, irq, n;
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	u8 __iomem *base;
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	u32 tmp;
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	u8 pos;
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	for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
	     pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
		u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
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		if (id == PCI_CAP_ID_HT) {
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			id = readb(devbase + pos + 3);
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			if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
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				break;
		}
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	}
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	if (pos == 0)
		return;

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	base = devbase + pos;
	writeb(0x01, base + 2);
	n = (readl(base + 4) >> 16) & 0xff;
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	printk(KERN_INFO "mpic:   - HT:%02x.%x [0x%02x] vendor %04x device %04x"
	       " has %d irqs\n",
	       devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
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	for (i = 0; i <= n; i++) {
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		writeb(0x10 + 2 * i, base + 2);
		tmp = readl(base + 4);
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		irq = (tmp >> 16) & 0xff;
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		DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
		/* mask it , will be unmasked later */
		tmp |= 0x1;
		writel(tmp, base + 4);
		mpic->fixups[irq].index = i;
		mpic->fixups[irq].base = base;
		/* Apple HT PIC has a non-standard way of doing EOIs */
		if ((vdid & 0xffff) == 0x106b)
			mpic->fixups[irq].applebase = devbase + 0x60;
		else
			mpic->fixups[irq].applebase = NULL;
		writeb(0x11 + 2 * i, base + 2);
		mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
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	}
}
 
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static void __init mpic_scan_ht_pics(struct mpic *mpic)
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{
	unsigned int devfn;
	u8 __iomem *cfgspace;

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	printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
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	/* Allocate fixups array */
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	mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL);
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	BUG_ON(mpic->fixups == NULL);

	/* Init spinlock */
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	raw_spin_lock_init(&mpic->fixup_lock);
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	/* Map U3 config space. We assume all IO-APICs are on the primary bus
	 * so we only need to map 64kB.
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	 */
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	cfgspace = ioremap(0xf2000000, 0x10000);
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	BUG_ON(cfgspace == NULL);

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	/* Now we scan all slots. We do a very quick scan, we read the header
	 * type, vendor ID and device ID only, that's plenty enough
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	 */
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	for (devfn = 0; devfn < 0x100; devfn++) {
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		u8 __iomem *devbase = cfgspace + (devfn << 8);
		u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
		u32 l = readl(devbase + PCI_VENDOR_ID);
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		u16 s;
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		DBG("devfn %x, l: %x\n", devfn, l);

		/* If no device, skip */
		if (l == 0xffffffff || l == 0x00000000 ||
		    l == 0x0000ffff || l == 0xffff0000)
			goto next;
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		/* Check if is supports capability lists */
		s = readw(devbase + PCI_STATUS);
		if (!(s & PCI_STATUS_CAP_LIST))
			goto next;
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		mpic_scan_ht_pic(mpic, devbase, devfn, l);
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		mpic_scan_ht_msi(mpic, devbase, devfn);
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	next:
		/* next device, if function 0 */
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		if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
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			devfn += 7;
	}
}

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#else /* CONFIG_MPIC_U3_HT_IRQS */
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static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
{
	return 0;
}

static void __init mpic_scan_ht_pics(struct mpic *mpic)
{
}

599
#endif /* CONFIG_MPIC_U3_HT_IRQS */
600

601
#ifdef CONFIG_SMP
602
static int irq_choose_cpu(const struct cpumask *mask)
603 604 605
{
	int cpuid;

606
	if (cpumask_equal(mask, cpu_all_mask)) {
607
		static int irq_rover = 0;
608
		static DEFINE_RAW_SPINLOCK(irq_rover_lock);
609 610 611 612
		unsigned long flags;

		/* Round-robin distribution... */
	do_round_robin:
613
		raw_spin_lock_irqsave(&irq_rover_lock, flags);
614

615 616 617 618
		irq_rover = cpumask_next(irq_rover, cpu_online_mask);
		if (irq_rover >= nr_cpu_ids)
			irq_rover = cpumask_first(cpu_online_mask);

619 620
		cpuid = irq_rover;

621
		raw_spin_unlock_irqrestore(&irq_rover_lock, flags);
622
	} else {
623 624
		cpuid = cpumask_first_and(mask, cpu_online_mask);
		if (cpuid >= nr_cpu_ids)
625 626 627
			goto do_round_robin;
	}

628
	return get_hard_smp_processor_id(cpuid);
629 630
}
#else
631
static int irq_choose_cpu(const struct cpumask *mask)
632 633 634 635
{
	return hard_smp_processor_id();
}
#endif
636 637

/* Find an mpic associated with a given linux interrupt */
638
static struct mpic *mpic_find(unsigned int irq)
639
{
640 641
	if (irq < NUM_ISA_INTERRUPTS)
		return NULL;
642

643
	return irq_get_chip_data(irq);
644
}
645

646 647 648
/* Determine if the linux irq is an IPI */
static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
{
649
	unsigned int src = virq_to_hw(irq);
650

651
	return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
652 653
}

654 655 656 657 658 659 660
/* Determine if the linux irq is a timer */
static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int irq)
{
	unsigned int src = virq_to_hw(irq);

	return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
}
661

662 663 664 665 666 667
/* Convert a cpu mask from logical to physical cpu numbers. */
static inline u32 mpic_physmask(u32 cpumask)
{
	int i;
	u32 mask = 0;

668
	for (i = 0; i < min(32, NR_CPUS); ++i, cpumask >>= 1)
669 670 671 672 673 674
		mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
	return mask;
}

#ifdef CONFIG_SMP
/* Get the mpic structure from the IPI number */
675
static inline struct mpic * mpic_from_ipi(struct irq_data *d)
676
{
677
	return irq_data_get_irq_chip_data(d);
678 679 680 681 682 683
}
#endif

/* Get the mpic structure from the irq number */
static inline struct mpic * mpic_from_irq(unsigned int irq)
{
684
	return irq_get_chip_data(irq);
685 686 687 688 689 690
}

/* Get the mpic structure from the irq data */
static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
{
	return irq_data_get_irq_chip_data(d);
691 692 693 694 695
}

/* Send an EOI */
static inline void mpic_eoi(struct mpic *mpic)
{
696 697
	mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
	(void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
698 699 700 701 702 703 704
}

/*
 * Linux descriptor level callbacks
 */


705
void mpic_unmask_irq(struct irq_data *d)
706 707
{
	unsigned int loops = 100000;
708
	struct mpic *mpic = mpic_from_irq_data(d);
709
	unsigned int src = irqd_to_hwirq(d);
710

711
	DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
712

713 714
	mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
		       mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
715
		       ~MPIC_VECPRI_MASK);
716 717 718
	/* make sure mask gets to controller before we return to user */
	do {
		if (!loops--) {
719 720
			printk(KERN_ERR "%s: timeout on hwirq %u\n",
			       __func__, src);
721 722
			break;
		}
723
	} while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
724 725
}

726
void mpic_mask_irq(struct irq_data *d)
727 728
{
	unsigned int loops = 100000;
729
	struct mpic *mpic = mpic_from_irq_data(d);
730
	unsigned int src = irqd_to_hwirq(d);
731

732
	DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
733

734 735
	mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
		       mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
736
		       MPIC_VECPRI_MASK);
737 738 739 740

	/* make sure mask gets to controller before we return to user */
	do {
		if (!loops--) {
741 742
			printk(KERN_ERR "%s: timeout on hwirq %u\n",
			       __func__, src);
743 744
			break;
		}
745
	} while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
746 747
}

748
void mpic_end_irq(struct irq_data *d)
749
{
750
	struct mpic *mpic = mpic_from_irq_data(d);
751 752

#ifdef DEBUG_IRQ
753
	DBG("%s: end_irq: %d\n", mpic->name, d->irq);
754 755 756 757 758 759 760 761 762
#endif
	/* We always EOI on end_irq() even for edge interrupts since that
	 * should only lower the priority, the MPIC should have properly
	 * latched another edge interrupt coming in anyway
	 */

	mpic_eoi(mpic);
}

763
#ifdef CONFIG_MPIC_U3_HT_IRQS
764

765
static void mpic_unmask_ht_irq(struct irq_data *d)
766
{
767
	struct mpic *mpic = mpic_from_irq_data(d);
768
	unsigned int src = irqd_to_hwirq(d);
769

770
	mpic_unmask_irq(d);
771

772
	if (irqd_is_level_type(d))
773 774 775
		mpic_ht_end_irq(mpic, src);
}

776
static unsigned int mpic_startup_ht_irq(struct irq_data *d)
777
{
778
	struct mpic *mpic = mpic_from_irq_data(d);
779
	unsigned int src = irqd_to_hwirq(d);
780

781
	mpic_unmask_irq(d);
782
	mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
783 784

	return 0;
785 786
}

787
static void mpic_shutdown_ht_irq(struct irq_data *d)
788
{
789
	struct mpic *mpic = mpic_from_irq_data(d);
790
	unsigned int src = irqd_to_hwirq(d);
791

792
	mpic_shutdown_ht_interrupt(mpic, src);
793
	mpic_mask_irq(d);
794 795
}

796
static void mpic_end_ht_irq(struct irq_data *d)
797
{
798
	struct mpic *mpic = mpic_from_irq_data(d);
799
	unsigned int src = irqd_to_hwirq(d);
800

801
#ifdef DEBUG_IRQ
802
	DBG("%s: end_irq: %d\n", mpic->name, d->irq);
803
#endif
804 805 806 807 808
	/* We always EOI on end_irq() even for edge interrupts since that
	 * should only lower the priority, the MPIC should have properly
	 * latched another edge interrupt coming in anyway
	 */

809
	if (irqd_is_level_type(d))
810
		mpic_ht_end_irq(mpic, src);
811 812
	mpic_eoi(mpic);
}
813
#endif /* !CONFIG_MPIC_U3_HT_IRQS */
814

815 816
#ifdef CONFIG_SMP

817
static void mpic_unmask_ipi(struct irq_data *d)
818
{
819
	struct mpic *mpic = mpic_from_ipi(d);
820
	unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0];
821

822
	DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
823 824 825
	mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
}

826
static void mpic_mask_ipi(struct irq_data *d)
827 828 829 830
{
	/* NEVER disable an IPI... that's just plain wrong! */
}

831
static void mpic_end_ipi(struct irq_data *d)
832
{
833
	struct mpic *mpic = mpic_from_ipi(d);
834 835 836 837 838

	/*
	 * IPIs are marked IRQ_PER_CPU. This has the side effect of
	 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
	 * applying to them. We EOI them late to avoid re-entering.
839
	 * We mark IPI's with IRQF_DISABLED as they must run with
840 841 842 843 844 845 846
	 * irqs disabled.
	 */
	mpic_eoi(mpic);
}

#endif /* CONFIG_SMP */

847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865
static void mpic_unmask_tm(struct irq_data *d)
{
	struct mpic *mpic = mpic_from_irq_data(d);
	unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];

	DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, irq, src);
	mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK);
	mpic_tm_read(src);
}

static void mpic_mask_tm(struct irq_data *d)
{
	struct mpic *mpic = mpic_from_irq_data(d);
	unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];

	mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK);
	mpic_tm_read(src);
}

866 867
int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
		      bool force)
868
{
869
	struct mpic *mpic = mpic_from_irq_data(d);
870
	unsigned int src = irqd_to_hwirq(d);
871

872
	if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
873
		int cpuid = irq_choose_cpu(cpumask);
874

875 876
		mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
	} else {
877
		u32 mask = cpumask_bits(cpumask)[0];
878

879
		mask &= cpumask_bits(cpu_online_mask)[0];
880 881

		mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
882
			       mpic_physmask(mask));
883
	}
884 885

	return 0;
886 887
}

888
static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
889 890
{
	/* Now convert sense value */
891
	switch(type & IRQ_TYPE_SENSE_MASK) {
892
	case IRQ_TYPE_EDGE_RISING:
893 894
		return MPIC_INFO(VECPRI_SENSE_EDGE) |
		       MPIC_INFO(VECPRI_POLARITY_POSITIVE);
895
	case IRQ_TYPE_EDGE_FALLING:
896
	case IRQ_TYPE_EDGE_BOTH:
897 898
		return MPIC_INFO(VECPRI_SENSE_EDGE) |
		       MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
899
	case IRQ_TYPE_LEVEL_HIGH:
900 901
		return MPIC_INFO(VECPRI_SENSE_LEVEL) |
		       MPIC_INFO(VECPRI_POLARITY_POSITIVE);
902 903
	case IRQ_TYPE_LEVEL_LOW:
	default:
904 905
		return MPIC_INFO(VECPRI_SENSE_LEVEL) |
		       MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
906
	}
907 908
}

909
int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
910
{
911
	struct mpic *mpic = mpic_from_irq_data(d);
912
	unsigned int src = irqd_to_hwirq(d);
913 914
	unsigned int vecpri, vold, vnew;

915
	DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
916
	    mpic, d->irq, src, flow_type);
917 918 919 920 921 922 923 924 925 926

	if (src >= mpic->irq_count)
		return -EINVAL;

	if (flow_type == IRQ_TYPE_NONE)
		if (mpic->senses && src < mpic->senses_count)
			flow_type = mpic->senses[src];
	if (flow_type == IRQ_TYPE_NONE)
		flow_type = IRQ_TYPE_LEVEL_LOW;

927
	irqd_set_trigger_type(d, flow_type);
928 929 930 931 932

	if (mpic_is_ht_interrupt(mpic, src))
		vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
			MPIC_VECPRI_SENSE_EDGE;
	else
933
		vecpri = mpic_type_to_vecpri(mpic, flow_type);
934

935 936 937
	vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
	vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
			MPIC_INFO(VECPRI_SENSE_MASK));
938 939
	vnew |= vecpri;
	if (vold != vnew)
940
		mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
941

942
	return IRQ_SET_MASK_OK_NOCOPY;;
943 944
}

945 946 947
void mpic_set_vector(unsigned int virq, unsigned int vector)
{
	struct mpic *mpic = mpic_from_irq(virq);
948
	unsigned int src = virq_to_hw(virq);
949 950 951 952 953 954 955 956 957 958 959 960 961 962
	unsigned int vecpri;

	DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
	    mpic, virq, src, vector);

	if (src >= mpic->irq_count)
		return;

	vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
	vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
	vecpri |= vector;
	mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
}

963 964 965
void mpic_set_destination(unsigned int virq, unsigned int cpuid)
{
	struct mpic *mpic = mpic_from_irq(virq);
966
	unsigned int src = virq_to_hw(virq);
967 968 969 970 971 972 973 974 975 976

	DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
	    mpic, virq, src, cpuid);

	if (src >= mpic->irq_count)
		return;

	mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
}

977
static struct irq_chip mpic_irq_chip = {
978 979 980 981
	.irq_mask	= mpic_mask_irq,
	.irq_unmask	= mpic_unmask_irq,
	.irq_eoi	= mpic_end_irq,
	.irq_set_type	= mpic_set_irq_type,
982 983 984 985
};

#ifdef CONFIG_SMP
static struct irq_chip mpic_ipi_chip = {
986 987 988
	.irq_mask	= mpic_mask_ipi,
	.irq_unmask	= mpic_unmask_ipi,
	.irq_eoi	= mpic_end_ipi,
989 990 991
};
#endif /* CONFIG_SMP */

992 993 994 995 996 997
static struct irq_chip mpic_tm_chip = {
	.irq_mask	= mpic_mask_tm,
	.irq_unmask	= mpic_unmask_tm,
	.irq_eoi	= mpic_end_irq,
};

998
#ifdef CONFIG_MPIC_U3_HT_IRQS
999
static struct irq_chip mpic_irq_ht_chip = {
1000 1001 1002 1003 1004 1005
	.irq_startup	= mpic_startup_ht_irq,
	.irq_shutdown	= mpic_shutdown_ht_irq,
	.irq_mask	= mpic_mask_irq,
	.irq_unmask	= mpic_unmask_ht_irq,
	.irq_eoi	= mpic_end_ht_irq,
	.irq_set_type	= mpic_set_irq_type,
1006
};
1007
#endif /* CONFIG_MPIC_U3_HT_IRQS */
1008

1009

1010 1011 1012
static int mpic_host_match(struct irq_host *h, struct device_node *node)
{
	/* Exact match, unless mpic node is NULL */
1013
	return h->of_node == NULL || h->of_node == node;
1014 1015 1016
}

static int mpic_host_map(struct irq_host *h, unsigned int virq,
1017
			 irq_hw_number_t hw)
1018 1019
{
	struct mpic *mpic = h->host_data;
1020
	struct irq_chip *chip;
1021

1022
	DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
1023

1024
	if (hw == mpic->spurious_vec)
1025
		return -EINVAL;
1026 1027
	if (mpic->protected && test_bit(hw, mpic->protected))
		return -EINVAL;
1028

1029
#ifdef CONFIG_SMP
1030
	else if (hw >= mpic->ipi_vecs[0]) {
1031 1032
		WARN_ON(!(mpic->flags & MPIC_PRIMARY));

1033
		DBG("mpic: mapping as IPI\n");
1034 1035
		irq_set_chip_data(virq, mpic);
		irq_set_chip_and_handler(virq, &mpic->hc_ipi,
1036 1037 1038 1039 1040
					 handle_percpu_irq);
		return 0;
	}
#endif /* CONFIG_SMP */

1041 1042 1043 1044 1045 1046 1047 1048 1049 1050
	if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) {
		WARN_ON(!(mpic->flags & MPIC_PRIMARY));

		DBG("mpic: mapping as timer\n");
		irq_set_chip_data(virq, mpic);
		irq_set_chip_and_handler(virq, &mpic->hc_tm,
					 handle_fasteoi_irq);
		return 0;
	}

1051 1052 1053
	if (hw >= mpic->irq_count)
		return -EINVAL;

M
Michael Ellerman 已提交
1054 1055
	mpic_msi_reserve_hwirq(mpic, hw);

1056
	/* Default chip */
1057 1058
	chip = &mpic->hc_irq;

1059
#ifdef CONFIG_MPIC_U3_HT_IRQS
1060
	/* Check for HT interrupts, override vecpri */
1061
	if (mpic_is_ht_interrupt(mpic, hw))
1062
		chip = &mpic->hc_ht_irq;
1063
#endif /* CONFIG_MPIC_U3_HT_IRQS */
1064

1065
	DBG("mpic: mapping to irq chip @%p\n", chip);
1066

1067 1068
	irq_set_chip_data(virq, mpic);
	irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
1069 1070

	/* Set default irq type */
1071
	irq_set_irq_type(virq, IRQ_TYPE_NONE);
1072

1073 1074 1075 1076 1077 1078
	/* If the MPIC was reset, then all vectors have already been
	 * initialized.  Otherwise, a per source lazy initialization
	 * is done here.
	 */
	if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
		mpic_set_vector(virq, hw);
1079
		mpic_set_destination(virq, mpic_processor_id(mpic));
1080 1081 1082
		mpic_irq_set_priority(virq, 8);
	}

1083 1084 1085 1086
	return 0;
}

static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
1087
			   const u32 *intspec, unsigned int intsize,
1088 1089 1090
			   irq_hw_number_t *out_hwirq, unsigned int *out_flags)

{
1091
	struct mpic *mpic = h->host_data;
1092 1093 1094 1095 1096 1097 1098 1099
	static unsigned char map_mpic_senses[4] = {
		IRQ_TYPE_EDGE_RISING,
		IRQ_TYPE_LEVEL_LOW,
		IRQ_TYPE_LEVEL_HIGH,
		IRQ_TYPE_EDGE_FALLING,
	};

	*out_hwirq = intspec[0];
1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131
	if (intsize >= 4 && (mpic->flags & MPIC_FSL)) {
		/*
		 * Freescale MPIC with extended intspec:
		 * First two cells are as usual.  Third specifies
		 * an "interrupt type".  Fourth is type-specific data.
		 *
		 * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
		 */
		switch (intspec[2]) {
		case 0:
		case 1: /* no EISR/EIMR support for now, treat as shared IRQ */
			break;
		case 2:
			if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
				return -EINVAL;

			*out_hwirq = mpic->ipi_vecs[intspec[0]];
			break;
		case 3:
			if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs))
				return -EINVAL;

			*out_hwirq = mpic->timer_vecs[intspec[0]];
			break;
		default:
			pr_debug("%s: unknown irq type %u\n",
				 __func__, intspec[2]);
			return -EINVAL;
		}

		*out_flags = map_mpic_senses[intspec[1] & 3];
	} else if (intsize > 1) {
1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147
		u32 mask = 0x3;

		/* Apple invented a new race of encoding on machines with
		 * an HT APIC. They encode, among others, the index within
		 * the HT APIC. We don't care about it here since thankfully,
		 * it appears that they have the APIC already properly
		 * configured, and thus our current fixup code that reads the
		 * APIC config works fine. However, we still need to mask out
		 * bits in the specifier to make sure we only get bit 0 which
		 * is the level/edge bit (the only sense bit exposed by Apple),
		 * as their bit 1 means something else.
		 */
		if (machine_is(powermac))
			mask = 0x1;
		*out_flags = map_mpic_senses[intspec[1] & mask];
	} else
1148 1149
		*out_flags = IRQ_TYPE_NONE;

1150 1151 1152
	DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
	    intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);

1153 1154 1155 1156 1157 1158 1159 1160 1161
	return 0;
}

static struct irq_host_ops mpic_host_ops = {
	.match = mpic_host_match,
	.map = mpic_host_map,
	.xlate = mpic_host_xlate,
};

1162 1163 1164 1165 1166
static int mpic_reset_prohibited(struct device_node *node)
{
	return node && of_get_property(node, "pic-no-reset", NULL);
}

1167 1168 1169 1170
/*
 * Exported functions
 */

1171
struct mpic * __init mpic_alloc(struct device_node *node,
1172
				phys_addr_t phys_addr,
1173 1174 1175 1176 1177 1178
				unsigned int flags,
				unsigned int isu_size,
				unsigned int irq_count,
				const char *name)
{
	struct mpic	*mpic;
1179
	u32		greg_feature;
1180 1181
	const char	*vers;
	int		i;
1182
	int		intvec_top;
1183
	u64		paddr = phys_addr;
1184

K
Kumar Gala 已提交
1185
	mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1186 1187
	if (mpic == NULL)
		return NULL;
K
Kumar Gala 已提交
1188

1189 1190
	mpic->name = name;

1191
	mpic->hc_irq = mpic_irq_chip;
1192
	mpic->hc_irq.name = name;
1193
	if (flags & MPIC_PRIMARY)
1194
		mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1195
#ifdef CONFIG_MPIC_U3_HT_IRQS
1196
	mpic->hc_ht_irq = mpic_irq_ht_chip;
1197
	mpic->hc_ht_irq.name = name;
1198
	if (flags & MPIC_PRIMARY)
1199
		mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1200
#endif /* CONFIG_MPIC_U3_HT_IRQS */
1201

1202
#ifdef CONFIG_SMP
1203
	mpic->hc_ipi = mpic_ipi_chip;
1204
	mpic->hc_ipi.name = name;
1205 1206
#endif /* CONFIG_SMP */

1207 1208 1209
	mpic->hc_tm = mpic_tm_chip;
	mpic->hc_tm.name = name;

1210 1211 1212 1213 1214
	mpic->flags = flags;
	mpic->isu_size = isu_size;
	mpic->irq_count = irq_count;
	mpic->num_sources = 0; /* so far */

1215 1216 1217 1218 1219
	if (flags & MPIC_LARGE_VECTORS)
		intvec_top = 2047;
	else
		intvec_top = 255;

1220 1221 1222 1223 1224 1225 1226 1227
	mpic->timer_vecs[0] = intvec_top - 12;
	mpic->timer_vecs[1] = intvec_top - 11;
	mpic->timer_vecs[2] = intvec_top - 10;
	mpic->timer_vecs[3] = intvec_top - 9;
	mpic->timer_vecs[4] = intvec_top - 8;
	mpic->timer_vecs[5] = intvec_top - 7;
	mpic->timer_vecs[6] = intvec_top - 6;
	mpic->timer_vecs[7] = intvec_top - 5;
1228 1229 1230 1231 1232 1233
	mpic->ipi_vecs[0]   = intvec_top - 4;
	mpic->ipi_vecs[1]   = intvec_top - 3;
	mpic->ipi_vecs[2]   = intvec_top - 2;
	mpic->ipi_vecs[3]   = intvec_top - 1;
	mpic->spurious_vec  = intvec_top;

1234
	/* Check for "big-endian" in device-tree */
1235
	if (node && of_get_property(node, "big-endian", NULL) != NULL)
1236
		mpic->flags |= MPIC_BIG_ENDIAN;
1237 1238
	if (node && of_device_is_compatible(node, "fsl,mpic"))
		mpic->flags |= MPIC_FSL;
1239

1240 1241
	/* Look for protected sources */
	if (node) {
1242 1243
		int psize;
		unsigned int bits, mapsize;
1244 1245 1246 1247 1248 1249
		const u32 *psrc =
			of_get_property(node, "protected-sources", &psize);
		if (psrc) {
			psize /= 4;
			bits = intvec_top + 1;
			mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long);
1250
			mpic->protected = kzalloc(mapsize, GFP_KERNEL);
1251 1252 1253 1254 1255 1256 1257 1258
			BUG_ON(mpic->protected == NULL);
			for (i = 0; i < psize; i++) {
				if (psrc[i] > intvec_top)
					continue;
				__set_bit(psrc[i], mpic->protected);
			}
		}
	}
1259

1260 1261 1262 1263
#ifdef CONFIG_MPIC_WEIRD
	mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
#endif

1264 1265 1266 1267
	/* default register type */
	mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?
		mpic_access_mmio_be : mpic_access_mmio_le;

1268 1269 1270 1271
	/* If no physical address is passed in, a device-node is mandatory */
	BUG_ON(paddr == 0 && node == NULL);

	/* If no physical address passed in, check if it's dcr based */
1272
	if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) {
1273
#ifdef CONFIG_PPC_DCR
1274
		mpic->flags |= MPIC_USES_DCR;
1275 1276
		mpic->reg_type = mpic_access_dcr;
#else
1277
		BUG();
1278
#endif /* CONFIG_PPC_DCR */
1279
	}
1280

1281 1282 1283 1284
	/* If the MPIC is not DCR based, and no physical address was passed
	 * in, try to obtain one
	 */
	if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
1285
		const u32 *reg = of_get_property(node, "reg", NULL);
1286 1287 1288 1289 1290
		BUG_ON(reg == NULL);
		paddr = of_translate_address(node, reg);
		BUG_ON(paddr == OF_BAD_ADDR);
	}

1291
	/* Map the global registers */
1292 1293
	mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
	mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1294 1295

	/* Reset */
1296 1297 1298 1299 1300 1301 1302 1303 1304

	/* When using a device-node, reset requests are only honored if the MPIC
	 * is allowed to reset.
	 */
	if (mpic_reset_prohibited(node))
		mpic->flags |= MPIC_NO_RESET;

	if ((flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) {
		printk(KERN_DEBUG "mpic: Resetting\n");
1305 1306
		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1307
			   | MPIC_GREG_GCONF_RESET);
1308
		while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1309 1310 1311 1312
		       & MPIC_GREG_GCONF_RESET)
			mb();
	}

1313 1314 1315 1316 1317 1318
	/* CoreInt */
	if (flags & MPIC_ENABLE_COREINT)
		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
			   | MPIC_GREG_GCONF_COREINT);

1319 1320 1321 1322 1323
	if (flags & MPIC_ENABLE_MCK)
		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
			   | MPIC_GREG_GCONF_MCK);

1324 1325 1326 1327
	/* Read feature register, calculate num CPUs and, for non-ISU
	 * MPICs, num sources as well. On ISU MPICs, sources are counted
	 * as ISUs are added
	 */
1328 1329
	greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
	mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK)
1330
			  >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
1331
	if (isu_size == 0) {
1332 1333 1334 1335 1336 1337
		if (flags & MPIC_BROKEN_FRR_NIRQS)
			mpic->num_sources = mpic->irq_count;
		else
			mpic->num_sources =
				((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
				 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
1338
	}
1339 1340 1341

	/* Map the per-CPU registers */
	for (i = 0; i < mpic->num_cpus; i++) {
1342
		mpic_map(mpic, node, paddr, &mpic->cpuregs[i],
1343 1344
			 MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE),
			 0x1000);
1345 1346 1347 1348 1349
	}

	/* Initialize main ISU if none provided */
	if (mpic->isu_size == 0) {
		mpic->isu_size = mpic->num_sources;
1350
		mpic_map(mpic, node, paddr, &mpic->isus[0],
1351
			 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1352 1353 1354 1355
	}
	mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
	mpic->isu_mask = (1 << mpic->isu_shift) - 1;

1356 1357 1358 1359 1360 1361 1362 1363 1364
	mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
				       isu_size ? isu_size : mpic->num_sources,
				       &mpic_host_ops,
				       flags & MPIC_LARGE_VECTORS ? 2048 : 256);
	if (mpic->irqhost == NULL)
		return NULL;

	mpic->irqhost->host_data = mpic;

1365
	/* Display version */
1366
	switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379
	case 1:
		vers = "1.0";
		break;
	case 2:
		vers = "1.2";
		break;
	case 3:
		vers = "1.3";
		break;
	default:
		vers = "<unknown>";
		break;
	}
1380 1381 1382 1383 1384
	printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
	       " max %d CPUs\n",
	       name, vers, (unsigned long long)paddr, mpic->num_cpus);
	printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
	       mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1385 1386 1387 1388

	mpic->next = mpics;
	mpics = mpic;

1389
	if (flags & MPIC_PRIMARY) {
1390
		mpic_primary = mpic;
1391 1392
		irq_set_default_host(mpic->irqhost);
	}
1393 1394 1395 1396 1397

	return mpic;
}

void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1398
			    phys_addr_t paddr)
1399 1400 1401 1402 1403
{
	unsigned int isu_first = isu_num * mpic->isu_size;

	BUG_ON(isu_num >= MPIC_MAX_ISU);

1404 1405
	mpic_map(mpic, mpic->irqhost->of_node,
		 paddr, &mpic->isus[isu_num], 0,
1406
		 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1407

1408 1409 1410 1411
	if ((isu_first + mpic->isu_size) > mpic->num_sources)
		mpic->num_sources = isu_first + mpic->isu_size;
}

1412 1413 1414 1415 1416 1417
void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
{
	mpic->senses = senses;
	mpic->senses_count = count;
}

1418 1419 1420
void __init mpic_init(struct mpic *mpic)
{
	int i;
1421
	int cpu;
1422 1423 1424 1425 1426 1427

	BUG_ON(mpic->num_sources == 0);

	printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);

	/* Set current processor priority to max */
1428
	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1429

1430
	/* Initialize timers to our reserved vectors and mask them for now */
1431 1432
	for (i = 0; i < 4; i++) {
		mpic_write(mpic->tmregs,
1433
			   i * MPIC_INFO(TIMER_STRIDE) +
1434 1435
			   MPIC_INFO(TIMER_DESTINATION),
			   1 << hard_smp_processor_id());
1436
		mpic_write(mpic->tmregs,
1437 1438
			   i * MPIC_INFO(TIMER_STRIDE) +
			   MPIC_INFO(TIMER_VECTOR_PRI),
1439
			   MPIC_VECPRI_MASK |
1440
			   (9 << MPIC_VECPRI_PRIORITY_SHIFT) |
1441
			   (mpic->timer_vecs[0] + i));
1442 1443 1444 1445 1446 1447 1448 1449
	}

	/* Initialize IPIs to our reserved vectors and mark them disabled for now */
	mpic_test_broken_ipi(mpic);
	for (i = 0; i < 4; i++) {
		mpic_ipi_write(i,
			       MPIC_VECPRI_MASK |
			       (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1450
			       (mpic->ipi_vecs[0] + i));
1451 1452 1453 1454 1455 1456
	}

	/* Initialize interrupt sources */
	if (mpic->irq_count == 0)
		mpic->irq_count = mpic->num_sources;

1457
	/* Do the HT PIC fixups on U3 broken mpic */
1458
	DBG("MPIC flags: %x\n", mpic->flags);
1459
	if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) {
1460
		mpic_scan_ht_pics(mpic);
1461 1462
		mpic_u3msi_init(mpic);
	}
1463

1464 1465
	mpic_pasemi_msi_init(mpic);

1466
	cpu = mpic_processor_id(mpic);
1467

1468 1469 1470 1471 1472
	if (!(mpic->flags & MPIC_NO_RESET)) {
		for (i = 0; i < mpic->num_sources; i++) {
			/* start with vector = source number, and masked */
			u32 vecpri = MPIC_VECPRI_MASK | i |
				(8 << MPIC_VECPRI_PRIORITY_SHIFT);
1473
		
1474 1475 1476 1477 1478 1479 1480
			/* check if protected */
			if (mpic->protected && test_bit(i, mpic->protected))
				continue;
			/* init hw */
			mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
			mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
		}
1481 1482
	}
	
1483 1484
	/* Init spurious vector */
	mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1485

1486 1487 1488 1489 1490
	/* Disable 8259 passthrough, if supported */
	if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
			   | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1491

1492 1493 1494 1495 1496
	if (mpic->flags & MPIC_NO_BIAS)
		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
			mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
			| MPIC_GREG_GCONF_NO_BIAS);

1497
	/* Set current processor priority to 0 */
1498
	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1499 1500 1501

#ifdef CONFIG_PM
	/* allocate memory to save mpic state */
1502 1503
	mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data),
				  GFP_KERNEL);
1504 1505
	BUG_ON(mpic->save_data == NULL);
#endif
1506 1507
}

1508 1509 1510 1511 1512 1513 1514 1515 1516
void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
{
	u32 v;

	v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
	v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
	v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
	mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
}
1517

1518 1519
void __init mpic_set_serial_int(struct mpic *mpic, int enable)
{
1520
	unsigned long flags;
1521 1522
	u32 v;

1523
	raw_spin_lock_irqsave(&mpic_lock, flags);
1524 1525 1526 1527 1528 1529
	v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
	if (enable)
		v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
	else
		v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
	mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1530
	raw_spin_unlock_irqrestore(&mpic_lock, flags);
1531
}
1532 1533 1534

void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
{
1535
	struct mpic *mpic = mpic_find(irq);
1536
	unsigned int src = virq_to_hw(irq);
1537 1538 1539
	unsigned long flags;
	u32 reg;

1540 1541 1542
	if (!mpic)
		return;

1543
	raw_spin_lock_irqsave(&mpic_lock, flags);
1544
	if (mpic_is_ipi(mpic, irq)) {
1545
		reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1546
			~MPIC_VECPRI_PRIORITY_MASK;
1547
		mpic_ipi_write(src - mpic->ipi_vecs[0],
1548
			       reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1549 1550 1551 1552 1553
	} else if (mpic_is_tm(mpic, irq)) {
		reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
			~MPIC_VECPRI_PRIORITY_MASK;
		mpic_tm_write(src - mpic->timer_vecs[0],
			      reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1554
	} else {
1555
		reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1556
			& ~MPIC_VECPRI_PRIORITY_MASK;
1557
		mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1558 1559
			       reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
	}
1560
	raw_spin_unlock_irqrestore(&mpic_lock, flags);
1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574
}

void mpic_setup_this_cpu(void)
{
#ifdef CONFIG_SMP
	struct mpic *mpic = mpic_primary;
	unsigned long flags;
	u32 msk = 1 << hard_smp_processor_id();
	unsigned int i;

	BUG_ON(mpic == NULL);

	DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());

1575
	raw_spin_lock_irqsave(&mpic_lock, flags);
1576 1577 1578 1579

 	/* let the mpic know we want intrs. default affinity is 0xffffffff
	 * until changed via /proc. That's how it's done on x86. If we want
	 * it differently, then we should make sure we also change the default
1580
	 * values of irq_desc[].affinity in irq.c.
1581 1582 1583
 	 */
	if (distribute_irqs) {
	 	for (i = 0; i < mpic->num_sources ; i++)
1584 1585
			mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
				mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1586 1587 1588
	}

	/* Set current processor priority to 0 */
1589
	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1590

1591
	raw_spin_unlock_irqrestore(&mpic_lock, flags);
1592 1593 1594 1595 1596 1597 1598
#endif /* CONFIG_SMP */
}

int mpic_cpu_get_priority(void)
{
	struct mpic *mpic = mpic_primary;

1599
	return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1600 1601 1602 1603 1604 1605 1606
}

void mpic_cpu_set_priority(int prio)
{
	struct mpic *mpic = mpic_primary;

	prio &= MPIC_CPU_TASKPRI_MASK;
1607
	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619
}

void mpic_teardown_this_cpu(int secondary)
{
	struct mpic *mpic = mpic_primary;
	unsigned long flags;
	u32 msk = 1 << hard_smp_processor_id();
	unsigned int i;

	BUG_ON(mpic == NULL);

	DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1620
	raw_spin_lock_irqsave(&mpic_lock, flags);
1621 1622 1623

	/* let the mpic know we don't want intrs.  */
	for (i = 0; i < mpic->num_sources ; i++)
1624 1625
		mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
			mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1626 1627

	/* Set current processor priority to max */
1628
	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1629 1630 1631 1632
	/* We need to EOI the IPI since not all platforms reset the MPIC
	 * on boot and new interrupts wouldn't get delivered otherwise.
	 */
	mpic_eoi(mpic);
1633

1634
	raw_spin_unlock_irqrestore(&mpic_lock, flags);
1635 1636 1637
}


1638
static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1639
{
1640
	u32 src;
1641

1642
	src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1643
#ifdef DEBUG_LOW
1644
	DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1645
#endif
1646 1647 1648
	if (unlikely(src == mpic->spurious_vec)) {
		if (mpic->flags & MPIC_SPV_EOI)
			mpic_eoi(mpic);
1649
		return NO_IRQ;
1650
	}
1651
	if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1652 1653
		printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
				   mpic->name, (int)src);
1654 1655 1656 1657
		mpic_eoi(mpic);
		return NO_IRQ;
	}

1658
	return irq_linear_revmap(mpic->irqhost, src);
1659 1660
}

1661 1662 1663 1664 1665
unsigned int mpic_get_one_irq(struct mpic *mpic)
{
	return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
}

O
Olaf Hering 已提交
1666
unsigned int mpic_get_irq(void)
1667 1668 1669 1670 1671
{
	struct mpic *mpic = mpic_primary;

	BUG_ON(mpic == NULL);

O
Olaf Hering 已提交
1672
	return mpic_get_one_irq(mpic);
1673 1674
}

1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690
unsigned int mpic_get_coreint_irq(void)
{
#ifdef CONFIG_BOOKE
	struct mpic *mpic = mpic_primary;
	u32 src;

	BUG_ON(mpic == NULL);

	src = mfspr(SPRN_EPR);

	if (unlikely(src == mpic->spurious_vec)) {
		if (mpic->flags & MPIC_SPV_EOI)
			mpic_eoi(mpic);
		return NO_IRQ;
	}
	if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1691 1692
		printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
				   mpic->name, (int)src);
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		return NO_IRQ;
	}

	return irq_linear_revmap(mpic->irqhost, src);
#else
	return NO_IRQ;
#endif
}

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unsigned int mpic_get_mcirq(void)
{
	struct mpic *mpic = mpic_primary;

	BUG_ON(mpic == NULL);

	return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
}
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#ifdef CONFIG_SMP
void mpic_request_ipis(void)
{
	struct mpic *mpic = mpic_primary;
1715
	int i;
1716 1717
	BUG_ON(mpic == NULL);

1718
	printk(KERN_INFO "mpic: requesting IPIs...\n");
1719 1720 1721

	for (i = 0; i < 4; i++) {
		unsigned int vipi = irq_create_mapping(mpic->irqhost,
1722
						       mpic->ipi_vecs[0] + i);
1723
		if (vipi == NO_IRQ) {
1724 1725
			printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
			continue;
1726
		}
1727
		smp_request_message_ipi(vipi, i);
1728
	}
1729
}
1730

1731
void smp_mpic_message_pass(int cpu, int msg)
1732 1733
{
	struct mpic *mpic = mpic_primary;
1734
	u32 physmask;
1735 1736 1737

	BUG_ON(mpic == NULL);

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	/* make sure we're sending something that translates to an IPI */
	if ((unsigned int)msg > 3) {
		printk("SMP %d: smp_message_pass: unknown msg %d\n",
		       smp_processor_id(), msg);
		return;
	}
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#ifdef DEBUG_IPI
	DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg);
#endif

	physmask = 1 << get_hard_smp_processor_id(cpu);

	mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
		       msg * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), physmask);
1753
}
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int __init smp_mpic_probe(void)
{
	int nr_cpus;

	DBG("smp_mpic_probe()...\n");

1761
	nr_cpus = cpumask_weight(cpu_possible_mask);
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	DBG("nr_cpus: %d\n", nr_cpus);

	if (nr_cpus > 1)
		mpic_request_ipis();

	return nr_cpus;
}

void __devinit smp_mpic_setup_cpu(int cpu)
{
	mpic_setup_this_cpu();
}
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void mpic_reset_core(int cpu)
{
	struct mpic *mpic = mpic_primary;
	u32 pir;
	int cpuid = get_hard_smp_processor_id(cpu);

	/* Set target bit for core reset */
	pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
	pir |= (1 << cpuid);
	mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
	mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));

	/* Restore target bit after reset complete */
	pir &= ~(1 << cpuid);
	mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
	mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
}
1793
#endif /* CONFIG_SMP */
1794 1795

#ifdef CONFIG_PM
1796
static void mpic_suspend_one(struct mpic *mpic)
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{
	int i;

	for (i = 0; i < mpic->num_sources; i++) {
		mpic->save_data[i].vecprio =
			mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
		mpic->save_data[i].dest =
			mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
	}
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}

static int mpic_suspend(void)
{
	struct mpic *mpic = mpics;

	while (mpic) {
		mpic_suspend_one(mpic);
		mpic = mpic->next;
	}
1816 1817 1818 1819

	return 0;
}

1820
static void mpic_resume_one(struct mpic *mpic)
1821 1822 1823 1824 1825 1826 1827 1828 1829 1830
{
	int i;

	for (i = 0; i < mpic->num_sources; i++) {
		mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
			       mpic->save_data[i].vecprio);
		mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
			       mpic->save_data[i].dest);

#ifdef CONFIG_MPIC_U3_HT_IRQS
1831
	if (mpic->fixups) {
1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847
		struct mpic_irq_fixup *fixup = &mpic->fixups[i];

		if (fixup->base) {
			/* we use the lowest bit in an inverted meaning */
			if ((mpic->save_data[i].fixup_data & 1) == 0)
				continue;

			/* Enable and configure */
			writeb(0x10 + 2 * fixup->index, fixup->base + 2);

			writel(mpic->save_data[i].fixup_data & ~1,
			       fixup->base + 4);
		}
	}
#endif
	} /* end for loop */
1848
}
1849

1850 1851 1852 1853 1854 1855 1856 1857
static void mpic_resume(void)
{
	struct mpic *mpic = mpics;

	while (mpic) {
		mpic_resume_one(mpic);
		mpic = mpic->next;
	}
1858 1859
}

1860
static struct syscore_ops mpic_syscore_ops = {
1861 1862 1863 1864 1865 1866
	.resume = mpic_resume,
	.suspend = mpic_suspend,
};

static int mpic_init_sys(void)
{
1867 1868
	register_syscore_ops(&mpic_syscore_ops);
	return 0;
1869 1870 1871
}

device_initcall(mpic_init_sys);
1872
#endif