mpic.c 44.4 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
/*
 *  arch/powerpc/kernel/mpic.c
 *
 *  Driver for interrupt controllers following the OpenPIC standard, the
 *  common implementation beeing IBM's MPIC. This driver also can deal
 *  with various broken implementations of this HW.
 *
 *  Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
 *
 *  This file is subject to the terms and conditions of the GNU General Public
 *  License.  See the file COPYING in the main directory of this archive
 *  for more details.
 */

#undef DEBUG
16 17 18
#undef DEBUG_IPI
#undef DEBUG_IRQ
#undef DEBUG_LOW
19 20 21 22 23 24 25 26 27 28

#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/smp.h>
#include <linux/interrupt.h>
#include <linux/bootmem.h>
#include <linux/spinlock.h>
#include <linux/pci.h>
29
#include <linux/slab.h>
30 31 32 33 34 35 36 37 38 39

#include <asm/ptrace.h>
#include <asm/signal.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/irq.h>
#include <asm/machdep.h>
#include <asm/mpic.h>
#include <asm/smp.h>

M
Michael Ellerman 已提交
40 41
#include "mpic.h"

42 43 44 45 46 47 48 49
#ifdef DEBUG
#define DBG(fmt...) printk(fmt)
#else
#define DBG(fmt...)
#endif

static struct mpic *mpics;
static struct mpic *mpic_primary;
50
static DEFINE_RAW_SPINLOCK(mpic_lock);
51

52
#ifdef CONFIG_PPC32	/* XXX for now */
53 54 55 56 57
#ifdef CONFIG_IRQ_ALL_CPUS
#define distribute_irqs	(1)
#else
#define distribute_irqs	(0)
#endif
58
#endif
59

60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
#ifdef CONFIG_MPIC_WEIRD
static u32 mpic_infos[][MPIC_IDX_END] = {
	[0] = {	/* Original OpenPIC compatible MPIC */
		MPIC_GREG_BASE,
		MPIC_GREG_FEATURE_0,
		MPIC_GREG_GLOBAL_CONF_0,
		MPIC_GREG_VENDOR_ID,
		MPIC_GREG_IPI_VECTOR_PRI_0,
		MPIC_GREG_IPI_STRIDE,
		MPIC_GREG_SPURIOUS,
		MPIC_GREG_TIMER_FREQ,

		MPIC_TIMER_BASE,
		MPIC_TIMER_STRIDE,
		MPIC_TIMER_CURRENT_CNT,
		MPIC_TIMER_BASE_CNT,
		MPIC_TIMER_VECTOR_PRI,
		MPIC_TIMER_DESTINATION,

		MPIC_CPU_BASE,
		MPIC_CPU_STRIDE,
		MPIC_CPU_IPI_DISPATCH_0,
		MPIC_CPU_IPI_DISPATCH_STRIDE,
		MPIC_CPU_CURRENT_TASK_PRI,
		MPIC_CPU_WHOAMI,
		MPIC_CPU_INTACK,
		MPIC_CPU_EOI,
87
		MPIC_CPU_MCACK,
88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125

		MPIC_IRQ_BASE,
		MPIC_IRQ_STRIDE,
		MPIC_IRQ_VECTOR_PRI,
		MPIC_VECPRI_VECTOR_MASK,
		MPIC_VECPRI_POLARITY_POSITIVE,
		MPIC_VECPRI_POLARITY_NEGATIVE,
		MPIC_VECPRI_SENSE_LEVEL,
		MPIC_VECPRI_SENSE_EDGE,
		MPIC_VECPRI_POLARITY_MASK,
		MPIC_VECPRI_SENSE_MASK,
		MPIC_IRQ_DESTINATION
	},
	[1] = {	/* Tsi108/109 PIC */
		TSI108_GREG_BASE,
		TSI108_GREG_FEATURE_0,
		TSI108_GREG_GLOBAL_CONF_0,
		TSI108_GREG_VENDOR_ID,
		TSI108_GREG_IPI_VECTOR_PRI_0,
		TSI108_GREG_IPI_STRIDE,
		TSI108_GREG_SPURIOUS,
		TSI108_GREG_TIMER_FREQ,

		TSI108_TIMER_BASE,
		TSI108_TIMER_STRIDE,
		TSI108_TIMER_CURRENT_CNT,
		TSI108_TIMER_BASE_CNT,
		TSI108_TIMER_VECTOR_PRI,
		TSI108_TIMER_DESTINATION,

		TSI108_CPU_BASE,
		TSI108_CPU_STRIDE,
		TSI108_CPU_IPI_DISPATCH_0,
		TSI108_CPU_IPI_DISPATCH_STRIDE,
		TSI108_CPU_CURRENT_TASK_PRI,
		TSI108_CPU_WHOAMI,
		TSI108_CPU_INTACK,
		TSI108_CPU_EOI,
126
		TSI108_CPU_MCACK,
127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149

		TSI108_IRQ_BASE,
		TSI108_IRQ_STRIDE,
		TSI108_IRQ_VECTOR_PRI,
		TSI108_VECPRI_VECTOR_MASK,
		TSI108_VECPRI_POLARITY_POSITIVE,
		TSI108_VECPRI_POLARITY_NEGATIVE,
		TSI108_VECPRI_SENSE_LEVEL,
		TSI108_VECPRI_SENSE_EDGE,
		TSI108_VECPRI_POLARITY_MASK,
		TSI108_VECPRI_SENSE_MASK,
		TSI108_IRQ_DESTINATION
	},
};

#define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]

#else /* CONFIG_MPIC_WEIRD */

#define MPIC_INFO(name) MPIC_##name

#endif /* CONFIG_MPIC_WEIRD */

150 151 152 153 154 155 156 157 158 159
static inline unsigned int mpic_processor_id(struct mpic *mpic)
{
	unsigned int cpu = 0;

	if (mpic->flags & MPIC_PRIMARY)
		cpu = hard_smp_processor_id();

	return cpu;
}

160 161 162 163 164
/*
 * Register accessor functions
 */


165 166 167
static inline u32 _mpic_read(enum mpic_reg_type type,
			     struct mpic_reg_bank *rb,
			     unsigned int reg)
168
{
169 170 171
	switch(type) {
#ifdef CONFIG_PPC_DCR
	case mpic_access_dcr:
172
		return dcr_read(rb->dhost, reg);
173 174 175 176 177 178 179
#endif
	case mpic_access_mmio_be:
		return in_be32(rb->base + (reg >> 2));
	case mpic_access_mmio_le:
	default:
		return in_le32(rb->base + (reg >> 2));
	}
180 181
}

182 183 184
static inline void _mpic_write(enum mpic_reg_type type,
			       struct mpic_reg_bank *rb,
 			       unsigned int reg, u32 value)
185
{
186 187 188
	switch(type) {
#ifdef CONFIG_PPC_DCR
	case mpic_access_dcr:
189 190
		dcr_write(rb->dhost, reg, value);
		break;
191 192
#endif
	case mpic_access_mmio_be:
193 194
		out_be32(rb->base + (reg >> 2), value);
		break;
195 196
	case mpic_access_mmio_le:
	default:
197 198
		out_le32(rb->base + (reg >> 2), value);
		break;
199
	}
200 201 202 203
}

static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
{
204
	enum mpic_reg_type type = mpic->reg_type;
205 206
	unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
			      (ipi * MPIC_INFO(GREG_IPI_STRIDE));
207

208 209 210
	if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
		type = mpic_access_mmio_be;
	return _mpic_read(type, &mpic->gregs, offset);
211 212 213 214
}

static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
{
215 216
	unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
			      (ipi * MPIC_INFO(GREG_IPI_STRIDE));
217

218
	_mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
219 220 221 222
}

static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
{
223
	unsigned int cpu = mpic_processor_id(mpic);
224

225
	return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
226 227 228 229
}

static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
{
230
	unsigned int cpu = mpic_processor_id(mpic);
231

232
	_mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
233 234 235 236 237 238
}

static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
{
	unsigned int	isu = src_no >> mpic->isu_shift;
	unsigned int	idx = src_no & mpic->isu_mask;
239
	unsigned int	val;
240

241 242
	val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
			 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
243 244
#ifdef CONFIG_MPIC_BROKEN_REGREAD
	if (reg == 0)
245 246
		val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
			mpic->isu_reg0_shadow[src_no];
247
#endif
248
	return val;
249 250 251 252 253 254 255 256
}

static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
				   unsigned int reg, u32 value)
{
	unsigned int	isu = src_no >> mpic->isu_shift;
	unsigned int	idx = src_no & mpic->isu_mask;

257
	_mpic_write(mpic->reg_type, &mpic->isus[isu],
258
		    reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
259 260 261

#ifdef CONFIG_MPIC_BROKEN_REGREAD
	if (reg == 0)
262 263
		mpic->isu_reg0_shadow[src_no] =
			value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
264
#endif
265 266
}

267 268
#define mpic_read(b,r)		_mpic_read(mpic->reg_type,&(b),(r))
#define mpic_write(b,r,v)	_mpic_write(mpic->reg_type,&(b),(r),(v))
269 270 271 272 273 274 275 276 277 278 279 280 281
#define mpic_ipi_read(i)	_mpic_ipi_read(mpic,(i))
#define mpic_ipi_write(i,v)	_mpic_ipi_write(mpic,(i),(v))
#define mpic_cpu_read(i)	_mpic_cpu_read(mpic,(i))
#define mpic_cpu_write(i,v)	_mpic_cpu_write(mpic,(i),(v))
#define mpic_irq_read(s,r)	_mpic_irq_read(mpic,(s),(r))
#define mpic_irq_write(s,r,v)	_mpic_irq_write(mpic,(s),(r),(v))


/*
 * Low level utility functions
 */


282
static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
283 284 285 286 287 288 289 290
			   struct mpic_reg_bank *rb, unsigned int offset,
			   unsigned int size)
{
	rb->base = ioremap(phys_addr + offset, size);
	BUG_ON(rb->base == NULL);
}

#ifdef CONFIG_PPC_DCR
291 292
static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node,
			  struct mpic_reg_bank *rb,
293 294
			  unsigned int offset, unsigned int size)
{
295 296
	const u32 *dbasep;

297
	dbasep = of_get_property(node, "dcr-reg", NULL);
298

299
	rb->dhost = dcr_map(node, *dbasep + offset, size);
300 301 302
	BUG_ON(!DCR_MAP_OK(rb->dhost));
}

303 304 305
static inline void mpic_map(struct mpic *mpic, struct device_node *node,
			    phys_addr_t phys_addr, struct mpic_reg_bank *rb,
			    unsigned int offset, unsigned int size)
306 307
{
	if (mpic->flags & MPIC_USES_DCR)
308
		_mpic_map_dcr(mpic, node, rb, offset, size);
309 310 311 312
	else
		_mpic_map_mmio(mpic, phys_addr, rb, offset, size);
}
#else /* CONFIG_PPC_DCR */
313
#define mpic_map(m,n,p,b,o,s)	_mpic_map_mmio(m,p,b,o,s)
314 315 316
#endif /* !CONFIG_PPC_DCR */


317 318 319 320 321 322 323 324

/* Check if we have one of those nice broken MPICs with a flipped endian on
 * reads from IPI registers
 */
static void __init mpic_test_broken_ipi(struct mpic *mpic)
{
	u32 r;

325 326
	mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
	r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
327 328 329 330 331 332 333

	if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
		printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
		mpic->flags |= MPIC_BROKEN_IPI;
	}
}

334
#ifdef CONFIG_MPIC_U3_HT_IRQS
335 336 337 338

/* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
 * to force the edge setting on the MPIC and do the ack workaround.
 */
339
static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
340
{
341
	if (source >= 128 || !mpic->fixups)
342
		return 0;
343
	return mpic->fixups[source].base != NULL;
344 345
}

346

347
static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
348
{
349
	struct mpic_irq_fixup *fixup = &mpic->fixups[source];
350

351 352 353 354 355
	if (fixup->applebase) {
		unsigned int soff = (fixup->index >> 3) & ~3;
		unsigned int mask = 1U << (fixup->index & 0x1f);
		writel(mask, fixup->applebase + soff);
	} else {
356
		raw_spin_lock(&mpic->fixup_lock);
357 358
		writeb(0x11 + 2 * fixup->index, fixup->base + 2);
		writel(fixup->data, fixup->base + 4);
359
		raw_spin_unlock(&mpic->fixup_lock);
360
	}
361 362
}

363
static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
364
				      bool level)
365 366 367 368 369 370 371 372
{
	struct mpic_irq_fixup *fixup = &mpic->fixups[source];
	unsigned long flags;
	u32 tmp;

	if (fixup->base == NULL)
		return;

373 374
	DBG("startup_ht_interrupt(0x%x) index: %d\n",
	    source, fixup->index);
375
	raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
376 377 378 379
	/* Enable and configure */
	writeb(0x10 + 2 * fixup->index, fixup->base + 2);
	tmp = readl(fixup->base + 4);
	tmp &= ~(0x23U);
380
	if (level)
381 382
		tmp |= 0x22;
	writel(tmp, fixup->base + 4);
383
	raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
384 385 386 387 388 389

#ifdef CONFIG_PM
	/* use the lowest bit inverted to the actual HW,
	 * set if this fixup was enabled, clear otherwise */
	mpic->save_data[source].fixup_data = tmp | 1;
#endif
390 391
}

392
static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
393 394 395 396 397 398 399 400
{
	struct mpic_irq_fixup *fixup = &mpic->fixups[source];
	unsigned long flags;
	u32 tmp;

	if (fixup->base == NULL)
		return;

401
	DBG("shutdown_ht_interrupt(0x%x)\n", source);
402 403

	/* Disable */
404
	raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
405 406
	writeb(0x10 + 2 * fixup->index, fixup->base + 2);
	tmp = readl(fixup->base + 4);
407
	tmp |= 1;
408
	writel(tmp, fixup->base + 4);
409
	raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
410 411 412 413 414 415

#ifdef CONFIG_PM
	/* use the lowest bit inverted to the actual HW,
	 * set if this fixup was enabled, clear otherwise */
	mpic->save_data[source].fixup_data = tmp & ~1;
#endif
416
}
417

418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446
#ifdef CONFIG_PCI_MSI
static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
				    unsigned int devfn)
{
	u8 __iomem *base;
	u8 pos, flags;
	u64 addr = 0;

	for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
	     pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
		u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
		if (id == PCI_CAP_ID_HT) {
			id = readb(devbase + pos + 3);
			if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
				break;
		}
	}

	if (pos == 0)
		return;

	base = devbase + pos;

	flags = readb(base + HT_MSI_FLAGS);
	if (!(flags & HT_MSI_FLAGS_FIXED)) {
		addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
		addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
	}

447
	printk(KERN_DEBUG "mpic:   - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
448 449 450 451 452 453 454 455 456 457 458 459 460 461
		PCI_SLOT(devfn), PCI_FUNC(devfn),
		flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);

	if (!(flags & HT_MSI_FLAGS_ENABLE))
		writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
}
#else
static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
				    unsigned int devfn)
{
	return;
}
#endif

462 463
static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
				    unsigned int devfn, u32 vdid)
464
{
465
	int i, irq, n;
466
	u8 __iomem *base;
467
	u32 tmp;
468
	u8 pos;
469

470 471 472
	for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
	     pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
		u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
473
		if (id == PCI_CAP_ID_HT) {
474
			id = readb(devbase + pos + 3);
475
			if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
476 477
				break;
		}
478
	}
479 480 481
	if (pos == 0)
		return;

482 483 484
	base = devbase + pos;
	writeb(0x01, base + 2);
	n = (readl(base + 4) >> 16) & 0xff;
485

486 487 488
	printk(KERN_INFO "mpic:   - HT:%02x.%x [0x%02x] vendor %04x device %04x"
	       " has %d irqs\n",
	       devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
489 490

	for (i = 0; i <= n; i++) {
491 492
		writeb(0x10 + 2 * i, base + 2);
		tmp = readl(base + 4);
493
		irq = (tmp >> 16) & 0xff;
494 495 496 497 498 499 500 501 502 503 504 505 506
		DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
		/* mask it , will be unmasked later */
		tmp |= 0x1;
		writel(tmp, base + 4);
		mpic->fixups[irq].index = i;
		mpic->fixups[irq].base = base;
		/* Apple HT PIC has a non-standard way of doing EOIs */
		if ((vdid & 0xffff) == 0x106b)
			mpic->fixups[irq].applebase = devbase + 0x60;
		else
			mpic->fixups[irq].applebase = NULL;
		writeb(0x11 + 2 * i, base + 2);
		mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
507 508 509
	}
}
 
510

511
static void __init mpic_scan_ht_pics(struct mpic *mpic)
512 513 514 515
{
	unsigned int devfn;
	u8 __iomem *cfgspace;

516
	printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
517 518

	/* Allocate fixups array */
519
	mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL);
520 521 522
	BUG_ON(mpic->fixups == NULL);

	/* Init spinlock */
523
	raw_spin_lock_init(&mpic->fixup_lock);
524

525 526
	/* Map U3 config space. We assume all IO-APICs are on the primary bus
	 * so we only need to map 64kB.
527
	 */
528
	cfgspace = ioremap(0xf2000000, 0x10000);
529 530
	BUG_ON(cfgspace == NULL);

531 532
	/* Now we scan all slots. We do a very quick scan, we read the header
	 * type, vendor ID and device ID only, that's plenty enough
533
	 */
534
	for (devfn = 0; devfn < 0x100; devfn++) {
535 536 537
		u8 __iomem *devbase = cfgspace + (devfn << 8);
		u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
		u32 l = readl(devbase + PCI_VENDOR_ID);
538
		u16 s;
539 540 541 542 543 544 545

		DBG("devfn %x, l: %x\n", devfn, l);

		/* If no device, skip */
		if (l == 0xffffffff || l == 0x00000000 ||
		    l == 0x0000ffff || l == 0xffff0000)
			goto next;
546 547 548 549
		/* Check if is supports capability lists */
		s = readw(devbase + PCI_STATUS);
		if (!(s & PCI_STATUS_CAP_LIST))
			goto next;
550

551
		mpic_scan_ht_pic(mpic, devbase, devfn, l);
552
		mpic_scan_ht_msi(mpic, devbase, devfn);
553

554 555
	next:
		/* next device, if function 0 */
556
		if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
557 558 559 560
			devfn += 7;
	}
}

561
#else /* CONFIG_MPIC_U3_HT_IRQS */
562 563 564 565 566 567 568 569 570 571

static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
{
	return 0;
}

static void __init mpic_scan_ht_pics(struct mpic *mpic)
{
}

572
#endif /* CONFIG_MPIC_U3_HT_IRQS */
573

574
#ifdef CONFIG_SMP
575
static int irq_choose_cpu(const struct cpumask *mask)
576 577 578
{
	int cpuid;

579
	if (cpumask_equal(mask, cpu_all_mask)) {
580
		static int irq_rover = 0;
581
		static DEFINE_RAW_SPINLOCK(irq_rover_lock);
582 583 584 585
		unsigned long flags;

		/* Round-robin distribution... */
	do_round_robin:
586
		raw_spin_lock_irqsave(&irq_rover_lock, flags);
587

588 589 590 591
		irq_rover = cpumask_next(irq_rover, cpu_online_mask);
		if (irq_rover >= nr_cpu_ids)
			irq_rover = cpumask_first(cpu_online_mask);

592 593
		cpuid = irq_rover;

594
		raw_spin_unlock_irqrestore(&irq_rover_lock, flags);
595
	} else {
596 597
		cpuid = cpumask_first_and(mask, cpu_online_mask);
		if (cpuid >= nr_cpu_ids)
598 599 600
			goto do_round_robin;
	}

601
	return get_hard_smp_processor_id(cpuid);
602 603
}
#else
604
static int irq_choose_cpu(const struct cpumask *mask)
605 606 607 608
{
	return hard_smp_processor_id();
}
#endif
609

610 611
#define mpic_irq_to_hw(virq)	((unsigned int)irq_map[virq].hwirq)

612
/* Find an mpic associated with a given linux interrupt */
613
static struct mpic *mpic_find(unsigned int irq)
614
{
615 616
	if (irq < NUM_ISA_INTERRUPTS)
		return NULL;
617

618
	return get_irq_chip_data(irq);
619
}
620

621 622 623 624
/* Determine if the linux irq is an IPI */
static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
{
	unsigned int src = mpic_irq_to_hw(irq);
625

626
	return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
627 628
}

629

630 631 632 633 634 635 636 637 638 639 640 641 642
/* Convert a cpu mask from logical to physical cpu numbers. */
static inline u32 mpic_physmask(u32 cpumask)
{
	int i;
	u32 mask = 0;

	for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
		mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
	return mask;
}

#ifdef CONFIG_SMP
/* Get the mpic structure from the IPI number */
643
static inline struct mpic * mpic_from_ipi(struct irq_data *d)
644
{
645
	return irq_data_get_irq_chip_data(d);
646 647 648 649 650 651
}
#endif

/* Get the mpic structure from the irq number */
static inline struct mpic * mpic_from_irq(unsigned int irq)
{
652 653 654 655 656 657 658
	return get_irq_chip_data(irq);
}

/* Get the mpic structure from the irq data */
static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
{
	return irq_data_get_irq_chip_data(d);
659 660 661 662 663
}

/* Send an EOI */
static inline void mpic_eoi(struct mpic *mpic)
{
664 665
	mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
	(void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
666 667 668 669 670 671 672
}

/*
 * Linux descriptor level callbacks
 */


673
void mpic_unmask_irq(struct irq_data *d)
674 675
{
	unsigned int loops = 100000;
676 677
	struct mpic *mpic = mpic_from_irq_data(d);
	unsigned int src = mpic_irq_to_hw(d->irq);
678

679
	DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
680

681 682
	mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
		       mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
683
		       ~MPIC_VECPRI_MASK);
684 685 686
	/* make sure mask gets to controller before we return to user */
	do {
		if (!loops--) {
687 688
			printk(KERN_ERR "%s: timeout on hwirq %u\n",
			       __func__, src);
689 690
			break;
		}
691
	} while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
692 693
}

694
void mpic_mask_irq(struct irq_data *d)
695 696
{
	unsigned int loops = 100000;
697 698
	struct mpic *mpic = mpic_from_irq_data(d);
	unsigned int src = mpic_irq_to_hw(d->irq);
699

700
	DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
701

702 703
	mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
		       mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
704
		       MPIC_VECPRI_MASK);
705 706 707 708

	/* make sure mask gets to controller before we return to user */
	do {
		if (!loops--) {
709 710
			printk(KERN_ERR "%s: timeout on hwirq %u\n",
			       __func__, src);
711 712
			break;
		}
713
	} while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
714 715
}

716
void mpic_end_irq(struct irq_data *d)
717
{
718
	struct mpic *mpic = mpic_from_irq_data(d);
719 720

#ifdef DEBUG_IRQ
721
	DBG("%s: end_irq: %d\n", mpic->name, d->irq);
722 723 724 725 726 727 728 729 730
#endif
	/* We always EOI on end_irq() even for edge interrupts since that
	 * should only lower the priority, the MPIC should have properly
	 * latched another edge interrupt coming in anyway
	 */

	mpic_eoi(mpic);
}

731
#ifdef CONFIG_MPIC_U3_HT_IRQS
732

733
static void mpic_unmask_ht_irq(struct irq_data *d)
734
{
735 736
	struct mpic *mpic = mpic_from_irq_data(d);
	unsigned int src = mpic_irq_to_hw(d->irq);
737

738
	mpic_unmask_irq(d);
739

740
	if (irqd_is_level_type(d))
741 742 743
		mpic_ht_end_irq(mpic, src);
}

744
static unsigned int mpic_startup_ht_irq(struct irq_data *d)
745
{
746 747
	struct mpic *mpic = mpic_from_irq_data(d);
	unsigned int src = mpic_irq_to_hw(d->irq);
748

749
	mpic_unmask_irq(d);
750
	mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
751 752

	return 0;
753 754
}

755
static void mpic_shutdown_ht_irq(struct irq_data *d)
756
{
757 758
	struct mpic *mpic = mpic_from_irq_data(d);
	unsigned int src = mpic_irq_to_hw(d->irq);
759

760
	mpic_shutdown_ht_interrupt(mpic, src);
761
	mpic_mask_irq(d);
762 763
}

764
static void mpic_end_ht_irq(struct irq_data *d)
765
{
766 767
	struct mpic *mpic = mpic_from_irq_data(d);
	unsigned int src = mpic_irq_to_hw(d->irq);
768

769
#ifdef DEBUG_IRQ
770
	DBG("%s: end_irq: %d\n", mpic->name, d->irq);
771
#endif
772 773 774 775 776
	/* We always EOI on end_irq() even for edge interrupts since that
	 * should only lower the priority, the MPIC should have properly
	 * latched another edge interrupt coming in anyway
	 */

777
	if (irqd_is_level_type(d))
778
		mpic_ht_end_irq(mpic, src);
779 780
	mpic_eoi(mpic);
}
781
#endif /* !CONFIG_MPIC_U3_HT_IRQS */
782

783 784
#ifdef CONFIG_SMP

785
static void mpic_unmask_ipi(struct irq_data *d)
786
{
787 788
	struct mpic *mpic = mpic_from_ipi(d);
	unsigned int src = mpic_irq_to_hw(d->irq) - mpic->ipi_vecs[0];
789

790
	DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
791 792 793
	mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
}

794
static void mpic_mask_ipi(struct irq_data *d)
795 796 797 798
{
	/* NEVER disable an IPI... that's just plain wrong! */
}

799
static void mpic_end_ipi(struct irq_data *d)
800
{
801
	struct mpic *mpic = mpic_from_ipi(d);
802 803 804 805 806

	/*
	 * IPIs are marked IRQ_PER_CPU. This has the side effect of
	 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
	 * applying to them. We EOI them late to avoid re-entering.
807
	 * We mark IPI's with IRQF_DISABLED as they must run with
808 809 810 811 812 813 814
	 * irqs disabled.
	 */
	mpic_eoi(mpic);
}

#endif /* CONFIG_SMP */

815 816
int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
		      bool force)
817
{
818 819
	struct mpic *mpic = mpic_from_irq_data(d);
	unsigned int src = mpic_irq_to_hw(d->irq);
820

821
	if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
822
		int cpuid = irq_choose_cpu(cpumask);
823

824 825
		mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
	} else {
826
		cpumask_var_t tmp;
827

828 829 830
		alloc_cpumask_var(&tmp, GFP_KERNEL);

		cpumask_and(tmp, cpumask, cpu_online_mask);
831 832

		mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
833 834 835
			       mpic_physmask(cpumask_bits(tmp)[0]));

		free_cpumask_var(tmp);
836
	}
837 838

	return 0;
839 840
}

841
static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
842 843
{
	/* Now convert sense value */
844
	switch(type & IRQ_TYPE_SENSE_MASK) {
845
	case IRQ_TYPE_EDGE_RISING:
846 847
		return MPIC_INFO(VECPRI_SENSE_EDGE) |
		       MPIC_INFO(VECPRI_POLARITY_POSITIVE);
848
	case IRQ_TYPE_EDGE_FALLING:
849
	case IRQ_TYPE_EDGE_BOTH:
850 851
		return MPIC_INFO(VECPRI_SENSE_EDGE) |
		       MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
852
	case IRQ_TYPE_LEVEL_HIGH:
853 854
		return MPIC_INFO(VECPRI_SENSE_LEVEL) |
		       MPIC_INFO(VECPRI_POLARITY_POSITIVE);
855 856
	case IRQ_TYPE_LEVEL_LOW:
	default:
857 858
		return MPIC_INFO(VECPRI_SENSE_LEVEL) |
		       MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
859
	}
860 861
}

862
int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
863
{
864 865
	struct mpic *mpic = mpic_from_irq_data(d);
	unsigned int src = mpic_irq_to_hw(d->irq);
866 867
	unsigned int vecpri, vold, vnew;

868
	DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
869
	    mpic, d->irq, src, flow_type);
870 871 872 873 874 875 876 877 878 879

	if (src >= mpic->irq_count)
		return -EINVAL;

	if (flow_type == IRQ_TYPE_NONE)
		if (mpic->senses && src < mpic->senses_count)
			flow_type = mpic->senses[src];
	if (flow_type == IRQ_TYPE_NONE)
		flow_type = IRQ_TYPE_LEVEL_LOW;

880
	irqd_set_trigger_type(d, flow_type);
881 882 883 884 885

	if (mpic_is_ht_interrupt(mpic, src))
		vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
			MPIC_VECPRI_SENSE_EDGE;
	else
886
		vecpri = mpic_type_to_vecpri(mpic, flow_type);
887

888 889 890
	vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
	vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
			MPIC_INFO(VECPRI_SENSE_MASK));
891 892
	vnew |= vecpri;
	if (vold != vnew)
893
		mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
894

895
	return IRQ_SET_MASK_OK_NOCOPY;;
896 897
}

898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915
void mpic_set_vector(unsigned int virq, unsigned int vector)
{
	struct mpic *mpic = mpic_from_irq(virq);
	unsigned int src = mpic_irq_to_hw(virq);
	unsigned int vecpri;

	DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
	    mpic, virq, src, vector);

	if (src >= mpic->irq_count)
		return;

	vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
	vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
	vecpri |= vector;
	mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
}

916 917 918 919 920 921 922 923 924 925 926 927 928 929
void mpic_set_destination(unsigned int virq, unsigned int cpuid)
{
	struct mpic *mpic = mpic_from_irq(virq);
	unsigned int src = mpic_irq_to_hw(virq);

	DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
	    mpic, virq, src, cpuid);

	if (src >= mpic->irq_count)
		return;

	mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
}

930
static struct irq_chip mpic_irq_chip = {
931 932 933 934
	.irq_mask	= mpic_mask_irq,
	.irq_unmask	= mpic_unmask_irq,
	.irq_eoi	= mpic_end_irq,
	.irq_set_type	= mpic_set_irq_type,
935 936 937 938
};

#ifdef CONFIG_SMP
static struct irq_chip mpic_ipi_chip = {
939 940 941
	.irq_mask	= mpic_mask_ipi,
	.irq_unmask	= mpic_unmask_ipi,
	.irq_eoi	= mpic_end_ipi,
942 943 944
};
#endif /* CONFIG_SMP */

945
#ifdef CONFIG_MPIC_U3_HT_IRQS
946
static struct irq_chip mpic_irq_ht_chip = {
947 948 949 950 951 952
	.irq_startup	= mpic_startup_ht_irq,
	.irq_shutdown	= mpic_shutdown_ht_irq,
	.irq_mask	= mpic_mask_irq,
	.irq_unmask	= mpic_unmask_ht_irq,
	.irq_eoi	= mpic_end_ht_irq,
	.irq_set_type	= mpic_set_irq_type,
953
};
954
#endif /* CONFIG_MPIC_U3_HT_IRQS */
955

956

957 958 959
static int mpic_host_match(struct irq_host *h, struct device_node *node)
{
	/* Exact match, unless mpic node is NULL */
960
	return h->of_node == NULL || h->of_node == node;
961 962 963
}

static int mpic_host_map(struct irq_host *h, unsigned int virq,
964
			 irq_hw_number_t hw)
965 966
{
	struct mpic *mpic = h->host_data;
967
	struct irq_chip *chip;
968

969
	DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
970

971
	if (hw == mpic->spurious_vec)
972
		return -EINVAL;
973 974
	if (mpic->protected && test_bit(hw, mpic->protected))
		return -EINVAL;
975

976
#ifdef CONFIG_SMP
977
	else if (hw >= mpic->ipi_vecs[0]) {
978 979
		WARN_ON(!(mpic->flags & MPIC_PRIMARY));

980
		DBG("mpic: mapping as IPI\n");
981 982 983 984 985 986 987 988 989 990
		set_irq_chip_data(virq, mpic);
		set_irq_chip_and_handler(virq, &mpic->hc_ipi,
					 handle_percpu_irq);
		return 0;
	}
#endif /* CONFIG_SMP */

	if (hw >= mpic->irq_count)
		return -EINVAL;

M
Michael Ellerman 已提交
991 992
	mpic_msi_reserve_hwirq(mpic, hw);

993
	/* Default chip */
994 995
	chip = &mpic->hc_irq;

996
#ifdef CONFIG_MPIC_U3_HT_IRQS
997
	/* Check for HT interrupts, override vecpri */
998
	if (mpic_is_ht_interrupt(mpic, hw))
999
		chip = &mpic->hc_ht_irq;
1000
#endif /* CONFIG_MPIC_U3_HT_IRQS */
1001

1002
	DBG("mpic: mapping to irq chip @%p\n", chip);
1003 1004 1005

	set_irq_chip_data(virq, mpic);
	set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq);
1006 1007 1008 1009

	/* Set default irq type */
	set_irq_type(virq, IRQ_TYPE_NONE);

1010 1011 1012 1013 1014 1015
	/* If the MPIC was reset, then all vectors have already been
	 * initialized.  Otherwise, a per source lazy initialization
	 * is done here.
	 */
	if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
		mpic_set_vector(virq, hw);
1016
		mpic_set_destination(virq, mpic_processor_id(mpic));
1017 1018 1019
		mpic_irq_set_priority(virq, 8);
	}

1020 1021 1022 1023
	return 0;
}

static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
1024
			   const u32 *intspec, unsigned int intsize,
1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035
			   irq_hw_number_t *out_hwirq, unsigned int *out_flags)

{
	static unsigned char map_mpic_senses[4] = {
		IRQ_TYPE_EDGE_RISING,
		IRQ_TYPE_LEVEL_LOW,
		IRQ_TYPE_LEVEL_HIGH,
		IRQ_TYPE_EDGE_FALLING,
	};

	*out_hwirq = intspec[0];
1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052
	if (intsize > 1) {
		u32 mask = 0x3;

		/* Apple invented a new race of encoding on machines with
		 * an HT APIC. They encode, among others, the index within
		 * the HT APIC. We don't care about it here since thankfully,
		 * it appears that they have the APIC already properly
		 * configured, and thus our current fixup code that reads the
		 * APIC config works fine. However, we still need to mask out
		 * bits in the specifier to make sure we only get bit 0 which
		 * is the level/edge bit (the only sense bit exposed by Apple),
		 * as their bit 1 means something else.
		 */
		if (machine_is(powermac))
			mask = 0x1;
		*out_flags = map_mpic_senses[intspec[1] & mask];
	} else
1053 1054
		*out_flags = IRQ_TYPE_NONE;

1055 1056 1057
	DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
	    intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);

1058 1059 1060 1061 1062 1063 1064 1065 1066
	return 0;
}

static struct irq_host_ops mpic_host_ops = {
	.match = mpic_host_match,
	.map = mpic_host_map,
	.xlate = mpic_host_xlate,
};

1067 1068 1069 1070 1071
static int mpic_reset_prohibited(struct device_node *node)
{
	return node && of_get_property(node, "pic-no-reset", NULL);
}

1072 1073 1074 1075
/*
 * Exported functions
 */

1076
struct mpic * __init mpic_alloc(struct device_node *node,
1077
				phys_addr_t phys_addr,
1078 1079 1080 1081 1082 1083
				unsigned int flags,
				unsigned int isu_size,
				unsigned int irq_count,
				const char *name)
{
	struct mpic	*mpic;
1084
	u32		greg_feature;
1085 1086
	const char	*vers;
	int		i;
1087
	int		intvec_top;
1088
	u64		paddr = phys_addr;
1089

K
Kumar Gala 已提交
1090
	mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1091 1092
	if (mpic == NULL)
		return NULL;
K
Kumar Gala 已提交
1093

1094 1095
	mpic->name = name;

1096
	mpic->hc_irq = mpic_irq_chip;
1097
	mpic->hc_irq.name = name;
1098
	if (flags & MPIC_PRIMARY)
1099
		mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1100
#ifdef CONFIG_MPIC_U3_HT_IRQS
1101
	mpic->hc_ht_irq = mpic_irq_ht_chip;
1102
	mpic->hc_ht_irq.name = name;
1103
	if (flags & MPIC_PRIMARY)
1104
		mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1105
#endif /* CONFIG_MPIC_U3_HT_IRQS */
1106

1107
#ifdef CONFIG_SMP
1108
	mpic->hc_ipi = mpic_ipi_chip;
1109
	mpic->hc_ipi.name = name;
1110 1111 1112 1113 1114 1115 1116
#endif /* CONFIG_SMP */

	mpic->flags = flags;
	mpic->isu_size = isu_size;
	mpic->irq_count = irq_count;
	mpic->num_sources = 0; /* so far */

1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131
	if (flags & MPIC_LARGE_VECTORS)
		intvec_top = 2047;
	else
		intvec_top = 255;

	mpic->timer_vecs[0] = intvec_top - 8;
	mpic->timer_vecs[1] = intvec_top - 7;
	mpic->timer_vecs[2] = intvec_top - 6;
	mpic->timer_vecs[3] = intvec_top - 5;
	mpic->ipi_vecs[0]   = intvec_top - 4;
	mpic->ipi_vecs[1]   = intvec_top - 3;
	mpic->ipi_vecs[2]   = intvec_top - 2;
	mpic->ipi_vecs[3]   = intvec_top - 1;
	mpic->spurious_vec  = intvec_top;

1132
	/* Check for "big-endian" in device-tree */
1133
	if (node && of_get_property(node, "big-endian", NULL) != NULL)
1134 1135
		mpic->flags |= MPIC_BIG_ENDIAN;

1136 1137
	/* Look for protected sources */
	if (node) {
1138 1139
		int psize;
		unsigned int bits, mapsize;
1140 1141 1142 1143 1144 1145
		const u32 *psrc =
			of_get_property(node, "protected-sources", &psize);
		if (psrc) {
			psize /= 4;
			bits = intvec_top + 1;
			mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long);
1146
			mpic->protected = kzalloc(mapsize, GFP_KERNEL);
1147 1148 1149 1150 1151 1152 1153 1154
			BUG_ON(mpic->protected == NULL);
			for (i = 0; i < psize; i++) {
				if (psrc[i] > intvec_top)
					continue;
				__set_bit(psrc[i], mpic->protected);
			}
		}
	}
1155

1156 1157 1158 1159
#ifdef CONFIG_MPIC_WEIRD
	mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
#endif

1160 1161 1162 1163
	/* default register type */
	mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?
		mpic_access_mmio_be : mpic_access_mmio_le;

1164 1165 1166 1167
	/* If no physical address is passed in, a device-node is mandatory */
	BUG_ON(paddr == 0 && node == NULL);

	/* If no physical address passed in, check if it's dcr based */
1168
	if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) {
1169
#ifdef CONFIG_PPC_DCR
1170
		mpic->flags |= MPIC_USES_DCR;
1171 1172
		mpic->reg_type = mpic_access_dcr;
#else
1173
		BUG();
1174
#endif /* CONFIG_PPC_DCR */
1175
	}
1176

1177 1178 1179 1180
	/* If the MPIC is not DCR based, and no physical address was passed
	 * in, try to obtain one
	 */
	if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
1181
		const u32 *reg = of_get_property(node, "reg", NULL);
1182 1183 1184 1185 1186
		BUG_ON(reg == NULL);
		paddr = of_translate_address(node, reg);
		BUG_ON(paddr == OF_BAD_ADDR);
	}

1187
	/* Map the global registers */
1188 1189
	mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
	mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1190 1191

	/* Reset */
1192 1193 1194 1195 1196 1197 1198 1199 1200

	/* When using a device-node, reset requests are only honored if the MPIC
	 * is allowed to reset.
	 */
	if (mpic_reset_prohibited(node))
		mpic->flags |= MPIC_NO_RESET;

	if ((flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) {
		printk(KERN_DEBUG "mpic: Resetting\n");
1201 1202
		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1203
			   | MPIC_GREG_GCONF_RESET);
1204
		while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1205 1206 1207 1208
		       & MPIC_GREG_GCONF_RESET)
			mb();
	}

1209 1210 1211 1212 1213 1214
	/* CoreInt */
	if (flags & MPIC_ENABLE_COREINT)
		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
			   | MPIC_GREG_GCONF_COREINT);

1215 1216 1217 1218 1219
	if (flags & MPIC_ENABLE_MCK)
		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
			   | MPIC_GREG_GCONF_MCK);

1220 1221 1222 1223
	/* Read feature register, calculate num CPUs and, for non-ISU
	 * MPICs, num sources as well. On ISU MPICs, sources are counted
	 * as ISUs are added
	 */
1224 1225
	greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
	mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK)
1226
			  >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
1227
	if (isu_size == 0) {
1228 1229 1230 1231 1232 1233
		if (flags & MPIC_BROKEN_FRR_NIRQS)
			mpic->num_sources = mpic->irq_count;
		else
			mpic->num_sources =
				((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
				 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
1234
	}
1235 1236 1237

	/* Map the per-CPU registers */
	for (i = 0; i < mpic->num_cpus; i++) {
1238
		mpic_map(mpic, node, paddr, &mpic->cpuregs[i],
1239 1240
			 MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE),
			 0x1000);
1241 1242 1243 1244 1245
	}

	/* Initialize main ISU if none provided */
	if (mpic->isu_size == 0) {
		mpic->isu_size = mpic->num_sources;
1246
		mpic_map(mpic, node, paddr, &mpic->isus[0],
1247
			 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1248 1249 1250 1251
	}
	mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
	mpic->isu_mask = (1 << mpic->isu_shift) - 1;

1252 1253 1254 1255 1256 1257 1258 1259 1260
	mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
				       isu_size ? isu_size : mpic->num_sources,
				       &mpic_host_ops,
				       flags & MPIC_LARGE_VECTORS ? 2048 : 256);
	if (mpic->irqhost == NULL)
		return NULL;

	mpic->irqhost->host_data = mpic;

1261
	/* Display version */
1262
	switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275
	case 1:
		vers = "1.0";
		break;
	case 2:
		vers = "1.2";
		break;
	case 3:
		vers = "1.3";
		break;
	default:
		vers = "<unknown>";
		break;
	}
1276 1277 1278 1279 1280
	printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
	       " max %d CPUs\n",
	       name, vers, (unsigned long long)paddr, mpic->num_cpus);
	printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
	       mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1281 1282 1283 1284

	mpic->next = mpics;
	mpics = mpic;

1285
	if (flags & MPIC_PRIMARY) {
1286
		mpic_primary = mpic;
1287 1288
		irq_set_default_host(mpic->irqhost);
	}
1289 1290 1291 1292 1293

	return mpic;
}

void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1294
			    phys_addr_t paddr)
1295 1296 1297 1298 1299
{
	unsigned int isu_first = isu_num * mpic->isu_size;

	BUG_ON(isu_num >= MPIC_MAX_ISU);

1300 1301
	mpic_map(mpic, mpic->irqhost->of_node,
		 paddr, &mpic->isus[isu_num], 0,
1302
		 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1303

1304 1305 1306 1307
	if ((isu_first + mpic->isu_size) > mpic->num_sources)
		mpic->num_sources = isu_first + mpic->isu_size;
}

1308 1309 1310 1311 1312 1313
void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
{
	mpic->senses = senses;
	mpic->senses_count = count;
}

1314 1315 1316
void __init mpic_init(struct mpic *mpic)
{
	int i;
1317
	int cpu;
1318 1319 1320 1321 1322 1323

	BUG_ON(mpic->num_sources == 0);

	printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);

	/* Set current processor priority to max */
1324
	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1325 1326 1327 1328

	/* Initialize timers: just disable them all */
	for (i = 0; i < 4; i++) {
		mpic_write(mpic->tmregs,
1329 1330
			   i * MPIC_INFO(TIMER_STRIDE) +
			   MPIC_INFO(TIMER_DESTINATION), 0);
1331
		mpic_write(mpic->tmregs,
1332 1333
			   i * MPIC_INFO(TIMER_STRIDE) +
			   MPIC_INFO(TIMER_VECTOR_PRI),
1334
			   MPIC_VECPRI_MASK |
1335
			   (mpic->timer_vecs[0] + i));
1336 1337 1338 1339 1340 1341 1342 1343
	}

	/* Initialize IPIs to our reserved vectors and mark them disabled for now */
	mpic_test_broken_ipi(mpic);
	for (i = 0; i < 4; i++) {
		mpic_ipi_write(i,
			       MPIC_VECPRI_MASK |
			       (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1344
			       (mpic->ipi_vecs[0] + i));
1345 1346 1347 1348 1349 1350
	}

	/* Initialize interrupt sources */
	if (mpic->irq_count == 0)
		mpic->irq_count = mpic->num_sources;

1351
	/* Do the HT PIC fixups on U3 broken mpic */
1352
	DBG("MPIC flags: %x\n", mpic->flags);
1353
	if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) {
1354
		mpic_scan_ht_pics(mpic);
1355 1356
		mpic_u3msi_init(mpic);
	}
1357

1358 1359
	mpic_pasemi_msi_init(mpic);

1360
	cpu = mpic_processor_id(mpic);
1361

1362 1363 1364 1365 1366
	if (!(mpic->flags & MPIC_NO_RESET)) {
		for (i = 0; i < mpic->num_sources; i++) {
			/* start with vector = source number, and masked */
			u32 vecpri = MPIC_VECPRI_MASK | i |
				(8 << MPIC_VECPRI_PRIORITY_SHIFT);
1367
		
1368 1369 1370 1371 1372 1373 1374
			/* check if protected */
			if (mpic->protected && test_bit(i, mpic->protected))
				continue;
			/* init hw */
			mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
			mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
		}
1375 1376
	}
	
1377 1378
	/* Init spurious vector */
	mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1379

1380 1381 1382 1383 1384
	/* Disable 8259 passthrough, if supported */
	if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
			   | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1385

1386 1387 1388 1389 1390
	if (mpic->flags & MPIC_NO_BIAS)
		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
			mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
			| MPIC_GREG_GCONF_NO_BIAS);

1391
	/* Set current processor priority to 0 */
1392
	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1393 1394 1395

#ifdef CONFIG_PM
	/* allocate memory to save mpic state */
1396 1397
	mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data),
				  GFP_KERNEL);
1398 1399
	BUG_ON(mpic->save_data == NULL);
#endif
1400 1401
}

1402 1403 1404 1405 1406 1407 1408 1409 1410
void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
{
	u32 v;

	v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
	v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
	v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
	mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
}
1411

1412 1413
void __init mpic_set_serial_int(struct mpic *mpic, int enable)
{
1414
	unsigned long flags;
1415 1416
	u32 v;

1417
	raw_spin_lock_irqsave(&mpic_lock, flags);
1418 1419 1420 1421 1422 1423
	v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
	if (enable)
		v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
	else
		v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
	mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1424
	raw_spin_unlock_irqrestore(&mpic_lock, flags);
1425
}
1426 1427 1428

void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
{
1429
	struct mpic *mpic = mpic_find(irq);
1430
	unsigned int src = mpic_irq_to_hw(irq);
1431 1432 1433
	unsigned long flags;
	u32 reg;

1434 1435 1436
	if (!mpic)
		return;

1437
	raw_spin_lock_irqsave(&mpic_lock, flags);
1438
	if (mpic_is_ipi(mpic, irq)) {
1439
		reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1440
			~MPIC_VECPRI_PRIORITY_MASK;
1441
		mpic_ipi_write(src - mpic->ipi_vecs[0],
1442 1443
			       reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
	} else {
1444
		reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1445
			& ~MPIC_VECPRI_PRIORITY_MASK;
1446
		mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1447 1448
			       reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
	}
1449
	raw_spin_unlock_irqrestore(&mpic_lock, flags);
1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463
}

void mpic_setup_this_cpu(void)
{
#ifdef CONFIG_SMP
	struct mpic *mpic = mpic_primary;
	unsigned long flags;
	u32 msk = 1 << hard_smp_processor_id();
	unsigned int i;

	BUG_ON(mpic == NULL);

	DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());

1464
	raw_spin_lock_irqsave(&mpic_lock, flags);
1465 1466 1467 1468

 	/* let the mpic know we want intrs. default affinity is 0xffffffff
	 * until changed via /proc. That's how it's done on x86. If we want
	 * it differently, then we should make sure we also change the default
1469
	 * values of irq_desc[].affinity in irq.c.
1470 1471 1472
 	 */
	if (distribute_irqs) {
	 	for (i = 0; i < mpic->num_sources ; i++)
1473 1474
			mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
				mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1475 1476 1477
	}

	/* Set current processor priority to 0 */
1478
	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1479

1480
	raw_spin_unlock_irqrestore(&mpic_lock, flags);
1481 1482 1483 1484 1485 1486 1487
#endif /* CONFIG_SMP */
}

int mpic_cpu_get_priority(void)
{
	struct mpic *mpic = mpic_primary;

1488
	return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1489 1490 1491 1492 1493 1494 1495
}

void mpic_cpu_set_priority(int prio)
{
	struct mpic *mpic = mpic_primary;

	prio &= MPIC_CPU_TASKPRI_MASK;
1496
	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508
}

void mpic_teardown_this_cpu(int secondary)
{
	struct mpic *mpic = mpic_primary;
	unsigned long flags;
	u32 msk = 1 << hard_smp_processor_id();
	unsigned int i;

	BUG_ON(mpic == NULL);

	DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1509
	raw_spin_lock_irqsave(&mpic_lock, flags);
1510 1511 1512

	/* let the mpic know we don't want intrs.  */
	for (i = 0; i < mpic->num_sources ; i++)
1513 1514
		mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
			mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1515 1516

	/* Set current processor priority to max */
1517
	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1518 1519 1520 1521
	/* We need to EOI the IPI since not all platforms reset the MPIC
	 * on boot and new interrupts wouldn't get delivered otherwise.
	 */
	mpic_eoi(mpic);
1522

1523
	raw_spin_unlock_irqrestore(&mpic_lock, flags);
1524 1525 1526
}


1527
static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1528
{
1529
	u32 src;
1530

1531
	src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1532
#ifdef DEBUG_LOW
1533
	DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1534
#endif
1535 1536 1537
	if (unlikely(src == mpic->spurious_vec)) {
		if (mpic->flags & MPIC_SPV_EOI)
			mpic_eoi(mpic);
1538
		return NO_IRQ;
1539
	}
1540 1541 1542 1543 1544 1545 1546 1547
	if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
		if (printk_ratelimit())
			printk(KERN_WARNING "%s: Got protected source %d !\n",
			       mpic->name, (int)src);
		mpic_eoi(mpic);
		return NO_IRQ;
	}

1548
	return irq_linear_revmap(mpic->irqhost, src);
1549 1550
}

1551 1552 1553 1554 1555
unsigned int mpic_get_one_irq(struct mpic *mpic)
{
	return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
}

O
Olaf Hering 已提交
1556
unsigned int mpic_get_irq(void)
1557 1558 1559 1560 1561
{
	struct mpic *mpic = mpic_primary;

	BUG_ON(mpic == NULL);

O
Olaf Hering 已提交
1562
	return mpic_get_one_irq(mpic);
1563 1564
}

1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592
unsigned int mpic_get_coreint_irq(void)
{
#ifdef CONFIG_BOOKE
	struct mpic *mpic = mpic_primary;
	u32 src;

	BUG_ON(mpic == NULL);

	src = mfspr(SPRN_EPR);

	if (unlikely(src == mpic->spurious_vec)) {
		if (mpic->flags & MPIC_SPV_EOI)
			mpic_eoi(mpic);
		return NO_IRQ;
	}
	if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
		if (printk_ratelimit())
			printk(KERN_WARNING "%s: Got protected source %d !\n",
			       mpic->name, (int)src);
		return NO_IRQ;
	}

	return irq_linear_revmap(mpic->irqhost, src);
#else
	return NO_IRQ;
#endif
}

1593 1594 1595 1596 1597 1598 1599 1600
unsigned int mpic_get_mcirq(void)
{
	struct mpic *mpic = mpic_primary;

	BUG_ON(mpic == NULL);

	return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
}
1601 1602 1603 1604 1605

#ifdef CONFIG_SMP
void mpic_request_ipis(void)
{
	struct mpic *mpic = mpic_primary;
1606
	int i;
1607 1608
	BUG_ON(mpic == NULL);

1609
	printk(KERN_INFO "mpic: requesting IPIs...\n");
1610 1611 1612

	for (i = 0; i < 4; i++) {
		unsigned int vipi = irq_create_mapping(mpic->irqhost,
1613
						       mpic->ipi_vecs[0] + i);
1614
		if (vipi == NO_IRQ) {
1615 1616
			printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
			continue;
1617
		}
1618
		smp_request_message_ipi(vipi, i);
1619
	}
1620
}
1621

1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636
static void mpic_send_ipi(unsigned int ipi_no, const struct cpumask *cpu_mask)
{
	struct mpic *mpic = mpic_primary;

	BUG_ON(mpic == NULL);

#ifdef DEBUG_IPI
	DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
#endif

	mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
		       ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
		       mpic_physmask(cpumask_bits(cpu_mask)[0]));
}

1637 1638
void smp_mpic_message_pass(int target, int msg)
{
1639 1640
	cpumask_var_t tmp;

1641 1642 1643 1644 1645 1646 1647 1648
	/* make sure we're sending something that translates to an IPI */
	if ((unsigned int)msg > 3) {
		printk("SMP %d: smp_message_pass: unknown msg %d\n",
		       smp_processor_id(), msg);
		return;
	}
	switch (target) {
	case MSG_ALL:
1649
		mpic_send_ipi(msg, cpu_online_mask);
1650 1651
		break;
	case MSG_ALL_BUT_SELF:
1652 1653 1654 1655 1656
		alloc_cpumask_var(&tmp, GFP_NOWAIT);
		cpumask_andnot(tmp, cpu_online_mask,
			       cpumask_of(smp_processor_id()));
		mpic_send_ipi(msg, tmp);
		free_cpumask_var(tmp);
1657 1658
		break;
	default:
1659
		mpic_send_ipi(msg, cpumask_of(target));
1660 1661 1662
		break;
	}
}
1663 1664 1665 1666 1667 1668 1669

int __init smp_mpic_probe(void)
{
	int nr_cpus;

	DBG("smp_mpic_probe()...\n");

1670
	nr_cpus = cpumask_weight(cpu_possible_mask);
1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683

	DBG("nr_cpus: %d\n", nr_cpus);

	if (nr_cpus > 1)
		mpic_request_ipis();

	return nr_cpus;
}

void __devinit smp_mpic_setup_cpu(int cpu)
{
	mpic_setup_this_cpu();
}
1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701

void mpic_reset_core(int cpu)
{
	struct mpic *mpic = mpic_primary;
	u32 pir;
	int cpuid = get_hard_smp_processor_id(cpu);

	/* Set target bit for core reset */
	pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
	pir |= (1 << cpuid);
	mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
	mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));

	/* Restore target bit after reset complete */
	pir &= ~(1 << cpuid);
	mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
	mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
}
1702
#endif /* CONFIG_SMP */
1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731

#ifdef CONFIG_PM
static int mpic_suspend(struct sys_device *dev, pm_message_t state)
{
	struct mpic *mpic = container_of(dev, struct mpic, sysdev);
	int i;

	for (i = 0; i < mpic->num_sources; i++) {
		mpic->save_data[i].vecprio =
			mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
		mpic->save_data[i].dest =
			mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
	}

	return 0;
}

static int mpic_resume(struct sys_device *dev)
{
	struct mpic *mpic = container_of(dev, struct mpic, sysdev);
	int i;

	for (i = 0; i < mpic->num_sources; i++) {
		mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
			       mpic->save_data[i].vecprio);
		mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
			       mpic->save_data[i].dest);

#ifdef CONFIG_MPIC_U3_HT_IRQS
1732
	if (mpic->fixups) {
1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758
		struct mpic_irq_fixup *fixup = &mpic->fixups[i];

		if (fixup->base) {
			/* we use the lowest bit in an inverted meaning */
			if ((mpic->save_data[i].fixup_data & 1) == 0)
				continue;

			/* Enable and configure */
			writeb(0x10 + 2 * fixup->index, fixup->base + 2);

			writel(mpic->save_data[i].fixup_data & ~1,
			       fixup->base + 4);
		}
	}
#endif
	} /* end for loop */

	return 0;
}
#endif

static struct sysdev_class mpic_sysclass = {
#ifdef CONFIG_PM
	.resume = mpic_resume,
	.suspend = mpic_suspend,
#endif
1759
	.name = "mpic",
1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778
};

static int mpic_init_sys(void)
{
	struct mpic *mpic = mpics;
	int error, id = 0;

	error = sysdev_class_register(&mpic_sysclass);

	while (mpic && !error) {
		mpic->sysdev.cls = &mpic_sysclass;
		mpic->sysdev.id = id++;
		error = sysdev_register(&mpic->sysdev);
		mpic = mpic->next;
	}
	return error;
}

device_initcall(mpic_init_sys);