mpic.c 42.3 KB
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/*
 *  arch/powerpc/kernel/mpic.c
 *
 *  Driver for interrupt controllers following the OpenPIC standard, the
 *  common implementation beeing IBM's MPIC. This driver also can deal
 *  with various broken implementations of this HW.
 *
 *  Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
 *
 *  This file is subject to the terms and conditions of the GNU General Public
 *  License.  See the file COPYING in the main directory of this archive
 *  for more details.
 */

#undef DEBUG
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#undef DEBUG_IPI
#undef DEBUG_IRQ
#undef DEBUG_LOW
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#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/smp.h>
#include <linux/interrupt.h>
#include <linux/bootmem.h>
#include <linux/spinlock.h>
#include <linux/pci.h>

#include <asm/ptrace.h>
#include <asm/signal.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/irq.h>
#include <asm/machdep.h>
#include <asm/mpic.h>
#include <asm/smp.h>

M
Michael Ellerman 已提交
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#include "mpic.h"

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#ifdef DEBUG
#define DBG(fmt...) printk(fmt)
#else
#define DBG(fmt...)
#endif

static struct mpic *mpics;
static struct mpic *mpic_primary;
static DEFINE_SPINLOCK(mpic_lock);

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#ifdef CONFIG_PPC32	/* XXX for now */
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#ifdef CONFIG_IRQ_ALL_CPUS
#define distribute_irqs	(1)
#else
#define distribute_irqs	(0)
#endif
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#endif
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#ifdef CONFIG_MPIC_WEIRD
static u32 mpic_infos[][MPIC_IDX_END] = {
	[0] = {	/* Original OpenPIC compatible MPIC */
		MPIC_GREG_BASE,
		MPIC_GREG_FEATURE_0,
		MPIC_GREG_GLOBAL_CONF_0,
		MPIC_GREG_VENDOR_ID,
		MPIC_GREG_IPI_VECTOR_PRI_0,
		MPIC_GREG_IPI_STRIDE,
		MPIC_GREG_SPURIOUS,
		MPIC_GREG_TIMER_FREQ,

		MPIC_TIMER_BASE,
		MPIC_TIMER_STRIDE,
		MPIC_TIMER_CURRENT_CNT,
		MPIC_TIMER_BASE_CNT,
		MPIC_TIMER_VECTOR_PRI,
		MPIC_TIMER_DESTINATION,

		MPIC_CPU_BASE,
		MPIC_CPU_STRIDE,
		MPIC_CPU_IPI_DISPATCH_0,
		MPIC_CPU_IPI_DISPATCH_STRIDE,
		MPIC_CPU_CURRENT_TASK_PRI,
		MPIC_CPU_WHOAMI,
		MPIC_CPU_INTACK,
		MPIC_CPU_EOI,
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		MPIC_CPU_MCACK,
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		MPIC_IRQ_BASE,
		MPIC_IRQ_STRIDE,
		MPIC_IRQ_VECTOR_PRI,
		MPIC_VECPRI_VECTOR_MASK,
		MPIC_VECPRI_POLARITY_POSITIVE,
		MPIC_VECPRI_POLARITY_NEGATIVE,
		MPIC_VECPRI_SENSE_LEVEL,
		MPIC_VECPRI_SENSE_EDGE,
		MPIC_VECPRI_POLARITY_MASK,
		MPIC_VECPRI_SENSE_MASK,
		MPIC_IRQ_DESTINATION
	},
	[1] = {	/* Tsi108/109 PIC */
		TSI108_GREG_BASE,
		TSI108_GREG_FEATURE_0,
		TSI108_GREG_GLOBAL_CONF_0,
		TSI108_GREG_VENDOR_ID,
		TSI108_GREG_IPI_VECTOR_PRI_0,
		TSI108_GREG_IPI_STRIDE,
		TSI108_GREG_SPURIOUS,
		TSI108_GREG_TIMER_FREQ,

		TSI108_TIMER_BASE,
		TSI108_TIMER_STRIDE,
		TSI108_TIMER_CURRENT_CNT,
		TSI108_TIMER_BASE_CNT,
		TSI108_TIMER_VECTOR_PRI,
		TSI108_TIMER_DESTINATION,

		TSI108_CPU_BASE,
		TSI108_CPU_STRIDE,
		TSI108_CPU_IPI_DISPATCH_0,
		TSI108_CPU_IPI_DISPATCH_STRIDE,
		TSI108_CPU_CURRENT_TASK_PRI,
		TSI108_CPU_WHOAMI,
		TSI108_CPU_INTACK,
		TSI108_CPU_EOI,
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		TSI108_CPU_MCACK,
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		TSI108_IRQ_BASE,
		TSI108_IRQ_STRIDE,
		TSI108_IRQ_VECTOR_PRI,
		TSI108_VECPRI_VECTOR_MASK,
		TSI108_VECPRI_POLARITY_POSITIVE,
		TSI108_VECPRI_POLARITY_NEGATIVE,
		TSI108_VECPRI_SENSE_LEVEL,
		TSI108_VECPRI_SENSE_EDGE,
		TSI108_VECPRI_POLARITY_MASK,
		TSI108_VECPRI_SENSE_MASK,
		TSI108_IRQ_DESTINATION
	},
};

#define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]

#else /* CONFIG_MPIC_WEIRD */

#define MPIC_INFO(name) MPIC_##name

#endif /* CONFIG_MPIC_WEIRD */

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/*
 * Register accessor functions
 */


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static inline u32 _mpic_read(enum mpic_reg_type type,
			     struct mpic_reg_bank *rb,
			     unsigned int reg)
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{
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	switch(type) {
#ifdef CONFIG_PPC_DCR
	case mpic_access_dcr:
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		return dcr_read(rb->dhost, reg);
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#endif
	case mpic_access_mmio_be:
		return in_be32(rb->base + (reg >> 2));
	case mpic_access_mmio_le:
	default:
		return in_le32(rb->base + (reg >> 2));
	}
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}

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static inline void _mpic_write(enum mpic_reg_type type,
			       struct mpic_reg_bank *rb,
 			       unsigned int reg, u32 value)
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{
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	switch(type) {
#ifdef CONFIG_PPC_DCR
	case mpic_access_dcr:
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		dcr_write(rb->dhost, reg, value);
		break;
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#endif
	case mpic_access_mmio_be:
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		out_be32(rb->base + (reg >> 2), value);
		break;
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	case mpic_access_mmio_le:
	default:
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		out_le32(rb->base + (reg >> 2), value);
		break;
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	}
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}

static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
{
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	enum mpic_reg_type type = mpic->reg_type;
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	unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
			      (ipi * MPIC_INFO(GREG_IPI_STRIDE));
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	if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
		type = mpic_access_mmio_be;
	return _mpic_read(type, &mpic->gregs, offset);
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}

static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
{
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	unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
			      (ipi * MPIC_INFO(GREG_IPI_STRIDE));
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	_mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
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}

static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
{
	unsigned int cpu = 0;

	if (mpic->flags & MPIC_PRIMARY)
		cpu = hard_smp_processor_id();
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	return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
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}

static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
{
	unsigned int cpu = 0;

	if (mpic->flags & MPIC_PRIMARY)
		cpu = hard_smp_processor_id();

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	_mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
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}

static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
{
	unsigned int	isu = src_no >> mpic->isu_shift;
	unsigned int	idx = src_no & mpic->isu_mask;

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#ifdef CONFIG_MPIC_BROKEN_REGREAD
	if (reg == 0)
		return mpic->isu_reg0_shadow[idx];
	else
#endif
		return _mpic_read(mpic->reg_type, &mpic->isus[isu],
				  reg + (idx * MPIC_INFO(IRQ_STRIDE)));
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}

static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
				   unsigned int reg, u32 value)
{
	unsigned int	isu = src_no >> mpic->isu_shift;
	unsigned int	idx = src_no & mpic->isu_mask;

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	_mpic_write(mpic->reg_type, &mpic->isus[isu],
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		    reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
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#ifdef CONFIG_MPIC_BROKEN_REGREAD
	if (reg == 0)
		mpic->isu_reg0_shadow[idx] = value;
#endif
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}

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#define mpic_read(b,r)		_mpic_read(mpic->reg_type,&(b),(r))
#define mpic_write(b,r,v)	_mpic_write(mpic->reg_type,&(b),(r),(v))
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#define mpic_ipi_read(i)	_mpic_ipi_read(mpic,(i))
#define mpic_ipi_write(i,v)	_mpic_ipi_write(mpic,(i),(v))
#define mpic_cpu_read(i)	_mpic_cpu_read(mpic,(i))
#define mpic_cpu_write(i,v)	_mpic_cpu_write(mpic,(i),(v))
#define mpic_irq_read(s,r)	_mpic_irq_read(mpic,(s),(r))
#define mpic_irq_write(s,r,v)	_mpic_irq_write(mpic,(s),(r),(v))


/*
 * Low level utility functions
 */


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static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
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			   struct mpic_reg_bank *rb, unsigned int offset,
			   unsigned int size)
{
	rb->base = ioremap(phys_addr + offset, size);
	BUG_ON(rb->base == NULL);
}

#ifdef CONFIG_PPC_DCR
static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
			  unsigned int offset, unsigned int size)
{
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	const u32 *dbasep;

	dbasep = of_get_property(mpic->irqhost->of_node, "dcr-reg", NULL);

	rb->dhost = dcr_map(mpic->irqhost->of_node, *dbasep + offset, size);
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	BUG_ON(!DCR_MAP_OK(rb->dhost));
}

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static inline void mpic_map(struct mpic *mpic, phys_addr_t phys_addr,
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			    struct mpic_reg_bank *rb, unsigned int offset,
			    unsigned int size)
{
	if (mpic->flags & MPIC_USES_DCR)
		_mpic_map_dcr(mpic, rb, offset, size);
	else
		_mpic_map_mmio(mpic, phys_addr, rb, offset, size);
}
#else /* CONFIG_PPC_DCR */
#define mpic_map(m,p,b,o,s)	_mpic_map_mmio(m,p,b,o,s)
#endif /* !CONFIG_PPC_DCR */


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/* Check if we have one of those nice broken MPICs with a flipped endian on
 * reads from IPI registers
 */
static void __init mpic_test_broken_ipi(struct mpic *mpic)
{
	u32 r;

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	mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
	r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
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	if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
		printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
		mpic->flags |= MPIC_BROKEN_IPI;
	}
}

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#ifdef CONFIG_MPIC_U3_HT_IRQS
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/* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
 * to force the edge setting on the MPIC and do the ack workaround.
 */
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static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
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{
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	if (source >= 128 || !mpic->fixups)
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		return 0;
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	return mpic->fixups[source].base != NULL;
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}

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static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
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{
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	struct mpic_irq_fixup *fixup = &mpic->fixups[source];
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	if (fixup->applebase) {
		unsigned int soff = (fixup->index >> 3) & ~3;
		unsigned int mask = 1U << (fixup->index & 0x1f);
		writel(mask, fixup->applebase + soff);
	} else {
		spin_lock(&mpic->fixup_lock);
		writeb(0x11 + 2 * fixup->index, fixup->base + 2);
		writel(fixup->data, fixup->base + 4);
		spin_unlock(&mpic->fixup_lock);
	}
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}

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static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
				      unsigned int irqflags)
{
	struct mpic_irq_fixup *fixup = &mpic->fixups[source];
	unsigned long flags;
	u32 tmp;

	if (fixup->base == NULL)
		return;

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	DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n",
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	    source, irqflags, fixup->index);
	spin_lock_irqsave(&mpic->fixup_lock, flags);
	/* Enable and configure */
	writeb(0x10 + 2 * fixup->index, fixup->base + 2);
	tmp = readl(fixup->base + 4);
	tmp &= ~(0x23U);
	if (irqflags & IRQ_LEVEL)
		tmp |= 0x22;
	writel(tmp, fixup->base + 4);
	spin_unlock_irqrestore(&mpic->fixup_lock, flags);
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#ifdef CONFIG_PM
	/* use the lowest bit inverted to the actual HW,
	 * set if this fixup was enabled, clear otherwise */
	mpic->save_data[source].fixup_data = tmp | 1;
#endif
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}

static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source,
				       unsigned int irqflags)
{
	struct mpic_irq_fixup *fixup = &mpic->fixups[source];
	unsigned long flags;
	u32 tmp;

	if (fixup->base == NULL)
		return;

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	DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags);
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	/* Disable */
	spin_lock_irqsave(&mpic->fixup_lock, flags);
	writeb(0x10 + 2 * fixup->index, fixup->base + 2);
	tmp = readl(fixup->base + 4);
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	tmp |= 1;
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	writel(tmp, fixup->base + 4);
	spin_unlock_irqrestore(&mpic->fixup_lock, flags);
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#ifdef CONFIG_PM
	/* use the lowest bit inverted to the actual HW,
	 * set if this fixup was enabled, clear otherwise */
	mpic->save_data[source].fixup_data = tmp & ~1;
#endif
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}
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#ifdef CONFIG_PCI_MSI
static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
				    unsigned int devfn)
{
	u8 __iomem *base;
	u8 pos, flags;
	u64 addr = 0;

	for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
	     pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
		u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
		if (id == PCI_CAP_ID_HT) {
			id = readb(devbase + pos + 3);
			if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
				break;
		}
	}

	if (pos == 0)
		return;

	base = devbase + pos;

	flags = readb(base + HT_MSI_FLAGS);
	if (!(flags & HT_MSI_FLAGS_FIXED)) {
		addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
		addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
	}

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	printk(KERN_DEBUG "mpic:   - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
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		PCI_SLOT(devfn), PCI_FUNC(devfn),
		flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);

	if (!(flags & HT_MSI_FLAGS_ENABLE))
		writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
}
#else
static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
				    unsigned int devfn)
{
	return;
}
#endif

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static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
				    unsigned int devfn, u32 vdid)
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{
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	int i, irq, n;
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	u8 __iomem *base;
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	u32 tmp;
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	u8 pos;
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	for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
	     pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
		u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
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		if (id == PCI_CAP_ID_HT) {
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			id = readb(devbase + pos + 3);
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			if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
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				break;
		}
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	}
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	if (pos == 0)
		return;

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	base = devbase + pos;
	writeb(0x01, base + 2);
	n = (readl(base + 4) >> 16) & 0xff;
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	printk(KERN_INFO "mpic:   - HT:%02x.%x [0x%02x] vendor %04x device %04x"
	       " has %d irqs\n",
	       devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
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	for (i = 0; i <= n; i++) {
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		writeb(0x10 + 2 * i, base + 2);
		tmp = readl(base + 4);
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		irq = (tmp >> 16) & 0xff;
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		DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
		/* mask it , will be unmasked later */
		tmp |= 0x1;
		writel(tmp, base + 4);
		mpic->fixups[irq].index = i;
		mpic->fixups[irq].base = base;
		/* Apple HT PIC has a non-standard way of doing EOIs */
		if ((vdid & 0xffff) == 0x106b)
			mpic->fixups[irq].applebase = devbase + 0x60;
		else
			mpic->fixups[irq].applebase = NULL;
		writeb(0x11 + 2 * i, base + 2);
		mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
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	}
}
 
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static void __init mpic_scan_ht_pics(struct mpic *mpic)
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{
	unsigned int devfn;
	u8 __iomem *cfgspace;

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	printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
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	/* Allocate fixups array */
	mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup));
	BUG_ON(mpic->fixups == NULL);
	memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup));

	/* Init spinlock */
	spin_lock_init(&mpic->fixup_lock);

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	/* Map U3 config space. We assume all IO-APICs are on the primary bus
	 * so we only need to map 64kB.
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	 */
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	cfgspace = ioremap(0xf2000000, 0x10000);
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	BUG_ON(cfgspace == NULL);

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	/* Now we scan all slots. We do a very quick scan, we read the header
	 * type, vendor ID and device ID only, that's plenty enough
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	 */
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	for (devfn = 0; devfn < 0x100; devfn++) {
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		u8 __iomem *devbase = cfgspace + (devfn << 8);
		u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
		u32 l = readl(devbase + PCI_VENDOR_ID);
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		u16 s;
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		DBG("devfn %x, l: %x\n", devfn, l);

		/* If no device, skip */
		if (l == 0xffffffff || l == 0x00000000 ||
		    l == 0x0000ffff || l == 0xffff0000)
			goto next;
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		/* Check if is supports capability lists */
		s = readw(devbase + PCI_STATUS);
		if (!(s & PCI_STATUS_CAP_LIST))
			goto next;
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		mpic_scan_ht_pic(mpic, devbase, devfn, l);
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		mpic_scan_ht_msi(mpic, devbase, devfn);
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	next:
		/* next device, if function 0 */
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		if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
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			devfn += 7;
	}
}

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#else /* CONFIG_MPIC_U3_HT_IRQS */
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static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
{
	return 0;
}

static void __init mpic_scan_ht_pics(struct mpic *mpic)
{
}

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#endif /* CONFIG_MPIC_U3_HT_IRQS */
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#ifdef CONFIG_SMP
static int irq_choose_cpu(unsigned int virt_irq)
{
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	cpumask_t mask;
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	int cpuid;

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	cpumask_copy(&mask, irq_desc[virt_irq].affinity);
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	if (cpus_equal(mask, CPU_MASK_ALL)) {
		static int irq_rover;
		static DEFINE_SPINLOCK(irq_rover_lock);
		unsigned long flags;

		/* Round-robin distribution... */
	do_round_robin:
		spin_lock_irqsave(&irq_rover_lock, flags);

		while (!cpu_online(irq_rover)) {
			if (++irq_rover >= NR_CPUS)
				irq_rover = 0;
		}
		cpuid = irq_rover;
		do {
			if (++irq_rover >= NR_CPUS)
				irq_rover = 0;
		} while (!cpu_online(irq_rover));

		spin_unlock_irqrestore(&irq_rover_lock, flags);
	} else {
		cpumask_t tmp;

		cpus_and(tmp, cpu_online_map, mask);

		if (cpus_empty(tmp))
			goto do_round_robin;

		cpuid = first_cpu(tmp);
	}

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	return get_hard_smp_processor_id(cpuid);
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}
#else
static int irq_choose_cpu(unsigned int virt_irq)
{
	return hard_smp_processor_id();
}
#endif
612

613 614
#define mpic_irq_to_hw(virq)	((unsigned int)irq_map[virq].hwirq)

615 616 617
/* Find an mpic associated with a given linux interrupt */
static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi)
{
618
	unsigned int src = mpic_irq_to_hw(irq);
619
	struct mpic *mpic;
620 621 622

	if (irq < NUM_ISA_INTERRUPTS)
		return NULL;
623 624 625

	mpic = irq_desc[irq].chip_data;

626
	if (is_ipi)
627 628
		*is_ipi = (src >= mpic->ipi_vecs[0] &&
			   src <= mpic->ipi_vecs[3]);
629

630
	return mpic;
631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647
}

/* Convert a cpu mask from logical to physical cpu numbers. */
static inline u32 mpic_physmask(u32 cpumask)
{
	int i;
	u32 mask = 0;

	for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
		mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
	return mask;
}

#ifdef CONFIG_SMP
/* Get the mpic structure from the IPI number */
static inline struct mpic * mpic_from_ipi(unsigned int ipi)
{
648
	return irq_desc[ipi].chip_data;
649 650 651 652 653 654
}
#endif

/* Get the mpic structure from the irq number */
static inline struct mpic * mpic_from_irq(unsigned int irq)
{
655
	return irq_desc[irq].chip_data;
656 657 658 659 660
}

/* Send an EOI */
static inline void mpic_eoi(struct mpic *mpic)
{
661 662
	mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
	(void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
663 664 665 666 667 668 669
}

/*
 * Linux descriptor level callbacks
 */


670
void mpic_unmask_irq(unsigned int irq)
671 672 673
{
	unsigned int loops = 100000;
	struct mpic *mpic = mpic_from_irq(irq);
674
	unsigned int src = mpic_irq_to_hw(irq);
675

676
	DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
677

678 679
	mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
		       mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
680
		       ~MPIC_VECPRI_MASK);
681 682 683 684 685 686
	/* make sure mask gets to controller before we return to user */
	do {
		if (!loops--) {
			printk(KERN_ERR "mpic_enable_irq timeout\n");
			break;
		}
687
	} while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
688 689
}

690
void mpic_mask_irq(unsigned int irq)
691 692 693
{
	unsigned int loops = 100000;
	struct mpic *mpic = mpic_from_irq(irq);
694
	unsigned int src = mpic_irq_to_hw(irq);
695 696 697

	DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);

698 699
	mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
		       mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
700
		       MPIC_VECPRI_MASK);
701 702 703 704 705 706 707

	/* make sure mask gets to controller before we return to user */
	do {
		if (!loops--) {
			printk(KERN_ERR "mpic_enable_irq timeout\n");
			break;
		}
708
	} while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
709 710
}

711
void mpic_end_irq(unsigned int irq)
712
{
713 714 715 716 717 718 719 720 721 722 723 724 725
	struct mpic *mpic = mpic_from_irq(irq);

#ifdef DEBUG_IRQ
	DBG("%s: end_irq: %d\n", mpic->name, irq);
#endif
	/* We always EOI on end_irq() even for edge interrupts since that
	 * should only lower the priority, the MPIC should have properly
	 * latched another edge interrupt coming in anyway
	 */

	mpic_eoi(mpic);
}

726
#ifdef CONFIG_MPIC_U3_HT_IRQS
727 728 729

static void mpic_unmask_ht_irq(unsigned int irq)
{
730
	struct mpic *mpic = mpic_from_irq(irq);
731
	unsigned int src = mpic_irq_to_hw(irq);
732

733
	mpic_unmask_irq(irq);
734

735 736 737 738 739 740 741
	if (irq_desc[irq].status & IRQ_LEVEL)
		mpic_ht_end_irq(mpic, src);
}

static unsigned int mpic_startup_ht_irq(unsigned int irq)
{
	struct mpic *mpic = mpic_from_irq(irq);
742
	unsigned int src = mpic_irq_to_hw(irq);
743

744 745 746 747
	mpic_unmask_irq(irq);
	mpic_startup_ht_interrupt(mpic, src, irq_desc[irq].status);

	return 0;
748 749
}

750 751 752
static void mpic_shutdown_ht_irq(unsigned int irq)
{
	struct mpic *mpic = mpic_from_irq(irq);
753
	unsigned int src = mpic_irq_to_hw(irq);
754 755 756 757 758 759

	mpic_shutdown_ht_interrupt(mpic, src, irq_desc[irq].status);
	mpic_mask_irq(irq);
}

static void mpic_end_ht_irq(unsigned int irq)
760 761
{
	struct mpic *mpic = mpic_from_irq(irq);
762
	unsigned int src = mpic_irq_to_hw(irq);
763

764
#ifdef DEBUG_IRQ
765
	DBG("%s: end_irq: %d\n", mpic->name, irq);
766
#endif
767 768 769 770 771
	/* We always EOI on end_irq() even for edge interrupts since that
	 * should only lower the priority, the MPIC should have properly
	 * latched another edge interrupt coming in anyway
	 */

772 773
	if (irq_desc[irq].status & IRQ_LEVEL)
		mpic_ht_end_irq(mpic, src);
774 775
	mpic_eoi(mpic);
}
776
#endif /* !CONFIG_MPIC_U3_HT_IRQS */
777

778 779
#ifdef CONFIG_SMP

780
static void mpic_unmask_ipi(unsigned int irq)
781 782
{
	struct mpic *mpic = mpic_from_ipi(irq);
783
	unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0];
784 785 786 787 788

	DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src);
	mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
}

789
static void mpic_mask_ipi(unsigned int irq)
790 791 792 793 794 795 796 797 798 799 800 801
{
	/* NEVER disable an IPI... that's just plain wrong! */
}

static void mpic_end_ipi(unsigned int irq)
{
	struct mpic *mpic = mpic_from_ipi(irq);

	/*
	 * IPIs are marked IRQ_PER_CPU. This has the side effect of
	 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
	 * applying to them. We EOI them late to avoid re-entering.
802
	 * We mark IPI's with IRQF_DISABLED as they must run with
803 804 805 806 807 808 809
	 * irqs disabled.
	 */
	mpic_eoi(mpic);
}

#endif /* CONFIG_SMP */

810
void mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask)
811 812
{
	struct mpic *mpic = mpic_from_irq(irq);
813
	unsigned int src = mpic_irq_to_hw(irq);
814

815 816
	if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
		int cpuid = irq_choose_cpu(irq);
817

818 819 820
		mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
	} else {
		cpumask_t tmp;
821

822
		cpumask_and(&tmp, cpumask, cpu_online_mask);
823 824 825 826

		mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
			       mpic_physmask(cpus_addr(tmp)[0]));
	}
827 828
}

829
static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
830 831
{
	/* Now convert sense value */
832
	switch(type & IRQ_TYPE_SENSE_MASK) {
833
	case IRQ_TYPE_EDGE_RISING:
834 835
		return MPIC_INFO(VECPRI_SENSE_EDGE) |
		       MPIC_INFO(VECPRI_POLARITY_POSITIVE);
836
	case IRQ_TYPE_EDGE_FALLING:
837
	case IRQ_TYPE_EDGE_BOTH:
838 839
		return MPIC_INFO(VECPRI_SENSE_EDGE) |
		       MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
840
	case IRQ_TYPE_LEVEL_HIGH:
841 842
		return MPIC_INFO(VECPRI_SENSE_LEVEL) |
		       MPIC_INFO(VECPRI_POLARITY_POSITIVE);
843 844
	case IRQ_TYPE_LEVEL_LOW:
	default:
845 846
		return MPIC_INFO(VECPRI_SENSE_LEVEL) |
		       MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
847
	}
848 849
}

850
int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)
851 852 853 854 855 856
{
	struct mpic *mpic = mpic_from_irq(virq);
	unsigned int src = mpic_irq_to_hw(virq);
	struct irq_desc *desc = get_irq_desc(virq);
	unsigned int vecpri, vold, vnew;

857 858
	DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
	    mpic, virq, src, flow_type);
859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877

	if (src >= mpic->irq_count)
		return -EINVAL;

	if (flow_type == IRQ_TYPE_NONE)
		if (mpic->senses && src < mpic->senses_count)
			flow_type = mpic->senses[src];
	if (flow_type == IRQ_TYPE_NONE)
		flow_type = IRQ_TYPE_LEVEL_LOW;

	desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
	desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
	if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
		desc->status |= IRQ_LEVEL;

	if (mpic_is_ht_interrupt(mpic, src))
		vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
			MPIC_VECPRI_SENSE_EDGE;
	else
878
		vecpri = mpic_type_to_vecpri(mpic, flow_type);
879

880 881 882
	vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
	vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
			MPIC_INFO(VECPRI_SENSE_MASK));
883 884
	vnew |= vecpri;
	if (vold != vnew)
885
		mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
886 887

	return 0;
888 889
}

890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907
void mpic_set_vector(unsigned int virq, unsigned int vector)
{
	struct mpic *mpic = mpic_from_irq(virq);
	unsigned int src = mpic_irq_to_hw(virq);
	unsigned int vecpri;

	DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
	    mpic, virq, src, vector);

	if (src >= mpic->irq_count)
		return;

	vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
	vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
	vecpri |= vector;
	mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
}

908
static struct irq_chip mpic_irq_chip = {
909 910 911 912
	.mask		= mpic_mask_irq,
	.unmask		= mpic_unmask_irq,
	.eoi		= mpic_end_irq,
	.set_type	= mpic_set_irq_type,
913 914 915 916
};

#ifdef CONFIG_SMP
static struct irq_chip mpic_ipi_chip = {
917 918 919
	.mask		= mpic_mask_ipi,
	.unmask		= mpic_unmask_ipi,
	.eoi		= mpic_end_ipi,
920 921 922
};
#endif /* CONFIG_SMP */

923
#ifdef CONFIG_MPIC_U3_HT_IRQS
924 925 926 927 928 929
static struct irq_chip mpic_irq_ht_chip = {
	.startup	= mpic_startup_ht_irq,
	.shutdown	= mpic_shutdown_ht_irq,
	.mask		= mpic_mask_irq,
	.unmask		= mpic_unmask_ht_irq,
	.eoi		= mpic_end_ht_irq,
930
	.set_type	= mpic_set_irq_type,
931
};
932
#endif /* CONFIG_MPIC_U3_HT_IRQS */
933

934

935 936 937
static int mpic_host_match(struct irq_host *h, struct device_node *node)
{
	/* Exact match, unless mpic node is NULL */
938
	return h->of_node == NULL || h->of_node == node;
939 940 941
}

static int mpic_host_map(struct irq_host *h, unsigned int virq,
942
			 irq_hw_number_t hw)
943 944
{
	struct mpic *mpic = h->host_data;
945
	struct irq_chip *chip;
946

947
	DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
948

949
	if (hw == mpic->spurious_vec)
950
		return -EINVAL;
951 952
	if (mpic->protected && test_bit(hw, mpic->protected))
		return -EINVAL;
953

954
#ifdef CONFIG_SMP
955
	else if (hw >= mpic->ipi_vecs[0]) {
956 957
		WARN_ON(!(mpic->flags & MPIC_PRIMARY));

958
		DBG("mpic: mapping as IPI\n");
959 960 961 962 963 964 965 966 967 968
		set_irq_chip_data(virq, mpic);
		set_irq_chip_and_handler(virq, &mpic->hc_ipi,
					 handle_percpu_irq);
		return 0;
	}
#endif /* CONFIG_SMP */

	if (hw >= mpic->irq_count)
		return -EINVAL;

M
Michael Ellerman 已提交
969 970
	mpic_msi_reserve_hwirq(mpic, hw);

971
	/* Default chip */
972 973
	chip = &mpic->hc_irq;

974
#ifdef CONFIG_MPIC_U3_HT_IRQS
975
	/* Check for HT interrupts, override vecpri */
976
	if (mpic_is_ht_interrupt(mpic, hw))
977
		chip = &mpic->hc_ht_irq;
978
#endif /* CONFIG_MPIC_U3_HT_IRQS */
979

980
	DBG("mpic: mapping to irq chip @%p\n", chip);
981 982 983

	set_irq_chip_data(virq, mpic);
	set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq);
984 985 986 987

	/* Set default irq type */
	set_irq_type(virq, IRQ_TYPE_NONE);

988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003
	return 0;
}

static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
			   u32 *intspec, unsigned int intsize,
			   irq_hw_number_t *out_hwirq, unsigned int *out_flags)

{
	static unsigned char map_mpic_senses[4] = {
		IRQ_TYPE_EDGE_RISING,
		IRQ_TYPE_LEVEL_LOW,
		IRQ_TYPE_LEVEL_HIGH,
		IRQ_TYPE_EDGE_FALLING,
	};

	*out_hwirq = intspec[0];
1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020
	if (intsize > 1) {
		u32 mask = 0x3;

		/* Apple invented a new race of encoding on machines with
		 * an HT APIC. They encode, among others, the index within
		 * the HT APIC. We don't care about it here since thankfully,
		 * it appears that they have the APIC already properly
		 * configured, and thus our current fixup code that reads the
		 * APIC config works fine. However, we still need to mask out
		 * bits in the specifier to make sure we only get bit 0 which
		 * is the level/edge bit (the only sense bit exposed by Apple),
		 * as their bit 1 means something else.
		 */
		if (machine_is(powermac))
			mask = 0x1;
		*out_flags = map_mpic_senses[intspec[1] & mask];
	} else
1021 1022
		*out_flags = IRQ_TYPE_NONE;

1023 1024 1025
	DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
	    intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);

1026 1027 1028 1029 1030 1031 1032 1033 1034
	return 0;
}

static struct irq_host_ops mpic_host_ops = {
	.match = mpic_host_match,
	.map = mpic_host_map,
	.xlate = mpic_host_xlate,
};

1035 1036 1037 1038
/*
 * Exported functions
 */

1039
struct mpic * __init mpic_alloc(struct device_node *node,
1040
				phys_addr_t phys_addr,
1041 1042 1043 1044 1045 1046
				unsigned int flags,
				unsigned int isu_size,
				unsigned int irq_count,
				const char *name)
{
	struct mpic	*mpic;
1047
	u32		greg_feature;
1048 1049
	const char	*vers;
	int		i;
1050
	int		intvec_top;
1051
	u64		paddr = phys_addr;
1052 1053 1054 1055 1056 1057 1058 1059

	mpic = alloc_bootmem(sizeof(struct mpic));
	if (mpic == NULL)
		return NULL;
	
	memset(mpic, 0, sizeof(struct mpic));
	mpic->name = name;

1060
	mpic->hc_irq = mpic_irq_chip;
1061 1062 1063
	mpic->hc_irq.typename = name;
	if (flags & MPIC_PRIMARY)
		mpic->hc_irq.set_affinity = mpic_set_affinity;
1064
#ifdef CONFIG_MPIC_U3_HT_IRQS
1065 1066 1067 1068
	mpic->hc_ht_irq = mpic_irq_ht_chip;
	mpic->hc_ht_irq.typename = name;
	if (flags & MPIC_PRIMARY)
		mpic->hc_ht_irq.set_affinity = mpic_set_affinity;
1069
#endif /* CONFIG_MPIC_U3_HT_IRQS */
1070

1071
#ifdef CONFIG_SMP
1072
	mpic->hc_ipi = mpic_ipi_chip;
1073
	mpic->hc_ipi.typename = name;
1074 1075 1076 1077 1078 1079 1080
#endif /* CONFIG_SMP */

	mpic->flags = flags;
	mpic->isu_size = isu_size;
	mpic->irq_count = irq_count;
	mpic->num_sources = 0; /* so far */

1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095
	if (flags & MPIC_LARGE_VECTORS)
		intvec_top = 2047;
	else
		intvec_top = 255;

	mpic->timer_vecs[0] = intvec_top - 8;
	mpic->timer_vecs[1] = intvec_top - 7;
	mpic->timer_vecs[2] = intvec_top - 6;
	mpic->timer_vecs[3] = intvec_top - 5;
	mpic->ipi_vecs[0]   = intvec_top - 4;
	mpic->ipi_vecs[1]   = intvec_top - 3;
	mpic->ipi_vecs[2]   = intvec_top - 2;
	mpic->ipi_vecs[3]   = intvec_top - 1;
	mpic->spurious_vec  = intvec_top;

1096
	/* Check for "big-endian" in device-tree */
1097
	if (node && of_get_property(node, "big-endian", NULL) != NULL)
1098 1099
		mpic->flags |= MPIC_BIG_ENDIAN;

1100 1101
	/* Look for protected sources */
	if (node) {
1102 1103
		int psize;
		unsigned int bits, mapsize;
1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119
		const u32 *psrc =
			of_get_property(node, "protected-sources", &psize);
		if (psrc) {
			psize /= 4;
			bits = intvec_top + 1;
			mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long);
			mpic->protected = alloc_bootmem(mapsize);
			BUG_ON(mpic->protected == NULL);
			memset(mpic->protected, 0, mapsize);
			for (i = 0; i < psize; i++) {
				if (psrc[i] > intvec_top)
					continue;
				__set_bit(psrc[i], mpic->protected);
			}
		}
	}
1120

1121 1122 1123 1124
#ifdef CONFIG_MPIC_WEIRD
	mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
#endif

1125 1126 1127 1128
	/* default register type */
	mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?
		mpic_access_mmio_be : mpic_access_mmio_le;

1129 1130 1131 1132
	/* If no physical address is passed in, a device-node is mandatory */
	BUG_ON(paddr == 0 && node == NULL);

	/* If no physical address passed in, check if it's dcr based */
1133
	if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) {
1134
#ifdef CONFIG_PPC_DCR
1135
		mpic->flags |= MPIC_USES_DCR;
1136 1137
		mpic->reg_type = mpic_access_dcr;
#else
1138
		BUG();
1139
#endif /* CONFIG_PPC_DCR */
1140
	}
1141

1142 1143 1144 1145
	/* If the MPIC is not DCR based, and no physical address was passed
	 * in, try to obtain one
	 */
	if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
1146
		const u32 *reg = of_get_property(node, "reg", NULL);
1147 1148 1149 1150 1151
		BUG_ON(reg == NULL);
		paddr = of_translate_address(node, reg);
		BUG_ON(paddr == OF_BAD_ADDR);
	}

1152
	/* Map the global registers */
1153 1154
	mpic_map(mpic, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
	mpic_map(mpic, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1155 1156 1157

	/* Reset */
	if (flags & MPIC_WANTS_RESET) {
1158 1159
		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1160
			   | MPIC_GREG_GCONF_RESET);
1161
		while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1162 1163 1164 1165
		       & MPIC_GREG_GCONF_RESET)
			mb();
	}

1166 1167 1168 1169 1170 1171
	/* CoreInt */
	if (flags & MPIC_ENABLE_COREINT)
		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
			   | MPIC_GREG_GCONF_COREINT);

1172 1173 1174 1175 1176
	if (flags & MPIC_ENABLE_MCK)
		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
			   | MPIC_GREG_GCONF_MCK);

1177 1178 1179 1180
	/* Read feature register, calculate num CPUs and, for non-ISU
	 * MPICs, num sources as well. On ISU MPICs, sources are counted
	 * as ISUs are added
	 */
1181 1182
	greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
	mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK)
1183
			  >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
1184
	if (isu_size == 0) {
1185 1186 1187 1188 1189 1190
		if (flags & MPIC_BROKEN_FRR_NIRQS)
			mpic->num_sources = mpic->irq_count;
		else
			mpic->num_sources =
				((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
				 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
1191
	}
1192 1193 1194

	/* Map the per-CPU registers */
	for (i = 0; i < mpic->num_cpus; i++) {
1195
		mpic_map(mpic, paddr, &mpic->cpuregs[i],
1196 1197
			 MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE),
			 0x1000);
1198 1199 1200 1201 1202
	}

	/* Initialize main ISU if none provided */
	if (mpic->isu_size == 0) {
		mpic->isu_size = mpic->num_sources;
1203
		mpic_map(mpic, paddr, &mpic->isus[0],
1204
			 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1205 1206 1207 1208
	}
	mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
	mpic->isu_mask = (1 << mpic->isu_shift) - 1;

1209 1210 1211 1212 1213 1214 1215 1216 1217
	mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
				       isu_size ? isu_size : mpic->num_sources,
				       &mpic_host_ops,
				       flags & MPIC_LARGE_VECTORS ? 2048 : 256);
	if (mpic->irqhost == NULL)
		return NULL;

	mpic->irqhost->host_data = mpic;

1218
	/* Display version */
1219
	switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232
	case 1:
		vers = "1.0";
		break;
	case 2:
		vers = "1.2";
		break;
	case 3:
		vers = "1.3";
		break;
	default:
		vers = "<unknown>";
		break;
	}
1233 1234 1235 1236 1237
	printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
	       " max %d CPUs\n",
	       name, vers, (unsigned long long)paddr, mpic->num_cpus);
	printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
	       mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1238 1239 1240 1241

	mpic->next = mpics;
	mpics = mpic;

1242
	if (flags & MPIC_PRIMARY) {
1243
		mpic_primary = mpic;
1244 1245
		irq_set_default_host(mpic->irqhost);
	}
1246 1247 1248 1249 1250

	return mpic;
}

void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1251
			    phys_addr_t paddr)
1252 1253 1254 1255 1256
{
	unsigned int isu_first = isu_num * mpic->isu_size;

	BUG_ON(isu_num >= MPIC_MAX_ISU);

1257
	mpic_map(mpic, paddr, &mpic->isus[isu_num], 0,
1258
		 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1259 1260 1261 1262
	if ((isu_first + mpic->isu_size) > mpic->num_sources)
		mpic->num_sources = isu_first + mpic->isu_size;
}

1263 1264 1265 1266 1267 1268
void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
{
	mpic->senses = senses;
	mpic->senses_count = count;
}

1269 1270 1271
void __init mpic_init(struct mpic *mpic)
{
	int i;
1272
	int cpu;
1273 1274 1275 1276 1277 1278

	BUG_ON(mpic->num_sources == 0);

	printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);

	/* Set current processor priority to max */
1279
	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1280 1281 1282 1283

	/* Initialize timers: just disable them all */
	for (i = 0; i < 4; i++) {
		mpic_write(mpic->tmregs,
1284 1285
			   i * MPIC_INFO(TIMER_STRIDE) +
			   MPIC_INFO(TIMER_DESTINATION), 0);
1286
		mpic_write(mpic->tmregs,
1287 1288
			   i * MPIC_INFO(TIMER_STRIDE) +
			   MPIC_INFO(TIMER_VECTOR_PRI),
1289
			   MPIC_VECPRI_MASK |
1290
			   (mpic->timer_vecs[0] + i));
1291 1292 1293 1294 1295 1296 1297 1298
	}

	/* Initialize IPIs to our reserved vectors and mark them disabled for now */
	mpic_test_broken_ipi(mpic);
	for (i = 0; i < 4; i++) {
		mpic_ipi_write(i,
			       MPIC_VECPRI_MASK |
			       (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1299
			       (mpic->ipi_vecs[0] + i));
1300 1301 1302 1303 1304 1305
	}

	/* Initialize interrupt sources */
	if (mpic->irq_count == 0)
		mpic->irq_count = mpic->num_sources;

1306
	/* Do the HT PIC fixups on U3 broken mpic */
1307
	DBG("MPIC flags: %x\n", mpic->flags);
1308
	if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) {
1309
		mpic_scan_ht_pics(mpic);
1310 1311
		mpic_u3msi_init(mpic);
	}
1312

1313 1314
	mpic_pasemi_msi_init(mpic);

1315 1316 1317 1318 1319
	if (mpic->flags & MPIC_PRIMARY)
		cpu = hard_smp_processor_id();
	else
		cpu = 0;

1320 1321
	for (i = 0; i < mpic->num_sources; i++) {
		/* start with vector = source number, and masked */
1322 1323
		u32 vecpri = MPIC_VECPRI_MASK | i |
			(8 << MPIC_VECPRI_PRIORITY_SHIFT);
1324
		
1325 1326 1327
		/* check if protected */
		if (mpic->protected && test_bit(i, mpic->protected))
			continue;
1328
		/* init hw */
1329
		mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1330
		mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1331 1332
	}
	
1333 1334
	/* Init spurious vector */
	mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1335

1336 1337 1338 1339 1340
	/* Disable 8259 passthrough, if supported */
	if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
			   | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1341

1342 1343 1344 1345 1346
	if (mpic->flags & MPIC_NO_BIAS)
		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
			mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
			| MPIC_GREG_GCONF_NO_BIAS);

1347
	/* Set current processor priority to 0 */
1348
	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1349 1350 1351 1352 1353 1354

#ifdef CONFIG_PM
	/* allocate memory to save mpic state */
	mpic->save_data = alloc_bootmem(mpic->num_sources * sizeof(struct mpic_irq_save));
	BUG_ON(mpic->save_data == NULL);
#endif
1355 1356
}

1357 1358 1359 1360 1361 1362 1363 1364 1365
void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
{
	u32 v;

	v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
	v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
	v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
	mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
}
1366

1367 1368
void __init mpic_set_serial_int(struct mpic *mpic, int enable)
{
1369
	unsigned long flags;
1370 1371
	u32 v;

1372
	spin_lock_irqsave(&mpic_lock, flags);
1373 1374 1375 1376 1377 1378
	v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
	if (enable)
		v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
	else
		v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
	mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1379
	spin_unlock_irqrestore(&mpic_lock, flags);
1380
}
1381 1382 1383

void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
{
1384
	unsigned int is_ipi;
1385
	struct mpic *mpic = mpic_find(irq, &is_ipi);
1386
	unsigned int src = mpic_irq_to_hw(irq);
1387 1388 1389
	unsigned long flags;
	u32 reg;

1390 1391 1392
	if (!mpic)
		return;

1393 1394
	spin_lock_irqsave(&mpic_lock, flags);
	if (is_ipi) {
1395
		reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1396
			~MPIC_VECPRI_PRIORITY_MASK;
1397
		mpic_ipi_write(src - mpic->ipi_vecs[0],
1398 1399
			       reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
	} else {
1400
		reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1401
			& ~MPIC_VECPRI_PRIORITY_MASK;
1402
		mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424
			       reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
	}
	spin_unlock_irqrestore(&mpic_lock, flags);
}

void mpic_setup_this_cpu(void)
{
#ifdef CONFIG_SMP
	struct mpic *mpic = mpic_primary;
	unsigned long flags;
	u32 msk = 1 << hard_smp_processor_id();
	unsigned int i;

	BUG_ON(mpic == NULL);

	DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());

	spin_lock_irqsave(&mpic_lock, flags);

 	/* let the mpic know we want intrs. default affinity is 0xffffffff
	 * until changed via /proc. That's how it's done on x86. If we want
	 * it differently, then we should make sure we also change the default
1425
	 * values of irq_desc[].affinity in irq.c.
1426 1427 1428
 	 */
	if (distribute_irqs) {
	 	for (i = 0; i < mpic->num_sources ; i++)
1429 1430
			mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
				mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1431 1432 1433
	}

	/* Set current processor priority to 0 */
1434
	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1435 1436 1437 1438 1439 1440 1441 1442 1443

	spin_unlock_irqrestore(&mpic_lock, flags);
#endif /* CONFIG_SMP */
}

int mpic_cpu_get_priority(void)
{
	struct mpic *mpic = mpic_primary;

1444
	return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1445 1446 1447 1448 1449 1450 1451
}

void mpic_cpu_set_priority(int prio)
{
	struct mpic *mpic = mpic_primary;

	prio &= MPIC_CPU_TASKPRI_MASK;
1452
	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468
}

void mpic_teardown_this_cpu(int secondary)
{
	struct mpic *mpic = mpic_primary;
	unsigned long flags;
	u32 msk = 1 << hard_smp_processor_id();
	unsigned int i;

	BUG_ON(mpic == NULL);

	DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
	spin_lock_irqsave(&mpic_lock, flags);

	/* let the mpic know we don't want intrs.  */
	for (i = 0; i < mpic->num_sources ; i++)
1469 1470
		mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
			mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1471 1472

	/* Set current processor priority to max */
1473
	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1474 1475 1476 1477
	/* We need to EOI the IPI since not all platforms reset the MPIC
	 * on boot and new interrupts wouldn't get delivered otherwise.
	 */
	mpic_eoi(mpic);
1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488

	spin_unlock_irqrestore(&mpic_lock, flags);
}


void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask)
{
	struct mpic *mpic = mpic_primary;

	BUG_ON(mpic == NULL);

1489
#ifdef DEBUG_IPI
1490
	DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
1491
#endif
1492

1493 1494
	mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
		       ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
1495 1496 1497
		       mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
}

1498
static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1499
{
1500
	u32 src;
1501

1502
	src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1503
#ifdef DEBUG_LOW
1504
	DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1505
#endif
1506 1507 1508
	if (unlikely(src == mpic->spurious_vec)) {
		if (mpic->flags & MPIC_SPV_EOI)
			mpic_eoi(mpic);
1509
		return NO_IRQ;
1510
	}
1511 1512 1513 1514 1515 1516 1517 1518
	if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
		if (printk_ratelimit())
			printk(KERN_WARNING "%s: Got protected source %d !\n",
			       mpic->name, (int)src);
		mpic_eoi(mpic);
		return NO_IRQ;
	}

1519
	return irq_linear_revmap(mpic->irqhost, src);
1520 1521
}

1522 1523 1524 1525 1526
unsigned int mpic_get_one_irq(struct mpic *mpic)
{
	return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
}

O
Olaf Hering 已提交
1527
unsigned int mpic_get_irq(void)
1528 1529 1530 1531 1532
{
	struct mpic *mpic = mpic_primary;

	BUG_ON(mpic == NULL);

O
Olaf Hering 已提交
1533
	return mpic_get_one_irq(mpic);
1534 1535
}

1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563
unsigned int mpic_get_coreint_irq(void)
{
#ifdef CONFIG_BOOKE
	struct mpic *mpic = mpic_primary;
	u32 src;

	BUG_ON(mpic == NULL);

	src = mfspr(SPRN_EPR);

	if (unlikely(src == mpic->spurious_vec)) {
		if (mpic->flags & MPIC_SPV_EOI)
			mpic_eoi(mpic);
		return NO_IRQ;
	}
	if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
		if (printk_ratelimit())
			printk(KERN_WARNING "%s: Got protected source %d !\n",
			       mpic->name, (int)src);
		return NO_IRQ;
	}

	return irq_linear_revmap(mpic->irqhost, src);
#else
	return NO_IRQ;
#endif
}

1564 1565 1566 1567 1568 1569 1570 1571
unsigned int mpic_get_mcirq(void)
{
	struct mpic *mpic = mpic_primary;

	BUG_ON(mpic == NULL);

	return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
}
1572 1573 1574 1575 1576

#ifdef CONFIG_SMP
void mpic_request_ipis(void)
{
	struct mpic *mpic = mpic_primary;
1577
	int i;
1578 1579
	BUG_ON(mpic == NULL);

1580 1581 1582 1583
	printk(KERN_INFO "mpic: requesting IPIs ... \n");

	for (i = 0; i < 4; i++) {
		unsigned int vipi = irq_create_mapping(mpic->irqhost,
1584
						       mpic->ipi_vecs[0] + i);
1585
		if (vipi == NO_IRQ) {
1586 1587
			printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
			continue;
1588
		}
1589
		smp_request_message_ipi(vipi, i);
1590
	}
1591
}
1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612

void smp_mpic_message_pass(int target, int msg)
{
	/* make sure we're sending something that translates to an IPI */
	if ((unsigned int)msg > 3) {
		printk("SMP %d: smp_message_pass: unknown msg %d\n",
		       smp_processor_id(), msg);
		return;
	}
	switch (target) {
	case MSG_ALL:
		mpic_send_ipi(msg, 0xffffffff);
		break;
	case MSG_ALL_BUT_SELF:
		mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id()));
		break;
	default:
		mpic_send_ipi(msg, 1 << target);
		break;
	}
}
1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633

int __init smp_mpic_probe(void)
{
	int nr_cpus;

	DBG("smp_mpic_probe()...\n");

	nr_cpus = cpus_weight(cpu_possible_map);

	DBG("nr_cpus: %d\n", nr_cpus);

	if (nr_cpus > 1)
		mpic_request_ipis();

	return nr_cpus;
}

void __devinit smp_mpic_setup_cpu(int cpu)
{
	mpic_setup_this_cpu();
}
1634
#endif /* CONFIG_SMP */
1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690

#ifdef CONFIG_PM
static int mpic_suspend(struct sys_device *dev, pm_message_t state)
{
	struct mpic *mpic = container_of(dev, struct mpic, sysdev);
	int i;

	for (i = 0; i < mpic->num_sources; i++) {
		mpic->save_data[i].vecprio =
			mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
		mpic->save_data[i].dest =
			mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
	}

	return 0;
}

static int mpic_resume(struct sys_device *dev)
{
	struct mpic *mpic = container_of(dev, struct mpic, sysdev);
	int i;

	for (i = 0; i < mpic->num_sources; i++) {
		mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
			       mpic->save_data[i].vecprio);
		mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
			       mpic->save_data[i].dest);

#ifdef CONFIG_MPIC_U3_HT_IRQS
	{
		struct mpic_irq_fixup *fixup = &mpic->fixups[i];

		if (fixup->base) {
			/* we use the lowest bit in an inverted meaning */
			if ((mpic->save_data[i].fixup_data & 1) == 0)
				continue;

			/* Enable and configure */
			writeb(0x10 + 2 * fixup->index, fixup->base + 2);

			writel(mpic->save_data[i].fixup_data & ~1,
			       fixup->base + 4);
		}
	}
#endif
	} /* end for loop */

	return 0;
}
#endif

static struct sysdev_class mpic_sysclass = {
#ifdef CONFIG_PM
	.resume = mpic_resume,
	.suspend = mpic_suspend,
#endif
1691
	.name = "mpic",
1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710
};

static int mpic_init_sys(void)
{
	struct mpic *mpic = mpics;
	int error, id = 0;

	error = sysdev_class_register(&mpic_sysclass);

	while (mpic && !error) {
		mpic->sysdev.cls = &mpic_sysclass;
		mpic->sysdev.id = id++;
		error = sysdev_register(&mpic->sysdev);
		mpic = mpic->next;
	}
	return error;
}

device_initcall(mpic_init_sys);