mpic.c 45.2 KB
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/*
 *  arch/powerpc/kernel/mpic.c
 *
 *  Driver for interrupt controllers following the OpenPIC standard, the
 *  common implementation beeing IBM's MPIC. This driver also can deal
 *  with various broken implementations of this HW.
 *
 *  Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
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 *  Copyright 2010-2011 Freescale Semiconductor, Inc.
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 *
 *  This file is subject to the terms and conditions of the GNU General Public
 *  License.  See the file COPYING in the main directory of this archive
 *  for more details.
 */

#undef DEBUG
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#undef DEBUG_IPI
#undef DEBUG_IRQ
#undef DEBUG_LOW
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#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/smp.h>
#include <linux/interrupt.h>
#include <linux/bootmem.h>
#include <linux/spinlock.h>
#include <linux/pci.h>
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#include <linux/slab.h>
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#include <asm/ptrace.h>
#include <asm/signal.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/irq.h>
#include <asm/machdep.h>
#include <asm/mpic.h>
#include <asm/smp.h>

M
Michael Ellerman 已提交
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#include "mpic.h"

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#ifdef DEBUG
#define DBG(fmt...) printk(fmt)
#else
#define DBG(fmt...)
#endif

static struct mpic *mpics;
static struct mpic *mpic_primary;
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static DEFINE_RAW_SPINLOCK(mpic_lock);
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#ifdef CONFIG_PPC32	/* XXX for now */
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#ifdef CONFIG_IRQ_ALL_CPUS
#define distribute_irqs	(1)
#else
#define distribute_irqs	(0)
#endif
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#endif
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#ifdef CONFIG_MPIC_WEIRD
static u32 mpic_infos[][MPIC_IDX_END] = {
	[0] = {	/* Original OpenPIC compatible MPIC */
		MPIC_GREG_BASE,
		MPIC_GREG_FEATURE_0,
		MPIC_GREG_GLOBAL_CONF_0,
		MPIC_GREG_VENDOR_ID,
		MPIC_GREG_IPI_VECTOR_PRI_0,
		MPIC_GREG_IPI_STRIDE,
		MPIC_GREG_SPURIOUS,
		MPIC_GREG_TIMER_FREQ,

		MPIC_TIMER_BASE,
		MPIC_TIMER_STRIDE,
		MPIC_TIMER_CURRENT_CNT,
		MPIC_TIMER_BASE_CNT,
		MPIC_TIMER_VECTOR_PRI,
		MPIC_TIMER_DESTINATION,

		MPIC_CPU_BASE,
		MPIC_CPU_STRIDE,
		MPIC_CPU_IPI_DISPATCH_0,
		MPIC_CPU_IPI_DISPATCH_STRIDE,
		MPIC_CPU_CURRENT_TASK_PRI,
		MPIC_CPU_WHOAMI,
		MPIC_CPU_INTACK,
		MPIC_CPU_EOI,
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		MPIC_CPU_MCACK,
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		MPIC_IRQ_BASE,
		MPIC_IRQ_STRIDE,
		MPIC_IRQ_VECTOR_PRI,
		MPIC_VECPRI_VECTOR_MASK,
		MPIC_VECPRI_POLARITY_POSITIVE,
		MPIC_VECPRI_POLARITY_NEGATIVE,
		MPIC_VECPRI_SENSE_LEVEL,
		MPIC_VECPRI_SENSE_EDGE,
		MPIC_VECPRI_POLARITY_MASK,
		MPIC_VECPRI_SENSE_MASK,
		MPIC_IRQ_DESTINATION
	},
	[1] = {	/* Tsi108/109 PIC */
		TSI108_GREG_BASE,
		TSI108_GREG_FEATURE_0,
		TSI108_GREG_GLOBAL_CONF_0,
		TSI108_GREG_VENDOR_ID,
		TSI108_GREG_IPI_VECTOR_PRI_0,
		TSI108_GREG_IPI_STRIDE,
		TSI108_GREG_SPURIOUS,
		TSI108_GREG_TIMER_FREQ,

		TSI108_TIMER_BASE,
		TSI108_TIMER_STRIDE,
		TSI108_TIMER_CURRENT_CNT,
		TSI108_TIMER_BASE_CNT,
		TSI108_TIMER_VECTOR_PRI,
		TSI108_TIMER_DESTINATION,

		TSI108_CPU_BASE,
		TSI108_CPU_STRIDE,
		TSI108_CPU_IPI_DISPATCH_0,
		TSI108_CPU_IPI_DISPATCH_STRIDE,
		TSI108_CPU_CURRENT_TASK_PRI,
		TSI108_CPU_WHOAMI,
		TSI108_CPU_INTACK,
		TSI108_CPU_EOI,
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		TSI108_CPU_MCACK,
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		TSI108_IRQ_BASE,
		TSI108_IRQ_STRIDE,
		TSI108_IRQ_VECTOR_PRI,
		TSI108_VECPRI_VECTOR_MASK,
		TSI108_VECPRI_POLARITY_POSITIVE,
		TSI108_VECPRI_POLARITY_NEGATIVE,
		TSI108_VECPRI_SENSE_LEVEL,
		TSI108_VECPRI_SENSE_EDGE,
		TSI108_VECPRI_POLARITY_MASK,
		TSI108_VECPRI_SENSE_MASK,
		TSI108_IRQ_DESTINATION
	},
};

#define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]

#else /* CONFIG_MPIC_WEIRD */

#define MPIC_INFO(name) MPIC_##name

#endif /* CONFIG_MPIC_WEIRD */

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static inline unsigned int mpic_processor_id(struct mpic *mpic)
{
	unsigned int cpu = 0;

	if (mpic->flags & MPIC_PRIMARY)
		cpu = hard_smp_processor_id();

	return cpu;
}

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/*
 * Register accessor functions
 */


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static inline u32 _mpic_read(enum mpic_reg_type type,
			     struct mpic_reg_bank *rb,
			     unsigned int reg)
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{
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	switch(type) {
#ifdef CONFIG_PPC_DCR
	case mpic_access_dcr:
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		return dcr_read(rb->dhost, reg);
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#endif
	case mpic_access_mmio_be:
		return in_be32(rb->base + (reg >> 2));
	case mpic_access_mmio_le:
	default:
		return in_le32(rb->base + (reg >> 2));
	}
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}

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static inline void _mpic_write(enum mpic_reg_type type,
			       struct mpic_reg_bank *rb,
 			       unsigned int reg, u32 value)
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{
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	switch(type) {
#ifdef CONFIG_PPC_DCR
	case mpic_access_dcr:
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		dcr_write(rb->dhost, reg, value);
		break;
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#endif
	case mpic_access_mmio_be:
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		out_be32(rb->base + (reg >> 2), value);
		break;
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	case mpic_access_mmio_le:
	default:
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		out_le32(rb->base + (reg >> 2), value);
		break;
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	}
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}

static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
{
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	enum mpic_reg_type type = mpic->reg_type;
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	unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
			      (ipi * MPIC_INFO(GREG_IPI_STRIDE));
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	if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
		type = mpic_access_mmio_be;
	return _mpic_read(type, &mpic->gregs, offset);
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}

static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
{
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	unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
			      (ipi * MPIC_INFO(GREG_IPI_STRIDE));
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	_mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
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}

static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
{
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	unsigned int cpu = mpic_processor_id(mpic);
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	return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
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}

static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
{
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	unsigned int cpu = mpic_processor_id(mpic);
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	_mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
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}

static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
{
	unsigned int	isu = src_no >> mpic->isu_shift;
	unsigned int	idx = src_no & mpic->isu_mask;
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	unsigned int	val;
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	val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
			 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
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#ifdef CONFIG_MPIC_BROKEN_REGREAD
	if (reg == 0)
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		val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
			mpic->isu_reg0_shadow[src_no];
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#endif
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	return val;
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}

static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
				   unsigned int reg, u32 value)
{
	unsigned int	isu = src_no >> mpic->isu_shift;
	unsigned int	idx = src_no & mpic->isu_mask;

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	_mpic_write(mpic->reg_type, &mpic->isus[isu],
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		    reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
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#ifdef CONFIG_MPIC_BROKEN_REGREAD
	if (reg == 0)
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		mpic->isu_reg0_shadow[src_no] =
			value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
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#endif
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}

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#define mpic_read(b,r)		_mpic_read(mpic->reg_type,&(b),(r))
#define mpic_write(b,r,v)	_mpic_write(mpic->reg_type,&(b),(r),(v))
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#define mpic_ipi_read(i)	_mpic_ipi_read(mpic,(i))
#define mpic_ipi_write(i,v)	_mpic_ipi_write(mpic,(i),(v))
#define mpic_cpu_read(i)	_mpic_cpu_read(mpic,(i))
#define mpic_cpu_write(i,v)	_mpic_cpu_write(mpic,(i),(v))
#define mpic_irq_read(s,r)	_mpic_irq_read(mpic,(s),(r))
#define mpic_irq_write(s,r,v)	_mpic_irq_write(mpic,(s),(r),(v))


/*
 * Low level utility functions
 */


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static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
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			   struct mpic_reg_bank *rb, unsigned int offset,
			   unsigned int size)
{
	rb->base = ioremap(phys_addr + offset, size);
	BUG_ON(rb->base == NULL);
}

#ifdef CONFIG_PPC_DCR
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static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node,
			  struct mpic_reg_bank *rb,
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			  unsigned int offset, unsigned int size)
{
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	const u32 *dbasep;

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	dbasep = of_get_property(node, "dcr-reg", NULL);
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	rb->dhost = dcr_map(node, *dbasep + offset, size);
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	BUG_ON(!DCR_MAP_OK(rb->dhost));
}

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static inline void mpic_map(struct mpic *mpic, struct device_node *node,
			    phys_addr_t phys_addr, struct mpic_reg_bank *rb,
			    unsigned int offset, unsigned int size)
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{
	if (mpic->flags & MPIC_USES_DCR)
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		_mpic_map_dcr(mpic, node, rb, offset, size);
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	else
		_mpic_map_mmio(mpic, phys_addr, rb, offset, size);
}
#else /* CONFIG_PPC_DCR */
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#define mpic_map(m,n,p,b,o,s)	_mpic_map_mmio(m,p,b,o,s)
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#endif /* !CONFIG_PPC_DCR */


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/* Check if we have one of those nice broken MPICs with a flipped endian on
 * reads from IPI registers
 */
static void __init mpic_test_broken_ipi(struct mpic *mpic)
{
	u32 r;

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	mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
	r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
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	if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
		printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
		mpic->flags |= MPIC_BROKEN_IPI;
	}
}

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#ifdef CONFIG_MPIC_U3_HT_IRQS
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/* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
 * to force the edge setting on the MPIC and do the ack workaround.
 */
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static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
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{
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	if (source >= 128 || !mpic->fixups)
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		return 0;
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	return mpic->fixups[source].base != NULL;
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}

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static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
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{
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	struct mpic_irq_fixup *fixup = &mpic->fixups[source];
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	if (fixup->applebase) {
		unsigned int soff = (fixup->index >> 3) & ~3;
		unsigned int mask = 1U << (fixup->index & 0x1f);
		writel(mask, fixup->applebase + soff);
	} else {
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		raw_spin_lock(&mpic->fixup_lock);
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		writeb(0x11 + 2 * fixup->index, fixup->base + 2);
		writel(fixup->data, fixup->base + 4);
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		raw_spin_unlock(&mpic->fixup_lock);
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	}
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}

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static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
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				      bool level)
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{
	struct mpic_irq_fixup *fixup = &mpic->fixups[source];
	unsigned long flags;
	u32 tmp;

	if (fixup->base == NULL)
		return;

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	DBG("startup_ht_interrupt(0x%x) index: %d\n",
	    source, fixup->index);
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	raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
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	/* Enable and configure */
	writeb(0x10 + 2 * fixup->index, fixup->base + 2);
	tmp = readl(fixup->base + 4);
	tmp &= ~(0x23U);
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	if (level)
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		tmp |= 0x22;
	writel(tmp, fixup->base + 4);
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	raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
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#ifdef CONFIG_PM
	/* use the lowest bit inverted to the actual HW,
	 * set if this fixup was enabled, clear otherwise */
	mpic->save_data[source].fixup_data = tmp | 1;
#endif
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}

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static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
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{
	struct mpic_irq_fixup *fixup = &mpic->fixups[source];
	unsigned long flags;
	u32 tmp;

	if (fixup->base == NULL)
		return;

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	DBG("shutdown_ht_interrupt(0x%x)\n", source);
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	/* Disable */
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	raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
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	writeb(0x10 + 2 * fixup->index, fixup->base + 2);
	tmp = readl(fixup->base + 4);
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	tmp |= 1;
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	writel(tmp, fixup->base + 4);
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	raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
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#ifdef CONFIG_PM
	/* use the lowest bit inverted to the actual HW,
	 * set if this fixup was enabled, clear otherwise */
	mpic->save_data[source].fixup_data = tmp & ~1;
#endif
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}
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#ifdef CONFIG_PCI_MSI
static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
				    unsigned int devfn)
{
	u8 __iomem *base;
	u8 pos, flags;
	u64 addr = 0;

	for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
	     pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
		u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
		if (id == PCI_CAP_ID_HT) {
			id = readb(devbase + pos + 3);
			if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
				break;
		}
	}

	if (pos == 0)
		return;

	base = devbase + pos;

	flags = readb(base + HT_MSI_FLAGS);
	if (!(flags & HT_MSI_FLAGS_FIXED)) {
		addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
		addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
	}

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	printk(KERN_DEBUG "mpic:   - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
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		PCI_SLOT(devfn), PCI_FUNC(devfn),
		flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);

	if (!(flags & HT_MSI_FLAGS_ENABLE))
		writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
}
#else
static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
				    unsigned int devfn)
{
	return;
}
#endif

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static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
				    unsigned int devfn, u32 vdid)
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{
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	int i, irq, n;
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	u8 __iomem *base;
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	u32 tmp;
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	u8 pos;
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	for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
	     pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
		u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
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		if (id == PCI_CAP_ID_HT) {
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			id = readb(devbase + pos + 3);
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			if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
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				break;
		}
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	}
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	if (pos == 0)
		return;

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	base = devbase + pos;
	writeb(0x01, base + 2);
	n = (readl(base + 4) >> 16) & 0xff;
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	printk(KERN_INFO "mpic:   - HT:%02x.%x [0x%02x] vendor %04x device %04x"
	       " has %d irqs\n",
	       devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
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	for (i = 0; i <= n; i++) {
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		writeb(0x10 + 2 * i, base + 2);
		tmp = readl(base + 4);
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		irq = (tmp >> 16) & 0xff;
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		DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
		/* mask it , will be unmasked later */
		tmp |= 0x1;
		writel(tmp, base + 4);
		mpic->fixups[irq].index = i;
		mpic->fixups[irq].base = base;
		/* Apple HT PIC has a non-standard way of doing EOIs */
		if ((vdid & 0xffff) == 0x106b)
			mpic->fixups[irq].applebase = devbase + 0x60;
		else
			mpic->fixups[irq].applebase = NULL;
		writeb(0x11 + 2 * i, base + 2);
		mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
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	}
}
 
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static void __init mpic_scan_ht_pics(struct mpic *mpic)
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{
	unsigned int devfn;
	u8 __iomem *cfgspace;

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	printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
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	/* Allocate fixups array */
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	mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL);
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	BUG_ON(mpic->fixups == NULL);

	/* Init spinlock */
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	raw_spin_lock_init(&mpic->fixup_lock);
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	/* Map U3 config space. We assume all IO-APICs are on the primary bus
	 * so we only need to map 64kB.
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	 */
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	cfgspace = ioremap(0xf2000000, 0x10000);
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	BUG_ON(cfgspace == NULL);

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	/* Now we scan all slots. We do a very quick scan, we read the header
	 * type, vendor ID and device ID only, that's plenty enough
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	 */
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	for (devfn = 0; devfn < 0x100; devfn++) {
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		u8 __iomem *devbase = cfgspace + (devfn << 8);
		u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
		u32 l = readl(devbase + PCI_VENDOR_ID);
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		u16 s;
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		DBG("devfn %x, l: %x\n", devfn, l);

		/* If no device, skip */
		if (l == 0xffffffff || l == 0x00000000 ||
		    l == 0x0000ffff || l == 0xffff0000)
			goto next;
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		/* Check if is supports capability lists */
		s = readw(devbase + PCI_STATUS);
		if (!(s & PCI_STATUS_CAP_LIST))
			goto next;
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		mpic_scan_ht_pic(mpic, devbase, devfn, l);
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		mpic_scan_ht_msi(mpic, devbase, devfn);
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	next:
		/* next device, if function 0 */
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		if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
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			devfn += 7;
	}
}

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#else /* CONFIG_MPIC_U3_HT_IRQS */
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static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
{
	return 0;
}

static void __init mpic_scan_ht_pics(struct mpic *mpic)
{
}

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#endif /* CONFIG_MPIC_U3_HT_IRQS */
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#ifdef CONFIG_SMP
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static int irq_choose_cpu(const struct cpumask *mask)
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{
	int cpuid;

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	if (cpumask_equal(mask, cpu_all_mask)) {
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		static int irq_rover = 0;
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		static DEFINE_RAW_SPINLOCK(irq_rover_lock);
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		unsigned long flags;

		/* Round-robin distribution... */
	do_round_robin:
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		raw_spin_lock_irqsave(&irq_rover_lock, flags);
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		irq_rover = cpumask_next(irq_rover, cpu_online_mask);
		if (irq_rover >= nr_cpu_ids)
			irq_rover = cpumask_first(cpu_online_mask);

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		cpuid = irq_rover;

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		raw_spin_unlock_irqrestore(&irq_rover_lock, flags);
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	} else {
597 598
		cpuid = cpumask_first_and(mask, cpu_online_mask);
		if (cpuid >= nr_cpu_ids)
599 600 601
			goto do_round_robin;
	}

602
	return get_hard_smp_processor_id(cpuid);
603 604
}
#else
605
static int irq_choose_cpu(const struct cpumask *mask)
606 607 608 609
{
	return hard_smp_processor_id();
}
#endif
610 611

/* Find an mpic associated with a given linux interrupt */
612
static struct mpic *mpic_find(unsigned int irq)
613
{
614 615
	if (irq < NUM_ISA_INTERRUPTS)
		return NULL;
616

617
	return irq_get_chip_data(irq);
618
}
619

620 621 622
/* Determine if the linux irq is an IPI */
static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
{
623
	unsigned int src = virq_to_hw(irq);
624

625
	return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
626 627
}

628

629 630 631 632 633 634 635 636 637 638 639 640 641
/* Convert a cpu mask from logical to physical cpu numbers. */
static inline u32 mpic_physmask(u32 cpumask)
{
	int i;
	u32 mask = 0;

	for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
		mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
	return mask;
}

#ifdef CONFIG_SMP
/* Get the mpic structure from the IPI number */
642
static inline struct mpic * mpic_from_ipi(struct irq_data *d)
643
{
644
	return irq_data_get_irq_chip_data(d);
645 646 647 648 649 650
}
#endif

/* Get the mpic structure from the irq number */
static inline struct mpic * mpic_from_irq(unsigned int irq)
{
651
	return irq_get_chip_data(irq);
652 653 654 655 656 657
}

/* Get the mpic structure from the irq data */
static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
{
	return irq_data_get_irq_chip_data(d);
658 659 660 661 662
}

/* Send an EOI */
static inline void mpic_eoi(struct mpic *mpic)
{
663 664
	mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
	(void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
665 666 667 668 669 670 671
}

/*
 * Linux descriptor level callbacks
 */


672
void mpic_unmask_irq(struct irq_data *d)
673 674
{
	unsigned int loops = 100000;
675
	struct mpic *mpic = mpic_from_irq_data(d);
676
	unsigned int src = irqd_to_hwirq(d);
677

678
	DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
679

680 681
	mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
		       mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
682
		       ~MPIC_VECPRI_MASK);
683 684 685
	/* make sure mask gets to controller before we return to user */
	do {
		if (!loops--) {
686 687
			printk(KERN_ERR "%s: timeout on hwirq %u\n",
			       __func__, src);
688 689
			break;
		}
690
	} while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
691 692
}

693
void mpic_mask_irq(struct irq_data *d)
694 695
{
	unsigned int loops = 100000;
696
	struct mpic *mpic = mpic_from_irq_data(d);
697
	unsigned int src = irqd_to_hwirq(d);
698

699
	DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
700

701 702
	mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
		       mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
703
		       MPIC_VECPRI_MASK);
704 705 706 707

	/* make sure mask gets to controller before we return to user */
	do {
		if (!loops--) {
708 709
			printk(KERN_ERR "%s: timeout on hwirq %u\n",
			       __func__, src);
710 711
			break;
		}
712
	} while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
713 714
}

715
void mpic_end_irq(struct irq_data *d)
716
{
717
	struct mpic *mpic = mpic_from_irq_data(d);
718 719

#ifdef DEBUG_IRQ
720
	DBG("%s: end_irq: %d\n", mpic->name, d->irq);
721 722 723 724 725 726 727 728 729
#endif
	/* We always EOI on end_irq() even for edge interrupts since that
	 * should only lower the priority, the MPIC should have properly
	 * latched another edge interrupt coming in anyway
	 */

	mpic_eoi(mpic);
}

730
#ifdef CONFIG_MPIC_U3_HT_IRQS
731

732
static void mpic_unmask_ht_irq(struct irq_data *d)
733
{
734
	struct mpic *mpic = mpic_from_irq_data(d);
735
	unsigned int src = irqd_to_hwirq(d);
736

737
	mpic_unmask_irq(d);
738

739
	if (irqd_is_level_type(d))
740 741 742
		mpic_ht_end_irq(mpic, src);
}

743
static unsigned int mpic_startup_ht_irq(struct irq_data *d)
744
{
745
	struct mpic *mpic = mpic_from_irq_data(d);
746
	unsigned int src = irqd_to_hwirq(d);
747

748
	mpic_unmask_irq(d);
749
	mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
750 751

	return 0;
752 753
}

754
static void mpic_shutdown_ht_irq(struct irq_data *d)
755
{
756
	struct mpic *mpic = mpic_from_irq_data(d);
757
	unsigned int src = irqd_to_hwirq(d);
758

759
	mpic_shutdown_ht_interrupt(mpic, src);
760
	mpic_mask_irq(d);
761 762
}

763
static void mpic_end_ht_irq(struct irq_data *d)
764
{
765
	struct mpic *mpic = mpic_from_irq_data(d);
766
	unsigned int src = irqd_to_hwirq(d);
767

768
#ifdef DEBUG_IRQ
769
	DBG("%s: end_irq: %d\n", mpic->name, d->irq);
770
#endif
771 772 773 774 775
	/* We always EOI on end_irq() even for edge interrupts since that
	 * should only lower the priority, the MPIC should have properly
	 * latched another edge interrupt coming in anyway
	 */

776
	if (irqd_is_level_type(d))
777
		mpic_ht_end_irq(mpic, src);
778 779
	mpic_eoi(mpic);
}
780
#endif /* !CONFIG_MPIC_U3_HT_IRQS */
781

782 783
#ifdef CONFIG_SMP

784
static void mpic_unmask_ipi(struct irq_data *d)
785
{
786
	struct mpic *mpic = mpic_from_ipi(d);
787
	unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0];
788

789
	DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
790 791 792
	mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
}

793
static void mpic_mask_ipi(struct irq_data *d)
794 795 796 797
{
	/* NEVER disable an IPI... that's just plain wrong! */
}

798
static void mpic_end_ipi(struct irq_data *d)
799
{
800
	struct mpic *mpic = mpic_from_ipi(d);
801 802 803 804 805

	/*
	 * IPIs are marked IRQ_PER_CPU. This has the side effect of
	 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
	 * applying to them. We EOI them late to avoid re-entering.
806
	 * We mark IPI's with IRQF_DISABLED as they must run with
807 808 809 810 811 812 813
	 * irqs disabled.
	 */
	mpic_eoi(mpic);
}

#endif /* CONFIG_SMP */

814 815
int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
		      bool force)
816
{
817
	struct mpic *mpic = mpic_from_irq_data(d);
818
	unsigned int src = irqd_to_hwirq(d);
819

820
	if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
821
		int cpuid = irq_choose_cpu(cpumask);
822

823 824
		mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
	} else {
825
		cpumask_var_t tmp;
826

827 828 829
		alloc_cpumask_var(&tmp, GFP_KERNEL);

		cpumask_and(tmp, cpumask, cpu_online_mask);
830 831

		mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
832 833 834
			       mpic_physmask(cpumask_bits(tmp)[0]));

		free_cpumask_var(tmp);
835
	}
836 837

	return 0;
838 839
}

840
static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
841 842
{
	/* Now convert sense value */
843
	switch(type & IRQ_TYPE_SENSE_MASK) {
844
	case IRQ_TYPE_EDGE_RISING:
845 846
		return MPIC_INFO(VECPRI_SENSE_EDGE) |
		       MPIC_INFO(VECPRI_POLARITY_POSITIVE);
847
	case IRQ_TYPE_EDGE_FALLING:
848
	case IRQ_TYPE_EDGE_BOTH:
849 850
		return MPIC_INFO(VECPRI_SENSE_EDGE) |
		       MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
851
	case IRQ_TYPE_LEVEL_HIGH:
852 853
		return MPIC_INFO(VECPRI_SENSE_LEVEL) |
		       MPIC_INFO(VECPRI_POLARITY_POSITIVE);
854 855
	case IRQ_TYPE_LEVEL_LOW:
	default:
856 857
		return MPIC_INFO(VECPRI_SENSE_LEVEL) |
		       MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
858
	}
859 860
}

861
int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
862
{
863
	struct mpic *mpic = mpic_from_irq_data(d);
864
	unsigned int src = irqd_to_hwirq(d);
865 866
	unsigned int vecpri, vold, vnew;

867
	DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
868
	    mpic, d->irq, src, flow_type);
869 870 871 872 873 874 875 876 877 878

	if (src >= mpic->irq_count)
		return -EINVAL;

	if (flow_type == IRQ_TYPE_NONE)
		if (mpic->senses && src < mpic->senses_count)
			flow_type = mpic->senses[src];
	if (flow_type == IRQ_TYPE_NONE)
		flow_type = IRQ_TYPE_LEVEL_LOW;

879
	irqd_set_trigger_type(d, flow_type);
880 881 882 883 884

	if (mpic_is_ht_interrupt(mpic, src))
		vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
			MPIC_VECPRI_SENSE_EDGE;
	else
885
		vecpri = mpic_type_to_vecpri(mpic, flow_type);
886

887 888 889
	vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
	vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
			MPIC_INFO(VECPRI_SENSE_MASK));
890 891
	vnew |= vecpri;
	if (vold != vnew)
892
		mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
893

894
	return IRQ_SET_MASK_OK_NOCOPY;;
895 896
}

897 898 899
void mpic_set_vector(unsigned int virq, unsigned int vector)
{
	struct mpic *mpic = mpic_from_irq(virq);
900
	unsigned int src = virq_to_hw(virq);
901 902 903 904 905 906 907 908 909 910 911 912 913 914
	unsigned int vecpri;

	DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
	    mpic, virq, src, vector);

	if (src >= mpic->irq_count)
		return;

	vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
	vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
	vecpri |= vector;
	mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
}

915 916 917
void mpic_set_destination(unsigned int virq, unsigned int cpuid)
{
	struct mpic *mpic = mpic_from_irq(virq);
918
	unsigned int src = virq_to_hw(virq);
919 920 921 922 923 924 925 926 927 928

	DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
	    mpic, virq, src, cpuid);

	if (src >= mpic->irq_count)
		return;

	mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
}

929
static struct irq_chip mpic_irq_chip = {
930 931 932 933
	.irq_mask	= mpic_mask_irq,
	.irq_unmask	= mpic_unmask_irq,
	.irq_eoi	= mpic_end_irq,
	.irq_set_type	= mpic_set_irq_type,
934 935 936 937
};

#ifdef CONFIG_SMP
static struct irq_chip mpic_ipi_chip = {
938 939 940
	.irq_mask	= mpic_mask_ipi,
	.irq_unmask	= mpic_unmask_ipi,
	.irq_eoi	= mpic_end_ipi,
941 942 943
};
#endif /* CONFIG_SMP */

944
#ifdef CONFIG_MPIC_U3_HT_IRQS
945
static struct irq_chip mpic_irq_ht_chip = {
946 947 948 949 950 951
	.irq_startup	= mpic_startup_ht_irq,
	.irq_shutdown	= mpic_shutdown_ht_irq,
	.irq_mask	= mpic_mask_irq,
	.irq_unmask	= mpic_unmask_ht_irq,
	.irq_eoi	= mpic_end_ht_irq,
	.irq_set_type	= mpic_set_irq_type,
952
};
953
#endif /* CONFIG_MPIC_U3_HT_IRQS */
954

955

956 957 958
static int mpic_host_match(struct irq_host *h, struct device_node *node)
{
	/* Exact match, unless mpic node is NULL */
959
	return h->of_node == NULL || h->of_node == node;
960 961 962
}

static int mpic_host_map(struct irq_host *h, unsigned int virq,
963
			 irq_hw_number_t hw)
964 965
{
	struct mpic *mpic = h->host_data;
966
	struct irq_chip *chip;
967

968
	DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
969

970
	if (hw == mpic->spurious_vec)
971
		return -EINVAL;
972 973
	if (mpic->protected && test_bit(hw, mpic->protected))
		return -EINVAL;
974

975
#ifdef CONFIG_SMP
976
	else if (hw >= mpic->ipi_vecs[0]) {
977 978
		WARN_ON(!(mpic->flags & MPIC_PRIMARY));

979
		DBG("mpic: mapping as IPI\n");
980 981
		irq_set_chip_data(virq, mpic);
		irq_set_chip_and_handler(virq, &mpic->hc_ipi,
982 983 984 985 986 987 988 989
					 handle_percpu_irq);
		return 0;
	}
#endif /* CONFIG_SMP */

	if (hw >= mpic->irq_count)
		return -EINVAL;

M
Michael Ellerman 已提交
990 991
	mpic_msi_reserve_hwirq(mpic, hw);

992
	/* Default chip */
993 994
	chip = &mpic->hc_irq;

995
#ifdef CONFIG_MPIC_U3_HT_IRQS
996
	/* Check for HT interrupts, override vecpri */
997
	if (mpic_is_ht_interrupt(mpic, hw))
998
		chip = &mpic->hc_ht_irq;
999
#endif /* CONFIG_MPIC_U3_HT_IRQS */
1000

1001
	DBG("mpic: mapping to irq chip @%p\n", chip);
1002

1003 1004
	irq_set_chip_data(virq, mpic);
	irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
1005 1006

	/* Set default irq type */
1007
	irq_set_irq_type(virq, IRQ_TYPE_NONE);
1008

1009 1010 1011 1012 1013 1014
	/* If the MPIC was reset, then all vectors have already been
	 * initialized.  Otherwise, a per source lazy initialization
	 * is done here.
	 */
	if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
		mpic_set_vector(virq, hw);
1015
		mpic_set_destination(virq, mpic_processor_id(mpic));
1016 1017 1018
		mpic_irq_set_priority(virq, 8);
	}

1019 1020 1021 1022
	return 0;
}

static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
1023
			   const u32 *intspec, unsigned int intsize,
1024 1025 1026
			   irq_hw_number_t *out_hwirq, unsigned int *out_flags)

{
1027
	struct mpic *mpic = h->host_data;
1028 1029 1030 1031 1032 1033 1034 1035
	static unsigned char map_mpic_senses[4] = {
		IRQ_TYPE_EDGE_RISING,
		IRQ_TYPE_LEVEL_LOW,
		IRQ_TYPE_LEVEL_HIGH,
		IRQ_TYPE_EDGE_FALLING,
	};

	*out_hwirq = intspec[0];
1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067
	if (intsize >= 4 && (mpic->flags & MPIC_FSL)) {
		/*
		 * Freescale MPIC with extended intspec:
		 * First two cells are as usual.  Third specifies
		 * an "interrupt type".  Fourth is type-specific data.
		 *
		 * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
		 */
		switch (intspec[2]) {
		case 0:
		case 1: /* no EISR/EIMR support for now, treat as shared IRQ */
			break;
		case 2:
			if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
				return -EINVAL;

			*out_hwirq = mpic->ipi_vecs[intspec[0]];
			break;
		case 3:
			if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs))
				return -EINVAL;

			*out_hwirq = mpic->timer_vecs[intspec[0]];
			break;
		default:
			pr_debug("%s: unknown irq type %u\n",
				 __func__, intspec[2]);
			return -EINVAL;
		}

		*out_flags = map_mpic_senses[intspec[1] & 3];
	} else if (intsize > 1) {
1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083
		u32 mask = 0x3;

		/* Apple invented a new race of encoding on machines with
		 * an HT APIC. They encode, among others, the index within
		 * the HT APIC. We don't care about it here since thankfully,
		 * it appears that they have the APIC already properly
		 * configured, and thus our current fixup code that reads the
		 * APIC config works fine. However, we still need to mask out
		 * bits in the specifier to make sure we only get bit 0 which
		 * is the level/edge bit (the only sense bit exposed by Apple),
		 * as their bit 1 means something else.
		 */
		if (machine_is(powermac))
			mask = 0x1;
		*out_flags = map_mpic_senses[intspec[1] & mask];
	} else
1084 1085
		*out_flags = IRQ_TYPE_NONE;

1086 1087 1088
	DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
	    intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);

1089 1090 1091 1092 1093 1094 1095 1096 1097
	return 0;
}

static struct irq_host_ops mpic_host_ops = {
	.match = mpic_host_match,
	.map = mpic_host_map,
	.xlate = mpic_host_xlate,
};

1098 1099 1100 1101 1102
static int mpic_reset_prohibited(struct device_node *node)
{
	return node && of_get_property(node, "pic-no-reset", NULL);
}

1103 1104 1105 1106
/*
 * Exported functions
 */

1107
struct mpic * __init mpic_alloc(struct device_node *node,
1108
				phys_addr_t phys_addr,
1109 1110 1111 1112 1113 1114
				unsigned int flags,
				unsigned int isu_size,
				unsigned int irq_count,
				const char *name)
{
	struct mpic	*mpic;
1115
	u32		greg_feature;
1116 1117
	const char	*vers;
	int		i;
1118
	int		intvec_top;
1119
	u64		paddr = phys_addr;
1120

K
Kumar Gala 已提交
1121
	mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1122 1123
	if (mpic == NULL)
		return NULL;
K
Kumar Gala 已提交
1124

1125 1126
	mpic->name = name;

1127
	mpic->hc_irq = mpic_irq_chip;
1128
	mpic->hc_irq.name = name;
1129
	if (flags & MPIC_PRIMARY)
1130
		mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1131
#ifdef CONFIG_MPIC_U3_HT_IRQS
1132
	mpic->hc_ht_irq = mpic_irq_ht_chip;
1133
	mpic->hc_ht_irq.name = name;
1134
	if (flags & MPIC_PRIMARY)
1135
		mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1136
#endif /* CONFIG_MPIC_U3_HT_IRQS */
1137

1138
#ifdef CONFIG_SMP
1139
	mpic->hc_ipi = mpic_ipi_chip;
1140
	mpic->hc_ipi.name = name;
1141 1142 1143 1144 1145 1146 1147
#endif /* CONFIG_SMP */

	mpic->flags = flags;
	mpic->isu_size = isu_size;
	mpic->irq_count = irq_count;
	mpic->num_sources = 0; /* so far */

1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162
	if (flags & MPIC_LARGE_VECTORS)
		intvec_top = 2047;
	else
		intvec_top = 255;

	mpic->timer_vecs[0] = intvec_top - 8;
	mpic->timer_vecs[1] = intvec_top - 7;
	mpic->timer_vecs[2] = intvec_top - 6;
	mpic->timer_vecs[3] = intvec_top - 5;
	mpic->ipi_vecs[0]   = intvec_top - 4;
	mpic->ipi_vecs[1]   = intvec_top - 3;
	mpic->ipi_vecs[2]   = intvec_top - 2;
	mpic->ipi_vecs[3]   = intvec_top - 1;
	mpic->spurious_vec  = intvec_top;

1163
	/* Check for "big-endian" in device-tree */
1164
	if (node && of_get_property(node, "big-endian", NULL) != NULL)
1165
		mpic->flags |= MPIC_BIG_ENDIAN;
1166 1167
	if (node && of_device_is_compatible(node, "fsl,mpic"))
		mpic->flags |= MPIC_FSL;
1168

1169 1170
	/* Look for protected sources */
	if (node) {
1171 1172
		int psize;
		unsigned int bits, mapsize;
1173 1174 1175 1176 1177 1178
		const u32 *psrc =
			of_get_property(node, "protected-sources", &psize);
		if (psrc) {
			psize /= 4;
			bits = intvec_top + 1;
			mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long);
1179
			mpic->protected = kzalloc(mapsize, GFP_KERNEL);
1180 1181 1182 1183 1184 1185 1186 1187
			BUG_ON(mpic->protected == NULL);
			for (i = 0; i < psize; i++) {
				if (psrc[i] > intvec_top)
					continue;
				__set_bit(psrc[i], mpic->protected);
			}
		}
	}
1188

1189 1190 1191 1192
#ifdef CONFIG_MPIC_WEIRD
	mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
#endif

1193 1194 1195 1196
	/* default register type */
	mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?
		mpic_access_mmio_be : mpic_access_mmio_le;

1197 1198 1199 1200
	/* If no physical address is passed in, a device-node is mandatory */
	BUG_ON(paddr == 0 && node == NULL);

	/* If no physical address passed in, check if it's dcr based */
1201
	if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) {
1202
#ifdef CONFIG_PPC_DCR
1203
		mpic->flags |= MPIC_USES_DCR;
1204 1205
		mpic->reg_type = mpic_access_dcr;
#else
1206
		BUG();
1207
#endif /* CONFIG_PPC_DCR */
1208
	}
1209

1210 1211 1212 1213
	/* If the MPIC is not DCR based, and no physical address was passed
	 * in, try to obtain one
	 */
	if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
1214
		const u32 *reg = of_get_property(node, "reg", NULL);
1215 1216 1217 1218 1219
		BUG_ON(reg == NULL);
		paddr = of_translate_address(node, reg);
		BUG_ON(paddr == OF_BAD_ADDR);
	}

1220
	/* Map the global registers */
1221 1222
	mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
	mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1223 1224

	/* Reset */
1225 1226 1227 1228 1229 1230 1231 1232 1233

	/* When using a device-node, reset requests are only honored if the MPIC
	 * is allowed to reset.
	 */
	if (mpic_reset_prohibited(node))
		mpic->flags |= MPIC_NO_RESET;

	if ((flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) {
		printk(KERN_DEBUG "mpic: Resetting\n");
1234 1235
		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1236
			   | MPIC_GREG_GCONF_RESET);
1237
		while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1238 1239 1240 1241
		       & MPIC_GREG_GCONF_RESET)
			mb();
	}

1242 1243 1244 1245 1246 1247
	/* CoreInt */
	if (flags & MPIC_ENABLE_COREINT)
		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
			   | MPIC_GREG_GCONF_COREINT);

1248 1249 1250 1251 1252
	if (flags & MPIC_ENABLE_MCK)
		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
			   | MPIC_GREG_GCONF_MCK);

1253 1254 1255 1256
	/* Read feature register, calculate num CPUs and, for non-ISU
	 * MPICs, num sources as well. On ISU MPICs, sources are counted
	 * as ISUs are added
	 */
1257 1258
	greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
	mpic->num_cpus = ((greg_feature & MPIC_GREG_FEATURE_LAST_CPU_MASK)
1259
			  >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
1260
	if (isu_size == 0) {
1261 1262 1263 1264 1265 1266
		if (flags & MPIC_BROKEN_FRR_NIRQS)
			mpic->num_sources = mpic->irq_count;
		else
			mpic->num_sources =
				((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
				 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
1267
	}
1268 1269 1270

	/* Map the per-CPU registers */
	for (i = 0; i < mpic->num_cpus; i++) {
1271
		mpic_map(mpic, node, paddr, &mpic->cpuregs[i],
1272 1273
			 MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE),
			 0x1000);
1274 1275 1276 1277 1278
	}

	/* Initialize main ISU if none provided */
	if (mpic->isu_size == 0) {
		mpic->isu_size = mpic->num_sources;
1279
		mpic_map(mpic, node, paddr, &mpic->isus[0],
1280
			 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1281 1282 1283 1284
	}
	mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
	mpic->isu_mask = (1 << mpic->isu_shift) - 1;

1285 1286 1287 1288 1289 1290 1291 1292 1293
	mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
				       isu_size ? isu_size : mpic->num_sources,
				       &mpic_host_ops,
				       flags & MPIC_LARGE_VECTORS ? 2048 : 256);
	if (mpic->irqhost == NULL)
		return NULL;

	mpic->irqhost->host_data = mpic;

1294
	/* Display version */
1295
	switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308
	case 1:
		vers = "1.0";
		break;
	case 2:
		vers = "1.2";
		break;
	case 3:
		vers = "1.3";
		break;
	default:
		vers = "<unknown>";
		break;
	}
1309 1310 1311 1312 1313
	printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
	       " max %d CPUs\n",
	       name, vers, (unsigned long long)paddr, mpic->num_cpus);
	printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
	       mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1314 1315 1316 1317

	mpic->next = mpics;
	mpics = mpic;

1318
	if (flags & MPIC_PRIMARY) {
1319
		mpic_primary = mpic;
1320 1321
		irq_set_default_host(mpic->irqhost);
	}
1322 1323 1324 1325 1326

	return mpic;
}

void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1327
			    phys_addr_t paddr)
1328 1329 1330 1331 1332
{
	unsigned int isu_first = isu_num * mpic->isu_size;

	BUG_ON(isu_num >= MPIC_MAX_ISU);

1333 1334
	mpic_map(mpic, mpic->irqhost->of_node,
		 paddr, &mpic->isus[isu_num], 0,
1335
		 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1336

1337 1338 1339 1340
	if ((isu_first + mpic->isu_size) > mpic->num_sources)
		mpic->num_sources = isu_first + mpic->isu_size;
}

1341 1342 1343 1344 1345 1346
void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
{
	mpic->senses = senses;
	mpic->senses_count = count;
}

1347 1348 1349
void __init mpic_init(struct mpic *mpic)
{
	int i;
1350
	int cpu;
1351 1352 1353 1354 1355 1356

	BUG_ON(mpic->num_sources == 0);

	printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);

	/* Set current processor priority to max */
1357
	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1358 1359 1360 1361

	/* Initialize timers: just disable them all */
	for (i = 0; i < 4; i++) {
		mpic_write(mpic->tmregs,
1362 1363
			   i * MPIC_INFO(TIMER_STRIDE) +
			   MPIC_INFO(TIMER_DESTINATION), 0);
1364
		mpic_write(mpic->tmregs,
1365 1366
			   i * MPIC_INFO(TIMER_STRIDE) +
			   MPIC_INFO(TIMER_VECTOR_PRI),
1367
			   MPIC_VECPRI_MASK |
1368
			   (mpic->timer_vecs[0] + i));
1369 1370 1371 1372 1373 1374 1375 1376
	}

	/* Initialize IPIs to our reserved vectors and mark them disabled for now */
	mpic_test_broken_ipi(mpic);
	for (i = 0; i < 4; i++) {
		mpic_ipi_write(i,
			       MPIC_VECPRI_MASK |
			       (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1377
			       (mpic->ipi_vecs[0] + i));
1378 1379 1380 1381 1382 1383
	}

	/* Initialize interrupt sources */
	if (mpic->irq_count == 0)
		mpic->irq_count = mpic->num_sources;

1384
	/* Do the HT PIC fixups on U3 broken mpic */
1385
	DBG("MPIC flags: %x\n", mpic->flags);
1386
	if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) {
1387
		mpic_scan_ht_pics(mpic);
1388 1389
		mpic_u3msi_init(mpic);
	}
1390

1391 1392
	mpic_pasemi_msi_init(mpic);

1393
	cpu = mpic_processor_id(mpic);
1394

1395 1396 1397 1398 1399
	if (!(mpic->flags & MPIC_NO_RESET)) {
		for (i = 0; i < mpic->num_sources; i++) {
			/* start with vector = source number, and masked */
			u32 vecpri = MPIC_VECPRI_MASK | i |
				(8 << MPIC_VECPRI_PRIORITY_SHIFT);
1400
		
1401 1402 1403 1404 1405 1406 1407
			/* check if protected */
			if (mpic->protected && test_bit(i, mpic->protected))
				continue;
			/* init hw */
			mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
			mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
		}
1408 1409
	}
	
1410 1411
	/* Init spurious vector */
	mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1412

1413 1414 1415 1416 1417
	/* Disable 8259 passthrough, if supported */
	if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
			   mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
			   | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1418

1419 1420 1421 1422 1423
	if (mpic->flags & MPIC_NO_BIAS)
		mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
			mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
			| MPIC_GREG_GCONF_NO_BIAS);

1424
	/* Set current processor priority to 0 */
1425
	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1426 1427 1428

#ifdef CONFIG_PM
	/* allocate memory to save mpic state */
1429 1430
	mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data),
				  GFP_KERNEL);
1431 1432
	BUG_ON(mpic->save_data == NULL);
#endif
1433 1434
}

1435 1436 1437 1438 1439 1440 1441 1442 1443
void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
{
	u32 v;

	v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
	v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
	v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
	mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
}
1444

1445 1446
void __init mpic_set_serial_int(struct mpic *mpic, int enable)
{
1447
	unsigned long flags;
1448 1449
	u32 v;

1450
	raw_spin_lock_irqsave(&mpic_lock, flags);
1451 1452 1453 1454 1455 1456
	v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
	if (enable)
		v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
	else
		v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
	mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1457
	raw_spin_unlock_irqrestore(&mpic_lock, flags);
1458
}
1459 1460 1461

void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
{
1462
	struct mpic *mpic = mpic_find(irq);
1463
	unsigned int src = virq_to_hw(irq);
1464 1465 1466
	unsigned long flags;
	u32 reg;

1467 1468 1469
	if (!mpic)
		return;

1470
	raw_spin_lock_irqsave(&mpic_lock, flags);
1471
	if (mpic_is_ipi(mpic, irq)) {
1472
		reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1473
			~MPIC_VECPRI_PRIORITY_MASK;
1474
		mpic_ipi_write(src - mpic->ipi_vecs[0],
1475 1476
			       reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
	} else {
1477
		reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1478
			& ~MPIC_VECPRI_PRIORITY_MASK;
1479
		mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1480 1481
			       reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
	}
1482
	raw_spin_unlock_irqrestore(&mpic_lock, flags);
1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496
}

void mpic_setup_this_cpu(void)
{
#ifdef CONFIG_SMP
	struct mpic *mpic = mpic_primary;
	unsigned long flags;
	u32 msk = 1 << hard_smp_processor_id();
	unsigned int i;

	BUG_ON(mpic == NULL);

	DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());

1497
	raw_spin_lock_irqsave(&mpic_lock, flags);
1498 1499 1500 1501

 	/* let the mpic know we want intrs. default affinity is 0xffffffff
	 * until changed via /proc. That's how it's done on x86. If we want
	 * it differently, then we should make sure we also change the default
1502
	 * values of irq_desc[].affinity in irq.c.
1503 1504 1505
 	 */
	if (distribute_irqs) {
	 	for (i = 0; i < mpic->num_sources ; i++)
1506 1507
			mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
				mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1508 1509 1510
	}

	/* Set current processor priority to 0 */
1511
	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1512

1513
	raw_spin_unlock_irqrestore(&mpic_lock, flags);
1514 1515 1516 1517 1518 1519 1520
#endif /* CONFIG_SMP */
}

int mpic_cpu_get_priority(void)
{
	struct mpic *mpic = mpic_primary;

1521
	return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1522 1523 1524 1525 1526 1527 1528
}

void mpic_cpu_set_priority(int prio)
{
	struct mpic *mpic = mpic_primary;

	prio &= MPIC_CPU_TASKPRI_MASK;
1529
	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541
}

void mpic_teardown_this_cpu(int secondary)
{
	struct mpic *mpic = mpic_primary;
	unsigned long flags;
	u32 msk = 1 << hard_smp_processor_id();
	unsigned int i;

	BUG_ON(mpic == NULL);

	DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1542
	raw_spin_lock_irqsave(&mpic_lock, flags);
1543 1544 1545

	/* let the mpic know we don't want intrs.  */
	for (i = 0; i < mpic->num_sources ; i++)
1546 1547
		mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
			mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1548 1549

	/* Set current processor priority to max */
1550
	mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1551 1552 1553 1554
	/* We need to EOI the IPI since not all platforms reset the MPIC
	 * on boot and new interrupts wouldn't get delivered otherwise.
	 */
	mpic_eoi(mpic);
1555

1556
	raw_spin_unlock_irqrestore(&mpic_lock, flags);
1557 1558 1559
}


1560
static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1561
{
1562
	u32 src;
1563

1564
	src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1565
#ifdef DEBUG_LOW
1566
	DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1567
#endif
1568 1569 1570
	if (unlikely(src == mpic->spurious_vec)) {
		if (mpic->flags & MPIC_SPV_EOI)
			mpic_eoi(mpic);
1571
		return NO_IRQ;
1572
	}
1573 1574 1575 1576 1577 1578 1579 1580
	if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
		if (printk_ratelimit())
			printk(KERN_WARNING "%s: Got protected source %d !\n",
			       mpic->name, (int)src);
		mpic_eoi(mpic);
		return NO_IRQ;
	}

1581
	return irq_linear_revmap(mpic->irqhost, src);
1582 1583
}

1584 1585 1586 1587 1588
unsigned int mpic_get_one_irq(struct mpic *mpic)
{
	return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
}

O
Olaf Hering 已提交
1589
unsigned int mpic_get_irq(void)
1590 1591 1592 1593 1594
{
	struct mpic *mpic = mpic_primary;

	BUG_ON(mpic == NULL);

O
Olaf Hering 已提交
1595
	return mpic_get_one_irq(mpic);
1596 1597
}

1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625
unsigned int mpic_get_coreint_irq(void)
{
#ifdef CONFIG_BOOKE
	struct mpic *mpic = mpic_primary;
	u32 src;

	BUG_ON(mpic == NULL);

	src = mfspr(SPRN_EPR);

	if (unlikely(src == mpic->spurious_vec)) {
		if (mpic->flags & MPIC_SPV_EOI)
			mpic_eoi(mpic);
		return NO_IRQ;
	}
	if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
		if (printk_ratelimit())
			printk(KERN_WARNING "%s: Got protected source %d !\n",
			       mpic->name, (int)src);
		return NO_IRQ;
	}

	return irq_linear_revmap(mpic->irqhost, src);
#else
	return NO_IRQ;
#endif
}

1626 1627 1628 1629 1630 1631 1632 1633
unsigned int mpic_get_mcirq(void)
{
	struct mpic *mpic = mpic_primary;

	BUG_ON(mpic == NULL);

	return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
}
1634 1635 1636 1637 1638

#ifdef CONFIG_SMP
void mpic_request_ipis(void)
{
	struct mpic *mpic = mpic_primary;
1639
	int i;
1640 1641
	BUG_ON(mpic == NULL);

1642
	printk(KERN_INFO "mpic: requesting IPIs...\n");
1643 1644 1645

	for (i = 0; i < 4; i++) {
		unsigned int vipi = irq_create_mapping(mpic->irqhost,
1646
						       mpic->ipi_vecs[0] + i);
1647
		if (vipi == NO_IRQ) {
1648 1649
			printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
			continue;
1650
		}
1651
		smp_request_message_ipi(vipi, i);
1652
	}
1653
}
1654

1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669
static void mpic_send_ipi(unsigned int ipi_no, const struct cpumask *cpu_mask)
{
	struct mpic *mpic = mpic_primary;

	BUG_ON(mpic == NULL);

#ifdef DEBUG_IPI
	DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
#endif

	mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
		       ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
		       mpic_physmask(cpumask_bits(cpu_mask)[0]));
}

1670 1671
void smp_mpic_message_pass(int target, int msg)
{
1672 1673
	cpumask_var_t tmp;

1674 1675 1676 1677 1678 1679 1680 1681
	/* make sure we're sending something that translates to an IPI */
	if ((unsigned int)msg > 3) {
		printk("SMP %d: smp_message_pass: unknown msg %d\n",
		       smp_processor_id(), msg);
		return;
	}
	switch (target) {
	case MSG_ALL:
1682
		mpic_send_ipi(msg, cpu_online_mask);
1683 1684
		break;
	case MSG_ALL_BUT_SELF:
1685 1686 1687 1688 1689
		alloc_cpumask_var(&tmp, GFP_NOWAIT);
		cpumask_andnot(tmp, cpu_online_mask,
			       cpumask_of(smp_processor_id()));
		mpic_send_ipi(msg, tmp);
		free_cpumask_var(tmp);
1690 1691
		break;
	default:
1692
		mpic_send_ipi(msg, cpumask_of(target));
1693 1694 1695
		break;
	}
}
1696 1697 1698 1699 1700 1701 1702

int __init smp_mpic_probe(void)
{
	int nr_cpus;

	DBG("smp_mpic_probe()...\n");

1703
	nr_cpus = cpumask_weight(cpu_possible_mask);
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	DBG("nr_cpus: %d\n", nr_cpus);

	if (nr_cpus > 1)
		mpic_request_ipis();

	return nr_cpus;
}

void __devinit smp_mpic_setup_cpu(int cpu)
{
	mpic_setup_this_cpu();
}
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void mpic_reset_core(int cpu)
{
	struct mpic *mpic = mpic_primary;
	u32 pir;
	int cpuid = get_hard_smp_processor_id(cpu);

	/* Set target bit for core reset */
	pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
	pir |= (1 << cpuid);
	mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
	mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));

	/* Restore target bit after reset complete */
	pir &= ~(1 << cpuid);
	mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
	mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
}
1735
#endif /* CONFIG_SMP */
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#ifdef CONFIG_PM
static int mpic_suspend(struct sys_device *dev, pm_message_t state)
{
	struct mpic *mpic = container_of(dev, struct mpic, sysdev);
	int i;

	for (i = 0; i < mpic->num_sources; i++) {
		mpic->save_data[i].vecprio =
			mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
		mpic->save_data[i].dest =
			mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
	}

	return 0;
}

static int mpic_resume(struct sys_device *dev)
{
	struct mpic *mpic = container_of(dev, struct mpic, sysdev);
	int i;

	for (i = 0; i < mpic->num_sources; i++) {
		mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
			       mpic->save_data[i].vecprio);
		mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
			       mpic->save_data[i].dest);

#ifdef CONFIG_MPIC_U3_HT_IRQS
1765
	if (mpic->fixups) {
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		struct mpic_irq_fixup *fixup = &mpic->fixups[i];

		if (fixup->base) {
			/* we use the lowest bit in an inverted meaning */
			if ((mpic->save_data[i].fixup_data & 1) == 0)
				continue;

			/* Enable and configure */
			writeb(0x10 + 2 * fixup->index, fixup->base + 2);

			writel(mpic->save_data[i].fixup_data & ~1,
			       fixup->base + 4);
		}
	}
#endif
	} /* end for loop */

	return 0;
}
#endif

static struct sysdev_class mpic_sysclass = {
#ifdef CONFIG_PM
	.resume = mpic_resume,
	.suspend = mpic_suspend,
#endif
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	.name = "mpic",
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};

static int mpic_init_sys(void)
{
	struct mpic *mpic = mpics;
	int error, id = 0;

	error = sysdev_class_register(&mpic_sysclass);

	while (mpic && !error) {
		mpic->sysdev.cls = &mpic_sysclass;
		mpic->sysdev.id = id++;
		error = sysdev_register(&mpic->sysdev);
		mpic = mpic->next;
	}
	return error;
}

device_initcall(mpic_init_sys);