pxa2xx_spi.c 47.0 KB
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/*
 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/ioport.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
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#include <linux/spi/pxa2xx_spi.h>
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#include <linux/dma-mapping.h>
#include <linux/spi/spi.h>
#include <linux/workqueue.h>
#include <linux/delay.h>
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#include <linux/gpio.h>
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#include <linux/slab.h>
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#include <asm/io.h>
#include <asm/irq.h>
#include <asm/delay.h>


MODULE_AUTHOR("Stephen Street");
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MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:pxa2xx-spi");
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#define MAX_BUSES 3

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#define TIMOUT_DFLT		1000

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#define DMA_INT_MASK		(DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
#define RESET_DMA_CHANNEL	(DCSR_NODESC | DMA_INT_MASK)
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#define IS_DMA_ALIGNED(x)	((((u32)(x)) & 0x07) == 0)
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#define MAX_DMA_LEN		8191
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#define DMA_ALIGNMENT		8
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/*
 * for testing SSCR1 changes that require SSP restart, basically
 * everything except the service and interrupt enables, the pxa270 developer
 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
 * list, but the PXA255 dev man says all bits without really meaning the
 * service and interrupt enables
 */
#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
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				| SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
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				| SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
				| SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
				| SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
				| SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
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#define DEFINE_SSP_REG(reg, off) \
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static inline u32 read_##reg(void const __iomem *p) \
{ return __raw_readl(p + (off)); } \
\
static inline void write_##reg(u32 v, void __iomem *p) \
{ __raw_writel(v, p + (off)); }
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DEFINE_SSP_REG(SSCR0, 0x00)
DEFINE_SSP_REG(SSCR1, 0x04)
DEFINE_SSP_REG(SSSR, 0x08)
DEFINE_SSP_REG(SSITR, 0x0c)
DEFINE_SSP_REG(SSDR, 0x10)
DEFINE_SSP_REG(SSTO, 0x28)
DEFINE_SSP_REG(SSPSP, 0x2c)

#define START_STATE ((void*)0)
#define RUNNING_STATE ((void*)1)
#define DONE_STATE ((void*)2)
#define ERROR_STATE ((void*)-1)

#define QUEUE_RUNNING 0
#define QUEUE_STOPPED 1

struct driver_data {
	/* Driver model hookup */
	struct platform_device *pdev;

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	/* SSP Info */
	struct ssp_device *ssp;

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	/* SPI framework hookup */
	enum pxa_ssp_type ssp_type;
	struct spi_master *master;

	/* PXA hookup */
	struct pxa2xx_spi_master *master_info;

	/* DMA setup stuff */
	int rx_channel;
	int tx_channel;
	u32 *null_dma_buf;

	/* SSP register addresses */
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	void __iomem *ioaddr;
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	u32 ssdr_physical;

	/* SSP masks*/
	u32 dma_cr1;
	u32 int_cr1;
	u32 clear_sr;
	u32 mask_sr;

	/* Driver message queue */
	struct workqueue_struct	*workqueue;
	struct work_struct pump_messages;
	spinlock_t lock;
	struct list_head queue;
	int busy;
	int run;

	/* Message Transfer pump */
	struct tasklet_struct pump_transfers;

	/* Current message transfer state info */
	struct spi_message* cur_msg;
	struct spi_transfer* cur_transfer;
	struct chip_data *cur_chip;
	size_t len;
	void *tx;
	void *tx_end;
	void *rx;
	void *rx_end;
	int dma_mapped;
	dma_addr_t rx_dma;
	dma_addr_t tx_dma;
	size_t rx_map_len;
	size_t tx_map_len;
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	u8 n_bytes;
	u32 dma_width;
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	int (*write)(struct driver_data *drv_data);
	int (*read)(struct driver_data *drv_data);
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	irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
	void (*cs_control)(u32 command);
};

struct chip_data {
	u32 cr0;
	u32 cr1;
	u32 psp;
	u32 timeout;
	u8 n_bytes;
	u32 dma_width;
	u32 dma_burst_size;
	u32 threshold;
	u32 dma_threshold;
	u8 enable_dma;
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	u8 bits_per_word;
	u32 speed_hz;
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	union {
		int gpio_cs;
		unsigned int frm;
	};
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	int gpio_cs_inverted;
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	int (*write)(struct driver_data *drv_data);
	int (*read)(struct driver_data *drv_data);
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	void (*cs_control)(u32 command);
};

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static void pump_messages(struct work_struct *work);
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static void cs_assert(struct driver_data *drv_data)
{
	struct chip_data *chip = drv_data->cur_chip;

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	if (drv_data->ssp_type == CE4100_SSP) {
		write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr);
		return;
	}

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	if (chip->cs_control) {
		chip->cs_control(PXA2XX_CS_ASSERT);
		return;
	}

	if (gpio_is_valid(chip->gpio_cs))
		gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
}

static void cs_deassert(struct driver_data *drv_data)
{
	struct chip_data *chip = drv_data->cur_chip;

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	if (drv_data->ssp_type == CE4100_SSP)
		return;

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	if (chip->cs_control) {
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		chip->cs_control(PXA2XX_CS_DEASSERT);
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		return;
	}

	if (gpio_is_valid(chip->gpio_cs))
		gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
}

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static void write_SSSR_CS(struct driver_data *drv_data, u32 val)
{
	void __iomem *reg = drv_data->ioaddr;

	if (drv_data->ssp_type == CE4100_SSP)
		val |= read_SSSR(reg) & SSSR_ALT_FRM_MASK;

	write_SSSR(val, reg);
}

static int pxa25x_ssp_comp(struct driver_data *drv_data)
{
	if (drv_data->ssp_type == PXA25x_SSP)
		return 1;
	if (drv_data->ssp_type == CE4100_SSP)
		return 1;
	return 0;
}

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static int flush(struct driver_data *drv_data)
{
	unsigned long limit = loops_per_jiffy << 1;

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	void __iomem *reg = drv_data->ioaddr;
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	do {
		while (read_SSSR(reg) & SSSR_RNE) {
			read_SSDR(reg);
		}
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	} while ((read_SSSR(reg) & SSSR_BSY) && --limit);
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	write_SSSR_CS(drv_data, SSSR_ROR);
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	return limit;
}

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static int null_writer(struct driver_data *drv_data)
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{
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	void __iomem *reg = drv_data->ioaddr;
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	u8 n_bytes = drv_data->n_bytes;
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	if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
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		|| (drv_data->tx == drv_data->tx_end))
		return 0;

	write_SSDR(0, reg);
	drv_data->tx += n_bytes;

	return 1;
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}

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static int null_reader(struct driver_data *drv_data)
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{
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	void __iomem *reg = drv_data->ioaddr;
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	u8 n_bytes = drv_data->n_bytes;
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	while ((read_SSSR(reg) & SSSR_RNE)
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		&& (drv_data->rx < drv_data->rx_end)) {
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		read_SSDR(reg);
		drv_data->rx += n_bytes;
	}
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	return drv_data->rx == drv_data->rx_end;
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}

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static int u8_writer(struct driver_data *drv_data)
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{
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	void __iomem *reg = drv_data->ioaddr;
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	if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
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		|| (drv_data->tx == drv_data->tx_end))
		return 0;

	write_SSDR(*(u8 *)(drv_data->tx), reg);
	++drv_data->tx;

	return 1;
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}

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static int u8_reader(struct driver_data *drv_data)
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{
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	void __iomem *reg = drv_data->ioaddr;
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	while ((read_SSSR(reg) & SSSR_RNE)
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		&& (drv_data->rx < drv_data->rx_end)) {
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		*(u8 *)(drv_data->rx) = read_SSDR(reg);
		++drv_data->rx;
	}
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	return drv_data->rx == drv_data->rx_end;
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}

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static int u16_writer(struct driver_data *drv_data)
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{
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	void __iomem *reg = drv_data->ioaddr;
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	if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
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		|| (drv_data->tx == drv_data->tx_end))
		return 0;

	write_SSDR(*(u16 *)(drv_data->tx), reg);
	drv_data->tx += 2;

	return 1;
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}

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static int u16_reader(struct driver_data *drv_data)
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{
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	void __iomem *reg = drv_data->ioaddr;
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	while ((read_SSSR(reg) & SSSR_RNE)
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		&& (drv_data->rx < drv_data->rx_end)) {
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		*(u16 *)(drv_data->rx) = read_SSDR(reg);
		drv_data->rx += 2;
	}
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	return drv_data->rx == drv_data->rx_end;
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}
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static int u32_writer(struct driver_data *drv_data)
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{
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	void __iomem *reg = drv_data->ioaddr;
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	if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
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		|| (drv_data->tx == drv_data->tx_end))
		return 0;

	write_SSDR(*(u32 *)(drv_data->tx), reg);
	drv_data->tx += 4;

	return 1;
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}

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static int u32_reader(struct driver_data *drv_data)
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{
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	void __iomem *reg = drv_data->ioaddr;
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	while ((read_SSSR(reg) & SSSR_RNE)
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		&& (drv_data->rx < drv_data->rx_end)) {
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		*(u32 *)(drv_data->rx) = read_SSDR(reg);
		drv_data->rx += 4;
	}
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	return drv_data->rx == drv_data->rx_end;
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}

static void *next_transfer(struct driver_data *drv_data)
{
	struct spi_message *msg = drv_data->cur_msg;
	struct spi_transfer *trans = drv_data->cur_transfer;

	/* Move to next transfer */
	if (trans->transfer_list.next != &msg->transfers) {
		drv_data->cur_transfer =
			list_entry(trans->transfer_list.next,
					struct spi_transfer,
					transfer_list);
		return RUNNING_STATE;
	} else
		return DONE_STATE;
}

static int map_dma_buffers(struct driver_data *drv_data)
{
	struct spi_message *msg = drv_data->cur_msg;
	struct device *dev = &msg->spi->dev;

	if (!drv_data->cur_chip->enable_dma)
		return 0;

	if (msg->is_dma_mapped)
		return  drv_data->rx_dma && drv_data->tx_dma;

	if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))
		return 0;

	/* Modify setup if rx buffer is null */
	if (drv_data->rx == NULL) {
		*drv_data->null_dma_buf = 0;
		drv_data->rx = drv_data->null_dma_buf;
		drv_data->rx_map_len = 4;
	} else
		drv_data->rx_map_len = drv_data->len;


	/* Modify setup if tx buffer is null */
	if (drv_data->tx == NULL) {
		*drv_data->null_dma_buf = 0;
		drv_data->tx = drv_data->null_dma_buf;
		drv_data->tx_map_len = 4;
	} else
		drv_data->tx_map_len = drv_data->len;

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	/* Stream map the tx buffer. Always do DMA_TO_DEVICE first
	 * so we flush the cache *before* invalidating it, in case
	 * the tx and rx buffers overlap.
	 */
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	drv_data->tx_dma = dma_map_single(dev, drv_data->tx,
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					drv_data->tx_map_len, DMA_TO_DEVICE);
	if (dma_mapping_error(dev, drv_data->tx_dma))
		return 0;
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	/* Stream map the rx buffer */
	drv_data->rx_dma = dma_map_single(dev, drv_data->rx,
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					drv_data->rx_map_len, DMA_FROM_DEVICE);
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	if (dma_mapping_error(dev, drv_data->rx_dma)) {
		dma_unmap_single(dev, drv_data->tx_dma,
					drv_data->tx_map_len, DMA_TO_DEVICE);
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		return 0;
	}

	return 1;
}

static void unmap_dma_buffers(struct driver_data *drv_data)
{
	struct device *dev;

	if (!drv_data->dma_mapped)
		return;

	if (!drv_data->cur_msg->is_dma_mapped) {
		dev = &drv_data->cur_msg->spi->dev;
		dma_unmap_single(dev, drv_data->rx_dma,
					drv_data->rx_map_len, DMA_FROM_DEVICE);
		dma_unmap_single(dev, drv_data->tx_dma,
					drv_data->tx_map_len, DMA_TO_DEVICE);
	}

	drv_data->dma_mapped = 0;
}

/* caller already set message->status; dma and pio irqs are blocked */
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static void giveback(struct driver_data *drv_data)
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{
	struct spi_transfer* last_transfer;
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	unsigned long flags;
	struct spi_message *msg;
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	spin_lock_irqsave(&drv_data->lock, flags);
	msg = drv_data->cur_msg;
	drv_data->cur_msg = NULL;
	drv_data->cur_transfer = NULL;
	queue_work(drv_data->workqueue, &drv_data->pump_messages);
	spin_unlock_irqrestore(&drv_data->lock, flags);

	last_transfer = list_entry(msg->transfers.prev,
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					struct spi_transfer,
					transfer_list);

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	/* Delay if requested before any change in chip select */
	if (last_transfer->delay_usecs)
		udelay(last_transfer->delay_usecs);

	/* Drop chip select UNLESS cs_change is true or we are returning
	 * a message with an error, or next message is for another chip
	 */
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	if (!last_transfer->cs_change)
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		cs_deassert(drv_data);
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	else {
		struct spi_message *next_msg;

		/* Holding of cs was hinted, but we need to make sure
		 * the next message is for the same chip.  Don't waste
		 * time with the following tests unless this was hinted.
		 *
		 * We cannot postpone this until pump_messages, because
		 * after calling msg->complete (below) the driver that
		 * sent the current message could be unloaded, which
		 * could invalidate the cs_control() callback...
		 */

		/* get a pointer to the next message, if any */
		spin_lock_irqsave(&drv_data->lock, flags);
		if (list_empty(&drv_data->queue))
			next_msg = NULL;
		else
			next_msg = list_entry(drv_data->queue.next,
					struct spi_message, queue);
		spin_unlock_irqrestore(&drv_data->lock, flags);

		/* see if the next and current messages point
		 * to the same chip
		 */
		if (next_msg && next_msg->spi != msg->spi)
			next_msg = NULL;
		if (!next_msg || msg->state == ERROR_STATE)
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			cs_deassert(drv_data);
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	}
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	msg->state = NULL;
	if (msg->complete)
		msg->complete(msg->context);
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	drv_data->cur_chip = NULL;
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}

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static int wait_ssp_rx_stall(void const __iomem *ioaddr)
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{
	unsigned long limit = loops_per_jiffy << 1;

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	while ((read_SSSR(ioaddr) & SSSR_BSY) && --limit)
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		cpu_relax();

	return limit;
}

static int wait_dma_channel_stop(int channel)
{
	unsigned long limit = loops_per_jiffy << 1;

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	while (!(DCSR(channel) & DCSR_STOPSTATE) && --limit)
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		cpu_relax();

	return limit;
}

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static void dma_error_stop(struct driver_data *drv_data, const char *msg)
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{
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	void __iomem *reg = drv_data->ioaddr;
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	/* Stop and reset */
	DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
	DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
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	write_SSSR_CS(drv_data, drv_data->clear_sr);
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	write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
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	if (!pxa25x_ssp_comp(drv_data))
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		write_SSTO(0, reg);
	flush(drv_data);
	write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
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	unmap_dma_buffers(drv_data);
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	dev_err(&drv_data->pdev->dev, "%s\n", msg);
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	drv_data->cur_msg->state = ERROR_STATE;
	tasklet_schedule(&drv_data->pump_transfers);
}

static void dma_transfer_complete(struct driver_data *drv_data)
{
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	void __iomem *reg = drv_data->ioaddr;
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	struct spi_message *msg = drv_data->cur_msg;

	/* Clear and disable interrupts on SSP and DMA channels*/
	write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
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	write_SSSR_CS(drv_data, drv_data->clear_sr);
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	DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
	DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;

	if (wait_dma_channel_stop(drv_data->rx_channel) == 0)
		dev_err(&drv_data->pdev->dev,
			"dma_handler: dma rx channel stop failed\n");

	if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
		dev_err(&drv_data->pdev->dev,
			"dma_transfer: ssp rx stall failed\n");

	unmap_dma_buffers(drv_data);

	/* update the buffer pointer for the amount completed in dma */
	drv_data->rx += drv_data->len -
			(DCMD(drv_data->rx_channel) & DCMD_LENGTH);

	/* read trailing data from fifo, it does not matter how many
	 * bytes are in the fifo just read until buffer is full
	 * or fifo is empty, which ever occurs first */
	drv_data->read(drv_data);

	/* return count of what was actually read */
	msg->actual_length += drv_data->len -
				(drv_data->rx_end - drv_data->rx);

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	/* Transfer delays and chip select release are
	 * handled in pump_transfers or giveback
	 */
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	/* Move to next transfer */
	msg->state = next_transfer(drv_data);

	/* Schedule transfer tasklet */
	tasklet_schedule(&drv_data->pump_transfers);
}

static void dma_handler(int channel, void *data)
{
	struct driver_data *drv_data = data;
	u32 irq_status = DCSR(channel) & DMA_INT_MASK;

	if (irq_status & DCSR_BUSERR) {
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		if (channel == drv_data->tx_channel)
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			dma_error_stop(drv_data,
					"dma_handler: "
					"bad bus address on tx channel");
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		else
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			dma_error_stop(drv_data,
					"dma_handler: "
					"bad bus address on rx channel");
		return;
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	}

	/* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */
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	if ((channel == drv_data->tx_channel)
		&& (irq_status & DCSR_ENDINTR)
		&& (drv_data->ssp_type == PXA25x_SSP)) {
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		/* Wait for rx to stall */
		if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
			dev_err(&drv_data->pdev->dev,
				"dma_handler: ssp rx stall failed\n");

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		/* finish this transfer, start the next */
		dma_transfer_complete(drv_data);
625 626 627 628 629 630
	}
}

static irqreturn_t dma_transfer(struct driver_data *drv_data)
{
	u32 irq_status;
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David Brownell 已提交
631
	void __iomem *reg = drv_data->ioaddr;
632 633 634

	irq_status = read_SSSR(reg) & drv_data->mask_sr;
	if (irq_status & SSSR_ROR) {
635
		dma_error_stop(drv_data, "dma_transfer: fifo overrun");
636 637 638 639
		return IRQ_HANDLED;
	}

	/* Check for false positive timeout */
640 641
	if ((irq_status & SSSR_TINT)
		&& (DCSR(drv_data->tx_channel) & DCSR_RUN)) {
642 643 644 645 646 647
		write_SSSR(SSSR_TINT, reg);
		return IRQ_HANDLED;
	}

	if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) {

648 649
		/* Clear and disable timeout interrupt, do the rest in
		 * dma_transfer_complete */
650
		if (!pxa25x_ssp_comp(drv_data))
651 652
			write_SSTO(0, reg);

653 654
		/* finish this transfer, start the next */
		dma_transfer_complete(drv_data);
655 656 657 658 659 660 661 662

		return IRQ_HANDLED;
	}

	/* Opps problem detected */
	return IRQ_NONE;
}

663 664 665 666 667 668 669 670 671 672 673 674
static void reset_sccr1(struct driver_data *drv_data)
{
	void __iomem *reg = drv_data->ioaddr;
	struct chip_data *chip = drv_data->cur_chip;
	u32 sccr1_reg;

	sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1;
	sccr1_reg &= ~SSCR1_RFT;
	sccr1_reg |= chip->threshold;
	write_SSCR1(sccr1_reg, reg);
}

675
static void int_error_stop(struct driver_data *drv_data, const char* msg)
676
{
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677
	void __iomem *reg = drv_data->ioaddr;
678

679
	/* Stop and reset SSP */
680
	write_SSSR_CS(drv_data, drv_data->clear_sr);
681
	reset_sccr1(drv_data);
682
	if (!pxa25x_ssp_comp(drv_data))
683 684 685
		write_SSTO(0, reg);
	flush(drv_data);
	write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
686

687
	dev_err(&drv_data->pdev->dev, "%s\n", msg);
688

689 690 691
	drv_data->cur_msg->state = ERROR_STATE;
	tasklet_schedule(&drv_data->pump_transfers);
}
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692

693 694
static void int_transfer_complete(struct driver_data *drv_data)
{
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695
	void __iomem *reg = drv_data->ioaddr;
696

697
	/* Stop SSP */
698
	write_SSSR_CS(drv_data, drv_data->clear_sr);
699
	reset_sccr1(drv_data);
700
	if (!pxa25x_ssp_comp(drv_data))
701
		write_SSTO(0, reg);
702

703 704 705
	/* Update total byte transfered return count actual bytes read */
	drv_data->cur_msg->actual_length += drv_data->len -
				(drv_data->rx_end - drv_data->rx);
706

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707 708 709
	/* Transfer delays and chip select release are
	 * handled in pump_transfers or giveback
	 */
710

711 712
	/* Move to next transfer */
	drv_data->cur_msg->state = next_transfer(drv_data);
713

714 715 716
	/* Schedule transfer tasklet */
	tasklet_schedule(&drv_data->pump_transfers);
}
717

718 719
static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
{
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720
	void __iomem *reg = drv_data->ioaddr;
721

722 723
	u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
			drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
724

725
	u32 irq_status = read_SSSR(reg) & irq_mask;
726

727 728 729 730
	if (irq_status & SSSR_ROR) {
		int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
		return IRQ_HANDLED;
	}
731

732 733 734 735 736 737 738
	if (irq_status & SSSR_TINT) {
		write_SSSR(SSSR_TINT, reg);
		if (drv_data->read(drv_data)) {
			int_transfer_complete(drv_data);
			return IRQ_HANDLED;
		}
	}
739

740 741 742 743 744 745 746
	/* Drain rx fifo, Fill tx fifo and prevent overruns */
	do {
		if (drv_data->read(drv_data)) {
			int_transfer_complete(drv_data);
			return IRQ_HANDLED;
		}
	} while (drv_data->write(drv_data));
747

748 749 750 751
	if (drv_data->read(drv_data)) {
		int_transfer_complete(drv_data);
		return IRQ_HANDLED;
	}
752

753
	if (drv_data->tx == drv_data->tx_end) {
754 755 756 757 758 759 760 761 762 763
		u32 bytes_left;
		u32 sccr1_reg;

		sccr1_reg = read_SSCR1(reg);
		sccr1_reg &= ~SSCR1_TIE;

		/*
		 * PXA25x_SSP has no timeout, set up rx threshould for the
		 * remaing RX bytes.
		 */
764
		if (pxa25x_ssp_comp(drv_data)) {
765 766 767 768 769 770 771 772 773

			sccr1_reg &= ~SSCR1_RFT;

			bytes_left = drv_data->rx_end - drv_data->rx;
			switch (drv_data->n_bytes) {
			case 4:
				bytes_left >>= 1;
			case 2:
				bytes_left >>= 1;
774
			}
775 776 777 778 779

			if (bytes_left > RX_THRESH_DFLT)
				bytes_left = RX_THRESH_DFLT;

			sccr1_reg |= SSCR1_RxTresh(bytes_left);
780
		}
781
		write_SSCR1(sccr1_reg, reg);
782 783
	}

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Stephen Street 已提交
784 785
	/* We did something */
	return IRQ_HANDLED;
786 787
}

788
static irqreturn_t ssp_int(int irq, void *dev_id)
789
{
790
	struct driver_data *drv_data = dev_id;
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791
	void __iomem *reg = drv_data->ioaddr;
792 793 794 795 796 797 798 799 800 801 802 803
	u32 sccr1_reg = read_SSCR1(reg);
	u32 mask = drv_data->mask_sr;
	u32 status;

	status = read_SSSR(reg);

	/* Ignore possible writes if we don't need to write */
	if (!(sccr1_reg & SSCR1_TIE))
		mask &= ~SSSR_TFS;

	if (!(status & mask))
		return IRQ_NONE;
804 805

	if (!drv_data->cur_msg) {
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Stephen Street 已提交
806 807 808

		write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
		write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
809
		if (!pxa25x_ssp_comp(drv_data))
S
Stephen Street 已提交
810
			write_SSTO(0, reg);
811
		write_SSSR_CS(drv_data, drv_data->clear_sr);
S
Stephen Street 已提交
812

813
		dev_err(&drv_data->pdev->dev, "bad message state "
814
			"in interrupt handler\n");
S
Stephen Street 已提交
815

816 817 818 819 820 821 822
		/* Never fail */
		return IRQ_HANDLED;
	}

	return drv_data->transfer_handler(drv_data);
}

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823 824
static int set_dma_burst_and_threshold(struct chip_data *chip,
				struct spi_device *spi,
825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919
				u8 bits_per_word, u32 *burst_code,
				u32 *threshold)
{
	struct pxa2xx_spi_chip *chip_info =
			(struct pxa2xx_spi_chip *)spi->controller_data;
	int bytes_per_word;
	int burst_bytes;
	int thresh_words;
	int req_burst_size;
	int retval = 0;

	/* Set the threshold (in registers) to equal the same amount of data
	 * as represented by burst size (in bytes).  The computation below
	 * is (burst_size rounded up to nearest 8 byte, word or long word)
	 * divided by (bytes/register); the tx threshold is the inverse of
	 * the rx, so that there will always be enough data in the rx fifo
	 * to satisfy a burst, and there will always be enough space in the
	 * tx fifo to accept a burst (a tx burst will overwrite the fifo if
	 * there is not enough space), there must always remain enough empty
	 * space in the rx fifo for any data loaded to the tx fifo.
	 * Whenever burst_size (in bytes) equals bits/word, the fifo threshold
	 * will be 8, or half the fifo;
	 * The threshold can only be set to 2, 4 or 8, but not 16, because
	 * to burst 16 to the tx fifo, the fifo would have to be empty;
	 * however, the minimum fifo trigger level is 1, and the tx will
	 * request service when the fifo is at this level, with only 15 spaces.
	 */

	/* find bytes/word */
	if (bits_per_word <= 8)
		bytes_per_word = 1;
	else if (bits_per_word <= 16)
		bytes_per_word = 2;
	else
		bytes_per_word = 4;

	/* use struct pxa2xx_spi_chip->dma_burst_size if available */
	if (chip_info)
		req_burst_size = chip_info->dma_burst_size;
	else {
		switch (chip->dma_burst_size) {
		default:
			/* if the default burst size is not set,
			 * do it now */
			chip->dma_burst_size = DCMD_BURST8;
		case DCMD_BURST8:
			req_burst_size = 8;
			break;
		case DCMD_BURST16:
			req_burst_size = 16;
			break;
		case DCMD_BURST32:
			req_burst_size = 32;
			break;
		}
	}
	if (req_burst_size <= 8) {
		*burst_code = DCMD_BURST8;
		burst_bytes = 8;
	} else if (req_burst_size <= 16) {
		if (bytes_per_word == 1) {
			/* don't burst more than 1/2 the fifo */
			*burst_code = DCMD_BURST8;
			burst_bytes = 8;
			retval = 1;
		} else {
			*burst_code = DCMD_BURST16;
			burst_bytes = 16;
		}
	} else {
		if (bytes_per_word == 1) {
			/* don't burst more than 1/2 the fifo */
			*burst_code = DCMD_BURST8;
			burst_bytes = 8;
			retval = 1;
		} else if (bytes_per_word == 2) {
			/* don't burst more than 1/2 the fifo */
			*burst_code = DCMD_BURST16;
			burst_bytes = 16;
			retval = 1;
		} else {
			*burst_code = DCMD_BURST32;
			burst_bytes = 32;
		}
	}

	thresh_words = burst_bytes / bytes_per_word;

	/* thresh_words will be between 2 and 8 */
	*threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT)
			| (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT);

	return retval;
}

920 921 922 923
static unsigned int ssp_get_clk_div(struct ssp_device *ssp, int rate)
{
	unsigned long ssp_clk = clk_get_rate(ssp->clk);

924
	if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
925 926 927 928 929
		return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
	else
		return ((ssp_clk / rate - 1) & 0xfff) << 8;
}

930 931 932 933 934 935 936
static void pump_transfers(unsigned long data)
{
	struct driver_data *drv_data = (struct driver_data *)data;
	struct spi_message *message = NULL;
	struct spi_transfer *transfer = NULL;
	struct spi_transfer *previous = NULL;
	struct chip_data *chip = NULL;
937
	struct ssp_device *ssp = drv_data->ssp;
D
David Brownell 已提交
938
	void __iomem *reg = drv_data->ioaddr;
939 940 941 942
	u32 clk_div = 0;
	u8 bits = 0;
	u32 speed = 0;
	u32 cr0;
943 944 945
	u32 cr1;
	u32 dma_thresh = drv_data->cur_chip->dma_threshold;
	u32 dma_burst = drv_data->cur_chip->dma_burst_size;
946 947 948 949 950 951 952 953 954

	/* Get current state information */
	message = drv_data->cur_msg;
	transfer = drv_data->cur_transfer;
	chip = drv_data->cur_chip;

	/* Handle for abort */
	if (message->state == ERROR_STATE) {
		message->status = -EIO;
S
Stephen Street 已提交
955
		giveback(drv_data);
956 957 958 959 960 961
		return;
	}

	/* Handle end of message */
	if (message->state == DONE_STATE) {
		message->status = 0;
S
Stephen Street 已提交
962
		giveback(drv_data);
963 964 965
		return;
	}

N
Ned Forrester 已提交
966
	/* Delay if requested at end of transfer before CS change */
967 968 969 970 971 972
	if (message->state == RUNNING_STATE) {
		previous = list_entry(transfer->transfer_list.prev,
					struct spi_transfer,
					transfer_list);
		if (previous->delay_usecs)
			udelay(previous->delay_usecs);
N
Ned Forrester 已提交
973 974 975

		/* Drop chip select only if cs_change is requested */
		if (previous->cs_change)
976
			cs_deassert(drv_data);
977 978
	}

N
Ned Forrester 已提交
979 980 981 982 983 984 985 986
	/* Check for transfers that need multiple DMA segments */
	if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {

		/* reject already-mapped transfers; PIO won't always work */
		if (message->is_dma_mapped
				|| transfer->rx_dma || transfer->tx_dma) {
			dev_err(&drv_data->pdev->dev,
				"pump_transfers: mapped transfer length "
M
Mike Rapoport 已提交
987
				"of %u is greater than %d\n",
N
Ned Forrester 已提交
988 989 990 991 992 993 994 995 996 997 998 999
				transfer->len, MAX_DMA_LEN);
			message->status = -EINVAL;
			giveback(drv_data);
			return;
		}

		/* warn ... we force this to PIO mode */
		if (printk_ratelimit())
			dev_warn(&message->spi->dev, "pump_transfers: "
				"DMA disabled for transfer length %ld "
				"greater than %d\n",
				(long)drv_data->len, MAX_DMA_LEN);
1000 1001
	}

1002 1003 1004 1005
	/* Setup the transfer state based on the type of transfer */
	if (flush(drv_data) == 0) {
		dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
		message->status = -EIO;
S
Stephen Street 已提交
1006
		giveback(drv_data);
1007 1008
		return;
	}
1009 1010
	drv_data->n_bytes = chip->n_bytes;
	drv_data->dma_width = chip->dma_width;
1011 1012 1013 1014 1015 1016
	drv_data->tx = (void *)transfer->tx_buf;
	drv_data->tx_end = drv_data->tx + transfer->len;
	drv_data->rx = transfer->rx_buf;
	drv_data->rx_end = drv_data->rx + transfer->len;
	drv_data->rx_dma = transfer->rx_dma;
	drv_data->tx_dma = transfer->tx_dma;
1017
	drv_data->len = transfer->len & DCMD_LENGTH;
1018 1019
	drv_data->write = drv_data->tx ? chip->write : null_writer;
	drv_data->read = drv_data->rx ? chip->read : null_reader;
1020 1021

	/* Change speed and bit per word on a per transfer */
1022
	cr0 = chip->cr0;
1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033
	if (transfer->speed_hz || transfer->bits_per_word) {

		bits = chip->bits_per_word;
		speed = chip->speed_hz;

		if (transfer->speed_hz)
			speed = transfer->speed_hz;

		if (transfer->bits_per_word)
			bits = transfer->bits_per_word;

1034
		clk_div = ssp_get_clk_div(ssp, speed);
1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057

		if (bits <= 8) {
			drv_data->n_bytes = 1;
			drv_data->dma_width = DCMD_WIDTH1;
			drv_data->read = drv_data->read != null_reader ?
						u8_reader : null_reader;
			drv_data->write = drv_data->write != null_writer ?
						u8_writer : null_writer;
		} else if (bits <= 16) {
			drv_data->n_bytes = 2;
			drv_data->dma_width = DCMD_WIDTH2;
			drv_data->read = drv_data->read != null_reader ?
						u16_reader : null_reader;
			drv_data->write = drv_data->write != null_writer ?
						u16_writer : null_writer;
		} else if (bits <= 32) {
			drv_data->n_bytes = 4;
			drv_data->dma_width = DCMD_WIDTH4;
			drv_data->read = drv_data->read != null_reader ?
						u32_reader : null_reader;
			drv_data->write = drv_data->write != null_writer ?
						u32_writer : null_writer;
		}
1058 1059 1060 1061 1062 1063 1064 1065
		/* if bits/word is changed in dma mode, then must check the
		 * thresholds and burst also */
		if (chip->enable_dma) {
			if (set_dma_burst_and_threshold(chip, message->spi,
							bits, &dma_burst,
							&dma_thresh))
				if (printk_ratelimit())
					dev_warn(&message->spi->dev,
N
Ned Forrester 已提交
1066
						"pump_transfers: "
1067 1068 1069
						"DMA burst size reduced to "
						"match bits_per_word\n");
		}
1070 1071 1072

		cr0 = clk_div
			| SSCR0_Motorola
S
Stephen Street 已提交
1073
			| SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
1074 1075 1076 1077
			| SSCR0_SSE
			| (bits > 16 ? SSCR0_EDSS : 0);
	}

1078 1079
	message->state = RUNNING_STATE;

N
Ned Forrester 已提交
1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096
	/* Try to map dma buffer and do a dma transfer if successful, but
	 * only if the length is non-zero and less than MAX_DMA_LEN.
	 *
	 * Zero-length non-descriptor DMA is illegal on PXA2xx; force use
	 * of PIO instead.  Care is needed above because the transfer may
	 * have have been passed with buffers that are already dma mapped.
	 * A zero-length transfer in PIO mode will not try to write/read
	 * to/from the buffers
	 *
	 * REVISIT large transfers are exactly where we most want to be
	 * using DMA.  If this happens much, split those transfers into
	 * multiple DMA segments rather than forcing PIO.
	 */
	drv_data->dma_mapped = 0;
	if (drv_data->len > 0 && drv_data->len <= MAX_DMA_LEN)
		drv_data->dma_mapped = map_dma_buffers(drv_data);
	if (drv_data->dma_mapped) {
1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107

		/* Ensure we have the correct interrupt handler */
		drv_data->transfer_handler = dma_transfer;

		/* Setup rx DMA Channel */
		DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
		DSADR(drv_data->rx_channel) = drv_data->ssdr_physical;
		DTADR(drv_data->rx_channel) = drv_data->rx_dma;
		if (drv_data->rx == drv_data->null_dma_buf)
			/* No target address increment */
			DCMD(drv_data->rx_channel) = DCMD_FLOWSRC
1108
							| drv_data->dma_width
1109
							| dma_burst
1110 1111 1112 1113
							| drv_data->len;
		else
			DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR
							| DCMD_FLOWSRC
1114
							| drv_data->dma_width
1115
							| dma_burst
1116 1117 1118 1119 1120 1121 1122 1123 1124
							| drv_data->len;

		/* Setup tx DMA Channel */
		DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
		DSADR(drv_data->tx_channel) = drv_data->tx_dma;
		DTADR(drv_data->tx_channel) = drv_data->ssdr_physical;
		if (drv_data->tx == drv_data->null_dma_buf)
			/* No source address increment */
			DCMD(drv_data->tx_channel) = DCMD_FLOWTRG
1125
							| drv_data->dma_width
1126
							| dma_burst
1127 1128 1129 1130
							| drv_data->len;
		else
			DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR
							| DCMD_FLOWTRG
1131
							| drv_data->dma_width
1132
							| dma_burst
1133 1134 1135 1136 1137 1138
							| drv_data->len;

		/* Enable dma end irqs on SSP to detect end of transfer */
		if (drv_data->ssp_type == PXA25x_SSP)
			DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN;

1139 1140
		/* Clear status and start DMA engine */
		cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1141 1142 1143 1144 1145 1146 1147
		write_SSSR(drv_data->clear_sr, reg);
		DCSR(drv_data->rx_channel) |= DCSR_RUN;
		DCSR(drv_data->tx_channel) |= DCSR_RUN;
	} else {
		/* Ensure we have the correct interrupt handler	*/
		drv_data->transfer_handler = interrupt_transfer;

1148 1149
		/* Clear status  */
		cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1150
		write_SSSR_CS(drv_data, drv_data->clear_sr);
1151 1152 1153 1154 1155 1156 1157
	}

	/* see if we need to reload the config registers */
	if ((read_SSCR0(reg) != cr0)
		|| (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
			(cr1 & SSCR1_CHANGE_MASK)) {

1158
		/* stop the SSP, and update the other bits */
1159
		write_SSCR0(cr0 & ~SSCR0_SSE, reg);
1160
		if (!pxa25x_ssp_comp(drv_data))
1161
			write_SSTO(chip->timeout, reg);
1162 1163 1164
		/* first set CR1 without interrupt and service enables */
		write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg);
		/* restart the SSP */
1165
		write_SSCR0(cr0, reg);
1166

1167
	} else {
1168
		if (!pxa25x_ssp_comp(drv_data))
1169
			write_SSTO(chip->timeout, reg);
1170
	}
1171

1172
	cs_assert(drv_data);
1173 1174 1175 1176

	/* after chip select, release the data by enabling service
	 * requests and interrupts, without changing any mode bits */
	write_SSCR1(cr1, reg);
1177 1178
}

1179
static void pump_messages(struct work_struct *work)
1180
{
1181 1182
	struct driver_data *drv_data =
		container_of(work, struct driver_data, pump_messages);
1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209
	unsigned long flags;

	/* Lock queue and check for queue work */
	spin_lock_irqsave(&drv_data->lock, flags);
	if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
		drv_data->busy = 0;
		spin_unlock_irqrestore(&drv_data->lock, flags);
		return;
	}

	/* Make sure we are not already running a message */
	if (drv_data->cur_msg) {
		spin_unlock_irqrestore(&drv_data->lock, flags);
		return;
	}

	/* Extract head of queue */
	drv_data->cur_msg = list_entry(drv_data->queue.next,
					struct spi_message, queue);
	list_del_init(&drv_data->cur_msg->queue);

	/* Initial message state*/
	drv_data->cur_msg->state = START_STATE;
	drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
						struct spi_transfer,
						transfer_list);

1210 1211
	/* prepare to setup the SSP, in pump_transfers, using the per
	 * chip configuration */
1212 1213 1214 1215
	drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);

	/* Mark as busy and launch transfers */
	tasklet_schedule(&drv_data->pump_transfers);
S
Stephen Street 已提交
1216 1217 1218

	drv_data->busy = 1;
	spin_unlock_irqrestore(&drv_data->lock, flags);
1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246
}

static int transfer(struct spi_device *spi, struct spi_message *msg)
{
	struct driver_data *drv_data = spi_master_get_devdata(spi->master);
	unsigned long flags;

	spin_lock_irqsave(&drv_data->lock, flags);

	if (drv_data->run == QUEUE_STOPPED) {
		spin_unlock_irqrestore(&drv_data->lock, flags);
		return -ESHUTDOWN;
	}

	msg->actual_length = 0;
	msg->status = -EINPROGRESS;
	msg->state = START_STATE;

	list_add_tail(&msg->queue, &drv_data->queue);

	if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
		queue_work(drv_data->workqueue, &drv_data->pump_messages);

	spin_unlock_irqrestore(&drv_data->lock, flags);

	return 0;
}

1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284
static int setup_cs(struct spi_device *spi, struct chip_data *chip,
		    struct pxa2xx_spi_chip *chip_info)
{
	int err = 0;

	if (chip == NULL || chip_info == NULL)
		return 0;

	/* NOTE: setup() can be called multiple times, possibly with
	 * different chip_info, release previously requested GPIO
	 */
	if (gpio_is_valid(chip->gpio_cs))
		gpio_free(chip->gpio_cs);

	/* If (*cs_control) is provided, ignore GPIO chip select */
	if (chip_info->cs_control) {
		chip->cs_control = chip_info->cs_control;
		return 0;
	}

	if (gpio_is_valid(chip_info->gpio_cs)) {
		err = gpio_request(chip_info->gpio_cs, "SPI_CS");
		if (err) {
			dev_err(&spi->dev, "failed to request chip select "
					"GPIO%d\n", chip_info->gpio_cs);
			return err;
		}

		chip->gpio_cs = chip_info->gpio_cs;
		chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;

		err = gpio_direction_output(chip->gpio_cs,
					!chip->gpio_cs_inverted);
	}

	return err;
}

1285 1286 1287 1288 1289
static int setup(struct spi_device *spi)
{
	struct pxa2xx_spi_chip *chip_info = NULL;
	struct chip_data *chip;
	struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1290
	struct ssp_device *ssp = drv_data->ssp;
1291
	unsigned int clk_div;
1292 1293
	uint tx_thres = TX_THRESH_DFLT;
	uint rx_thres = RX_THRESH_DFLT;
1294

1295
	if (!pxa25x_ssp_comp(drv_data)
1296 1297 1298 1299
		&& (spi->bits_per_word < 4 || spi->bits_per_word > 32)) {
		dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
				"b/w not 4-32 for type non-PXA25x_SSP\n",
				drv_data->ssp_type, spi->bits_per_word);
1300
		return -EINVAL;
1301
	} else if (pxa25x_ssp_comp(drv_data)
1302 1303 1304 1305 1306
			&& (spi->bits_per_word < 4
				|| spi->bits_per_word > 16)) {
		dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
				"b/w not 4-16 for type PXA25x_SSP\n",
				drv_data->ssp_type, spi->bits_per_word);
1307
		return -EINVAL;
1308
	}
1309

1310
	/* Only alloc on first setup */
1311
	chip = spi_get_ctldata(spi);
1312
	if (!chip) {
1313
		chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1314 1315 1316
		if (!chip) {
			dev_err(&spi->dev,
				"failed setup: can't allocate chip data\n");
1317
			return -ENOMEM;
1318
		}
1319

1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330
		if (drv_data->ssp_type == CE4100_SSP) {
			if (spi->chip_select > 4) {
				dev_err(&spi->dev, "failed setup: "
				"cs number must not be > 4.\n");
				kfree(chip);
				return -EINVAL;
			}

			chip->frm = spi->chip_select;
		} else
			chip->gpio_cs = -1;
1331
		chip->enable_dma = 0;
1332
		chip->timeout = TIMOUT_DFLT;
1333 1334 1335 1336
		chip->dma_burst_size = drv_data->master_info->enable_dma ?
					DCMD_BURST8 : 0;
	}

1337 1338 1339 1340
	/* protocol drivers may change the chip settings, so...
	 * if chip_info exists, use it */
	chip_info = spi->controller_data;

1341
	/* chip_info isn't always needed */
1342
	chip->cr1 = 0;
1343
	if (chip_info) {
1344 1345 1346 1347 1348 1349 1350
		if (chip_info->timeout)
			chip->timeout = chip_info->timeout;
		if (chip_info->tx_threshold)
			tx_thres = chip_info->tx_threshold;
		if (chip_info->rx_threshold)
			rx_thres = chip_info->rx_threshold;
		chip->enable_dma = drv_data->master_info->enable_dma;
1351 1352 1353 1354 1355
		chip->dma_threshold = 0;
		if (chip_info->enable_loopback)
			chip->cr1 = SSCR1_LBM;
	}

1356 1357 1358
	chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
			(SSCR1_TxTresh(tx_thres) & SSCR1_TFT);

1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371
	/* set dma burst and threshold outside of chip_info path so that if
	 * chip_info goes away after setting chip->enable_dma, the
	 * burst and threshold can still respond to changes in bits_per_word */
	if (chip->enable_dma) {
		/* set up legal burst and threshold for dma */
		if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word,
						&chip->dma_burst_size,
						&chip->dma_threshold)) {
			dev_warn(&spi->dev, "in setup: DMA burst size reduced "
					"to match bits_per_word\n");
		}
	}

1372
	clk_div = ssp_get_clk_div(ssp, spi->max_speed_hz);
1373
	chip->speed_hz = spi->max_speed_hz;
1374 1375 1376

	chip->cr0 = clk_div
			| SSCR0_Motorola
S
Stephen Street 已提交
1377 1378
			| SSCR0_DataSize(spi->bits_per_word > 16 ?
				spi->bits_per_word - 16 : spi->bits_per_word)
1379 1380
			| SSCR0_SSE
			| (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
1381 1382 1383
	chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
	chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
			| (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1384 1385

	/* NOTE:  PXA25x_SSP _could_ use external clocking ... */
1386
	if (!pxa25x_ssp_comp(drv_data))
1387
		dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
1388 1389 1390
			clk_get_rate(ssp->clk)
				/ (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)),
			chip->enable_dma ? "DMA" : "PIO");
1391
	else
1392
		dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
1393 1394 1395
			clk_get_rate(ssp->clk) / 2
				/ (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)),
			chip->enable_dma ? "DMA" : "PIO");
1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416

	if (spi->bits_per_word <= 8) {
		chip->n_bytes = 1;
		chip->dma_width = DCMD_WIDTH1;
		chip->read = u8_reader;
		chip->write = u8_writer;
	} else if (spi->bits_per_word <= 16) {
		chip->n_bytes = 2;
		chip->dma_width = DCMD_WIDTH2;
		chip->read = u16_reader;
		chip->write = u16_writer;
	} else if (spi->bits_per_word <= 32) {
		chip->cr0 |= SSCR0_EDSS;
		chip->n_bytes = 4;
		chip->dma_width = DCMD_WIDTH4;
		chip->read = u32_reader;
		chip->write = u32_writer;
	} else {
		dev_err(&spi->dev, "invalid wordsize\n");
		return -ENODEV;
	}
1417
	chip->bits_per_word = spi->bits_per_word;
1418 1419 1420

	spi_set_ctldata(spi, chip);

1421 1422 1423
	if (drv_data->ssp_type == CE4100_SSP)
		return 0;

1424
	return setup_cs(spi, chip, chip_info);
1425 1426
}

1427
static void cleanup(struct spi_device *spi)
1428
{
1429
	struct chip_data *chip = spi_get_ctldata(spi);
1430
	struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1431

1432 1433 1434
	if (!chip)
		return;

1435
	if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
1436 1437
		gpio_free(chip->gpio_cs);

1438 1439 1440
	kfree(chip);
}

1441
static int __devinit init_queue(struct driver_data *drv_data)
1442 1443 1444 1445 1446 1447 1448 1449 1450 1451
{
	INIT_LIST_HEAD(&drv_data->queue);
	spin_lock_init(&drv_data->lock);

	drv_data->run = QUEUE_STOPPED;
	drv_data->busy = 0;

	tasklet_init(&drv_data->pump_transfers,
			pump_transfers,	(unsigned long)drv_data);

1452
	INIT_WORK(&drv_data->pump_messages, pump_messages);
1453
	drv_data->workqueue = create_singlethread_workqueue(
1454
				dev_name(drv_data->master->dev.parent));
1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514
	if (drv_data->workqueue == NULL)
		return -EBUSY;

	return 0;
}

static int start_queue(struct driver_data *drv_data)
{
	unsigned long flags;

	spin_lock_irqsave(&drv_data->lock, flags);

	if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
		spin_unlock_irqrestore(&drv_data->lock, flags);
		return -EBUSY;
	}

	drv_data->run = QUEUE_RUNNING;
	drv_data->cur_msg = NULL;
	drv_data->cur_transfer = NULL;
	drv_data->cur_chip = NULL;
	spin_unlock_irqrestore(&drv_data->lock, flags);

	queue_work(drv_data->workqueue, &drv_data->pump_messages);

	return 0;
}

static int stop_queue(struct driver_data *drv_data)
{
	unsigned long flags;
	unsigned limit = 500;
	int status = 0;

	spin_lock_irqsave(&drv_data->lock, flags);

	/* This is a bit lame, but is optimized for the common execution path.
	 * A wait_queue on the drv_data->busy could be used, but then the common
	 * execution path (pump_messages) would be required to call wake_up or
	 * friends on every SPI message. Do this instead */
	drv_data->run = QUEUE_STOPPED;
	while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
		spin_unlock_irqrestore(&drv_data->lock, flags);
		msleep(10);
		spin_lock_irqsave(&drv_data->lock, flags);
	}

	if (!list_empty(&drv_data->queue) || drv_data->busy)
		status = -EBUSY;

	spin_unlock_irqrestore(&drv_data->lock, flags);

	return status;
}

static int destroy_queue(struct driver_data *drv_data)
{
	int status;

	status = stop_queue(drv_data);
1515 1516 1517 1518 1519 1520
	/* we are unloading the module or failing to load (only two calls
	 * to this routine), and neither call can handle a return value.
	 * However, destroy_workqueue calls flush_workqueue, and that will
	 * block until all work is done.  If the reason that stop_queue
	 * timed out is that the work will never finish, then it does no
	 * good to call destroy_workqueue, so return anyway. */
1521 1522 1523 1524 1525 1526 1527 1528
	if (status != 0)
		return status;

	destroy_workqueue(drv_data->workqueue);

	return 0;
}

1529
static int __devinit pxa2xx_spi_probe(struct platform_device *pdev)
1530 1531 1532 1533
{
	struct device *dev = &pdev->dev;
	struct pxa2xx_spi_master *platform_info;
	struct spi_master *master;
G
Guennadi Liakhovetski 已提交
1534
	struct driver_data *drv_data;
1535
	struct ssp_device *ssp;
G
Guennadi Liakhovetski 已提交
1536
	int status;
1537 1538 1539

	platform_info = dev->platform_data;

H
Haojian Zhuang 已提交
1540
	ssp = pxa_ssp_request(pdev->id, pdev->name);
1541 1542
	if (ssp == NULL) {
		dev_err(&pdev->dev, "failed to request SSP%d\n", pdev->id);
1543 1544 1545 1546 1547 1548
		return -ENODEV;
	}

	/* Allocate master with space for drv_data and null dma buffer */
	master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
	if (!master) {
G
Guennadi Liakhovetski 已提交
1549
		dev_err(&pdev->dev, "cannot alloc spi_master\n");
H
Haojian Zhuang 已提交
1550
		pxa_ssp_free(ssp);
1551 1552 1553 1554 1555 1556
		return -ENOMEM;
	}
	drv_data = spi_master_get_devdata(master);
	drv_data->master = master;
	drv_data->master_info = platform_info;
	drv_data->pdev = pdev;
1557
	drv_data->ssp = ssp;
1558

1559
	/* the spi->mode bits understood by this driver: */
D
Daniel Ribeiro 已提交
1560
	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1561

1562 1563
	master->bus_num = pdev->id;
	master->num_chipselect = platform_info->num_chipselect;
1564
	master->dma_alignment = DMA_ALIGNMENT;
1565 1566 1567 1568
	master->cleanup = cleanup;
	master->setup = setup;
	master->transfer = transfer;

1569
	drv_data->ssp_type = ssp->type;
1570 1571 1572
	drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data +
						sizeof(struct driver_data)), 8);

1573 1574
	drv_data->ioaddr = ssp->mmio_base;
	drv_data->ssdr_physical = ssp->phys_base + SSDR;
1575
	if (pxa25x_ssp_comp(drv_data)) {
1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586
		drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
		drv_data->dma_cr1 = 0;
		drv_data->clear_sr = SSSR_ROR;
		drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
	} else {
		drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
		drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE;
		drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
		drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
	}

1587 1588
	status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
			drv_data);
1589
	if (status < 0) {
G
Guennadi Liakhovetski 已提交
1590
		dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620
		goto out_error_master_alloc;
	}

	/* Setup DMA if requested */
	drv_data->tx_channel = -1;
	drv_data->rx_channel = -1;
	if (platform_info->enable_dma) {

		/* Get two DMA channels	(rx and tx) */
		drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx",
							DMA_PRIO_HIGH,
							dma_handler,
							drv_data);
		if (drv_data->rx_channel < 0) {
			dev_err(dev, "problem (%d) requesting rx channel\n",
				drv_data->rx_channel);
			status = -ENODEV;
			goto out_error_irq_alloc;
		}
		drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx",
							DMA_PRIO_MEDIUM,
							dma_handler,
							drv_data);
		if (drv_data->tx_channel < 0) {
			dev_err(dev, "problem (%d) requesting tx channel\n",
				drv_data->tx_channel);
			status = -ENODEV;
			goto out_error_dma_alloc;
		}

1621 1622
		DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel;
		DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel;
1623 1624 1625
	}

	/* Enable SOC clock */
1626
	clk_enable(ssp->clk);
1627 1628 1629

	/* Load default SSP configuration */
	write_SSCR0(0, drv_data->ioaddr);
1630 1631 1632
	write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
				SSCR1_TxTresh(TX_THRESH_DFLT),
				drv_data->ioaddr);
1633
	write_SSCR0(SSCR0_SCR(2)
1634 1635 1636
			| SSCR0_Motorola
			| SSCR0_DataSize(8),
			drv_data->ioaddr);
1637
	if (!pxa25x_ssp_comp(drv_data))
1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666
		write_SSTO(0, drv_data->ioaddr);
	write_SSPSP(0, drv_data->ioaddr);

	/* Initial and start queue */
	status = init_queue(drv_data);
	if (status != 0) {
		dev_err(&pdev->dev, "problem initializing queue\n");
		goto out_error_clock_enabled;
	}
	status = start_queue(drv_data);
	if (status != 0) {
		dev_err(&pdev->dev, "problem starting queue\n");
		goto out_error_clock_enabled;
	}

	/* Register with the SPI framework */
	platform_set_drvdata(pdev, drv_data);
	status = spi_register_master(master);
	if (status != 0) {
		dev_err(&pdev->dev, "problem registering spi master\n");
		goto out_error_queue_alloc;
	}

	return status;

out_error_queue_alloc:
	destroy_queue(drv_data);

out_error_clock_enabled:
1667
	clk_disable(ssp->clk);
1668 1669 1670 1671 1672 1673 1674 1675

out_error_dma_alloc:
	if (drv_data->tx_channel != -1)
		pxa_free_dma(drv_data->tx_channel);
	if (drv_data->rx_channel != -1)
		pxa_free_dma(drv_data->rx_channel);

out_error_irq_alloc:
1676
	free_irq(ssp->irq, drv_data);
1677 1678 1679

out_error_master_alloc:
	spi_master_put(master);
H
Haojian Zhuang 已提交
1680
	pxa_ssp_free(ssp);
1681 1682 1683 1684 1685 1686
	return status;
}

static int pxa2xx_spi_remove(struct platform_device *pdev)
{
	struct driver_data *drv_data = platform_get_drvdata(pdev);
1687
	struct ssp_device *ssp;
1688 1689 1690 1691
	int status = 0;

	if (!drv_data)
		return 0;
1692
	ssp = drv_data->ssp;
1693 1694 1695 1696

	/* Remove the queue */
	status = destroy_queue(drv_data);
	if (status != 0)
1697 1698 1699 1700 1701 1702 1703 1704 1705 1706
		/* the kernel does not check the return status of this
		 * this routine (mod->exit, within the kernel).  Therefore
		 * nothing is gained by returning from here, the module is
		 * going away regardless, and we should not leave any more
		 * resources allocated than necessary.  We cannot free the
		 * message memory in drv_data->queue, but we can release the
		 * resources below.  I think the kernel should honor -EBUSY
		 * returns but... */
		dev_err(&pdev->dev, "pxa2xx_spi_remove: workqueue will not "
			"complete, message memory not freed\n");
1707 1708 1709

	/* Disable the SSP at the peripheral and SOC level */
	write_SSCR0(0, drv_data->ioaddr);
1710
	clk_disable(ssp->clk);
1711 1712 1713

	/* Release DMA */
	if (drv_data->master_info->enable_dma) {
1714 1715
		DRCMR(ssp->drcmr_rx) = 0;
		DRCMR(ssp->drcmr_tx) = 0;
1716 1717 1718 1719 1720
		pxa_free_dma(drv_data->tx_channel);
		pxa_free_dma(drv_data->rx_channel);
	}

	/* Release IRQ */
1721 1722 1723
	free_irq(ssp->irq, drv_data);

	/* Release SSP */
H
Haojian Zhuang 已提交
1724
	pxa_ssp_free(ssp);
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	/* Disconnect from the SPI framework */
	spi_unregister_master(drv_data->master);

	/* Prevent double remove */
	platform_set_drvdata(pdev, NULL);

	return 0;
}

static void pxa2xx_spi_shutdown(struct platform_device *pdev)
{
	int status = 0;

	if ((status = pxa2xx_spi_remove(pdev)) != 0)
		dev_err(&pdev->dev, "shutdown failed with %d\n", status);
}

#ifdef CONFIG_PM
1744
static int pxa2xx_spi_suspend(struct device *dev)
1745
{
1746
	struct driver_data *drv_data = dev_get_drvdata(dev);
1747
	struct ssp_device *ssp = drv_data->ssp;
1748 1749 1750 1751 1752 1753
	int status = 0;

	status = stop_queue(drv_data);
	if (status != 0)
		return status;
	write_SSCR0(0, drv_data->ioaddr);
1754
	clk_disable(ssp->clk);
1755 1756 1757 1758

	return 0;
}

1759
static int pxa2xx_spi_resume(struct device *dev)
1760
{
1761
	struct driver_data *drv_data = dev_get_drvdata(dev);
1762
	struct ssp_device *ssp = drv_data->ssp;
1763 1764
	int status = 0;

1765 1766 1767 1768 1769 1770 1771
	if (drv_data->rx_channel != -1)
		DRCMR(drv_data->ssp->drcmr_rx) =
			DRCMR_MAPVLD | drv_data->rx_channel;
	if (drv_data->tx_channel != -1)
		DRCMR(drv_data->ssp->drcmr_tx) =
			DRCMR_MAPVLD | drv_data->tx_channel;

1772
	/* Enable the SSP clock */
1773
	clk_enable(ssp->clk);
1774 1775 1776 1777

	/* Start the queue running */
	status = start_queue(drv_data);
	if (status != 0) {
1778
		dev_err(dev, "problem starting queue (%d)\n", status);
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		return status;
	}

	return 0;
}
1784

1785
static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
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	.suspend	= pxa2xx_spi_suspend,
	.resume		= pxa2xx_spi_resume,
};
#endif
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static struct platform_driver driver = {
	.driver = {
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		.name	= "pxa2xx-spi",
		.owner	= THIS_MODULE,
#ifdef CONFIG_PM
		.pm	= &pxa2xx_spi_pm_ops,
#endif
1798
	},
1799
	.probe = pxa2xx_spi_probe,
1800
	.remove = pxa2xx_spi_remove,
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	.shutdown = pxa2xx_spi_shutdown,
};

static int __init pxa2xx_spi_init(void)
{
1806
	return platform_driver_register(&driver);
1807
}
A
Antonio Ospite 已提交
1808
subsys_initcall(pxa2xx_spi_init);
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static void __exit pxa2xx_spi_exit(void)
{
	platform_driver_unregister(&driver);
}
module_exit(pxa2xx_spi_exit);