mmci.c 46.6 KB
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/*
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 *  linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
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 *
 *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
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 *  Copyright (C) 2010 ST-Ericsson SA
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 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/device.h>
#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
#include <linux/err.h>
#include <linux/highmem.h>
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#include <linux/log2.h>
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#include <linux/mmc/pm.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/card.h>
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#include <linux/amba/bus.h>
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#include <linux/clk.h>
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#include <linux/scatterlist.h>
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#include <linux/gpio.h>
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#include <linux/of_gpio.h>
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#include <linux/regulator/consumer.h>
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#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/amba/mmci.h>
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#include <linux/pm_runtime.h>
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#include <linux/types.h>
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#include <linux/pinctrl/consumer.h>
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#include <asm/div64.h>
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#include <asm/io.h>
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#include <asm/sizes.h>
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#include "mmci.h"

#define DRIVER_NAME "mmci-pl18x"

static unsigned int fmax = 515633;

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/**
 * struct variant_data - MMCI variant-specific quirks
 * @clkreg: default value for MCICLOCK register
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 * @clkreg_enable: enable value for MMCICLOCK register
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 * @datalength_bits: number of bits in the MMCIDATALENGTH register
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 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
 *	      is asserted (likewise for RX)
 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
 *		  is asserted (likewise for RX)
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 * @sdio: variant supports SDIO
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 * @st_clkdiv: true if using a ST-specific clock divider algorithm
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 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
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 * @pwrreg_powerup: power up value for MMCIPOWER register
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 * @signal_direction: input/out direction of bus signals can be indicated
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 * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
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 * @busy_detect: true if busy detection on dat0 is supported
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 * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
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 */
struct variant_data {
	unsigned int		clkreg;
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	unsigned int		clkreg_enable;
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	unsigned int		datalength_bits;
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	unsigned int		fifosize;
	unsigned int		fifohalfsize;
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	bool			sdio;
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	bool			st_clkdiv;
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	bool			blksz_datactrl16;
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	u32			pwrreg_powerup;
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	bool			signal_direction;
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	bool			pwrreg_clkgate;
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	bool			busy_detect;
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	bool			pwrreg_nopower;
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};

static struct variant_data variant_arm = {
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	.fifosize		= 16 * 4,
	.fifohalfsize		= 8 * 4,
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	.datalength_bits	= 16,
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	.pwrreg_powerup		= MCI_PWR_UP,
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};

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static struct variant_data variant_arm_extended_fifo = {
	.fifosize		= 128 * 4,
	.fifohalfsize		= 64 * 4,
	.datalength_bits	= 16,
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	.pwrreg_powerup		= MCI_PWR_UP,
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};

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static struct variant_data variant_arm_extended_fifo_hwfc = {
	.fifosize		= 128 * 4,
	.fifohalfsize		= 64 * 4,
	.clkreg_enable		= MCI_ARM_HWFCEN,
	.datalength_bits	= 16,
	.pwrreg_powerup		= MCI_PWR_UP,
};

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static struct variant_data variant_u300 = {
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	.fifosize		= 16 * 4,
	.fifohalfsize		= 8 * 4,
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	.clkreg_enable		= MCI_ST_U300_HWFCEN,
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	.datalength_bits	= 16,
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	.sdio			= true,
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	.pwrreg_powerup		= MCI_PWR_ON,
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	.signal_direction	= true,
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	.pwrreg_clkgate		= true,
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	.pwrreg_nopower		= true,
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};

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static struct variant_data variant_nomadik = {
	.fifosize		= 16 * 4,
	.fifohalfsize		= 8 * 4,
	.clkreg			= MCI_CLK_ENABLE,
	.datalength_bits	= 24,
	.sdio			= true,
	.st_clkdiv		= true,
	.pwrreg_powerup		= MCI_PWR_ON,
	.signal_direction	= true,
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	.pwrreg_clkgate		= true,
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	.pwrreg_nopower		= true,
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};

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static struct variant_data variant_ux500 = {
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	.fifosize		= 30 * 4,
	.fifohalfsize		= 8 * 4,
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	.clkreg			= MCI_CLK_ENABLE,
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	.clkreg_enable		= MCI_ST_UX500_HWFCEN,
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	.datalength_bits	= 24,
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	.sdio			= true,
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	.st_clkdiv		= true,
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	.pwrreg_powerup		= MCI_PWR_ON,
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	.signal_direction	= true,
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	.pwrreg_clkgate		= true,
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	.busy_detect		= true,
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	.pwrreg_nopower		= true,
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};
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static struct variant_data variant_ux500v2 = {
	.fifosize		= 30 * 4,
	.fifohalfsize		= 8 * 4,
	.clkreg			= MCI_CLK_ENABLE,
	.clkreg_enable		= MCI_ST_UX500_HWFCEN,
	.datalength_bits	= 24,
	.sdio			= true,
	.st_clkdiv		= true,
	.blksz_datactrl16	= true,
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	.pwrreg_powerup		= MCI_PWR_ON,
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	.signal_direction	= true,
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	.pwrreg_clkgate		= true,
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	.busy_detect		= true,
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	.pwrreg_nopower		= true,
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};

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static int mmci_card_busy(struct mmc_host *mmc)
{
	struct mmci_host *host = mmc_priv(mmc);
	unsigned long flags;
	int busy = 0;

	pm_runtime_get_sync(mmc_dev(mmc));

	spin_lock_irqsave(&host->lock, flags);
	if (readl(host->base + MMCISTATUS) & MCI_ST_CARDBUSY)
		busy = 1;
	spin_unlock_irqrestore(&host->lock, flags);

	pm_runtime_mark_last_busy(mmc_dev(mmc));
	pm_runtime_put_autosuspend(mmc_dev(mmc));

	return busy;
}

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/*
 * Validate mmc prerequisites
 */
static int mmci_validate_data(struct mmci_host *host,
			      struct mmc_data *data)
{
	if (!data)
		return 0;

	if (!is_power_of_2(data->blksz)) {
		dev_err(mmc_dev(host->mmc),
			"unsupported block size (%d bytes)\n", data->blksz);
		return -EINVAL;
	}

	return 0;
}

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static void mmci_reg_delay(struct mmci_host *host)
{
	/*
	 * According to the spec, at least three feedback clock cycles
	 * of max 52 MHz must pass between two writes to the MMCICLOCK reg.
	 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes.
	 * Worst delay time during card init is at 100 kHz => 30 us.
	 * Worst delay time when up and running is at 25 MHz => 120 ns.
	 */
	if (host->cclk < 25000000)
		udelay(30);
	else
		ndelay(120);
}

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/*
 * This must be called with host->lock held
 */
static void mmci_write_clkreg(struct mmci_host *host, u32 clk)
{
	if (host->clk_reg != clk) {
		host->clk_reg = clk;
		writel(clk, host->base + MMCICLOCK);
	}
}

/*
 * This must be called with host->lock held
 */
static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
{
	if (host->pwr_reg != pwr) {
		host->pwr_reg = pwr;
		writel(pwr, host->base + MMCIPOWER);
	}
}

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/*
 * This must be called with host->lock held
 */
static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
{
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	/* Keep ST Micro busy mode if enabled */
	datactrl |= host->datactrl_reg & MCI_ST_DPSM_BUSYMODE;

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	if (host->datactrl_reg != datactrl) {
		host->datactrl_reg = datactrl;
		writel(datactrl, host->base + MMCIDATACTRL);
	}
}

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/*
 * This must be called with host->lock held
 */
static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
{
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	struct variant_data *variant = host->variant;
	u32 clk = variant->clkreg;
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	/* Make sure cclk reflects the current calculated clock */
	host->cclk = 0;

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	if (desired) {
		if (desired >= host->mclk) {
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			clk = MCI_CLK_BYPASS;
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			if (variant->st_clkdiv)
				clk |= MCI_ST_UX500_NEG_EDGE;
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			host->cclk = host->mclk;
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		} else if (variant->st_clkdiv) {
			/*
			 * DB8500 TRM says f = mclk / (clkdiv + 2)
			 * => clkdiv = (mclk / f) - 2
			 * Round the divider up so we don't exceed the max
			 * frequency
			 */
			clk = DIV_ROUND_UP(host->mclk, desired) - 2;
			if (clk >= 256)
				clk = 255;
			host->cclk = host->mclk / (clk + 2);
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		} else {
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			/*
			 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
			 * => clkdiv = mclk / (2 * f) - 1
			 */
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			clk = host->mclk / (2 * desired) - 1;
			if (clk >= 256)
				clk = 255;
			host->cclk = host->mclk / (2 * (clk + 1));
		}
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		clk |= variant->clkreg_enable;
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		clk |= MCI_CLK_ENABLE;
		/* This hasn't proven to be worthwhile */
		/* clk |= MCI_CLK_PWRSAVE; */
	}

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	/* Set actual clock for debug */
	host->mmc->actual_clock = host->cclk;

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	if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
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		clk |= MCI_4BIT_BUS;
	if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
		clk |= MCI_ST_8BIT_BUS;
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	if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
		clk |= MCI_ST_UX500_NEG_EDGE;

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	mmci_write_clkreg(host, clk);
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}

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static void
mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
{
	writel(0, host->base + MMCICOMMAND);

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	BUG_ON(host->data);

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	host->mrq = NULL;
	host->cmd = NULL;

	mmc_request_done(host->mmc, mrq);
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	pm_runtime_mark_last_busy(mmc_dev(host->mmc));
	pm_runtime_put_autosuspend(mmc_dev(host->mmc));
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}

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static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
{
	void __iomem *base = host->base;

	if (host->singleirq) {
		unsigned int mask0 = readl(base + MMCIMASK0);

		mask0 &= ~MCI_IRQ1MASK;
		mask0 |= mask;

		writel(mask0, base + MMCIMASK0);
	}

	writel(mask, base + MMCIMASK1);
}

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static void mmci_stop_data(struct mmci_host *host)
{
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	mmci_write_datactrlreg(host, 0);
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	mmci_set_mask1(host, 0);
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	host->data = NULL;
}

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static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
{
	unsigned int flags = SG_MITER_ATOMIC;

	if (data->flags & MMC_DATA_READ)
		flags |= SG_MITER_TO_SG;
	else
		flags |= SG_MITER_FROM_SG;

	sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
}

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/*
 * All the DMA operation mode stuff goes inside this ifdef.
 * This assumes that you have a generic DMA device interface,
 * no custom DMA interfaces are supported.
 */
#ifdef CONFIG_DMA_ENGINE
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static void mmci_dma_setup(struct mmci_host *host)
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{
	struct mmci_platform_data *plat = host->plat;
	const char *rxname, *txname;
	dma_cap_mask_t mask;

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	host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx");
	host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx");
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	/* initialize pre request cookie */
	host->next_data.cookie = 1;

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	/* Try to acquire a generic DMA engine slave channel */
	dma_cap_zero(mask);
	dma_cap_set(DMA_SLAVE, mask);

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	if (plat && plat->dma_filter) {
		if (!host->dma_rx_channel && plat->dma_rx_param) {
			host->dma_rx_channel = dma_request_channel(mask,
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							   plat->dma_filter,
							   plat->dma_rx_param);
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			/* E.g if no DMA hardware is present */
			if (!host->dma_rx_channel)
				dev_err(mmc_dev(host->mmc), "no RX DMA channel\n");
		}
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		if (!host->dma_tx_channel && plat->dma_tx_param) {
			host->dma_tx_channel = dma_request_channel(mask,
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							   plat->dma_filter,
							   plat->dma_tx_param);
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			if (!host->dma_tx_channel)
				dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n");
		}
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	}

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	/*
	 * If only an RX channel is specified, the driver will
	 * attempt to use it bidirectionally, however if it is
	 * is specified but cannot be located, DMA will be disabled.
	 */
	if (host->dma_rx_channel && !host->dma_tx_channel)
		host->dma_tx_channel = host->dma_rx_channel;

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	if (host->dma_rx_channel)
		rxname = dma_chan_name(host->dma_rx_channel);
	else
		rxname = "none";

	if (host->dma_tx_channel)
		txname = dma_chan_name(host->dma_tx_channel);
	else
		txname = "none";

	dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
		 rxname, txname);

	/*
	 * Limit the maximum segment size in any SG entry according to
	 * the parameters of the DMA engine device.
	 */
	if (host->dma_tx_channel) {
		struct device *dev = host->dma_tx_channel->device->dev;
		unsigned int max_seg_size = dma_get_max_seg_size(dev);

		if (max_seg_size < host->mmc->max_seg_size)
			host->mmc->max_seg_size = max_seg_size;
	}
	if (host->dma_rx_channel) {
		struct device *dev = host->dma_rx_channel->device->dev;
		unsigned int max_seg_size = dma_get_max_seg_size(dev);

		if (max_seg_size < host->mmc->max_seg_size)
			host->mmc->max_seg_size = max_seg_size;
	}
}

/*
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 * This is used in or so inline it
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 * so it can be discarded.
 */
static inline void mmci_dma_release(struct mmci_host *host)
{
	struct mmci_platform_data *plat = host->plat;

	if (host->dma_rx_channel)
		dma_release_channel(host->dma_rx_channel);
	if (host->dma_tx_channel && plat->dma_tx_param)
		dma_release_channel(host->dma_tx_channel);
	host->dma_rx_channel = host->dma_tx_channel = NULL;
}

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static void mmci_dma_data_error(struct mmci_host *host)
{
	dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
	dmaengine_terminate_all(host->dma_current);
	host->dma_current = NULL;
	host->dma_desc_current = NULL;
	host->data->host_cookie = 0;
}

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static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
{
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	struct dma_chan *chan;
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	enum dma_data_direction dir;
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	if (data->flags & MMC_DATA_READ) {
		dir = DMA_FROM_DEVICE;
		chan = host->dma_rx_channel;
	} else {
		dir = DMA_TO_DEVICE;
		chan = host->dma_tx_channel;
	}

	dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
}

static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data)
{
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	u32 status;
	int i;

	/* Wait up to 1ms for the DMA to complete */
	for (i = 0; ; i++) {
		status = readl(host->base + MMCISTATUS);
		if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
			break;
		udelay(10);
	}

	/*
	 * Check to see whether we still have some data left in the FIFO -
	 * this catches DMA controllers which are unable to monitor the
	 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
	 * contiguous buffers.  On TX, we'll get a FIFO underrun error.
	 */
	if (status & MCI_RXDATAAVLBLMASK) {
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		mmci_dma_data_error(host);
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		if (!data->error)
			data->error = -EIO;
	}

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	if (!data->host_cookie)
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		mmci_dma_unmap(host, data);
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	/*
	 * Use of DMA with scatter-gather is impossible.
	 * Give up with DMA and switch back to PIO mode.
	 */
	if (status & MCI_RXDATAAVLBLMASK) {
		dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
		mmci_dma_release(host);
	}

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	host->dma_current = NULL;
	host->dma_desc_current = NULL;
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}

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/* prepares DMA channel and DMA descriptor, returns non-zero on failure */
static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data,
				struct dma_chan **dma_chan,
				struct dma_async_tx_descriptor **dma_desc)
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{
	struct variant_data *variant = host->variant;
	struct dma_slave_config conf = {
		.src_addr = host->phybase + MMCIFIFO,
		.dst_addr = host->phybase + MMCIFIFO,
		.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
		.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
		.src_maxburst = variant->fifohalfsize >> 2, /* # of words */
		.dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
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		.device_fc = false,
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	};
	struct dma_chan *chan;
	struct dma_device *device;
	struct dma_async_tx_descriptor *desc;
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	enum dma_data_direction buffer_dirn;
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	int nr_sg;

	if (data->flags & MMC_DATA_READ) {
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		conf.direction = DMA_DEV_TO_MEM;
		buffer_dirn = DMA_FROM_DEVICE;
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		chan = host->dma_rx_channel;
	} else {
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		conf.direction = DMA_MEM_TO_DEV;
		buffer_dirn = DMA_TO_DEVICE;
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		chan = host->dma_tx_channel;
	}

	/* If there's no DMA channel, fall back to PIO */
	if (!chan)
		return -EINVAL;

	/* If less than or equal to the fifo size, don't bother with DMA */
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	if (data->blksz * data->blocks <= variant->fifosize)
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		return -EINVAL;

	device = chan->device;
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	nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
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	if (nr_sg == 0)
		return -EINVAL;

	dmaengine_slave_config(chan, &conf);
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	desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg,
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					    conf.direction, DMA_CTRL_ACK);
	if (!desc)
		goto unmap_exit;

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	*dma_chan = chan;
	*dma_desc = desc;
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	return 0;
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 unmap_exit:
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	dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
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	return -ENOMEM;
}

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static inline int mmci_dma_prep_data(struct mmci_host *host,
				     struct mmc_data *data)
{
	/* Check if next job is already prepared. */
	if (host->dma_current && host->dma_desc_current)
		return 0;

	/* No job were prepared thus do it now. */
	return __mmci_dma_prep_data(host, data, &host->dma_current,
				    &host->dma_desc_current);
}

static inline int mmci_dma_prep_next(struct mmci_host *host,
				     struct mmc_data *data)
{
	struct mmci_host_next *nd = &host->next_data;
	return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc);
}

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static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
{
	int ret;
	struct mmc_data *data = host->data;

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	ret = mmci_dma_prep_data(host, host->data);
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	if (ret)
		return ret;

	/* Okay, go for it. */
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	dev_vdbg(mmc_dev(host->mmc),
		 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
		 data->sg_len, data->blksz, data->blocks, data->flags);
614 615
	dmaengine_submit(host->dma_desc_current);
	dma_async_issue_pending(host->dma_current);
616 617 618 619

	datactrl |= MCI_DPSM_DMAENABLE;

	/* Trigger the DMA transfer */
620
	mmci_write_datactrlreg(host, datactrl);
621 622 623 624 625 626 627 628 629

	/*
	 * Let the MMCI say when the data is ended and it's time
	 * to fire next DMA request. When that happens, MMCI will
	 * call mmci_data_end()
	 */
	writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
	       host->base + MMCIMASK0);
	return 0;
630
}
631

632 633 634 635
static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
{
	struct mmci_host_next *next = &host->next_data;

636 637
	WARN_ON(data->host_cookie && data->host_cookie != next->cookie);
	WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan));
638 639 640 641 642

	host->dma_desc_current = next->dma_desc;
	host->dma_current = next->dma_chan;
	next->dma_desc = NULL;
	next->dma_chan = NULL;
643
}
644 645 646 647 648 649 650 651 652 653 654

static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq,
			     bool is_first_req)
{
	struct mmci_host *host = mmc_priv(mmc);
	struct mmc_data *data = mrq->data;
	struct mmci_host_next *nd = &host->next_data;

	if (!data)
		return;

655 656 657
	BUG_ON(data->host_cookie);

	if (mmci_validate_data(host, data))
658 659
		return;

660 661
	if (!mmci_dma_prep_next(host, data))
		data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie;
662 663 664 665 666 667 668 669
}

static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
			      int err)
{
	struct mmci_host *host = mmc_priv(mmc);
	struct mmc_data *data = mrq->data;

670
	if (!data || !data->host_cookie)
671 672
		return;

673
	mmci_dma_unmap(host, data);
674

675 676 677 678 679 680 681 682
	if (err) {
		struct mmci_host_next *next = &host->next_data;
		struct dma_chan *chan;
		if (data->flags & MMC_DATA_READ)
			chan = host->dma_rx_channel;
		else
			chan = host->dma_tx_channel;
		dmaengine_terminate_all(chan);
683

684 685
		next->dma_desc = NULL;
		next->dma_chan = NULL;
686 687 688
	}
}

689 690
#else
/* Blank functions if the DMA engine is not available */
691 692 693
static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
{
}
694 695 696 697 698 699 700 701 702 703 704 705
static inline void mmci_dma_setup(struct mmci_host *host)
{
}

static inline void mmci_dma_release(struct mmci_host *host)
{
}

static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
{
}

706 707 708 709 710
static inline void mmci_dma_finalize(struct mmci_host *host,
				     struct mmc_data *data)
{
}

711 712 713 714 715 716 717 718
static inline void mmci_dma_data_error(struct mmci_host *host)
{
}

static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
{
	return -ENOSYS;
}
719 720 721 722

#define mmci_pre_request NULL
#define mmci_post_request NULL

723 724
#endif

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static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
{
727
	struct variant_data *variant = host->variant;
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	unsigned int datactrl, timeout, irqmask;
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	unsigned long long clks;
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	void __iomem *base;
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	int blksz_bits;
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	dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
		data->blksz, data->blocks, data->flags);
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	host->data = data;
737
	host->size = data->blksz * data->blocks;
738
	data->bytes_xfered = 0;
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	clks = (unsigned long long)data->timeout_ns * host->cclk;
	do_div(clks, 1000000000UL);

	timeout = data->timeout_clks + (unsigned int)clks;
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	base = host->base;
	writel(timeout, base + MMCIDATATIMER);
	writel(host->size, base + MMCIDATALENGTH);

749 750 751
	blksz_bits = ffs(data->blksz) - 1;
	BUG_ON(1 << blksz_bits != data->blksz);

752 753 754 755
	if (variant->blksz_datactrl16)
		datactrl = MCI_DPSM_ENABLE | (data->blksz << 16);
	else
		datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
756 757

	if (data->flags & MMC_DATA_READ)
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		datactrl |= MCI_DPSM_DIRECTION;
759

760 761
	/* The ST Micro variants has a special bit to enable SDIO */
	if (variant->sdio && host->mmc->card)
762 763 764 765 766 767 768
		if (mmc_card_sdio(host->mmc->card)) {
			/*
			 * The ST Micro variants has a special bit
			 * to enable SDIO.
			 */
			u32 clk;

769 770
			datactrl |= MCI_ST_DPSM_SDIOEN;

771
			/*
772 773 774 775
			 * The ST Micro variant for SDIO small write transfers
			 * needs to have clock H/W flow control disabled,
			 * otherwise the transfer will not start. The threshold
			 * depends on the rate of MCLK.
776
			 */
777 778 779
			if (data->flags & MMC_DATA_WRITE &&
			    (host->size < 8 ||
			     (host->size <= 8 && host->mclk > 50000000)))
780 781 782 783 784 785 786
				clk = host->clk_reg & ~variant->clkreg_enable;
			else
				clk = host->clk_reg | variant->clkreg_enable;

			mmci_write_clkreg(host, clk);
		}

787 788 789
	if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
		datactrl |= MCI_ST_DPSM_DDRMODE;

790 791 792 793 794 795 796 797 798 799 800
	/*
	 * Attempt to use DMA operation mode, if this
	 * should fail, fall back to PIO mode
	 */
	if (!mmci_dma_start_data(host, datactrl))
		return;

	/* IRQ mode, map the SG list for CPU reading/writing */
	mmci_init_sg(host, data);

	if (data->flags & MMC_DATA_READ) {
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		irqmask = MCI_RXFIFOHALFFULLMASK;
802 803

		/*
804 805 806
		 * If we have less than the fifo 'half-full' threshold to
		 * transfer, trigger a PIO interrupt as soon as any data
		 * is available.
807
		 */
808
		if (host->size < variant->fifohalfsize)
809
			irqmask |= MCI_RXDATAAVLBLMASK;
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	} else {
		/*
		 * We don't actually need to include "FIFO empty" here
		 * since its implicit in "FIFO half empty".
		 */
		irqmask = MCI_TXFIFOHALFEMPTYMASK;
	}

818
	mmci_write_datactrlreg(host, datactrl);
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	writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
820
	mmci_set_mask1(host, irqmask);
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}

static void
mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
{
	void __iomem *base = host->base;

828
	dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
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	    cmd->opcode, cmd->arg, cmd->flags);

	if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
		writel(0, base + MMCICOMMAND);
		udelay(1);
	}

	c |= cmd->opcode | MCI_CPSM_ENABLE;
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	if (cmd->flags & MMC_RSP_PRESENT) {
		if (cmd->flags & MMC_RSP_136)
			c |= MCI_CPSM_LONGRSP;
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		c |= MCI_CPSM_RESPONSE;
	}
	if (/*interrupt*/0)
		c |= MCI_CPSM_INTERRUPT;

	host->cmd = cmd;

	writel(cmd->arg, base + MMCIARGUMENT);
	writel(c, base + MMCICOMMAND);
}

static void
mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
	      unsigned int status)
{
855
	/* First check for errors */
856 857
	if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
		      MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
858
		u32 remain, success;
859

860
		/* Terminate the DMA transfer */
861
		if (dma_inprogress(host)) {
862
			mmci_dma_data_error(host);
863 864
			mmci_dma_unmap(host, data);
		}
865 866

		/*
867 868 869 870 871
		 * Calculate how far we are into the transfer.  Note that
		 * the data counter gives the number of bytes transferred
		 * on the MMC bus, not on the host side.  On reads, this
		 * can be as much as a FIFO-worth of data ahead.  This
		 * matters for FIFO overruns only.
872
		 */
873
		remain = readl(host->base + MMCIDATACNT);
874 875
		success = data->blksz * data->blocks - remain;

876 877
		dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
			status, success);
878 879
		if (status & MCI_DATACRCFAIL) {
			/* Last block was not successful */
880
			success -= 1;
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			data->error = -EILSEQ;
882
		} else if (status & MCI_DATATIMEOUT) {
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			data->error = -ETIMEDOUT;
884 885
		} else if (status & MCI_STARTBITERR) {
			data->error = -ECOMM;
886 887 888 889 890 891 892
		} else if (status & MCI_TXUNDERRUN) {
			data->error = -EIO;
		} else if (status & MCI_RXOVERRUN) {
			if (success > host->variant->fifosize)
				success -= host->variant->fifosize;
			else
				success = 0;
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			data->error = -EIO;
894
		}
895
		data->bytes_xfered = round_down(success, data->blksz);
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	}
897

898 899
	if (status & MCI_DATABLOCKEND)
		dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
900

901
	if (status & MCI_DATAEND || data->error) {
902
		if (dma_inprogress(host))
903
			mmci_dma_finalize(host, data);
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		mmci_stop_data(host);

906 907
		if (!data->error)
			/* The error clause is handled above, success! */
908
			data->bytes_xfered = data->blksz * data->blocks;
909

910
		if (!data->stop || host->mrq->sbc) {
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			mmci_request_end(host, data->mrq);
		} else {
			mmci_start_command(host, data->stop, 0);
		}
	}
}

static void
mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
	     unsigned int status)
{
	void __iomem *base = host->base;
923
	bool sbc = (cmd == host->mrq->sbc);
924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946
	bool busy_resp = host->variant->busy_detect &&
			(cmd->flags & MMC_RSP_BUSY);

	/* Check if we need to wait for busy completion. */
	if (host->busy_status && (status & MCI_ST_CARDBUSY))
		return;

	/* Enable busy completion if needed and supported. */
	if (!host->busy_status && busy_resp &&
		!(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) &&
		(readl(base + MMCISTATUS) & MCI_ST_CARDBUSY)) {
		writel(readl(base + MMCIMASK0) | MCI_ST_BUSYEND,
			base + MMCIMASK0);
		host->busy_status = status & (MCI_CMDSENT|MCI_CMDRESPEND);
		return;
	}

	/* At busy completion, mask the IRQ and complete the request. */
	if (host->busy_status) {
		writel(readl(base + MMCIMASK0) & ~MCI_ST_BUSYEND,
			base + MMCIMASK0);
		host->busy_status = 0;
	}
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	host->cmd = NULL;

	if (status & MCI_CMDTIMEOUT) {
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		cmd->error = -ETIMEDOUT;
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	} else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
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		cmd->error = -EILSEQ;
954 955 956 957 958
	} else {
		cmd->resp[0] = readl(base + MMCIRESPONSE0);
		cmd->resp[1] = readl(base + MMCIRESPONSE1);
		cmd->resp[2] = readl(base + MMCIRESPONSE2);
		cmd->resp[3] = readl(base + MMCIRESPONSE3);
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	}

961
	if ((!sbc && !cmd->data) || cmd->error) {
962 963
		if (host->data) {
			/* Terminate the DMA transfer */
964
			if (dma_inprogress(host)) {
965
				mmci_dma_data_error(host);
966 967
				mmci_dma_unmap(host, host->data);
			}
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			mmci_stop_data(host);
969
		}
970 971 972
		mmci_request_end(host, host->mrq);
	} else if (sbc) {
		mmci_start_command(host, host->mrq->cmd, 0);
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	} else if (!(cmd->data->flags & MMC_DATA_READ)) {
		mmci_start_data(host, cmd->data);
	}
}

static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
{
	void __iomem *base = host->base;
	char *ptr = buffer;
	u32 status;
983
	int host_remain = host->size;
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	do {
986
		int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
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		if (count > remain)
			count = remain;

		if (count <= 0)
			break;

994 995 996 997 998 999 1000 1001 1002
		/*
		 * SDIO especially may want to send something that is
		 * not divisible by 4 (as opposed to card sectors
		 * etc). Therefore make sure to always read the last bytes
		 * while only doing full 32-bit reads towards the FIFO.
		 */
		if (unlikely(count & 0x3)) {
			if (count < 4) {
				unsigned char buf[4];
1003
				ioread32_rep(base + MMCIFIFO, buf, 1);
1004 1005
				memcpy(ptr, buf, count);
			} else {
1006
				ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
1007 1008 1009
				count &= ~0x3;
			}
		} else {
1010
			ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
1011
		}
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		ptr += count;
		remain -= count;
1015
		host_remain -= count;
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		if (remain == 0)
			break;

		status = readl(base + MMCISTATUS);
	} while (status & MCI_RXDATAAVLBL);

	return ptr - buffer;
}

static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
{
1028
	struct variant_data *variant = host->variant;
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	void __iomem *base = host->base;
	char *ptr = buffer;

	do {
		unsigned int count, maxcnt;

1035 1036
		maxcnt = status & MCI_TXFIFOEMPTY ?
			 variant->fifosize : variant->fifohalfsize;
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		count = min(remain, maxcnt);

1039 1040 1041 1042 1043 1044 1045 1046
		/*
		 * SDIO especially may want to send something that is
		 * not divisible by 4 (as opposed to card sectors
		 * etc), and the FIFO only accept full 32-bit writes.
		 * So compensate by adding +3 on the count, a single
		 * byte become a 32bit write, 7 bytes will be two
		 * 32bit writes etc.
		 */
1047
		iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2);
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		ptr += count;
		remain -= count;

		if (remain == 0)
			break;

		status = readl(base + MMCISTATUS);
	} while (status & MCI_TXFIFOHALFEMPTY);

	return ptr - buffer;
}

/*
 * PIO data transfer IRQ handler.
 */
1064
static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
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{
	struct mmci_host *host = dev_id;
1067
	struct sg_mapping_iter *sg_miter = &host->sg_miter;
1068
	struct variant_data *variant = host->variant;
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	void __iomem *base = host->base;
1070
	unsigned long flags;
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	u32 status;

	status = readl(base + MMCISTATUS);

1075
	dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
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1077 1078
	local_irq_save(flags);

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	do {
		unsigned int remain, len;
		char *buffer;

		/*
		 * For write, we only need to test the half-empty flag
		 * here - if the FIFO is completely empty, then by
		 * definition it is more than half empty.
		 *
		 * For read, check for data available.
		 */
		if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
			break;

1093 1094 1095 1096 1097
		if (!sg_miter_next(sg_miter))
			break;

		buffer = sg_miter->addr;
		remain = sg_miter->length;
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		len = 0;
		if (status & MCI_RXACTIVE)
			len = mmci_pio_read(host, buffer, remain);
		if (status & MCI_TXACTIVE)
			len = mmci_pio_write(host, buffer, remain, status);

1105
		sg_miter->consumed = len;
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		host->size -= len;
		remain -= len;

		if (remain)
			break;

		status = readl(base + MMCISTATUS);
	} while (1);

1116 1117 1118 1119
	sg_miter_stop(sg_miter);

	local_irq_restore(flags);

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	/*
1121 1122
	 * If we have less than the fifo 'half-full' threshold to transfer,
	 * trigger a PIO interrupt as soon as any data is available.
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	 */
1124
	if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
1125
		mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
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	/*
	 * If we run out of data, disable the data IRQs; this
	 * prevents a race where the FIFO becomes empty before
	 * the chip itself has disabled the data path, and
	 * stops us racing with our data end IRQ.
	 */
	if (host->size == 0) {
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		mmci_set_mask1(host, 0);
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		writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
	}

	return IRQ_HANDLED;
}

/*
 * Handle completion of command and data transfers.
 */
1144
static irqreturn_t mmci_irq(int irq, void *dev_id)
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{
	struct mmci_host *host = dev_id;
	u32 status;
	int ret = 0;

	spin_lock(&host->lock);

	do {
		struct mmc_command *cmd;
		struct mmc_data *data;

		status = readl(host->base + MMCISTATUS);
1157 1158 1159 1160 1161 1162 1163 1164

		if (host->singleirq) {
			if (status & readl(host->base + MMCIMASK1))
				mmci_pio_irq(irq, dev_id);

			status &= ~MCI_IRQ1MASK;
		}

1165 1166 1167 1168 1169
		/*
		 * We intentionally clear the MCI_ST_CARDBUSY IRQ here (if it's
		 * enabled) since the HW seems to be triggering the IRQ on both
		 * edges while monitoring DAT0 for busy completion.
		 */
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		status &= readl(host->base + MMCIMASK0);
		writel(status, host->base + MMCICLEAR);

1173
		dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
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1175
		cmd = host->cmd;
1176 1177
		if ((status|host->busy_status) & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|
			MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
1178 1179
			mmci_cmd_irq(host, cmd, status);

L
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1180
		data = host->data;
1181 1182 1183
		if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
			      MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND|
			      MCI_DATABLOCKEND) && data)
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1184 1185
			mmci_data_irq(host, data, status);

1186 1187 1188 1189
		/* Don't poll for busy completion in irq context. */
		if (host->busy_status)
			status &= ~MCI_ST_CARDBUSY;

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1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200
		ret = 1;
	} while (status);

	spin_unlock(&host->lock);

	return IRQ_RETVAL(ret);
}

static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
{
	struct mmci_host *host = mmc_priv(mmc);
1201
	unsigned long flags;
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1202 1203 1204

	WARN_ON(host->mrq != NULL);

1205 1206
	mrq->cmd->error = mmci_validate_data(host, mrq->data);
	if (mrq->cmd->error) {
P
Pierre Ossman 已提交
1207 1208 1209 1210
		mmc_request_done(mmc, mrq);
		return;
	}

1211 1212
	pm_runtime_get_sync(mmc_dev(mmc));

1213
	spin_lock_irqsave(&host->lock, flags);
L
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1214 1215 1216

	host->mrq = mrq;

1217 1218 1219
	if (mrq->data)
		mmci_get_next_data(host, mrq->data);

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1220 1221 1222
	if (mrq->data && mrq->data->flags & MMC_DATA_READ)
		mmci_start_data(host, mrq->data);

1223 1224 1225 1226
	if (mrq->sbc)
		mmci_start_command(host, mrq->sbc, 0);
	else
		mmci_start_command(host, mrq->cmd, 0);
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1227

1228
	spin_unlock_irqrestore(&host->lock, flags);
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1229 1230 1231 1232 1233
}

static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
	struct mmci_host *host = mmc_priv(mmc);
1234
	struct variant_data *variant = host->variant;
1235 1236
	u32 pwr = 0;
	unsigned long flags;
1237
	int ret;
L
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1238

1239 1240
	pm_runtime_get_sync(mmc_dev(mmc));

1241 1242 1243 1244
	if (host->plat->ios_handler &&
		host->plat->ios_handler(mmc_dev(mmc), ios))
			dev_err(mmc_dev(mmc), "platform ios_handler failed\n");

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1245 1246
	switch (ios->power_mode) {
	case MMC_POWER_OFF:
1247 1248
		if (!IS_ERR(mmc->supply.vmmc))
			mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1249

1250
		if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1251
			regulator_disable(mmc->supply.vqmmc);
1252 1253
			host->vqmmc_enabled = false;
		}
1254

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1255 1256
		break;
	case MMC_POWER_UP:
1257 1258 1259
		if (!IS_ERR(mmc->supply.vmmc))
			mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);

1260 1261 1262 1263 1264 1265 1266 1267
		/*
		 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
		 * and instead uses MCI_PWR_ON so apply whatever value is
		 * configured in the variant data.
		 */
		pwr |= variant->pwrreg_powerup;

		break;
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1268
	case MMC_POWER_ON:
1269
		if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1270 1271 1272 1273
			ret = regulator_enable(mmc->supply.vqmmc);
			if (ret < 0)
				dev_err(mmc_dev(mmc),
					"failed to enable vqmmc regulator\n");
1274 1275
			else
				host->vqmmc_enabled = true;
1276
		}
1277

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1278 1279 1280 1281
		pwr |= MCI_PWR_ON;
		break;
	}

1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297
	if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
		/*
		 * The ST Micro variant has some additional bits
		 * indicating signal direction for the signals in
		 * the SD/MMC bus and feedback-clock usage.
		 */
		pwr |= host->plat->sigdir;

		if (ios->bus_width == MMC_BUS_WIDTH_4)
			pwr &= ~MCI_ST_DATA74DIREN;
		else if (ios->bus_width == MMC_BUS_WIDTH_1)
			pwr &= (~MCI_ST_DATA74DIREN &
				~MCI_ST_DATA31DIREN &
				~MCI_ST_DATA2DIREN);
	}

1298
	if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
1299
		if (host->hw_designer != AMBA_VENDOR_ST)
1300 1301 1302 1303 1304 1305 1306 1307 1308
			pwr |= MCI_ROD;
		else {
			/*
			 * The ST Micro variant use the ROD bit for something
			 * else and only has OD (Open Drain).
			 */
			pwr |= MCI_OD;
		}
	}
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Linus Torvalds 已提交
1309

1310 1311 1312 1313 1314 1315 1316
	/*
	 * If clock = 0 and the variant requires the MMCIPOWER to be used for
	 * gating the clock, the MCI_PWR_ON bit is cleared.
	 */
	if (!ios->clock && variant->pwrreg_clkgate)
		pwr &= ~MCI_PWR_ON;

1317 1318 1319
	spin_lock_irqsave(&host->lock, flags);

	mmci_set_clkreg(host, ios->clock);
1320
	mmci_write_pwrreg(host, pwr);
1321
	mmci_reg_delay(host);
1322 1323

	spin_unlock_irqrestore(&host->lock, flags);
1324 1325 1326

	pm_runtime_mark_last_busy(mmc_dev(mmc));
	pm_runtime_put_autosuspend(mmc_dev(mmc));
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1327 1328
}

1329 1330 1331 1332 1333 1334 1335
static int mmci_get_ro(struct mmc_host *mmc)
{
	struct mmci_host *host = mmc_priv(mmc);

	if (host->gpio_wp == -ENOSYS)
		return -ENOSYS;

1336
	return gpio_get_value_cansleep(host->gpio_wp);
1337 1338 1339 1340 1341
}

static int mmci_get_cd(struct mmc_host *mmc)
{
	struct mmci_host *host = mmc_priv(mmc);
1342
	struct mmci_platform_data *plat = host->plat;
1343 1344
	unsigned int status;

1345 1346 1347 1348
	if (host->gpio_cd == -ENOSYS) {
		if (!plat->status)
			return 1; /* Assume always present */

1349
		status = plat->status(mmc_dev(host->mmc));
1350
	} else
1351 1352
		status = !!gpio_get_value_cansleep(host->gpio_cd)
			^ plat->cd_invert;
1353

1354 1355 1356 1357 1358
	/*
	 * Use positive logic throughout - status is zero for no card,
	 * non-zero for card inserted.
	 */
	return status;
1359 1360
}

1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393
static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
{
	int ret = 0;

	if (!IS_ERR(mmc->supply.vqmmc)) {

		pm_runtime_get_sync(mmc_dev(mmc));

		switch (ios->signal_voltage) {
		case MMC_SIGNAL_VOLTAGE_330:
			ret = regulator_set_voltage(mmc->supply.vqmmc,
						2700000, 3600000);
			break;
		case MMC_SIGNAL_VOLTAGE_180:
			ret = regulator_set_voltage(mmc->supply.vqmmc,
						1700000, 1950000);
			break;
		case MMC_SIGNAL_VOLTAGE_120:
			ret = regulator_set_voltage(mmc->supply.vqmmc,
						1100000, 1300000);
			break;
		}

		if (ret)
			dev_warn(mmc_dev(mmc), "Voltage switch failed\n");

		pm_runtime_mark_last_busy(mmc_dev(mmc));
		pm_runtime_put_autosuspend(mmc_dev(mmc));
	}

	return ret;
}

1394 1395 1396 1397 1398 1399 1400 1401 1402
static irqreturn_t mmci_cd_irq(int irq, void *dev_id)
{
	struct mmci_host *host = dev_id;

	mmc_detect_change(host->mmc, msecs_to_jiffies(500));

	return IRQ_HANDLED;
}

1403
static struct mmc_host_ops mmci_ops = {
L
Linus Torvalds 已提交
1404
	.request	= mmci_request,
1405 1406
	.pre_req	= mmci_pre_request,
	.post_req	= mmci_post_request,
L
Linus Torvalds 已提交
1407
	.set_ios	= mmci_set_ios,
1408 1409
	.get_ro		= mmci_get_ro,
	.get_cd		= mmci_get_cd,
1410
	.start_signal_voltage_switch = mmci_sig_volt_switch,
L
Linus Torvalds 已提交
1411 1412
};

1413 1414 1415 1416 1417 1418
#ifdef CONFIG_OF
static void mmci_dt_populate_generic_pdata(struct device_node *np,
					struct mmci_platform_data *pdata)
{
	int bus_width = 0;

1419 1420
	pdata->gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
	pdata->gpio_cd = of_get_named_gpio(np, "cd-gpios", 0);
1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450

	if (of_get_property(np, "cd-inverted", NULL))
		pdata->cd_invert = true;
	else
		pdata->cd_invert = false;

	of_property_read_u32(np, "max-frequency", &pdata->f_max);
	if (!pdata->f_max)
		pr_warn("%s has no 'max-frequency' property\n", np->full_name);

	if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
		pdata->capabilities |= MMC_CAP_MMC_HIGHSPEED;
	if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
		pdata->capabilities |= MMC_CAP_SD_HIGHSPEED;

	of_property_read_u32(np, "bus-width", &bus_width);
	switch (bus_width) {
	case 0 :
		/* No bus-width supplied. */
		break;
	case 4 :
		pdata->capabilities |= MMC_CAP_4_BIT_DATA;
		break;
	case 8 :
		pdata->capabilities |= MMC_CAP_8_BIT_DATA;
		break;
	default :
		pr_warn("%s: Unsupported bus width\n", np->full_name);
	}
}
1451 1452 1453 1454 1455 1456
#else
static void mmci_dt_populate_generic_pdata(struct device_node *np,
					struct mmci_platform_data *pdata)
{
	return;
}
1457 1458
#endif

B
Bill Pemberton 已提交
1459
static int mmci_probe(struct amba_device *dev,
1460
	const struct amba_id *id)
L
Linus Torvalds 已提交
1461
{
1462
	struct mmci_platform_data *plat = dev->dev.platform_data;
1463
	struct device_node *np = dev->dev.of_node;
1464
	struct variant_data *variant = id->data;
L
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1465 1466 1467 1468
	struct mmci_host *host;
	struct mmc_host *mmc;
	int ret;

1469 1470 1471 1472
	/* Must have platform data or Device Tree. */
	if (!plat && !np) {
		dev_err(&dev->dev, "No plat data or DT found\n");
		return -EINVAL;
L
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1473 1474
	}

1475 1476 1477 1478 1479 1480
	if (!plat) {
		plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL);
		if (!plat)
			return -ENOMEM;
	}

1481 1482 1483
	if (np)
		mmci_dt_populate_generic_pdata(np, plat);

L
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1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494
	ret = amba_request_regions(dev, DRIVER_NAME);
	if (ret)
		goto out;

	mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
	if (!mmc) {
		ret = -ENOMEM;
		goto rel_regions;
	}

	host = mmc_priv(mmc);
1495
	host->mmc = mmc;
R
Russell King 已提交
1496

1497 1498
	host->gpio_wp = -ENOSYS;
	host->gpio_cd = -ENOSYS;
1499
	host->gpio_cd_irq = -1;
1500

R
Russell King 已提交
1501 1502
	host->hw_designer = amba_manf(dev);
	host->hw_revision = amba_rev(dev);
1503 1504
	dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
	dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
R
Russell King 已提交
1505

1506
	host->clk = devm_clk_get(&dev->dev, NULL);
L
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1507 1508 1509 1510 1511
	if (IS_ERR(host->clk)) {
		ret = PTR_ERR(host->clk);
		goto host_free;
	}

1512
	ret = clk_prepare_enable(host->clk);
L
Linus Torvalds 已提交
1513
	if (ret)
1514
		goto host_free;
L
Linus Torvalds 已提交
1515 1516

	host->plat = plat;
1517
	host->variant = variant;
L
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1518
	host->mclk = clk_get_rate(host->clk);
1519 1520 1521 1522 1523 1524 1525 1526 1527 1528
	/*
	 * According to the spec, mclk is max 100 MHz,
	 * so we try to adjust the clock down to this,
	 * (if possible).
	 */
	if (host->mclk > 100000000) {
		ret = clk_set_rate(host->clk, 100000000);
		if (ret < 0)
			goto clk_disable;
		host->mclk = clk_get_rate(host->clk);
1529 1530
		dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
			host->mclk);
1531
	}
1532
	host->phybase = dev->res.start;
1533
	host->base = ioremap(dev->res.start, resource_size(&dev->res));
L
Linus Torvalds 已提交
1534 1535 1536 1537 1538
	if (!host->base) {
		ret = -ENOMEM;
		goto clk_disable;
	}

1539 1540 1541 1542 1543 1544 1545 1546 1547
	/*
	 * The ARM and ST versions of the block have slightly different
	 * clock divider equations which means that the minimum divider
	 * differs too.
	 */
	if (variant->st_clkdiv)
		mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
	else
		mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559
	/*
	 * If the platform data supplies a maximum operating
	 * frequency, this takes precedence. Else, we fall back
	 * to using the module parameter, which has a (low)
	 * default value in case it is not specified. Either
	 * value must not exceed the clock rate into the block,
	 * of course.
	 */
	if (plat->f_max)
		mmc->f_max = min(host->mclk, plat->f_max);
	else
		mmc->f_max = min(host->mclk, fmax);
1560 1561
	dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);

1562 1563 1564
	/* Get regulators and the supported OCR mask */
	mmc_regulator_get_supply(mmc);
	if (!mmc->ocr_avail)
1565
		mmc->ocr_avail = plat->ocr_mask;
1566 1567 1568
	else if (plat->ocr_mask)
		dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");

1569
	mmc->caps = plat->capabilities;
1570
	mmc->caps2 = plat->capabilities2;
L
Linus Torvalds 已提交
1571

1572 1573 1574 1575 1576 1577 1578 1579 1580
	if (variant->busy_detect) {
		mmci_ops.card_busy = mmci_card_busy;
		mmci_write_datactrlreg(host, MCI_ST_DPSM_BUSYMODE);
		mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
		mmc->max_busy_timeout = 0;
	}

	mmc->ops = &mmci_ops;

1581 1582 1583
	/* We support these PM capabilities. */
	mmc->pm_caps = MMC_PM_KEEP_POWER;

L
Linus Torvalds 已提交
1584 1585 1586
	/*
	 * We can do SGIO
	 */
1587
	mmc->max_segs = NR_SG;
L
Linus Torvalds 已提交
1588 1589

	/*
1590 1591 1592
	 * Since only a certain number of bits are valid in the data length
	 * register, we must ensure that we don't exceed 2^num-1 bytes in a
	 * single request.
L
Linus Torvalds 已提交
1593
	 */
1594
	mmc->max_req_size = (1 << variant->datalength_bits) - 1;
L
Linus Torvalds 已提交
1595 1596 1597 1598 1599

	/*
	 * Set the maximum segment size.  Since we aren't doing DMA
	 * (yet) we are only limited by the data length register.
	 */
1600
	mmc->max_seg_size = mmc->max_req_size;
L
Linus Torvalds 已提交
1601

1602 1603 1604
	/*
	 * Block size can be up to 2048 bytes, but must be a power of two.
	 */
1605
	mmc->max_blk_size = 1 << 11;
1606

1607
	/*
1608 1609
	 * Limit the number of blocks transferred so that we don't overflow
	 * the maximum request size.
1610
	 */
1611
	mmc->max_blk_count = mmc->max_req_size >> 11;
1612

L
Linus Torvalds 已提交
1613 1614 1615 1616 1617 1618
	spin_lock_init(&host->lock);

	writel(0, host->base + MMCIMASK0);
	writel(0, host->base + MMCIMASK1);
	writel(0xfff, host->base + MMCICLEAR);

1619 1620 1621 1622
	if (plat->gpio_cd == -EPROBE_DEFER) {
		ret = -EPROBE_DEFER;
		goto err_gpio_cd;
	}
1623 1624 1625 1626 1627 1628 1629 1630
	if (gpio_is_valid(plat->gpio_cd)) {
		ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)");
		if (ret == 0)
			ret = gpio_direction_input(plat->gpio_cd);
		if (ret == 0)
			host->gpio_cd = plat->gpio_cd;
		else if (ret != -ENOSYS)
			goto err_gpio_cd;
1631

1632 1633 1634 1635 1636 1637 1638
		/*
		 * A gpio pin that will detect cards when inserted and removed
		 * will most likely want to trigger on the edges if it is
		 * 0 when ejected and 1 when inserted (or mutatis mutandis
		 * for the inverted case) so we request triggers on both
		 * edges.
		 */
1639
		ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd),
1640 1641 1642
				mmci_cd_irq,
				IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
				DRIVER_NAME " (cd)", host);
1643 1644
		if (ret >= 0)
			host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd);
1645
	}
1646 1647 1648 1649
	if (plat->gpio_wp == -EPROBE_DEFER) {
		ret = -EPROBE_DEFER;
		goto err_gpio_wp;
	}
1650 1651 1652 1653 1654 1655 1656 1657 1658 1659
	if (gpio_is_valid(plat->gpio_wp)) {
		ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)");
		if (ret == 0)
			ret = gpio_direction_input(plat->gpio_wp);
		if (ret == 0)
			host->gpio_wp = plat->gpio_wp;
		else if (ret != -ENOSYS)
			goto err_gpio_wp;
	}

1660 1661
	if ((host->plat->status || host->gpio_cd != -ENOSYS)
	    && host->gpio_cd_irq < 0)
1662 1663
		mmc->caps |= MMC_CAP_NEEDS_POLL;

1664
	ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
L
Linus Torvalds 已提交
1665 1666 1667
	if (ret)
		goto unmap;

1668
	if (!dev->irq[1])
1669 1670 1671 1672 1673 1674 1675
		host->singleirq = true;
	else {
		ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED,
				  DRIVER_NAME " (pio)", host);
		if (ret)
			goto irq0_free;
	}
L
Linus Torvalds 已提交
1676

1677
	writel(MCI_IRQENABLE, host->base + MMCIMASK0);
L
Linus Torvalds 已提交
1678 1679 1680

	amba_set_drvdata(dev, mmc);

1681 1682 1683 1684 1685 1686
	dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
		 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
		 amba_rev(dev), (unsigned long long)dev->res.start,
		 dev->irq[0], dev->irq[1]);

	mmci_dma_setup(host);
L
Linus Torvalds 已提交
1687

1688 1689
	pm_runtime_set_autosuspend_delay(&dev->dev, 50);
	pm_runtime_use_autosuspend(&dev->dev);
1690 1691
	pm_runtime_put(&dev->dev);

1692 1693
	mmc_add_host(mmc);

L
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1694 1695 1696 1697 1698
	return 0;

 irq0_free:
	free_irq(dev->irq[0], host);
 unmap:
1699 1700 1701
	if (host->gpio_wp != -ENOSYS)
		gpio_free(host->gpio_wp);
 err_gpio_wp:
1702 1703
	if (host->gpio_cd_irq >= 0)
		free_irq(host->gpio_cd_irq, host);
1704 1705 1706
	if (host->gpio_cd != -ENOSYS)
		gpio_free(host->gpio_cd);
 err_gpio_cd:
L
Linus Torvalds 已提交
1707 1708
	iounmap(host->base);
 clk_disable:
1709
	clk_disable_unprepare(host->clk);
L
Linus Torvalds 已提交
1710 1711 1712 1713 1714 1715 1716 1717
 host_free:
	mmc_free_host(mmc);
 rel_regions:
	amba_release_regions(dev);
 out:
	return ret;
}

B
Bill Pemberton 已提交
1718
static int mmci_remove(struct amba_device *dev)
L
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{
	struct mmc_host *mmc = amba_get_drvdata(dev);

	if (mmc) {
		struct mmci_host *host = mmc_priv(mmc);

1725 1726 1727 1728 1729 1730
		/*
		 * Undo pm_runtime_put() in probe.  We use the _sync
		 * version here so that we can access the primecell.
		 */
		pm_runtime_get_sync(&dev->dev);

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		mmc_remove_host(mmc);

		writel(0, host->base + MMCIMASK0);
		writel(0, host->base + MMCIMASK1);

		writel(0, host->base + MMCICOMMAND);
		writel(0, host->base + MMCIDATACTRL);

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		mmci_dma_release(host);
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		free_irq(dev->irq[0], host);
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		if (!host->singleirq)
			free_irq(dev->irq[1], host);
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		if (host->gpio_wp != -ENOSYS)
			gpio_free(host->gpio_wp);
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		if (host->gpio_cd_irq >= 0)
			free_irq(host->gpio_cd_irq, host);
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		if (host->gpio_cd != -ENOSYS)
			gpio_free(host->gpio_cd);

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		iounmap(host->base);
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		clk_disable_unprepare(host->clk);
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		mmc_free_host(mmc);

		amba_release_regions(dev);
	}

	return 0;
}

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#ifdef CONFIG_SUSPEND
static int mmci_suspend(struct device *dev)
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{
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	struct amba_device *adev = to_amba_device(dev);
	struct mmc_host *mmc = amba_get_drvdata(adev);
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	if (mmc) {
		struct mmci_host *host = mmc_priv(mmc);
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		pm_runtime_get_sync(dev);
		writel(0, host->base + MMCIMASK0);
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	}

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	return 0;
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}

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static int mmci_resume(struct device *dev)
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{
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	struct amba_device *adev = to_amba_device(dev);
	struct mmc_host *mmc = amba_get_drvdata(adev);
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	if (mmc) {
		struct mmci_host *host = mmc_priv(mmc);
		writel(MCI_IRQENABLE, host->base + MMCIMASK0);
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		pm_runtime_put(dev);
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	}

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	return 0;
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}
#endif

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#ifdef CONFIG_PM
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static void mmci_save(struct mmci_host *host)
{
	unsigned long flags;

1797
	spin_lock_irqsave(&host->lock, flags);
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	writel(0, host->base + MMCIMASK0);
	if (host->variant->pwrreg_nopower) {
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		writel(0, host->base + MMCIDATACTRL);
		writel(0, host->base + MMCIPOWER);
		writel(0, host->base + MMCICLOCK);
	}
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	mmci_reg_delay(host);
1806

1807
	spin_unlock_irqrestore(&host->lock, flags);
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}

static void mmci_restore(struct mmci_host *host)
{
	unsigned long flags;

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	spin_lock_irqsave(&host->lock, flags);
1815

1816
	if (host->variant->pwrreg_nopower) {
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		writel(host->clk_reg, host->base + MMCICLOCK);
		writel(host->datactrl_reg, host->base + MMCIDATACTRL);
		writel(host->pwr_reg, host->base + MMCIPOWER);
	}
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	writel(MCI_IRQENABLE, host->base + MMCIMASK0);
	mmci_reg_delay(host);

	spin_unlock_irqrestore(&host->lock, flags);
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}

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static int mmci_runtime_suspend(struct device *dev)
{
	struct amba_device *adev = to_amba_device(dev);
	struct mmc_host *mmc = amba_get_drvdata(adev);

	if (mmc) {
		struct mmci_host *host = mmc_priv(mmc);
1834
		pinctrl_pm_select_sleep_state(dev);
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		mmci_save(host);
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		clk_disable_unprepare(host->clk);
	}

	return 0;
}

static int mmci_runtime_resume(struct device *dev)
{
	struct amba_device *adev = to_amba_device(dev);
	struct mmc_host *mmc = amba_get_drvdata(adev);

	if (mmc) {
		struct mmci_host *host = mmc_priv(mmc);
		clk_prepare_enable(host->clk);
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		mmci_restore(host);
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		pinctrl_pm_select_default_state(dev);
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	}

	return 0;
}
#endif

1858 1859
static const struct dev_pm_ops mmci_dev_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume)
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	SET_PM_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL)
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};

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static struct amba_id mmci_ids[] = {
	{
		.id	= 0x00041180,
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		.mask	= 0xff0fffff,
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		.data	= &variant_arm,
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	},
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	{
		.id	= 0x01041180,
		.mask	= 0xff0fffff,
		.data	= &variant_arm_extended_fifo,
	},
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	{
		.id	= 0x02041180,
		.mask	= 0xff0fffff,
		.data	= &variant_arm_extended_fifo_hwfc,
	},
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	{
		.id	= 0x00041181,
		.mask	= 0x000fffff,
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		.data	= &variant_arm,
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	},
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	/* ST Micro variants */
	{
		.id     = 0x00180180,
		.mask   = 0x00ffffff,
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		.data	= &variant_u300,
1889
	},
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	{
		.id     = 0x10180180,
		.mask   = 0xf0ffffff,
		.data	= &variant_nomadik,
	},
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	{
		.id     = 0x00280180,
		.mask   = 0x00ffffff,
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		.data	= &variant_u300,
	},
	{
		.id     = 0x00480180,
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		.mask   = 0xf0ffffff,
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		.data	= &variant_ux500,
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	},
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	{
		.id     = 0x10480180,
		.mask   = 0xf0ffffff,
		.data	= &variant_ux500v2,
	},
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	{ 0, 0 },
};

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MODULE_DEVICE_TABLE(amba, mmci_ids);

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static struct amba_driver mmci_driver = {
	.drv		= {
		.name	= DRIVER_NAME,
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		.pm	= &mmci_dev_pm_ops,
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	},
	.probe		= mmci_probe,
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	.remove		= mmci_remove,
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	.id_table	= mmci_ids,
};

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module_amba_driver(mmci_driver);
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module_param(fmax, uint, 0444);

MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
MODULE_LICENSE("GPL");