mmci.c 37.4 KB
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/*
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 *  linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
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 *
 *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
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 *  Copyright (C) 2010 ST-Ericsson SA
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 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/device.h>
#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
#include <linux/err.h>
#include <linux/highmem.h>
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#include <linux/log2.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/card.h>
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#include <linux/amba/bus.h>
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#include <linux/clk.h>
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#include <linux/scatterlist.h>
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#include <linux/gpio.h>
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#include <linux/regulator/consumer.h>
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#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
#include <linux/amba/mmci.h>
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#include <linux/pm_runtime.h>
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#include <asm/div64.h>
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#include <asm/io.h>
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#include <asm/sizes.h>
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#include "mmci.h"

#define DRIVER_NAME "mmci-pl18x"

static unsigned int fmax = 515633;

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/**
 * struct variant_data - MMCI variant-specific quirks
 * @clkreg: default value for MCICLOCK register
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 * @clkreg_enable: enable value for MMCICLOCK register
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 * @datalength_bits: number of bits in the MMCIDATALENGTH register
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 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
 *	      is asserted (likewise for RX)
 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
 *		  is asserted (likewise for RX)
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 * @sdio: variant supports SDIO
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 * @st_clkdiv: true if using a ST-specific clock divider algorithm
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 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
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 * @pwrreg_powerup: power up value for MMCIPOWER register
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 * @signal_direction: input/out direction of bus signals can be indicated
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 */
struct variant_data {
	unsigned int		clkreg;
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	unsigned int		clkreg_enable;
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	unsigned int		datalength_bits;
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	unsigned int		fifosize;
	unsigned int		fifohalfsize;
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	bool			sdio;
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	bool			st_clkdiv;
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	bool			blksz_datactrl16;
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	u32			pwrreg_powerup;
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	bool			signal_direction;
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};

static struct variant_data variant_arm = {
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	.fifosize		= 16 * 4,
	.fifohalfsize		= 8 * 4,
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	.datalength_bits	= 16,
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	.pwrreg_powerup		= MCI_PWR_UP,
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};

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static struct variant_data variant_arm_extended_fifo = {
	.fifosize		= 128 * 4,
	.fifohalfsize		= 64 * 4,
	.datalength_bits	= 16,
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	.pwrreg_powerup		= MCI_PWR_UP,
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};

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static struct variant_data variant_u300 = {
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	.fifosize		= 16 * 4,
	.fifohalfsize		= 8 * 4,
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	.clkreg_enable		= MCI_ST_U300_HWFCEN,
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	.datalength_bits	= 16,
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	.sdio			= true,
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	.pwrreg_powerup		= MCI_PWR_ON,
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	.signal_direction	= true,
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};

static struct variant_data variant_ux500 = {
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	.fifosize		= 30 * 4,
	.fifohalfsize		= 8 * 4,
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	.clkreg			= MCI_CLK_ENABLE,
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	.clkreg_enable		= MCI_ST_UX500_HWFCEN,
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	.datalength_bits	= 24,
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	.sdio			= true,
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	.st_clkdiv		= true,
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	.pwrreg_powerup		= MCI_PWR_ON,
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	.signal_direction	= true,
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};
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static struct variant_data variant_ux500v2 = {
	.fifosize		= 30 * 4,
	.fifohalfsize		= 8 * 4,
	.clkreg			= MCI_CLK_ENABLE,
	.clkreg_enable		= MCI_ST_UX500_HWFCEN,
	.datalength_bits	= 24,
	.sdio			= true,
	.st_clkdiv		= true,
	.blksz_datactrl16	= true,
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	.pwrreg_powerup		= MCI_PWR_ON,
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	.signal_direction	= true,
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};

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/*
 * This must be called with host->lock held
 */
static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
{
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	struct variant_data *variant = host->variant;
	u32 clk = variant->clkreg;
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	if (desired) {
		if (desired >= host->mclk) {
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			clk = MCI_CLK_BYPASS;
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			if (variant->st_clkdiv)
				clk |= MCI_ST_UX500_NEG_EDGE;
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			host->cclk = host->mclk;
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		} else if (variant->st_clkdiv) {
			/*
			 * DB8500 TRM says f = mclk / (clkdiv + 2)
			 * => clkdiv = (mclk / f) - 2
			 * Round the divider up so we don't exceed the max
			 * frequency
			 */
			clk = DIV_ROUND_UP(host->mclk, desired) - 2;
			if (clk >= 256)
				clk = 255;
			host->cclk = host->mclk / (clk + 2);
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		} else {
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			/*
			 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
			 * => clkdiv = mclk / (2 * f) - 1
			 */
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			clk = host->mclk / (2 * desired) - 1;
			if (clk >= 256)
				clk = 255;
			host->cclk = host->mclk / (2 * (clk + 1));
		}
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		clk |= variant->clkreg_enable;
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		clk |= MCI_CLK_ENABLE;
		/* This hasn't proven to be worthwhile */
		/* clk |= MCI_CLK_PWRSAVE; */
	}

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	if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
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		clk |= MCI_4BIT_BUS;
	if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
		clk |= MCI_ST_8BIT_BUS;
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	writel(clk, host->base + MMCICLOCK);
}

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static void
mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
{
	writel(0, host->base + MMCICOMMAND);

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	BUG_ON(host->data);

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	host->mrq = NULL;
	host->cmd = NULL;

	mmc_request_done(host->mmc, mrq);
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	pm_runtime_mark_last_busy(mmc_dev(host->mmc));
	pm_runtime_put_autosuspend(mmc_dev(host->mmc));
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}

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static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
{
	void __iomem *base = host->base;

	if (host->singleirq) {
		unsigned int mask0 = readl(base + MMCIMASK0);

		mask0 &= ~MCI_IRQ1MASK;
		mask0 |= mask;

		writel(mask0, base + MMCIMASK0);
	}

	writel(mask, base + MMCIMASK1);
}

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static void mmci_stop_data(struct mmci_host *host)
{
	writel(0, host->base + MMCIDATACTRL);
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	mmci_set_mask1(host, 0);
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	host->data = NULL;
}

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static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
{
	unsigned int flags = SG_MITER_ATOMIC;

	if (data->flags & MMC_DATA_READ)
		flags |= SG_MITER_TO_SG;
	else
		flags |= SG_MITER_FROM_SG;

	sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
}

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/*
 * All the DMA operation mode stuff goes inside this ifdef.
 * This assumes that you have a generic DMA device interface,
 * no custom DMA interfaces are supported.
 */
#ifdef CONFIG_DMA_ENGINE
static void __devinit mmci_dma_setup(struct mmci_host *host)
{
	struct mmci_platform_data *plat = host->plat;
	const char *rxname, *txname;
	dma_cap_mask_t mask;

	if (!plat || !plat->dma_filter) {
		dev_info(mmc_dev(host->mmc), "no DMA platform data\n");
		return;
	}

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	/* initialize pre request cookie */
	host->next_data.cookie = 1;

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	/* Try to acquire a generic DMA engine slave channel */
	dma_cap_zero(mask);
	dma_cap_set(DMA_SLAVE, mask);

	/*
	 * If only an RX channel is specified, the driver will
	 * attempt to use it bidirectionally, however if it is
	 * is specified but cannot be located, DMA will be disabled.
	 */
	if (plat->dma_rx_param) {
		host->dma_rx_channel = dma_request_channel(mask,
							   plat->dma_filter,
							   plat->dma_rx_param);
		/* E.g if no DMA hardware is present */
		if (!host->dma_rx_channel)
			dev_err(mmc_dev(host->mmc), "no RX DMA channel\n");
	}

	if (plat->dma_tx_param) {
		host->dma_tx_channel = dma_request_channel(mask,
							   plat->dma_filter,
							   plat->dma_tx_param);
		if (!host->dma_tx_channel)
			dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n");
	} else {
		host->dma_tx_channel = host->dma_rx_channel;
	}

	if (host->dma_rx_channel)
		rxname = dma_chan_name(host->dma_rx_channel);
	else
		rxname = "none";

	if (host->dma_tx_channel)
		txname = dma_chan_name(host->dma_tx_channel);
	else
		txname = "none";

	dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
		 rxname, txname);

	/*
	 * Limit the maximum segment size in any SG entry according to
	 * the parameters of the DMA engine device.
	 */
	if (host->dma_tx_channel) {
		struct device *dev = host->dma_tx_channel->device->dev;
		unsigned int max_seg_size = dma_get_max_seg_size(dev);

		if (max_seg_size < host->mmc->max_seg_size)
			host->mmc->max_seg_size = max_seg_size;
	}
	if (host->dma_rx_channel) {
		struct device *dev = host->dma_rx_channel->device->dev;
		unsigned int max_seg_size = dma_get_max_seg_size(dev);

		if (max_seg_size < host->mmc->max_seg_size)
			host->mmc->max_seg_size = max_seg_size;
	}
}

/*
 * This is used in __devinit or __devexit so inline it
 * so it can be discarded.
 */
static inline void mmci_dma_release(struct mmci_host *host)
{
	struct mmci_platform_data *plat = host->plat;

	if (host->dma_rx_channel)
		dma_release_channel(host->dma_rx_channel);
	if (host->dma_tx_channel && plat->dma_tx_param)
		dma_release_channel(host->dma_tx_channel);
	host->dma_rx_channel = host->dma_tx_channel = NULL;
}

static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
{
	struct dma_chan *chan = host->dma_current;
	enum dma_data_direction dir;
	u32 status;
	int i;

	/* Wait up to 1ms for the DMA to complete */
	for (i = 0; ; i++) {
		status = readl(host->base + MMCISTATUS);
		if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
			break;
		udelay(10);
	}

	/*
	 * Check to see whether we still have some data left in the FIFO -
	 * this catches DMA controllers which are unable to monitor the
	 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
	 * contiguous buffers.  On TX, we'll get a FIFO underrun error.
	 */
	if (status & MCI_RXDATAAVLBLMASK) {
		dmaengine_terminate_all(chan);
		if (!data->error)
			data->error = -EIO;
	}

	if (data->flags & MMC_DATA_WRITE) {
		dir = DMA_TO_DEVICE;
	} else {
		dir = DMA_FROM_DEVICE;
	}

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	if (!data->host_cookie)
		dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
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	/*
	 * Use of DMA with scatter-gather is impossible.
	 * Give up with DMA and switch back to PIO mode.
	 */
	if (status & MCI_RXDATAAVLBLMASK) {
		dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
		mmci_dma_release(host);
	}
}

static void mmci_dma_data_error(struct mmci_host *host)
{
	dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
	dmaengine_terminate_all(host->dma_current);
}

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static int mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data,
			      struct mmci_host_next *next)
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{
	struct variant_data *variant = host->variant;
	struct dma_slave_config conf = {
		.src_addr = host->phybase + MMCIFIFO,
		.dst_addr = host->phybase + MMCIFIFO,
		.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
		.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
		.src_maxburst = variant->fifohalfsize >> 2, /* # of words */
		.dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
	};
	struct dma_chan *chan;
	struct dma_device *device;
	struct dma_async_tx_descriptor *desc;
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	enum dma_data_direction buffer_dirn;
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	int nr_sg;

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	/* Check if next job is already prepared */
	if (data->host_cookie && !next &&
	    host->dma_current && host->dma_desc_current)
		return 0;

	if (!next) {
		host->dma_current = NULL;
		host->dma_desc_current = NULL;
	}
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	if (data->flags & MMC_DATA_READ) {
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		conf.direction = DMA_DEV_TO_MEM;
		buffer_dirn = DMA_FROM_DEVICE;
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		chan = host->dma_rx_channel;
	} else {
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		conf.direction = DMA_MEM_TO_DEV;
		buffer_dirn = DMA_TO_DEVICE;
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		chan = host->dma_tx_channel;
	}

	/* If there's no DMA channel, fall back to PIO */
	if (!chan)
		return -EINVAL;

	/* If less than or equal to the fifo size, don't bother with DMA */
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	if (data->blksz * data->blocks <= variant->fifosize)
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		return -EINVAL;

	device = chan->device;
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	nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
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	if (nr_sg == 0)
		return -EINVAL;

	dmaengine_slave_config(chan, &conf);
	desc = device->device_prep_slave_sg(chan, data->sg, nr_sg,
					    conf.direction, DMA_CTRL_ACK);
	if (!desc)
		goto unmap_exit;

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	if (next) {
		next->dma_chan = chan;
		next->dma_desc = desc;
	} else {
		host->dma_current = chan;
		host->dma_desc_current = desc;
	}

	return 0;
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 unmap_exit:
	if (!next)
		dmaengine_terminate_all(chan);
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	dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn);
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	return -ENOMEM;
}

static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
{
	int ret;
	struct mmc_data *data = host->data;

	ret = mmci_dma_prep_data(host, host->data, NULL);
	if (ret)
		return ret;

	/* Okay, go for it. */
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	dev_vdbg(mmc_dev(host->mmc),
		 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
		 data->sg_len, data->blksz, data->blocks, data->flags);
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	dmaengine_submit(host->dma_desc_current);
	dma_async_issue_pending(host->dma_current);
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	datactrl |= MCI_DPSM_DMAENABLE;

	/* Trigger the DMA transfer */
	writel(datactrl, host->base + MMCIDATACTRL);

	/*
	 * Let the MMCI say when the data is ended and it's time
	 * to fire next DMA request. When that happens, MMCI will
	 * call mmci_data_end()
	 */
	writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
	       host->base + MMCIMASK0);
	return 0;
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}
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static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
{
	struct mmci_host_next *next = &host->next_data;

	if (data->host_cookie && data->host_cookie != next->cookie) {
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		pr_warning("[%s] invalid cookie: data->host_cookie %d"
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		       " host->next_data.cookie %d\n",
		       __func__, data->host_cookie, host->next_data.cookie);
		data->host_cookie = 0;
	}

	if (!data->host_cookie)
		return;

	host->dma_desc_current = next->dma_desc;
	host->dma_current = next->dma_chan;

	next->dma_desc = NULL;
	next->dma_chan = NULL;
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}
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static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq,
			     bool is_first_req)
{
	struct mmci_host *host = mmc_priv(mmc);
	struct mmc_data *data = mrq->data;
	struct mmci_host_next *nd = &host->next_data;

	if (!data)
		return;

	if (data->host_cookie) {
		data->host_cookie = 0;
		return;
	}

	/* if config for dma */
	if (((data->flags & MMC_DATA_WRITE) && host->dma_tx_channel) ||
	    ((data->flags & MMC_DATA_READ) && host->dma_rx_channel)) {
		if (mmci_dma_prep_data(host, data, nd))
			data->host_cookie = 0;
		else
			data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie;
	}
}

static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
			      int err)
{
	struct mmci_host *host = mmc_priv(mmc);
	struct mmc_data *data = mrq->data;
	struct dma_chan *chan;
	enum dma_data_direction dir;

	if (!data)
		return;

	if (data->flags & MMC_DATA_READ) {
		dir = DMA_FROM_DEVICE;
		chan = host->dma_rx_channel;
	} else {
		dir = DMA_TO_DEVICE;
		chan = host->dma_tx_channel;
	}


	/* if config for dma */
	if (chan) {
		if (err)
			dmaengine_terminate_all(chan);
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		if (data->host_cookie)
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			dma_unmap_sg(mmc_dev(host->mmc), data->sg,
				     data->sg_len, dir);
		mrq->data->host_cookie = 0;
	}
}

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#else
/* Blank functions if the DMA engine is not available */
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static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
{
}
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static inline void mmci_dma_setup(struct mmci_host *host)
{
}

static inline void mmci_dma_release(struct mmci_host *host)
{
}

static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
{
}

static inline void mmci_dma_data_error(struct mmci_host *host)
{
}

static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
{
	return -ENOSYS;
}
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#define mmci_pre_request NULL
#define mmci_post_request NULL

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#endif

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static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
{
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	struct variant_data *variant = host->variant;
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	unsigned int datactrl, timeout, irqmask;
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	unsigned long long clks;
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	void __iomem *base;
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	int blksz_bits;
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	dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
		data->blksz, data->blocks, data->flags);
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	host->data = data;
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	host->size = data->blksz * data->blocks;
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	data->bytes_xfered = 0;
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	clks = (unsigned long long)data->timeout_ns * host->cclk;
	do_div(clks, 1000000000UL);

	timeout = data->timeout_clks + (unsigned int)clks;
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	base = host->base;
	writel(timeout, base + MMCIDATATIMER);
	writel(host->size, base + MMCIDATALENGTH);

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	blksz_bits = ffs(data->blksz) - 1;
	BUG_ON(1 << blksz_bits != data->blksz);

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	if (variant->blksz_datactrl16)
		datactrl = MCI_DPSM_ENABLE | (data->blksz << 16);
	else
		datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
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	if (data->flags & MMC_DATA_READ)
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		datactrl |= MCI_DPSM_DIRECTION;
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	/*
	 * Attempt to use DMA operation mode, if this
	 * should fail, fall back to PIO mode
	 */
	if (!mmci_dma_start_data(host, datactrl))
		return;

	/* IRQ mode, map the SG list for CPU reading/writing */
	mmci_init_sg(host, data);

	if (data->flags & MMC_DATA_READ) {
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		irqmask = MCI_RXFIFOHALFFULLMASK;
630 631

		/*
632 633 634
		 * If we have less than the fifo 'half-full' threshold to
		 * transfer, trigger a PIO interrupt as soon as any data
		 * is available.
635
		 */
636
		if (host->size < variant->fifohalfsize)
637
			irqmask |= MCI_RXDATAAVLBLMASK;
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638 639 640 641 642 643 644 645
	} else {
		/*
		 * We don't actually need to include "FIFO empty" here
		 * since its implicit in "FIFO half empty".
		 */
		irqmask = MCI_TXFIFOHALFEMPTYMASK;
	}

646 647 648 649 650
	/* The ST Micro variants has a special bit to enable SDIO */
	if (variant->sdio && host->mmc->card)
		if (mmc_card_sdio(host->mmc->card))
			datactrl |= MCI_ST_DPSM_SDIOEN;

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	writel(datactrl, base + MMCIDATACTRL);
	writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
653
	mmci_set_mask1(host, irqmask);
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}

static void
mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
{
	void __iomem *base = host->base;

661
	dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
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662 663 664 665 666 667 668 669
	    cmd->opcode, cmd->arg, cmd->flags);

	if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
		writel(0, base + MMCICOMMAND);
		udelay(1);
	}

	c |= cmd->opcode | MCI_CPSM_ENABLE;
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	if (cmd->flags & MMC_RSP_PRESENT) {
		if (cmd->flags & MMC_RSP_136)
			c |= MCI_CPSM_LONGRSP;
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		c |= MCI_CPSM_RESPONSE;
	}
	if (/*interrupt*/0)
		c |= MCI_CPSM_INTERRUPT;

	host->cmd = cmd;

	writel(cmd->arg, base + MMCIARGUMENT);
	writel(c, base + MMCICOMMAND);
}

static void
mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
	      unsigned int status)
{
688
	/* First check for errors */
689 690
	if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
		      MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
691
		u32 remain, success;
692

693 694 695
		/* Terminate the DMA transfer */
		if (dma_inprogress(host))
			mmci_dma_data_error(host);
696 697

		/*
698 699 700 701 702
		 * Calculate how far we are into the transfer.  Note that
		 * the data counter gives the number of bytes transferred
		 * on the MMC bus, not on the host side.  On reads, this
		 * can be as much as a FIFO-worth of data ahead.  This
		 * matters for FIFO overruns only.
703
		 */
704
		remain = readl(host->base + MMCIDATACNT);
705 706
		success = data->blksz * data->blocks - remain;

707 708
		dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
			status, success);
709 710
		if (status & MCI_DATACRCFAIL) {
			/* Last block was not successful */
711
			success -= 1;
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			data->error = -EILSEQ;
713
		} else if (status & MCI_DATATIMEOUT) {
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			data->error = -ETIMEDOUT;
715 716
		} else if (status & MCI_STARTBITERR) {
			data->error = -ECOMM;
717 718 719 720 721 722 723
		} else if (status & MCI_TXUNDERRUN) {
			data->error = -EIO;
		} else if (status & MCI_RXOVERRUN) {
			if (success > host->variant->fifosize)
				success -= host->variant->fifosize;
			else
				success = 0;
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			data->error = -EIO;
725
		}
726
		data->bytes_xfered = round_down(success, data->blksz);
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727
	}
728

729 730
	if (status & MCI_DATABLOCKEND)
		dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
731

732
	if (status & MCI_DATAEND || data->error) {
733 734
		if (dma_inprogress(host))
			mmci_dma_unmap(host, data);
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		mmci_stop_data(host);

737 738
		if (!data->error)
			/* The error clause is handled above, success! */
739
			data->bytes_xfered = data->blksz * data->blocks;
740

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		if (!data->stop) {
			mmci_request_end(host, data->mrq);
		} else {
			mmci_start_command(host, data->stop, 0);
		}
	}
}

static void
mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
	     unsigned int status)
{
	void __iomem *base = host->base;

	host->cmd = NULL;

	if (status & MCI_CMDTIMEOUT) {
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		cmd->error = -ETIMEDOUT;
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	} else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
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		cmd->error = -EILSEQ;
761 762 763 764 765
	} else {
		cmd->resp[0] = readl(base + MMCIRESPONSE0);
		cmd->resp[1] = readl(base + MMCIRESPONSE1);
		cmd->resp[2] = readl(base + MMCIRESPONSE2);
		cmd->resp[3] = readl(base + MMCIRESPONSE3);
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	}

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	if (!cmd->data || cmd->error) {
769 770 771 772
		if (host->data) {
			/* Terminate the DMA transfer */
			if (dma_inprogress(host))
				mmci_dma_data_error(host);
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			mmci_stop_data(host);
774
		}
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		mmci_request_end(host, cmd->mrq);
	} else if (!(cmd->data->flags & MMC_DATA_READ)) {
		mmci_start_data(host, cmd->data);
	}
}

static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
{
	void __iomem *base = host->base;
	char *ptr = buffer;
	u32 status;
786
	int host_remain = host->size;
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787 788

	do {
789
		int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
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		if (count > remain)
			count = remain;

		if (count <= 0)
			break;

		readsl(base + MMCIFIFO, ptr, count >> 2);

		ptr += count;
		remain -= count;
801
		host_remain -= count;
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		if (remain == 0)
			break;

		status = readl(base + MMCISTATUS);
	} while (status & MCI_RXDATAAVLBL);

	return ptr - buffer;
}

static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
{
814
	struct variant_data *variant = host->variant;
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	void __iomem *base = host->base;
	char *ptr = buffer;

	do {
		unsigned int count, maxcnt;

821 822
		maxcnt = status & MCI_TXFIFOEMPTY ?
			 variant->fifosize : variant->fifohalfsize;
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		count = min(remain, maxcnt);

825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850
		/*
		 * The ST Micro variant for SDIO transfer sizes
		 * less then 8 bytes should have clock H/W flow
		 * control disabled.
		 */
		if (variant->sdio &&
		    mmc_card_sdio(host->mmc->card)) {
			if (count < 8)
				writel(readl(host->base + MMCICLOCK) &
					~variant->clkreg_enable,
					host->base + MMCICLOCK);
			else
				writel(readl(host->base + MMCICLOCK) |
					variant->clkreg_enable,
					host->base + MMCICLOCK);
		}

		/*
		 * SDIO especially may want to send something that is
		 * not divisible by 4 (as opposed to card sectors
		 * etc), and the FIFO only accept full 32-bit writes.
		 * So compensate by adding +3 on the count, a single
		 * byte become a 32bit write, 7 bytes will be two
		 * 32bit writes etc.
		 */
		writesl(base + MMCIFIFO, ptr, (count + 3) >> 2);
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		ptr += count;
		remain -= count;

		if (remain == 0)
			break;

		status = readl(base + MMCISTATUS);
	} while (status & MCI_TXFIFOHALFEMPTY);

	return ptr - buffer;
}

/*
 * PIO data transfer IRQ handler.
 */
867
static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
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{
	struct mmci_host *host = dev_id;
870
	struct sg_mapping_iter *sg_miter = &host->sg_miter;
871
	struct variant_data *variant = host->variant;
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	void __iomem *base = host->base;
873
	unsigned long flags;
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	u32 status;

	status = readl(base + MMCISTATUS);

878
	dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
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880 881
	local_irq_save(flags);

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	do {
		unsigned int remain, len;
		char *buffer;

		/*
		 * For write, we only need to test the half-empty flag
		 * here - if the FIFO is completely empty, then by
		 * definition it is more than half empty.
		 *
		 * For read, check for data available.
		 */
		if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
			break;

896 897 898 899 900
		if (!sg_miter_next(sg_miter))
			break;

		buffer = sg_miter->addr;
		remain = sg_miter->length;
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901 902 903 904 905 906 907

		len = 0;
		if (status & MCI_RXACTIVE)
			len = mmci_pio_read(host, buffer, remain);
		if (status & MCI_TXACTIVE)
			len = mmci_pio_write(host, buffer, remain, status);

908
		sg_miter->consumed = len;
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		host->size -= len;
		remain -= len;

		if (remain)
			break;

		status = readl(base + MMCISTATUS);
	} while (1);

919 920 921 922
	sg_miter_stop(sg_miter);

	local_irq_restore(flags);

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923
	/*
924 925
	 * If we have less than the fifo 'half-full' threshold to transfer,
	 * trigger a PIO interrupt as soon as any data is available.
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926
	 */
927
	if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
928
		mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
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929 930 931 932 933 934 935 936

	/*
	 * If we run out of data, disable the data IRQs; this
	 * prevents a race where the FIFO becomes empty before
	 * the chip itself has disabled the data path, and
	 * stops us racing with our data end IRQ.
	 */
	if (host->size == 0) {
937
		mmci_set_mask1(host, 0);
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		writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
	}

	return IRQ_HANDLED;
}

/*
 * Handle completion of command and data transfers.
 */
947
static irqreturn_t mmci_irq(int irq, void *dev_id)
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{
	struct mmci_host *host = dev_id;
	u32 status;
	int ret = 0;

	spin_lock(&host->lock);

	do {
		struct mmc_command *cmd;
		struct mmc_data *data;

		status = readl(host->base + MMCISTATUS);
960 961 962 963 964 965 966 967

		if (host->singleirq) {
			if (status & readl(host->base + MMCIMASK1))
				mmci_pio_irq(irq, dev_id);

			status &= ~MCI_IRQ1MASK;
		}

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		status &= readl(host->base + MMCIMASK0);
		writel(status, host->base + MMCICLEAR);

971
		dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
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		data = host->data;
974 975 976
		if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
			      MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND|
			      MCI_DATABLOCKEND) && data)
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977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993
			mmci_data_irq(host, data, status);

		cmd = host->cmd;
		if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
			mmci_cmd_irq(host, cmd, status);

		ret = 1;
	} while (status);

	spin_unlock(&host->lock);

	return IRQ_RETVAL(ret);
}

static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
{
	struct mmci_host *host = mmc_priv(mmc);
994
	unsigned long flags;
L
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995 996 997

	WARN_ON(host->mrq != NULL);

N
Nicolas Pitre 已提交
998
	if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
999 1000
		dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n",
			mrq->data->blksz);
P
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1001 1002 1003 1004 1005
		mrq->cmd->error = -EINVAL;
		mmc_request_done(mmc, mrq);
		return;
	}

1006 1007
	pm_runtime_get_sync(mmc_dev(mmc));

1008
	spin_lock_irqsave(&host->lock, flags);
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	host->mrq = mrq;

1012 1013 1014
	if (mrq->data)
		mmci_get_next_data(host, mrq->data);

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	if (mrq->data && mrq->data->flags & MMC_DATA_READ)
		mmci_start_data(host, mrq->data);

	mmci_start_command(host, mrq->cmd, 0);

1020
	spin_unlock_irqrestore(&host->lock, flags);
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}

static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
	struct mmci_host *host = mmc_priv(mmc);
1026
	struct variant_data *variant = host->variant;
1027 1028
	u32 pwr = 0;
	unsigned long flags;
1029
	int ret;
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1030

1031 1032
	pm_runtime_get_sync(mmc_dev(mmc));

1033 1034 1035 1036
	if (host->plat->ios_handler &&
		host->plat->ios_handler(mmc_dev(mmc), ios))
			dev_err(mmc_dev(mmc), "platform ios_handler failed\n");

L
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	switch (ios->power_mode) {
	case MMC_POWER_OFF:
1039 1040
		if (host->vcc)
			ret = mmc_regulator_set_ocr(mmc, host->vcc, 0);
L
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		break;
	case MMC_POWER_UP:
1043 1044 1045 1046 1047 1048 1049 1050 1051 1052
		if (host->vcc) {
			ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd);
			if (ret) {
				dev_err(mmc_dev(mmc), "unable to set OCR\n");
				/*
				 * The .set_ios() function in the mmc_host_ops
				 * struct return void, and failing to set the
				 * power should be rare so we print an error
				 * and return here.
				 */
1053
				goto out;
1054 1055
			}
		}
1056 1057 1058 1059 1060 1061 1062 1063
		/*
		 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
		 * and instead uses MCI_PWR_ON so apply whatever value is
		 * configured in the variant data.
		 */
		pwr |= variant->pwrreg_powerup;

		break;
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	case MMC_POWER_ON:
		pwr |= MCI_PWR_ON;
		break;
	}

1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084
	if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
		/*
		 * The ST Micro variant has some additional bits
		 * indicating signal direction for the signals in
		 * the SD/MMC bus and feedback-clock usage.
		 */
		pwr |= host->plat->sigdir;

		if (ios->bus_width == MMC_BUS_WIDTH_4)
			pwr &= ~MCI_ST_DATA74DIREN;
		else if (ios->bus_width == MMC_BUS_WIDTH_1)
			pwr &= (~MCI_ST_DATA74DIREN &
				~MCI_ST_DATA31DIREN &
				~MCI_ST_DATA2DIREN);
	}

1085
	if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
1086
		if (host->hw_designer != AMBA_VENDOR_ST)
1087 1088 1089 1090 1091 1092 1093 1094 1095
			pwr |= MCI_ROD;
		else {
			/*
			 * The ST Micro variant use the ROD bit for something
			 * else and only has OD (Open Drain).
			 */
			pwr |= MCI_OD;
		}
	}
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1097 1098 1099
	spin_lock_irqsave(&host->lock, flags);

	mmci_set_clkreg(host, ios->clock);
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1100 1101 1102 1103 1104

	if (host->pwr != pwr) {
		host->pwr = pwr;
		writel(pwr, host->base + MMCIPOWER);
	}
1105 1106

	spin_unlock_irqrestore(&host->lock, flags);
1107 1108 1109 1110

 out:
	pm_runtime_mark_last_busy(mmc_dev(mmc));
	pm_runtime_put_autosuspend(mmc_dev(mmc));
L
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}

1113 1114 1115 1116 1117 1118 1119
static int mmci_get_ro(struct mmc_host *mmc)
{
	struct mmci_host *host = mmc_priv(mmc);

	if (host->gpio_wp == -ENOSYS)
		return -ENOSYS;

1120
	return gpio_get_value_cansleep(host->gpio_wp);
1121 1122 1123 1124 1125
}

static int mmci_get_cd(struct mmc_host *mmc)
{
	struct mmci_host *host = mmc_priv(mmc);
1126
	struct mmci_platform_data *plat = host->plat;
1127 1128
	unsigned int status;

1129 1130 1131 1132
	if (host->gpio_cd == -ENOSYS) {
		if (!plat->status)
			return 1; /* Assume always present */

1133
		status = plat->status(mmc_dev(host->mmc));
1134
	} else
1135 1136
		status = !!gpio_get_value_cansleep(host->gpio_cd)
			^ plat->cd_invert;
1137

1138 1139 1140 1141 1142
	/*
	 * Use positive logic throughout - status is zero for no card,
	 * non-zero for card inserted.
	 */
	return status;
1143 1144
}

1145 1146 1147 1148 1149 1150 1151 1152 1153
static irqreturn_t mmci_cd_irq(int irq, void *dev_id)
{
	struct mmci_host *host = dev_id;

	mmc_detect_change(host->mmc, msecs_to_jiffies(500));

	return IRQ_HANDLED;
}

1154
static const struct mmc_host_ops mmci_ops = {
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	.request	= mmci_request,
1156 1157
	.pre_req	= mmci_pre_request,
	.post_req	= mmci_post_request,
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	.set_ios	= mmci_set_ios,
1159 1160
	.get_ro		= mmci_get_ro,
	.get_cd		= mmci_get_cd,
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};

1163 1164
static int __devinit mmci_probe(struct amba_device *dev,
	const struct amba_id *id)
L
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{
1166
	struct mmci_platform_data *plat = dev->dev.platform_data;
1167
	struct variant_data *variant = id->data;
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	struct mmci_host *host;
	struct mmc_host *mmc;
	int ret;

	/* must have platform data */
	if (!plat) {
		ret = -EINVAL;
		goto out;
	}

	ret = amba_request_regions(dev, DRIVER_NAME);
	if (ret)
		goto out;

	mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
	if (!mmc) {
		ret = -ENOMEM;
		goto rel_regions;
	}

	host = mmc_priv(mmc);
1189
	host->mmc = mmc;
R
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1191 1192
	host->gpio_wp = -ENOSYS;
	host->gpio_cd = -ENOSYS;
1193
	host->gpio_cd_irq = -1;
1194

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	host->hw_designer = amba_manf(dev);
	host->hw_revision = amba_rev(dev);
1197 1198
	dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
	dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
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1200
	host->clk = clk_get(&dev->dev, NULL);
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	if (IS_ERR(host->clk)) {
		ret = PTR_ERR(host->clk);
		host->clk = NULL;
		goto host_free;
	}

1207
	ret = clk_prepare(host->clk);
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	if (ret)
1209
		goto clk_free;
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1211 1212 1213 1214
	ret = clk_enable(host->clk);
	if (ret)
		goto clk_unprep;

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	host->plat = plat;
1216
	host->variant = variant;
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	host->mclk = clk_get_rate(host->clk);
1218 1219 1220 1221 1222 1223 1224 1225 1226 1227
	/*
	 * According to the spec, mclk is max 100 MHz,
	 * so we try to adjust the clock down to this,
	 * (if possible).
	 */
	if (host->mclk > 100000000) {
		ret = clk_set_rate(host->clk, 100000000);
		if (ret < 0)
			goto clk_disable;
		host->mclk = clk_get_rate(host->clk);
1228 1229
		dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
			host->mclk);
1230
	}
1231
	host->phybase = dev->res.start;
1232
	host->base = ioremap(dev->res.start, resource_size(&dev->res));
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	if (!host->base) {
		ret = -ENOMEM;
		goto clk_disable;
	}

	mmc->ops = &mmci_ops;
1239 1240 1241 1242 1243 1244 1245 1246 1247
	/*
	 * The ARM and ST versions of the block have slightly different
	 * clock divider equations which means that the minimum divider
	 * differs too.
	 */
	if (variant->st_clkdiv)
		mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
	else
		mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259
	/*
	 * If the platform data supplies a maximum operating
	 * frequency, this takes precedence. Else, we fall back
	 * to using the module parameter, which has a (low)
	 * default value in case it is not specified. Either
	 * value must not exceed the clock rate into the block,
	 * of course.
	 */
	if (plat->f_max)
		mmc->f_max = min(host->mclk, plat->f_max);
	else
		mmc->f_max = min(host->mclk, fmax);
1260 1261
	dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);

1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284
#ifdef CONFIG_REGULATOR
	/* If we're using the regulator framework, try to fetch a regulator */
	host->vcc = regulator_get(&dev->dev, "vmmc");
	if (IS_ERR(host->vcc))
		host->vcc = NULL;
	else {
		int mask = mmc_regulator_get_ocrmask(host->vcc);

		if (mask < 0)
			dev_err(&dev->dev, "error getting OCR mask (%d)\n",
				mask);
		else {
			host->mmc->ocr_avail = (u32) mask;
			if (plat->ocr_mask)
				dev_warn(&dev->dev,
				 "Provided ocr_mask/setpower will not be used "
				 "(using regulator instead)\n");
		}
	}
#endif
	/* Fall back to platform data if no regulator is found */
	if (host->vcc == NULL)
		mmc->ocr_avail = plat->ocr_mask;
1285
	mmc->caps = plat->capabilities;
1286
	mmc->caps2 = plat->capabilities2;
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	/*
	 * We can do SGIO
	 */
1291
	mmc->max_segs = NR_SG;
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	/*
1294 1295 1296
	 * Since only a certain number of bits are valid in the data length
	 * register, we must ensure that we don't exceed 2^num-1 bytes in a
	 * single request.
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	 */
1298
	mmc->max_req_size = (1 << variant->datalength_bits) - 1;
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	/*
	 * Set the maximum segment size.  Since we aren't doing DMA
	 * (yet) we are only limited by the data length register.
	 */
1304
	mmc->max_seg_size = mmc->max_req_size;
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1306 1307 1308 1309 1310
	/*
	 * Block size can be up to 2048 bytes, but must be a power of two.
	 */
	mmc->max_blk_size = 2048;

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	/*
	 * No limit on the number of blocks transferred.
	 */
	mmc->max_blk_count = mmc->max_req_size;

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	spin_lock_init(&host->lock);

	writel(0, host->base + MMCIMASK0);
	writel(0, host->base + MMCIMASK1);
	writel(0xfff, host->base + MMCICLEAR);

1322 1323 1324 1325 1326 1327 1328 1329
	if (gpio_is_valid(plat->gpio_cd)) {
		ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)");
		if (ret == 0)
			ret = gpio_direction_input(plat->gpio_cd);
		if (ret == 0)
			host->gpio_cd = plat->gpio_cd;
		else if (ret != -ENOSYS)
			goto err_gpio_cd;
1330

1331 1332 1333 1334 1335 1336 1337
		/*
		 * A gpio pin that will detect cards when inserted and removed
		 * will most likely want to trigger on the edges if it is
		 * 0 when ejected and 1 when inserted (or mutatis mutandis
		 * for the inverted case) so we request triggers on both
		 * edges.
		 */
1338
		ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd),
1339 1340 1341
				mmci_cd_irq,
				IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
				DRIVER_NAME " (cd)", host);
1342 1343
		if (ret >= 0)
			host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd);
1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354
	}
	if (gpio_is_valid(plat->gpio_wp)) {
		ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)");
		if (ret == 0)
			ret = gpio_direction_input(plat->gpio_wp);
		if (ret == 0)
			host->gpio_wp = plat->gpio_wp;
		else if (ret != -ENOSYS)
			goto err_gpio_wp;
	}

1355 1356
	if ((host->plat->status || host->gpio_cd != -ENOSYS)
	    && host->gpio_cd_irq < 0)
1357 1358
		mmc->caps |= MMC_CAP_NEEDS_POLL;

1359
	ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
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	if (ret)
		goto unmap;

1363 1364 1365 1366 1367 1368 1369 1370
	if (dev->irq[1] == NO_IRQ)
		host->singleirq = true;
	else {
		ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED,
				  DRIVER_NAME " (pio)", host);
		if (ret)
			goto irq0_free;
	}
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1372
	writel(MCI_IRQENABLE, host->base + MMCIMASK0);
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	amba_set_drvdata(dev, mmc);

1376 1377 1378 1379 1380 1381
	dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
		 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
		 amba_rev(dev), (unsigned long long)dev->res.start,
		 dev->irq[0], dev->irq[1]);

	mmci_dma_setup(host);
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1383 1384
	pm_runtime_set_autosuspend_delay(&dev->dev, 50);
	pm_runtime_use_autosuspend(&dev->dev);
1385 1386
	pm_runtime_put(&dev->dev);

1387 1388
	mmc_add_host(mmc);

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	return 0;

 irq0_free:
	free_irq(dev->irq[0], host);
 unmap:
1394 1395 1396
	if (host->gpio_wp != -ENOSYS)
		gpio_free(host->gpio_wp);
 err_gpio_wp:
1397 1398
	if (host->gpio_cd_irq >= 0)
		free_irq(host->gpio_cd_irq, host);
1399 1400 1401
	if (host->gpio_cd != -ENOSYS)
		gpio_free(host->gpio_cd);
 err_gpio_cd:
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	iounmap(host->base);
 clk_disable:
	clk_disable(host->clk);
1405 1406
 clk_unprep:
	clk_unprepare(host->clk);
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 clk_free:
	clk_put(host->clk);
 host_free:
	mmc_free_host(mmc);
 rel_regions:
	amba_release_regions(dev);
 out:
	return ret;
}

1417
static int __devexit mmci_remove(struct amba_device *dev)
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{
	struct mmc_host *mmc = amba_get_drvdata(dev);

	amba_set_drvdata(dev, NULL);

	if (mmc) {
		struct mmci_host *host = mmc_priv(mmc);

1426 1427 1428 1429 1430 1431
		/*
		 * Undo pm_runtime_put() in probe.  We use the _sync
		 * version here so that we can access the primecell.
		 */
		pm_runtime_get_sync(&dev->dev);

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		mmc_remove_host(mmc);

		writel(0, host->base + MMCIMASK0);
		writel(0, host->base + MMCIMASK1);

		writel(0, host->base + MMCICOMMAND);
		writel(0, host->base + MMCIDATACTRL);

1440
		mmci_dma_release(host);
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		free_irq(dev->irq[0], host);
1442 1443
		if (!host->singleirq)
			free_irq(dev->irq[1], host);
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1445 1446
		if (host->gpio_wp != -ENOSYS)
			gpio_free(host->gpio_wp);
1447 1448
		if (host->gpio_cd_irq >= 0)
			free_irq(host->gpio_cd_irq, host);
1449 1450 1451
		if (host->gpio_cd != -ENOSYS)
			gpio_free(host->gpio_cd);

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		iounmap(host->base);
		clk_disable(host->clk);
1454
		clk_unprepare(host->clk);
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		clk_put(host->clk);

1457 1458
		if (host->vcc)
			mmc_regulator_set_ocr(mmc, host->vcc, 0);
1459 1460
		regulator_put(host->vcc);

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		mmc_free_host(mmc);

		amba_release_regions(dev);
	}

	return 0;
}

1469 1470
#ifdef CONFIG_SUSPEND
static int mmci_suspend(struct device *dev)
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{
1472 1473
	struct amba_device *adev = to_amba_device(dev);
	struct mmc_host *mmc = amba_get_drvdata(adev);
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	int ret = 0;

	if (mmc) {
		struct mmci_host *host = mmc_priv(mmc);

1479
		ret = mmc_suspend_host(mmc);
1480 1481
		if (ret == 0) {
			pm_runtime_get_sync(dev);
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			writel(0, host->base + MMCIMASK0);
1483
		}
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	}

	return ret;
}

1489
static int mmci_resume(struct device *dev)
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{
1491 1492
	struct amba_device *adev = to_amba_device(dev);
	struct mmc_host *mmc = amba_get_drvdata(adev);
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	int ret = 0;

	if (mmc) {
		struct mmci_host *host = mmc_priv(mmc);

		writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1499
		pm_runtime_put(dev);
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		ret = mmc_resume_host(mmc);
	}

	return ret;
}
#endif

1508 1509 1510 1511
static const struct dev_pm_ops mmci_dev_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume)
};

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static struct amba_id mmci_ids[] = {
	{
		.id	= 0x00041180,
1515
		.mask	= 0xff0fffff,
1516
		.data	= &variant_arm,
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	},
1518 1519 1520 1521 1522
	{
		.id	= 0x01041180,
		.mask	= 0xff0fffff,
		.data	= &variant_arm_extended_fifo,
	},
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	{
		.id	= 0x00041181,
		.mask	= 0x000fffff,
1526
		.data	= &variant_arm,
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1527
	},
1528 1529 1530 1531
	/* ST Micro variants */
	{
		.id     = 0x00180180,
		.mask   = 0x00ffffff,
1532
		.data	= &variant_u300,
1533 1534 1535 1536
	},
	{
		.id     = 0x00280180,
		.mask   = 0x00ffffff,
1537 1538 1539 1540
		.data	= &variant_u300,
	},
	{
		.id     = 0x00480180,
1541
		.mask   = 0xf0ffffff,
1542
		.data	= &variant_ux500,
1543
	},
1544 1545 1546 1547 1548
	{
		.id     = 0x10480180,
		.mask   = 0xf0ffffff,
		.data	= &variant_ux500v2,
	},
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	{ 0, 0 },
};

1552 1553
MODULE_DEVICE_TABLE(amba, mmci_ids);

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static struct amba_driver mmci_driver = {
	.drv		= {
		.name	= DRIVER_NAME,
1557
		.pm	= &mmci_dev_pm_ops,
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	},
	.probe		= mmci_probe,
1560
	.remove		= __devexit_p(mmci_remove),
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	.id_table	= mmci_ids,
};

static int __init mmci_init(void)
{
	return amba_driver_register(&mmci_driver);
}

static void __exit mmci_exit(void)
{
	amba_driver_unregister(&mmci_driver);
}

module_init(mmci_init);
module_exit(mmci_exit);
module_param(fmax, uint, 0444);

MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
MODULE_LICENSE("GPL");