intel_drv.h 58.6 KB
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/*
 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
 * Copyright (c) 2007-2008 Intel Corporation
 *   Jesse Barnes <jesse.barnes@intel.com>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 */
#ifndef __INTEL_DRV_H__
#define __INTEL_DRV_H__

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#include <linux/async.h>
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#include <linux/i2c.h>
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#include <linux/hdmi.h>
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_fb_helper.h>
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#include <drm/drm_dp_dual_mode_helper.h>
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#include <drm/drm_dp_mst_helper.h>
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#include <drm/drm_rect.h>
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#include <drm/drm_atomic.h>
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/**
 * _wait_for - magic (register) wait macro
 *
 * Does the right thing for modeset paths when run under kdgb or similar atomic
 * contexts. Note that it's important that we check the condition again after
 * having timed out, since the timeout could be due to preemption or similar and
 * we've never had a chance to check the condition before the timeout.
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 *
 * TODO: When modesetting has fully transitioned to atomic, the below
 * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
 * added.
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 */
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#define _wait_for(COND, US, W) ({ \
	unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;	\
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	int ret__ = 0;							\
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	while (!(COND)) {						\
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		if (time_after(jiffies, timeout__)) {			\
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			if (!(COND))					\
				ret__ = -ETIMEDOUT;			\
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			break;						\
		}							\
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		if ((W) && drm_can_sleep()) {				\
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			usleep_range((W), (W)*2);			\
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		} else {						\
			cpu_relax();					\
		}							\
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	}								\
	ret__;								\
})

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#define wait_for(COND, MS)	  	_wait_for((COND), (MS) * 1000, 1000)

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/* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
#if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
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# define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
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#else
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# define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
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#endif

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#define _wait_for_atomic(COND, US, ATOMIC) \
({ \
	int cpu, ret, timeout = (US) * 1000; \
	u64 base; \
	_WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
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	BUILD_BUG_ON((US) > 50000); \
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	if (!(ATOMIC)) { \
		preempt_disable(); \
		cpu = smp_processor_id(); \
	} \
	base = local_clock(); \
	for (;;) { \
		u64 now = local_clock(); \
		if (!(ATOMIC)) \
			preempt_enable(); \
		if (COND) { \
			ret = 0; \
			break; \
		} \
		if (now - base >= timeout) { \
			ret = -ETIMEDOUT; \
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			break; \
		} \
		cpu_relax(); \
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		if (!(ATOMIC)) { \
			preempt_disable(); \
			if (unlikely(cpu != smp_processor_id())) { \
				timeout -= now - base; \
				cpu = smp_processor_id(); \
				base = local_clock(); \
			} \
		} \
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	} \
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	ret; \
})

#define wait_for_us(COND, US) \
({ \
	int ret__; \
	BUILD_BUG_ON(!__builtin_constant_p(US)); \
	if ((US) > 10) \
		ret__ = _wait_for((COND), (US), 10); \
	else \
		ret__ = _wait_for_atomic((COND), (US), 0); \
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	ret__; \
})

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#define wait_for_atomic(COND, MS)	_wait_for_atomic((COND), (MS) * 1000, 1)
#define wait_for_atomic_us(COND, US)	_wait_for_atomic((COND), (US), 1)
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#define KHz(x) (1000 * (x))
#define MHz(x) KHz(1000 * (x))
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/*
 * Display related stuff
 */

/* store information about an Ixxx DVO */
/* The i830->i865 use multiple DVOs with multiple i2cs */
/* the i915, i945 have a single sDVO i2c bus - which is different */
#define MAX_OUTPUTS 6
/* maximum connectors per crtcs in the mode set */

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/* Maximum cursor sizes */
#define GEN2_CURSOR_WIDTH 64
#define GEN2_CURSOR_HEIGHT 64
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#define MAX_CURSOR_WIDTH 256
#define MAX_CURSOR_HEIGHT 256
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#define INTEL_I2C_BUS_DVO 1
#define INTEL_I2C_BUS_SDVO 2

/* these are outputs from the chip - integrated only
   external chips are via DVO or SDVO output */
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enum intel_output_type {
	INTEL_OUTPUT_UNUSED = 0,
	INTEL_OUTPUT_ANALOG = 1,
	INTEL_OUTPUT_DVO = 2,
	INTEL_OUTPUT_SDVO = 3,
	INTEL_OUTPUT_LVDS = 4,
	INTEL_OUTPUT_TVOUT = 5,
	INTEL_OUTPUT_HDMI = 6,
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	INTEL_OUTPUT_DP = 7,
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	INTEL_OUTPUT_EDP = 8,
	INTEL_OUTPUT_DSI = 9,
	INTEL_OUTPUT_UNKNOWN = 10,
	INTEL_OUTPUT_DP_MST = 11,
};
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#define INTEL_DVO_CHIP_NONE 0
#define INTEL_DVO_CHIP_LVDS 1
#define INTEL_DVO_CHIP_TMDS 2
#define INTEL_DVO_CHIP_TVOUT 4

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#define INTEL_DSI_VIDEO_MODE	0
#define INTEL_DSI_COMMAND_MODE	1
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struct intel_framebuffer {
	struct drm_framebuffer base;
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	struct drm_i915_gem_object *obj;
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	struct intel_rotation_info rot_info;
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};

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struct intel_fbdev {
	struct drm_fb_helper helper;
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	struct intel_framebuffer *fb;
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	async_cookie_t cookie;
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	int preferred_bpp;
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};
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struct intel_encoder {
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	struct drm_encoder base;
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	enum intel_output_type type;
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	unsigned int cloneable;
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	void (*hot_plug)(struct intel_encoder *);
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	bool (*compute_config)(struct intel_encoder *,
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			       struct intel_crtc_state *);
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	void (*pre_pll_enable)(struct intel_encoder *);
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	void (*pre_enable)(struct intel_encoder *);
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	void (*enable)(struct intel_encoder *);
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	void (*mode_set)(struct intel_encoder *intel_encoder);
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	void (*disable)(struct intel_encoder *);
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	void (*post_disable)(struct intel_encoder *);
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	void (*post_pll_disable)(struct intel_encoder *);
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	/* Read out the current hw state of this connector, returning true if
	 * the encoder is active. If the encoder is enabled it also set the pipe
	 * it is connected to in the pipe parameter. */
	bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
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	/* Reconstructs the equivalent mode flags for the current hardware
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	 * state. This must be called _after_ display->get_pipe_config has
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	 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
	 * be set correctly before calling this function. */
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	void (*get_config)(struct intel_encoder *,
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			   struct intel_crtc_state *pipe_config);
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	/*
	 * Called during system suspend after all pending requests for the
	 * encoder are flushed (for example for DP AUX transactions) and
	 * device interrupts are disabled.
	 */
	void (*suspend)(struct intel_encoder *);
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	int crtc_mask;
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	enum hpd_pin hpd_pin;
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};

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struct intel_panel {
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	struct drm_display_mode *fixed_mode;
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	struct drm_display_mode *downclock_mode;
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	int fitting_mode;
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	/* backlight */
	struct {
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		bool present;
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		u32 level;
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		u32 min;
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		u32 max;
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		bool enabled;
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		bool combination_mode;	/* gen 2/4 only */
		bool active_low_pwm;
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		/* PWM chip */
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		bool util_pin_active_low;	/* bxt+ */
		u8 controller;		/* bxt+ only */
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		struct pwm_device *pwm;

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		struct backlight_device *device;
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		/* Connector and platform specific backlight functions */
		int (*setup)(struct intel_connector *connector, enum pipe pipe);
		uint32_t (*get)(struct intel_connector *connector);
		void (*set)(struct intel_connector *connector, uint32_t level);
		void (*disable)(struct intel_connector *connector);
		void (*enable)(struct intel_connector *connector);
		uint32_t (*hz_to_pwm)(struct intel_connector *connector,
				      uint32_t hz);
		void (*power)(struct intel_connector *, bool enable);
	} backlight;
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};

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struct intel_connector {
	struct drm_connector base;
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	/*
	 * The fixed encoder this connector is connected to.
	 */
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	struct intel_encoder *encoder;
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	/* Reads out the current hw, returning true if the connector is enabled
	 * and active (i.e. dpms ON state). */
	bool (*get_hw_state)(struct intel_connector *);
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	/* Panel info for eDP and LVDS */
	struct intel_panel panel;
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	/* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
	struct edid *edid;
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	struct edid *detect_edid;
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	/* since POLL and HPD connectors may use the same HPD line keep the native
	   state of connector->polled in case hotplug storm detection changes it */
	u8 polled;
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	void *port; /* store this opaque as its illegal to dereference it */

	struct intel_dp *mst_port;
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};

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struct dpll {
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	/* given values */
	int n;
	int m1, m2;
	int p1, p2;
	/* derived values */
	int	dot;
	int	vco;
	int	m;
	int	p;
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};
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struct intel_atomic_state {
	struct drm_atomic_state base;

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	unsigned int cdclk;
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	/*
	 * Calculated device cdclk, can be different from cdclk
	 * only when all crtc's are DPMS off.
	 */
	unsigned int dev_cdclk;

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	bool dpll_set, modeset;

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	/*
	 * Does this transaction change the pipes that are active?  This mask
	 * tracks which CRTC's have changed their active state at the end of
	 * the transaction (not counting the temporary disable during modesets).
	 * This mask should only be non-zero when intel_state->modeset is true,
	 * but the converse is not necessarily true; simply changing a mode may
	 * not flip the final active status of any CRTC's
	 */
	unsigned int active_pipe_changes;

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	unsigned int active_crtcs;
	unsigned int min_pixclk[I915_MAX_PIPES];

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	/* SKL/KBL Only */
	unsigned int cdclk_pll_vco;

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	struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
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	/*
	 * Current watermarks can't be trusted during hardware readout, so
	 * don't bother calculating intermediate watermarks.
	 */
	bool skip_intermediate_wm;
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	/* Gen9+ only */
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	struct skl_wm_values wm_results;
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};

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struct intel_plane_state {
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	struct drm_plane_state base;
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	struct drm_rect src;
	struct drm_rect dst;
	struct drm_rect clip;
	bool visible;
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	/*
	 * scaler_id
	 *    = -1 : not using a scaler
	 *    >=  0 : using a scalers
	 *
	 * plane requiring a scaler:
	 *   - During check_plane, its bit is set in
	 *     crtc_state->scaler_state.scaler_users by calling helper function
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	 *     update_scaler_plane.
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	 *   - scaler_id indicates the scaler it got assigned.
	 *
	 * plane doesn't require a scaler:
	 *   - this can happen when scaling is no more required or plane simply
	 *     got disabled.
	 *   - During check_plane, corresponding bit is reset in
	 *     crtc_state->scaler_state.scaler_users by calling helper function
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	 *     update_scaler_plane.
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	 */
	int scaler_id;
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	struct drm_intel_sprite_colorkey ckey;
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	/* async flip related structures */
	struct drm_i915_gem_request *wait_req;
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};

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struct intel_initial_plane_config {
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	struct intel_framebuffer *fb;
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	unsigned int tiling;
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	int size;
	u32 base;
};

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#define SKL_MIN_SRC_W 8
#define SKL_MAX_SRC_W 4096
#define SKL_MIN_SRC_H 8
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#define SKL_MAX_SRC_H 4096
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#define SKL_MIN_DST_W 8
#define SKL_MAX_DST_W 4096
#define SKL_MIN_DST_H 8
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#define SKL_MAX_DST_H 4096
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struct intel_scaler {
	int in_use;
	uint32_t mode;
};

struct intel_crtc_scaler_state {
#define SKL_NUM_SCALERS 2
	struct intel_scaler scalers[SKL_NUM_SCALERS];

	/*
	 * scaler_users: keeps track of users requesting scalers on this crtc.
	 *
	 *     If a bit is set, a user is using a scaler.
	 *     Here user can be a plane or crtc as defined below:
	 *       bits 0-30 - plane (bit position is index from drm_plane_index)
	 *       bit 31    - crtc
	 *
	 * Instead of creating a new index to cover planes and crtc, using
	 * existing drm_plane_index for planes which is well less than 31
	 * planes and bit 31 for crtc. This should be fine to cover all
	 * our platforms.
	 *
	 * intel_atomic_setup_scalers will setup available scalers to users
	 * requesting scalers. It will gracefully fail if request exceeds
	 * avilability.
	 */
#define SKL_CRTC_INDEX 31
	unsigned scaler_users;

	/* scaler used by crtc for panel fitting purpose */
	int scaler_id;
};

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/* drm_mode->private_flags */
#define I915_MODE_FLAG_INHERITED 1

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struct intel_pipe_wm {
	struct intel_wm_level wm[5];
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	struct intel_wm_level raw_wm[5];
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	uint32_t linetime;
	bool fbc_wm_enabled;
	bool pipe_enabled;
	bool sprites_enabled;
	bool sprites_scaled;
};

struct skl_pipe_wm {
	struct skl_wm_level wm[8];
	struct skl_wm_level trans_wm;
	uint32_t linetime;
};

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struct intel_crtc_wm_state {
	union {
		struct {
			/*
			 * Intermediate watermarks; these can be
			 * programmed immediately since they satisfy
			 * both the current configuration we're
			 * switching away from and the new
			 * configuration we're switching to.
			 */
			struct intel_pipe_wm intermediate;

			/*
			 * Optimal watermarks, programmed post-vblank
			 * when this state is committed.
			 */
			struct intel_pipe_wm optimal;
		} ilk;

		struct {
			/* gen9+ only needs 1-step wm programming */
			struct skl_pipe_wm optimal;
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			/* cached plane data rate */
			unsigned plane_data_rate[I915_MAX_PLANES];
			unsigned plane_y_data_rate[I915_MAX_PLANES];
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			/* minimum block allocation */
			uint16_t minimum_blocks[I915_MAX_PLANES];
			uint16_t minimum_y_blocks[I915_MAX_PLANES];
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		} skl;
	};

	/*
	 * Platforms with two-step watermark programming will need to
	 * update watermark programming post-vblank to switch from the
	 * safe intermediate watermarks to the optimal final
	 * watermarks.
	 */
	bool need_postvbl_update;
};

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struct intel_crtc_state {
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	struct drm_crtc_state base;

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	/**
	 * quirks - bitfield with hw state readout quirks
	 *
	 * For various reasons the hw state readout code might not be able to
	 * completely faithfully read out the current state. These cases are
	 * tracked with quirk flags so that fastboot and state checker can act
	 * accordingly.
	 */
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#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS	(1<<0) /* unreliable sync mode.flags */
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	unsigned long quirks;

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	unsigned fb_bits; /* framebuffers to flip */
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	bool update_pipe; /* can a fast modeset be performed? */
	bool disable_cxsr;
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	bool update_wm_pre, update_wm_post; /* watermarks are updated */
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	bool fb_changed; /* fb on any of the planes is changed */
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	/* Pipe source size (ie. panel fitter input size)
	 * All planes will be positioned inside this space,
	 * and get clipped at the edges. */
	int pipe_src_w, pipe_src_h;

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	/* Whether to set up the PCH/FDI. Note that we never allow sharing
	 * between pch encoders and cpu encoders. */
	bool has_pch_encoder;
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	/* Are we sending infoframes on the attached port */
	bool has_infoframe;

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	/* CPU Transcoder for the pipe. Currently this can only differ from the
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	 * pipe on Haswell and later (where we have a special eDP transcoder)
	 * and Broxton (where we have special DSI transcoders). */
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	enum transcoder cpu_transcoder;

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	/*
	 * Use reduced/limited/broadcast rbg range, compressing from the full
	 * range fed into the crtcs.
	 */
	bool limited_color_range;

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	/* Bitmask of encoder types (enum intel_output_type)
	 * driven by the pipe.
	 */
	unsigned int output_types;

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	/* Whether we should send NULL infoframes. Required for audio. */
	bool has_hdmi_sink;

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	/* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
	 * has_dp_encoder is set. */
	bool has_audio;

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	/*
	 * Enable dithering, used when the selected pipe bpp doesn't match the
	 * plane bpp.
	 */
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	bool dither;
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	/* Controls for the clock computation, to override various stages. */
	bool clock_set;

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	/* SDVO TV has a bunch of special case. To make multifunction encoders
	 * work correctly, we need to track this at runtime.*/
	bool sdvo_tv_clock;

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	/*
	 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
	 * required. This is set in the 2nd loop of calling encoder's
	 * ->compute_config if the first pick doesn't work out.
	 */
	bool bw_constrained;

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	/* Settings for the intel dpll used on pretty much everything but
	 * haswell. */
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	struct dpll dpll;
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	/* Selected dpll when shared or NULL. */
	struct intel_shared_dpll *shared_dpll;
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	/*
	 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
	 * - enum skl_dpll on SKL
	 */
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	uint32_t ddi_pll_sel;

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	/* Actual register state of the dpll, for shared dpll cross-checking. */
	struct intel_dpll_hw_state dpll_hw_state;

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	/* DSI PLL registers */
	struct {
		u32 ctrl, div;
	} dsi_pll;

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	int pipe_bpp;
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	struct intel_link_m_n dp_m_n;
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	/* m2_n2 for eDP downclock */
	struct intel_link_m_n dp_m2_n2;
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	bool has_drrs;
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	/*
	 * Frequence the dpll for the port should run at. Differs from the
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	 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
	 * already multiplied by pixel_multiplier.
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	 */
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	int port_clock;

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	/* Used by SDVO (and if we ever fix it, HDMI). */
	unsigned pixel_multiplier;
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	uint8_t lane_count;

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	/*
	 * Used by platforms having DP/HDMI PHY with programmable lane
	 * latency optimization.
	 */
	uint8_t lane_lat_optim_mask;

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	/* Panel fitter controls for gen2-gen4 + VLV */
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	struct {
		u32 control;
		u32 pgm_ratios;
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		u32 lvds_border_bits;
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	} gmch_pfit;

	/* Panel fitter placement and size for Ironlake+ */
	struct {
		u32 pos;
		u32 size;
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		bool enabled;
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		bool force_thru;
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	} pch_pfit;
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	/* FDI configuration, only valid if has_pch_encoder is set. */
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	int fdi_lanes;
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	struct intel_link_m_n fdi_m_n;
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	bool ips_enabled;
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	bool enable_fbc;

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	bool double_wide;
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	bool dp_encoder_is_mst;
	int pbn;
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	struct intel_crtc_scaler_state scaler_state;
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	/* w/a for waiting 2 vblanks during crtc enable */
	enum pipe hsw_workaround_pipe;
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	/* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
	bool disable_lp_wm;
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	struct intel_crtc_wm_state wm;
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	/* Gamma mode programmed on the pipe */
	uint32_t gamma_mode;
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};

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struct vlv_wm_state {
	struct vlv_pipe_wm wm[3];
	struct vlv_sr_wm sr[3];
	uint8_t num_active_planes;
	uint8_t num_levels;
	uint8_t level;
	bool cxsr;
};

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struct intel_crtc {
	struct drm_crtc base;
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	enum pipe pipe;
	enum plane plane;
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	u8 lut_r[256], lut_g[256], lut_b[256];
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	/*
	 * Whether the crtc and the connected output pipeline is active. Implies
	 * that crtc->enabled is set, i.e. the current mode configuration has
	 * some outputs connected to this crtc.
	 */
	bool active;
665
	unsigned long enabled_power_domains;
666
	bool lowfreq_avail;
667
	struct intel_overlay *overlay;
668
	struct intel_flip_work *flip_work;
669

670 671
	atomic_t unpin_work_count;

672 673 674
	/* Display surface base address adjustement for pageflips. Note that on
	 * gen4+ this only adjusts up to a tile, offsets within a tile are
	 * handled in the hw itself (with the TILEOFF register). */
675
	u32 dspaddr_offset;
676 677
	int adjusted_x;
	int adjusted_y;
678

679
	uint32_t cursor_addr;
680
	uint32_t cursor_cntl;
681
	uint32_t cursor_size;
682
	uint32_t cursor_base;
683

684
	struct intel_crtc_state *config;
685

686 687 688
	/* reset counter value when the last flip was submitted */
	unsigned int reset_counter;

689 690 691
	/* Access to these should be protected by dev_priv->irq_lock. */
	bool cpu_fifo_underrun_disabled;
	bool pch_fifo_underrun_disabled;
692 693 694 695

	/* per-pipe watermark state */
	struct {
		/* watermarks currently being used  */
696 697 698 699
		union {
			struct intel_pipe_wm ilk;
			struct skl_pipe_wm skl;
		} active;
700

701 702
		/* allow CxSR on this pipe */
		bool cxsr_allowed;
703
	} wm;
704

705
	int scanline_offset;
706

707 708 709 710 711 712
	struct {
		unsigned start_vbl_count;
		ktime_t start_vbl_time;
		int min_vbl, max_vbl;
		int scanline_start;
	} debug;
713

714 715
	/* scalers available on this crtc */
	int num_scalers;
716 717

	struct vlv_wm_state wm_state;
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718 719
};

720 721
struct intel_plane_wm_parameters {
	uint32_t horiz_pixels;
722
	uint32_t vert_pixels;
723 724 725 726 727 728 729
	/*
	 *   For packed pixel formats:
	 *     bytes_per_pixel - holds bytes per pixel
	 *   For planar pixel formats:
	 *     bytes_per_pixel - holds bytes per pixel for uv-plane
	 *     y_bytes_per_pixel - holds bytes per pixel for y-plane
	 */
730
	uint8_t bytes_per_pixel;
731
	uint8_t y_bytes_per_pixel;
732 733
	bool enabled;
	bool scaled;
734
	u64 tiling;
735
	unsigned int rotation;
736
	uint16_t fifo_size;
737 738
};

739 740
struct intel_plane {
	struct drm_plane base;
741
	int plane;
742
	enum pipe pipe;
743
	bool can_scale;
744
	int max_downscale;
745
	uint32_t frontbuffer_bit;
746 747 748 749 750 751

	/* Since we need to change the watermarks before/after
	 * enabling/disabling the planes, we need to store the parameters here
	 * as the other pieces of the struct may not reflect the values we want
	 * for the watermark calculations. Currently only Haswell uses this.
	 */
752
	struct intel_plane_wm_parameters wm;
753

754 755 756
	/*
	 * NOTE: Do not place new plane state fields here (e.g., when adding
	 * new plane properties).  New runtime state should now be placed in
757
	 * the intel_plane_state structure and accessed via plane_state.
758 759
	 */

760
	void (*update_plane)(struct drm_plane *plane,
761 762
			     const struct intel_crtc_state *crtc_state,
			     const struct intel_plane_state *plane_state);
763
	void (*disable_plane)(struct drm_plane *plane,
764
			      struct drm_crtc *crtc);
765
	int (*check_plane)(struct drm_plane *plane,
766
			   struct intel_crtc_state *crtc_state,
767
			   struct intel_plane_state *state);
768 769
};

770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788
struct intel_watermark_params {
	unsigned long fifo_size;
	unsigned long max_wm;
	unsigned long default_wm;
	unsigned long guard_size;
	unsigned long cacheline_size;
};

struct cxsr_latency {
	int is_desktop;
	int is_ddr3;
	unsigned long fsb_freq;
	unsigned long mem_freq;
	unsigned long display_sr;
	unsigned long display_hpll_disable;
	unsigned long cursor_sr;
	unsigned long cursor_hpll_disable;
};

789
#define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
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790
#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
791
#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
792
#define to_intel_connector(x) container_of(x, struct intel_connector, base)
793
#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
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#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
795
#define to_intel_plane(x) container_of(x, struct intel_plane, base)
796
#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
797
#define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
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798

799
struct intel_hdmi {
800
	i915_reg_t hdmi_reg;
801
	int ddc_bus;
802 803 804 805
	struct {
		enum drm_dp_dual_mode_type type;
		int max_tmds_clock;
	} dp_dual_mode;
806
	bool limited_color_range;
807
	bool color_range_auto;
808 809 810
	bool has_hdmi_sink;
	bool has_audio;
	enum hdmi_force_audio force_audio;
811
	bool rgb_quant_range_selectable;
812
	enum hdmi_picture_aspect aspect_ratio;
813
	struct intel_connector *attached_connector;
814
	void (*write_infoframe)(struct drm_encoder *encoder,
815
				enum hdmi_infoframe_type type,
816
				const void *frame, ssize_t len);
817
	void (*set_infoframes)(struct drm_encoder *encoder,
818
			       bool enable,
819
			       const struct drm_display_mode *adjusted_mode);
820 821
	bool (*infoframe_enabled)(struct drm_encoder *encoder,
				  const struct intel_crtc_state *pipe_config);
822 823
};

824
struct intel_dp_mst_encoder;
825
#define DP_MAX_DOWNSTREAM_PORTS		0x10
826

827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846
/*
 * enum link_m_n_set:
 *	When platform provides two set of M_N registers for dp, we can
 *	program them and switch between them incase of DRRS.
 *	But When only one such register is provided, we have to program the
 *	required divider value on that registers itself based on the DRRS state.
 *
 * M1_N1	: Program dp_m_n on M1_N1 registers
 *			  dp_m2_n2 on M2_N2 registers (If supported)
 *
 * M2_N2	: Program dp_m2_n2 on M1_N1 registers
 *			  M2_N2 registers are not supported
 */

enum link_m_n_set {
	/* Sets the m1_n1 and m2_n2 */
	M1_N1 = 0,
	M2_N2
};

847
struct intel_dp {
848 849 850
	i915_reg_t output_reg;
	i915_reg_t aux_ch_ctl_reg;
	i915_reg_t aux_ch_data_reg[5];
851
	uint32_t DP;
852 853
	int link_rate;
	uint8_t lane_count;
854
	uint8_t sink_count;
855
	bool has_audio;
856
	bool detect_done;
857
	enum hdmi_force_audio force_audio;
858
	bool limited_color_range;
859
	bool color_range_auto;
860
	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
861
	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
862
	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
863
	uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
864 865 866
	/* sink rates as reported by DP_SUPPORTED_LINK_RATES */
	uint8_t num_sink_rates;
	int sink_rates[DP_MAX_SUPPORTED_RATES];
867
	struct drm_dp_aux aux;
868 869 870 871 872 873 874 875
	uint8_t train_set[4];
	int panel_power_up_delay;
	int panel_power_down_delay;
	int panel_power_cycle_delay;
	int backlight_on_delay;
	int backlight_off_delay;
	struct delayed_work panel_vdd_work;
	bool want_panel_vdd;
876 877
	unsigned long last_power_on;
	unsigned long last_backlight_off;
878
	ktime_t panel_power_off_time;
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879

880 881
	struct notifier_block edp_notifier;

882 883 884 885 886
	/*
	 * Pipe whose power sequencer is currently locked into
	 * this port. Only relevant on VLV/CHV.
	 */
	enum pipe pps_pipe;
887 888 889 890 891
	/*
	 * Set if the sequencer may be reset due to a power transition,
	 * requiring a reinitialization. Only relevant on BXT.
	 */
	bool pps_reset;
892
	struct edp_power_seq pps_delays;
893

894 895 896 897
	bool can_mst; /* this port supports mst */
	bool is_mst;
	int active_mst_links;
	/* connector directly attached - won't be use for modeset in mst world */
898
	struct intel_connector *attached_connector;
899

900 901 902 903
	/* mst connector list */
	struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
	struct drm_dp_mst_topology_mgr mst_mgr;

904
	uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
905 906 907 908 909 910 911 912
	/*
	 * This function returns the value we have to program the AUX_CTL
	 * register with to kick off an AUX transaction.
	 */
	uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
				     bool has_aux_irq,
				     int send_bytes,
				     uint32_t aux_clock_divider);
913 914 915 916

	/* This is called before a link training is starterd */
	void (*prepare_link_retrain)(struct intel_dp *intel_dp);

917 918
	/* Displayport compliance testing */
	unsigned long compliance_test_type;
919 920
	unsigned long compliance_test_data;
	bool compliance_test_active;
921 922
};

923 924
struct intel_digital_port {
	struct intel_encoder base;
925
	enum port port;
926
	u32 saved_port_bits;
927 928
	struct intel_dp dp;
	struct intel_hdmi hdmi;
929
	enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
930
	bool release_cl2_override;
931
	uint8_t max_lanes;
932 933
	/* for communication with audio component; protected by av_mutex */
	const struct drm_connector *audio_connector;
934 935
};

936 937 938 939
struct intel_dp_mst_encoder {
	struct intel_encoder base;
	enum pipe pipe;
	struct intel_digital_port *primary;
940
	struct intel_connector *connector;
941 942
};

943
static inline enum dpio_channel
944 945 946 947
vlv_dport_to_channel(struct intel_digital_port *dport)
{
	switch (dport->port) {
	case PORT_B:
948
	case PORT_D:
949
		return DPIO_CH0;
950
	case PORT_C:
951
		return DPIO_CH1;
952 953 954 955 956
	default:
		BUG();
	}
}

957 958 959 960 961 962 963 964 965 966 967 968 969 970 971
static inline enum dpio_phy
vlv_dport_to_phy(struct intel_digital_port *dport)
{
	switch (dport->port) {
	case PORT_B:
	case PORT_C:
		return DPIO_PHY0;
	case PORT_D:
		return DPIO_PHY1;
	default:
		BUG();
	}
}

static inline enum dpio_channel
972 973 974 975 976 977 978 979 980 981 982 983 984
vlv_pipe_to_channel(enum pipe pipe)
{
	switch (pipe) {
	case PIPE_A:
	case PIPE_C:
		return DPIO_CH0;
	case PIPE_B:
		return DPIO_CH1;
	default:
		BUG();
	}
}

985 986 987
static inline struct drm_crtc *
intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
{
988
	struct drm_i915_private *dev_priv = to_i915(dev);
989 990 991
	return dev_priv->pipe_to_crtc_mapping[pipe];
}

992 993 994
static inline struct drm_crtc *
intel_get_crtc_for_plane(struct drm_device *dev, int plane)
{
995
	struct drm_i915_private *dev_priv = to_i915(dev);
996 997 998
	return dev_priv->plane_to_crtc_mapping[plane];
}

999 1000 1001 1002
struct intel_flip_work {
	struct work_struct unpin_work;
	struct work_struct mmio_work;

1003 1004 1005
	struct drm_crtc *crtc;
	struct drm_framebuffer *old_fb;
	struct drm_i915_gem_object *pending_flip_obj;
1006
	struct drm_pending_vblank_event *event;
1007
	atomic_t pending;
1008 1009 1010
	u32 flip_count;
	u32 gtt_offset;
	struct drm_i915_gem_request *flip_queued_req;
1011
	u32 flip_queued_vblank;
1012 1013
	u32 flip_ready_vblank;
	unsigned int rotation;
1014 1015
};

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struct intel_load_detect_pipe {
1017
	struct drm_atomic_state *restore_state;
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1018
};
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1020 1021
static inline struct intel_encoder *
intel_attached_encoder(struct drm_connector *connector)
1022 1023 1024 1025
{
	return to_intel_connector(connector)->encoder;
}

1026 1027 1028 1029
static inline struct intel_digital_port *
enc_to_dig_port(struct drm_encoder *encoder)
{
	return container_of(encoder, struct intel_digital_port, base.base);
1030 1031
}

1032 1033 1034 1035 1036 1037
static inline struct intel_dp_mst_encoder *
enc_to_mst(struct drm_encoder *encoder)
{
	return container_of(encoder, struct intel_dp_mst_encoder, base.base);
}

1038 1039 1040
static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
{
	return &enc_to_dig_port(encoder)->dp;
1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052
}

static inline struct intel_digital_port *
dp_to_dig_port(struct intel_dp *intel_dp)
{
	return container_of(intel_dp, struct intel_digital_port, dp);
}

static inline struct intel_digital_port *
hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
{
	return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1053 1054
}

1055 1056 1057 1058 1059 1060 1061 1062
/*
 * Returns the number of planes for this pipe, ie the number of sprites + 1
 * (primary plane). This doesn't count the cursor plane then.
 */
static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
{
	return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
}
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1064
/* intel_fifo_underrun.c */
1065
bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1066
					   enum pipe pipe, bool enable);
1067
bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1068 1069
					   enum transcoder pch_transcoder,
					   bool enable);
1070 1071 1072 1073
void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
					 enum pipe pipe);
void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
					 enum transcoder pch_transcoder);
1074 1075
void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1076 1077

/* i915_irq.c */
1078 1079 1080 1081
void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1082
void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1083 1084
void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1085
u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
1086 1087
void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1088 1089 1090 1091 1092 1093
static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
{
	/*
	 * We only use drm_irq_uninstall() at unload and VT switch, so
	 * this is the only thing we need to check.
	 */
1094
	return dev_priv->pm.irqs_enabled;
1095 1096
}

1097
int intel_get_crtc_scanline(struct intel_crtc *crtc);
1098 1099
void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
				     unsigned int pipe_mask);
1100 1101
void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
				     unsigned int pipe_mask);
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1102 1103

/* intel_crt.c */
1104
void intel_crt_init(struct drm_device *dev);
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1105 1106 1107


/* intel_ddi.c */
1108 1109
void intel_ddi_clk_select(struct intel_encoder *encoder,
			  const struct intel_crtc_state *pipe_config);
1110
void intel_prepare_ddi_buffer(struct intel_encoder *encoder);
1111 1112 1113 1114 1115 1116 1117 1118 1119
void hsw_fdi_link_train(struct drm_crtc *crtc);
void intel_ddi_init(struct drm_device *dev, enum port port);
enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
				       enum transcoder cpu_transcoder);
void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
1120 1121
bool intel_ddi_pll_select(struct intel_crtc *crtc,
			  struct intel_crtc_state *crtc_state);
1122
void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
1123
void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1124 1125 1126
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
void intel_ddi_fdi_disable(struct drm_crtc *crtc);
void intel_ddi_get_config(struct intel_encoder *encoder,
1127
			  struct intel_crtc_state *pipe_config);
1128 1129
struct intel_encoder *
intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
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1130

1131
void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
1132
void intel_ddi_clock_get(struct intel_encoder *encoder,
1133
			 struct intel_crtc_state *pipe_config);
1134
void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
1135
uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
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1136

1137
/* intel_frontbuffer.c */
1138
void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
1139
			     enum fb_op_origin origin);
1140 1141 1142 1143 1144
void intel_frontbuffer_flip_prepare(struct drm_device *dev,
				    unsigned frontbuffer_bits);
void intel_frontbuffer_flip_complete(struct drm_device *dev,
				     unsigned frontbuffer_bits);
void intel_frontbuffer_flip(struct drm_device *dev,
1145
			    unsigned frontbuffer_bits);
1146 1147 1148 1149
unsigned int intel_fb_align_height(struct drm_device *dev,
				   unsigned int height,
				   uint32_t pixel_format,
				   uint64_t fb_format_modifier);
1150 1151
void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire,
			enum fb_op_origin origin);
1152 1153
u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
			      uint64_t fb_modifier, uint32_t pixel_format);
1154

1155
/* intel_audio.c */
1156
void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1157 1158
void intel_audio_codec_enable(struct intel_encoder *encoder);
void intel_audio_codec_disable(struct intel_encoder *encoder);
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Imre Deak 已提交
1159 1160
void i915_audio_component_init(struct drm_i915_private *dev_priv);
void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1161

1162
/* intel_display.c */
1163
void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco);
1164
void intel_update_rawclk(struct drm_i915_private *dev_priv);
1165 1166
int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
		      const char *name, u32 reg, int ref_freq);
1167
extern const struct drm_plane_funcs intel_plane_funcs;
1168
void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1169
unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1170
bool intel_has_pending_fb_unpin(struct drm_device *dev);
1171 1172
void intel_mark_busy(struct drm_i915_private *dev_priv);
void intel_mark_idle(struct drm_i915_private *dev_priv);
1173
void intel_crtc_restore_mode(struct drm_crtc *crtc);
1174
int intel_display_suspend(struct drm_device *dev);
1175
void intel_encoder_destroy(struct drm_encoder *encoder);
1176 1177
int intel_connector_init(struct intel_connector *);
struct intel_connector *intel_connector_alloc(void);
1178 1179 1180 1181 1182
bool intel_connector_get_hw_state(struct intel_connector *connector);
void intel_connector_attach_encoder(struct intel_connector *connector,
				    struct intel_encoder *encoder);
struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
					     struct drm_crtc *crtc);
1183
enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1184 1185
int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
1186 1187
enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
					     enum pipe pipe);
1188 1189 1190 1191 1192 1193
static inline bool
intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
		    enum intel_output_type type)
{
	return crtc_state->output_types & (1 << type);
}
1194 1195 1196 1197
static inline bool
intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
{
	return crtc_state->output_types &
1198
		((1 << INTEL_OUTPUT_DP) |
1199 1200 1201
		 (1 << INTEL_OUTPUT_DP_MST) |
		 (1 << INTEL_OUTPUT_EDP));
}
1202 1203 1204 1205 1206
static inline void
intel_wait_for_vblank(struct drm_device *dev, int pipe)
{
	drm_wait_one_vblank(dev, pipe);
}
1207 1208 1209 1210 1211 1212 1213 1214 1215
static inline void
intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
{
	const struct intel_crtc *crtc =
		to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));

	if (crtc->active)
		intel_wait_for_vblank(dev, pipe);
}
1216 1217 1218

u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);

1219
int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1220
void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1221 1222
			 struct intel_digital_port *dport,
			 unsigned int expected_mask);
1223 1224
bool intel_get_load_detect_pipe(struct drm_connector *connector,
				struct drm_display_mode *mode,
1225 1226
				struct intel_load_detect_pipe *old,
				struct drm_modeset_acquire_ctx *ctx);
1227
void intel_release_load_detect_pipe(struct drm_connector *connector,
1228 1229
				    struct intel_load_detect_pipe *old,
				    struct drm_modeset_acquire_ctx *ctx);
1230 1231
int intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
			       unsigned int rotation);
1232
void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1233 1234
struct drm_framebuffer *
__intel_framebuffer_create(struct drm_device *dev,
1235 1236
			   struct drm_mode_fb_cmd2 *mode_cmd,
			   struct drm_i915_gem_object *obj);
1237
void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
1238
void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
1239
void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
1240
int intel_prepare_plane_fb(struct drm_plane *plane,
1241
			   const struct drm_plane_state *new_state);
1242
void intel_cleanup_plane_fb(struct drm_plane *plane,
1243
			    const struct drm_plane_state *old_state);
1244 1245 1246 1247 1248 1249 1250 1251
int intel_plane_atomic_get_property(struct drm_plane *plane,
				    const struct drm_plane_state *state,
				    struct drm_property *property,
				    uint64_t *val);
int intel_plane_atomic_set_property(struct drm_plane *plane,
				    struct drm_plane_state *state,
				    struct drm_property *property,
				    uint64_t val);
1252 1253
int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
				    struct drm_plane_state *plane_state);
1254

1255 1256
unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
			       uint64_t fb_modifier, unsigned int cpp);
1257

1258 1259 1260 1261 1262 1263
static inline bool
intel_rotation_90_or_270(unsigned int rotation)
{
	return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
}

1264 1265 1266
void intel_create_rotation_property(struct drm_device *dev,
					struct intel_plane *plane);

1267 1268 1269
void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
				    enum pipe pipe);

1270 1271
int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
		     const struct dpll *dpll);
1272
void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1273
int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1274

1275
/* modesetting asserts */
1276 1277
void assert_panel_unlocked(struct drm_i915_private *dev_priv,
			   enum pipe pipe);
1278 1279 1280 1281
void assert_pll(struct drm_i915_private *dev_priv,
		enum pipe pipe, bool state);
#define assert_pll_enabled(d, p) assert_pll(d, p, true)
#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1282 1283 1284
void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1285 1286 1287 1288
void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
		       enum pipe pipe, bool state);
#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1289
void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1290 1291
#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1292 1293
u32 intel_compute_tile_offset(int *x, int *y,
			      const struct drm_framebuffer *fb, int plane,
1294 1295
			      unsigned int pitch,
			      unsigned int rotation);
1296 1297
void intel_prepare_reset(struct drm_i915_private *dev_priv);
void intel_finish_reset(struct drm_i915_private *dev_priv);
1298 1299
void hsw_enable_pc8(struct drm_i915_private *dev_priv);
void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1300 1301
void bxt_init_cdclk(struct drm_i915_private *dev_priv);
void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1302 1303 1304 1305 1306 1307
void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
			    enum dpio_phy phy);
bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
			      enum dpio_phy phy);
1308
void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1309 1310
void bxt_enable_dc9(struct drm_i915_private *dev_priv);
void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1311
void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1312 1313
void skl_init_cdclk(struct drm_i915_private *dev_priv);
void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1314
unsigned int skl_cdclk_get_vco(unsigned int freq);
1315 1316
void skl_enable_dc6(struct drm_i915_private *dev_priv);
void skl_disable_dc6(struct drm_i915_private *dev_priv);
1317
void intel_dp_get_m_n(struct intel_crtc *crtc,
1318
		      struct intel_crtc_state *pipe_config);
1319
void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1320
int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
I
Imre Deak 已提交
1321
bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1322 1323
			struct dpll *best_clock);
int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1324

1325
bool intel_crtc_active(struct drm_crtc *crtc);
1326 1327
void hsw_enable_ips(struct intel_crtc *crtc);
void hsw_disable_ips(struct intel_crtc *crtc);
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Imre Deak 已提交
1328 1329
enum intel_display_power_domain
intel_display_port_power_domain(struct intel_encoder *intel_encoder);
1330 1331
enum intel_display_power_domain
intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
1332
void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1333
				 struct intel_crtc_state *pipe_config);
1334

1335
int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1336
int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1337

1338 1339 1340
u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
			   struct drm_i915_gem_object *obj,
			   unsigned int plane);
1341

1342 1343 1344
u32 skl_plane_ctl_format(uint32_t pixel_format);
u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
u32 skl_plane_ctl_rotation(unsigned int rotation);
1345

1346
/* intel_csr.c */
1347
void intel_csr_ucode_init(struct drm_i915_private *);
1348
void intel_csr_load_program(struct drm_i915_private *);
1349
void intel_csr_ucode_fini(struct drm_i915_private *);
1350 1351
void intel_csr_ucode_suspend(struct drm_i915_private *);
void intel_csr_ucode_resume(struct drm_i915_private *);
1352

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1353
/* intel_dp.c */
1354
bool intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
1355 1356
bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
			     struct intel_connector *intel_connector);
1357 1358
void intel_dp_set_link_params(struct intel_dp *intel_dp,
			      const struct intel_crtc_state *pipe_config);
1359 1360 1361
void intel_dp_start_link_train(struct intel_dp *intel_dp);
void intel_dp_stop_link_train(struct intel_dp *intel_dp);
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1362 1363
void intel_dp_encoder_reset(struct drm_encoder *encoder);
void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1364
void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1365
int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1366
bool intel_dp_compute_config(struct intel_encoder *encoder,
1367
			     struct intel_crtc_state *pipe_config);
1368
bool intel_dp_is_edp(struct drm_device *dev, enum port port);
1369 1370
enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
				  bool long_hpd);
1371 1372
void intel_edp_backlight_on(struct intel_dp *intel_dp);
void intel_edp_backlight_off(struct intel_dp *intel_dp);
1373
void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1374 1375
void intel_edp_panel_on(struct intel_dp *intel_dp);
void intel_edp_panel_off(struct intel_dp *intel_dp);
1376 1377 1378
void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
void intel_dp_mst_suspend(struct drm_device *dev);
void intel_dp_mst_resume(struct drm_device *dev);
1379
int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1380
int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1381
void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1382
void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
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Rodrigo Vivi 已提交
1383
uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1384
void intel_plane_destroy(struct drm_plane *plane);
V
Vandana Kannan 已提交
1385 1386
void intel_edp_drrs_enable(struct intel_dp *intel_dp);
void intel_edp_drrs_disable(struct intel_dp *intel_dp);
1387 1388 1389
void intel_edp_drrs_invalidate(struct drm_device *dev,
		unsigned frontbuffer_bits);
void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
1390 1391
bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
					 struct intel_digital_port *port);
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1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404
void
intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
				       uint8_t dp_train_pat);
void
intel_dp_set_signal_levels(struct intel_dp *intel_dp);
void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
uint8_t
intel_dp_voltage_max(struct intel_dp *intel_dp);
uint8_t
intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
			   uint8_t *link_bw, uint8_t *rate_select);
1405
bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1406 1407 1408
bool
intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);

1409 1410 1411 1412 1413
static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
{
	return ~((1 << lane_count) - 1) & 0xf;
}

1414 1415 1416
/* intel_dp_aux_backlight.c */
int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);

1417 1418 1419
/* intel_dp_mst.c */
int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
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1420
/* intel_dsi.c */
1421
void intel_dsi_init(struct drm_device *dev);
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1422

1423 1424
/* intel_dsi_dcs_backlight.c */
int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
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1425 1426

/* intel_dvo.c */
1427
void intel_dvo_init(struct drm_device *dev);
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1428 1429


1430
/* legacy fbdev emulation in intel_fbdev.c */
1431
#ifdef CONFIG_DRM_FBDEV_EMULATION
1432
extern int intel_fbdev_init(struct drm_device *dev);
1433
extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1434
extern void intel_fbdev_fini(struct drm_device *dev);
1435
extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1436 1437
extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
extern void intel_fbdev_restore_mode(struct drm_device *dev);
1438 1439 1440 1441 1442
#else
static inline int intel_fbdev_init(struct drm_device *dev)
{
	return 0;
}
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1443

1444
static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1445 1446 1447 1448 1449 1450 1451
{
}

static inline void intel_fbdev_fini(struct drm_device *dev)
{
}

1452
static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1453 1454 1455
{
}

1456
static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1457 1458 1459
{
}
#endif
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Paulo Zanoni 已提交
1460

1461
/* intel_fbc.c */
1462 1463
void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
			   struct drm_atomic_state *state);
1464
bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1465 1466 1467
void intel_fbc_pre_update(struct intel_crtc *crtc,
			  struct intel_crtc_state *crtc_state,
			  struct intel_plane_state *plane_state);
1468
void intel_fbc_post_update(struct intel_crtc *crtc);
1469
void intel_fbc_init(struct drm_i915_private *dev_priv);
1470
void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1471 1472 1473
void intel_fbc_enable(struct intel_crtc *crtc,
		      struct intel_crtc_state *crtc_state,
		      struct intel_plane_state *plane_state);
1474 1475
void intel_fbc_disable(struct intel_crtc *crtc);
void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1476 1477 1478 1479
void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
			  unsigned int frontbuffer_bits,
			  enum fb_op_origin origin);
void intel_fbc_flush(struct drm_i915_private *dev_priv,
1480
		     unsigned int frontbuffer_bits, enum fb_op_origin origin);
1481
void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1482

P
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1483
/* intel_hdmi.c */
1484
void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
1485 1486 1487 1488
void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
			       struct intel_connector *intel_connector);
struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1489
			       struct intel_crtc_state *pipe_config);
1490
void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
P
Paulo Zanoni 已提交
1491 1492 1493


/* intel_lvds.c */
1494
void intel_lvds_init(struct drm_device *dev);
1495
struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1496
bool intel_is_dual_link_lvds(struct drm_device *dev);
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1497 1498 1499 1500


/* intel_modes.c */
int intel_connector_update_modes(struct drm_connector *connector,
1501
				 struct edid *edid);
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Paulo Zanoni 已提交
1502
int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1503 1504
void intel_attach_force_audio_property(struct drm_connector *connector);
void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1505
void intel_attach_aspect_ratio_property(struct drm_connector *connector);
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1506 1507 1508


/* intel_overlay.c */
1509 1510
void intel_setup_overlay(struct drm_i915_private *dev_priv);
void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1511
int intel_overlay_switch_off(struct intel_overlay *overlay);
1512 1513 1514 1515
int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
				  struct drm_file *file_priv);
int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
1516
void intel_overlay_reset(struct drm_i915_private *dev_priv);
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1517 1518 1519


/* intel_panel.c */
1520
int intel_panel_init(struct intel_panel *panel,
1521 1522
		     struct drm_display_mode *fixed_mode,
		     struct drm_display_mode *downclock_mode);
1523 1524 1525 1526
void intel_panel_fini(struct intel_panel *panel);
void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
			    struct drm_display_mode *adjusted_mode);
void intel_pch_panel_fitting(struct intel_crtc *crtc,
1527
			     struct intel_crtc_state *pipe_config,
1528 1529
			     int fitting_mode);
void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1530
			      struct intel_crtc_state *pipe_config,
1531
			      int fitting_mode);
1532 1533
void intel_panel_set_backlight_acpi(struct intel_connector *connector,
				    u32 level, u32 max);
1534 1535
int intel_panel_setup_backlight(struct drm_connector *connector,
				enum pipe pipe);
1536 1537
void intel_panel_enable_backlight(struct intel_connector *connector);
void intel_panel_disable_backlight(struct intel_connector *connector);
1538
void intel_panel_destroy_backlight(struct drm_connector *connector);
1539
enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1540 1541 1542 1543
extern struct drm_display_mode *intel_find_panel_downclock(
				struct drm_device *dev,
				struct drm_display_mode *fixed_mode,
				struct drm_connector *connector);
1544 1545

#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1546
int intel_backlight_device_register(struct intel_connector *connector);
1547 1548
void intel_backlight_device_unregister(struct intel_connector *connector);
#else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1549 1550 1551 1552
static int intel_backlight_device_register(struct intel_connector *connector)
{
	return 0;
}
1553 1554 1555 1556
static inline void intel_backlight_device_unregister(struct intel_connector *connector)
{
}
#endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1557

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1558

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1559 1560 1561 1562
/* intel_psr.c */
void intel_psr_enable(struct intel_dp *intel_dp);
void intel_psr_disable(struct intel_dp *intel_dp);
void intel_psr_invalidate(struct drm_device *dev,
1563
			  unsigned frontbuffer_bits);
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Rodrigo Vivi 已提交
1564
void intel_psr_flush(struct drm_device *dev,
1565 1566
		     unsigned frontbuffer_bits,
		     enum fb_op_origin origin);
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Rodrigo Vivi 已提交
1567
void intel_psr_init(struct drm_device *dev);
1568 1569
void intel_psr_single_frame_update(struct drm_device *dev,
				   unsigned frontbuffer_bits);
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1570

1571 1572
/* intel_runtime_pm.c */
int intel_power_domains_init(struct drm_i915_private *);
1573
void intel_power_domains_fini(struct drm_i915_private *);
1574 1575
void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1576 1577
void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1578
void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1579 1580
const char *
intel_display_power_domain_str(enum intel_display_power_domain domain);
1581

1582 1583 1584 1585
bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
				    enum intel_display_power_domain domain);
bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
				      enum intel_display_power_domain domain);
1586 1587
void intel_display_power_get(struct drm_i915_private *dev_priv,
			     enum intel_display_power_domain domain);
1588 1589
bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
					enum intel_display_power_domain domain);
1590 1591
void intel_display_power_put(struct drm_i915_private *dev_priv,
			     enum intel_display_power_domain domain);
1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603

static inline void
assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
{
	WARN_ONCE(dev_priv->pm.suspended,
		  "Device suspended during HW access\n");
}

static inline void
assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
{
	assert_rpm_device_not_suspended(dev_priv);
1604 1605 1606 1607
	/* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
	 * too much noise. */
	if (!atomic_read(&dev_priv->pm.wakeref_count))
		DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
1608 1609
}

1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626
static inline int
assert_rpm_atomic_begin(struct drm_i915_private *dev_priv)
{
	int seq = atomic_read(&dev_priv->pm.atomic_seq);

	assert_rpm_wakelock_held(dev_priv);

	return seq;
}

static inline void
assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq)
{
	WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq,
		  "HW access outside of RPM atomic section\n");
}

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/**
 * disable_rpm_wakeref_asserts - disable the RPM assert checks
 * @dev_priv: i915 device instance
 *
 * This function disable asserts that check if we hold an RPM wakelock
 * reference, while keeping the device-not-suspended checks still enabled.
 * It's meant to be used only in special circumstances where our rule about
 * the wakelock refcount wrt. the device power state doesn't hold. According
 * to this rule at any point where we access the HW or want to keep the HW in
 * an active state we must hold an RPM wakelock reference acquired via one of
 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
 * forcewake release timer, and the GPU RPS and hangcheck works. All other
 * users should avoid using this function.
 *
 * Any calls to this function must have a symmetric call to
 * enable_rpm_wakeref_asserts().
 */
static inline void
disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
{
	atomic_inc(&dev_priv->pm.wakeref_count);
}

/**
 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
 * @dev_priv: i915 device instance
 *
 * This function re-enables the RPM assert checks after disabling them with
 * disable_rpm_wakeref_asserts. It's meant to be used only in special
 * circumstances otherwise its use should be avoided.
 *
 * Any calls to this function must have a symmetric call to
 * disable_rpm_wakeref_asserts().
 */
static inline void
enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
{
	atomic_dec(&dev_priv->pm.wakeref_count);
}

/* TODO: convert users of these to rely instead on proper RPM refcounting */
#define DISABLE_RPM_WAKEREF_ASSERTS(dev_priv)	\
	disable_rpm_wakeref_asserts(dev_priv)

#define ENABLE_RPM_WAKEREF_ASSERTS(dev_priv)	\
	enable_rpm_wakeref_asserts(dev_priv)

1675
void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1676
bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
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void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
void intel_runtime_pm_put(struct drm_i915_private *dev_priv);

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void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);

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void chv_phy_powergate_lanes(struct intel_encoder *encoder,
			     bool override, unsigned int mask);
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bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
			  enum dpio_channel ch, bool override);
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Paulo Zanoni 已提交
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/* intel_pm.c */
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void intel_init_clock_gating(struct drm_device *dev);
void intel_suspend_hw(struct drm_device *dev);
1691
int ilk_wm_max_level(const struct drm_device *dev);
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void intel_update_watermarks(struct drm_crtc *crtc);
void intel_init_pm(struct drm_device *dev);
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void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
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Daniel Vetter 已提交
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void intel_pm_setup(struct drm_device *dev);
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void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
void intel_gpu_ips_teardown(void);
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void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
void intel_reset_gt_powersave(struct drm_i915_private *dev_priv);
void gen6_update_ring_freq(struct drm_i915_private *dev_priv);
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void gen6_rps_busy(struct drm_i915_private *dev_priv);
void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
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Daniel Vetter 已提交
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void gen6_rps_idle(struct drm_i915_private *dev_priv);
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void gen6_rps_boost(struct drm_i915_private *dev_priv,
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		    struct intel_rps_client *rps,
		    unsigned long submitted);
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void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1712
void vlv_wm_get_hw_state(struct drm_device *dev);
1713
void ilk_wm_get_hw_state(struct drm_device *dev);
1714
void skl_wm_get_hw_state(struct drm_device *dev);
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void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
			  struct skl_ddb_allocation *ddb /* out */);
1717
uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
1718
bool ilk_disable_lp_wm(struct drm_device *dev);
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int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
static inline int intel_enable_rc6(void)
{
	return i915.enable_rc6;
}
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P
Paulo Zanoni 已提交
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/* intel_sdvo.c */
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bool intel_sdvo_init(struct drm_device *dev,
		     i915_reg_t reg, enum port port);
1728

R
Rodrigo Vivi 已提交
1729

P
Paulo Zanoni 已提交
1730
/* intel_sprite.c */
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int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
1734
void intel_pipe_update_start(struct intel_crtc *crtc);
1735
void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
P
Paulo Zanoni 已提交
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/* intel_tv.c */
1738
void intel_tv_init(struct drm_device *dev);
1739

1740
/* intel_atomic.c */
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int intel_connector_atomic_get_property(struct drm_connector *connector,
					const struct drm_connector_state *state,
					struct drm_property *property,
					uint64_t *val);
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struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
void intel_crtc_destroy_state(struct drm_crtc *crtc,
			       struct drm_crtc_state *state);
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struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
void intel_atomic_state_clear(struct drm_atomic_state *);
struct intel_shared_dpll_config *
intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);

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static inline struct intel_crtc_state *
intel_atomic_get_crtc_state(struct drm_atomic_state *state,
			    struct intel_crtc *crtc)
{
	struct drm_crtc_state *crtc_state;
	crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
	if (IS_ERR(crtc_state))
1760
		return ERR_CAST(crtc_state);
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	return to_intel_crtc_state(crtc_state);
}
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static inline struct intel_plane_state *
intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
				      struct intel_plane *plane)
{
	struct drm_plane_state *plane_state;

	plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);

	return to_intel_plane_state(plane_state);
}

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int intel_atomic_setup_scalers(struct drm_device *dev,
	struct intel_crtc *intel_crtc,
	struct intel_crtc_state *crtc_state);
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/* intel_atomic_plane.c */
1781
struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
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struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
void intel_plane_destroy_state(struct drm_plane *plane,
			       struct drm_plane_state *state);
extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;

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/* intel_color.c */
void intel_color_init(struct drm_crtc *crtc);
1789
int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
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void intel_color_set_csc(struct drm_crtc_state *crtc_state);
void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1792

J
Jesse Barnes 已提交
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#endif /* __INTEL_DRV_H__ */