i2c-omap.c 34.9 KB
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/*
 * TI OMAP I2C master mode driver
 *
 * Copyright (C) 2003 MontaVista Software, Inc.
 * Copyright (C) 2005 Nokia Corporation
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 * Copyright (C) 2004 - 2007 Texas Instruments.
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 *
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 * Originally written by MontaVista Software, Inc.
 * Additional contributions by:
 *	Tony Lindgren <tony@atomide.com>
 *	Imre Deak <imre.deak@nokia.com>
 *	Juha Yrjölä <juha.yrjola@solidboot.com>
 *	Syed Khasim <x0khasim@ti.com>
 *	Nishant Menon <nm@ti.com>
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 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/completion.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/of.h>
#include <linux/of_i2c.h>
#include <linux/of_device.h>
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#include <linux/slab.h>
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#include <linux/i2c-omap.h>
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#include <linux/pm_runtime.h>
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#include <linux/pinctrl/consumer.h>
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/* I2C controller revisions */
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#define OMAP_I2C_OMAP1_REV_2		0x20
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/* I2C controller revisions present on specific hardware */
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#define OMAP_I2C_REV_ON_2430		0x00000036
#define OMAP_I2C_REV_ON_3430_3530	0x0000003C
#define OMAP_I2C_REV_ON_3630		0x00000040
#define OMAP_I2C_REV_ON_4430_PLUS	0x50400002
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/* timeout waiting for the controller to respond */
#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))

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/* timeout for pm runtime autosuspend */
#define OMAP_I2C_PM_TIMEOUT		1000	/* ms */

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/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
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enum {
	OMAP_I2C_REV_REG = 0,
	OMAP_I2C_IE_REG,
	OMAP_I2C_STAT_REG,
	OMAP_I2C_IV_REG,
	OMAP_I2C_WE_REG,
	OMAP_I2C_SYSS_REG,
	OMAP_I2C_BUF_REG,
	OMAP_I2C_CNT_REG,
	OMAP_I2C_DATA_REG,
	OMAP_I2C_SYSC_REG,
	OMAP_I2C_CON_REG,
	OMAP_I2C_OA_REG,
	OMAP_I2C_SA_REG,
	OMAP_I2C_PSC_REG,
	OMAP_I2C_SCLL_REG,
	OMAP_I2C_SCLH_REG,
	OMAP_I2C_SYSTEST_REG,
	OMAP_I2C_BUFSTAT_REG,
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	/* only on OMAP4430 */
	OMAP_I2C_IP_V2_REVNB_LO,
	OMAP_I2C_IP_V2_REVNB_HI,
	OMAP_I2C_IP_V2_IRQSTATUS_RAW,
	OMAP_I2C_IP_V2_IRQENABLE_SET,
	OMAP_I2C_IP_V2_IRQENABLE_CLR,
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};
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/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
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#define OMAP_I2C_IE_XDR		(1 << 14)	/* TX Buffer drain int enable */
#define OMAP_I2C_IE_RDR		(1 << 13)	/* RX Buffer drain int enable */
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#define OMAP_I2C_IE_XRDY	(1 << 4)	/* TX data ready int enable */
#define OMAP_I2C_IE_RRDY	(1 << 3)	/* RX data ready int enable */
#define OMAP_I2C_IE_ARDY	(1 << 2)	/* Access ready int enable */
#define OMAP_I2C_IE_NACK	(1 << 1)	/* No ack interrupt enable */
#define OMAP_I2C_IE_AL		(1 << 0)	/* Arbitration lost int ena */

/* I2C Status Register (OMAP_I2C_STAT): */
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#define OMAP_I2C_STAT_XDR	(1 << 14)	/* TX Buffer draining */
#define OMAP_I2C_STAT_RDR	(1 << 13)	/* RX Buffer draining */
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#define OMAP_I2C_STAT_BB	(1 << 12)	/* Bus busy */
#define OMAP_I2C_STAT_ROVR	(1 << 11)	/* Receive overrun */
#define OMAP_I2C_STAT_XUDF	(1 << 10)	/* Transmit underflow */
#define OMAP_I2C_STAT_AAS	(1 << 9)	/* Address as slave */
#define OMAP_I2C_STAT_AD0	(1 << 8)	/* Address zero */
#define OMAP_I2C_STAT_XRDY	(1 << 4)	/* Transmit data ready */
#define OMAP_I2C_STAT_RRDY	(1 << 3)	/* Receive data ready */
#define OMAP_I2C_STAT_ARDY	(1 << 2)	/* Register access ready */
#define OMAP_I2C_STAT_NACK	(1 << 1)	/* No ack interrupt enable */
#define OMAP_I2C_STAT_AL	(1 << 0)	/* Arbitration lost int ena */

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/* I2C WE wakeup enable register */
#define OMAP_I2C_WE_XDR_WE	(1 << 14)	/* TX drain wakup */
#define OMAP_I2C_WE_RDR_WE	(1 << 13)	/* RX drain wakeup */
#define OMAP_I2C_WE_AAS_WE	(1 << 9)	/* Address as slave wakeup*/
#define OMAP_I2C_WE_BF_WE	(1 << 8)	/* Bus free wakeup */
#define OMAP_I2C_WE_STC_WE	(1 << 6)	/* Start condition wakeup */
#define OMAP_I2C_WE_GC_WE	(1 << 5)	/* General call wakeup */
#define OMAP_I2C_WE_DRDY_WE	(1 << 3)	/* TX/RX data ready wakeup */
#define OMAP_I2C_WE_ARDY_WE	(1 << 2)	/* Reg access ready wakeup */
#define OMAP_I2C_WE_NACK_WE	(1 << 1)	/* No acknowledgment wakeup */
#define OMAP_I2C_WE_AL_WE	(1 << 0)	/* Arbitration lost wakeup */

#define OMAP_I2C_WE_ALL		(OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
				OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
				OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
				OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
				OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)

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/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
#define OMAP_I2C_BUF_RDMA_EN	(1 << 15)	/* RX DMA channel enable */
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#define OMAP_I2C_BUF_RXFIF_CLR	(1 << 14)	/* RX FIFO Clear */
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#define OMAP_I2C_BUF_XDMA_EN	(1 << 7)	/* TX DMA channel enable */
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#define OMAP_I2C_BUF_TXFIF_CLR	(1 << 6)	/* TX FIFO Clear */
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/* I2C Configuration Register (OMAP_I2C_CON): */
#define OMAP_I2C_CON_EN		(1 << 15)	/* I2C module enable */
#define OMAP_I2C_CON_BE		(1 << 14)	/* Big endian mode */
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#define OMAP_I2C_CON_OPMODE_HS	(1 << 12)	/* High Speed support */
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#define OMAP_I2C_CON_STB	(1 << 11)	/* Start byte mode (master) */
#define OMAP_I2C_CON_MST	(1 << 10)	/* Master/slave mode */
#define OMAP_I2C_CON_TRX	(1 << 9)	/* TX/RX mode (master only) */
#define OMAP_I2C_CON_XA		(1 << 8)	/* Expand address */
#define OMAP_I2C_CON_RM		(1 << 2)	/* Repeat mode (master only) */
#define OMAP_I2C_CON_STP	(1 << 1)	/* Stop cond (master only) */
#define OMAP_I2C_CON_STT	(1 << 0)	/* Start condition (master) */

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/* I2C SCL time value when Master */
#define OMAP_I2C_SCLL_HSSCLL	8
#define OMAP_I2C_SCLH_HSSCLH	8

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/* I2C System Test Register (OMAP_I2C_SYSTEST): */
#ifdef DEBUG
#define OMAP_I2C_SYSTEST_ST_EN		(1 << 15)	/* System test enable */
#define OMAP_I2C_SYSTEST_FREE		(1 << 14)	/* Free running mode */
#define OMAP_I2C_SYSTEST_TMODE_MASK	(3 << 12)	/* Test mode select */
#define OMAP_I2C_SYSTEST_TMODE_SHIFT	(12)		/* Test mode select */
#define OMAP_I2C_SYSTEST_SCL_I		(1 << 3)	/* SCL line sense in */
#define OMAP_I2C_SYSTEST_SCL_O		(1 << 2)	/* SCL line drive out */
#define OMAP_I2C_SYSTEST_SDA_I		(1 << 1)	/* SDA line sense in */
#define OMAP_I2C_SYSTEST_SDA_O		(1 << 0)	/* SDA line drive out */
#endif

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/* OCP_SYSSTATUS bit definitions */
#define SYSS_RESETDONE_MASK		(1 << 0)

/* OCP_SYSCONFIG bit definitions */
#define SYSC_CLOCKACTIVITY_MASK		(0x3 << 8)
#define SYSC_SIDLEMODE_MASK		(0x3 << 3)
#define SYSC_ENAWAKEUP_MASK		(1 << 2)
#define SYSC_SOFTRESET_MASK		(1 << 1)
#define SYSC_AUTOIDLE_MASK		(1 << 0)

#define SYSC_IDLEMODE_SMART		0x2
#define SYSC_CLOCKACTIVITY_FCLK		0x2
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/* Errata definitions */
#define I2C_OMAP_ERRATA_I207		(1 << 0)
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#define I2C_OMAP_ERRATA_I462		(1 << 1)
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struct omap_i2c_dev {
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	spinlock_t		lock;		/* IRQ synchronization */
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	struct device		*dev;
	void __iomem		*base;		/* virtual */
	int			irq;
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	int			reg_shift;      /* bit shift for I2C register addresses */
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	struct completion	cmd_complete;
	struct resource		*ioarea;
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	u32			latency;	/* maximum mpu wkup latency */
	void			(*set_mpu_wkup_lat)(struct device *dev,
						    long latency);
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	u32			speed;		/* Speed of bus in kHz */
	u32			flags;
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	u16			cmd_err;
	u8			*buf;
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	u8			*regs;
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	size_t			buf_len;
	struct i2c_adapter	adapter;
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	u8			threshold;
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	u8			fifo_size;	/* use as flag and value
						 * fifo_size==0 implies no fifo
						 * if set, should be trsh+1
						 */
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	u32			rev;
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	unsigned		b_hw:1;		/* bad h/w fixes */
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	unsigned		receiver:1;	/* true when we're in receiver mode */
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	u16			iestate;	/* Saved interrupt register */
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	u16			pscstate;
	u16			scllstate;
	u16			sclhstate;
	u16			syscstate;
	u16			westate;
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	u16			errata;
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	struct pinctrl		*pins;
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};

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static const u8 reg_map_ip_v1[] = {
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	[OMAP_I2C_REV_REG] = 0x00,
	[OMAP_I2C_IE_REG] = 0x01,
	[OMAP_I2C_STAT_REG] = 0x02,
	[OMAP_I2C_IV_REG] = 0x03,
	[OMAP_I2C_WE_REG] = 0x03,
	[OMAP_I2C_SYSS_REG] = 0x04,
	[OMAP_I2C_BUF_REG] = 0x05,
	[OMAP_I2C_CNT_REG] = 0x06,
	[OMAP_I2C_DATA_REG] = 0x07,
	[OMAP_I2C_SYSC_REG] = 0x08,
	[OMAP_I2C_CON_REG] = 0x09,
	[OMAP_I2C_OA_REG] = 0x0a,
	[OMAP_I2C_SA_REG] = 0x0b,
	[OMAP_I2C_PSC_REG] = 0x0c,
	[OMAP_I2C_SCLL_REG] = 0x0d,
	[OMAP_I2C_SCLH_REG] = 0x0e,
	[OMAP_I2C_SYSTEST_REG] = 0x0f,
	[OMAP_I2C_BUFSTAT_REG] = 0x10,
};

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static const u8 reg_map_ip_v2[] = {
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	[OMAP_I2C_REV_REG] = 0x04,
	[OMAP_I2C_IE_REG] = 0x2c,
	[OMAP_I2C_STAT_REG] = 0x28,
	[OMAP_I2C_IV_REG] = 0x34,
	[OMAP_I2C_WE_REG] = 0x34,
	[OMAP_I2C_SYSS_REG] = 0x90,
	[OMAP_I2C_BUF_REG] = 0x94,
	[OMAP_I2C_CNT_REG] = 0x98,
	[OMAP_I2C_DATA_REG] = 0x9c,
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	[OMAP_I2C_SYSC_REG] = 0x10,
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	[OMAP_I2C_CON_REG] = 0xa4,
	[OMAP_I2C_OA_REG] = 0xa8,
	[OMAP_I2C_SA_REG] = 0xac,
	[OMAP_I2C_PSC_REG] = 0xb0,
	[OMAP_I2C_SCLL_REG] = 0xb4,
	[OMAP_I2C_SCLH_REG] = 0xb8,
	[OMAP_I2C_SYSTEST_REG] = 0xbC,
	[OMAP_I2C_BUFSTAT_REG] = 0xc0,
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	[OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
	[OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
	[OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
	[OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
	[OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
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};

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static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
				      int reg, u16 val)
{
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	__raw_writew(val, i2c_dev->base +
			(i2c_dev->regs[reg] << i2c_dev->reg_shift));
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}

static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
{
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	return __raw_readw(i2c_dev->base +
				(i2c_dev->regs[reg] << i2c_dev->reg_shift));
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}

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static void __omap_i2c_init(struct omap_i2c_dev *dev)
{

	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);

	/* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
	omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);

	/* SCL low and high time values */
	omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
	omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
	if (dev->rev >= OMAP_I2C_REV_ON_3430_3530)
		omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);

	/* Take the I2C module out of reset: */
	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);

	/*
	 * Don't write to this register if the IE state is 0 as it can
	 * cause deadlock.
	 */
	if (dev->iestate)
		omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
}

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static int omap_i2c_reset(struct omap_i2c_dev *dev)
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{
	unsigned long timeout;
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	u16 sysc;

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	if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
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		sysc = omap_i2c_read_reg(dev, OMAP_I2C_SYSC_REG);

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		/* Disable I2C controller before soft reset */
		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
			omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
				~(OMAP_I2C_CON_EN));

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		omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
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		/* For some reason we need to set the EN bit before the
		 * reset done bit gets set. */
		timeout = jiffies + OMAP_I2C_TIMEOUT;
		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
		while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
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			 SYSS_RESETDONE_MASK)) {
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			if (time_after(jiffies, timeout)) {
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				dev_warn(dev->dev, "timeout waiting "
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						"for controller reset\n");
				return -ETIMEDOUT;
			}
			msleep(1);
		}
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		/* SYSC register is cleared by the reset; rewrite it */
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		omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, sysc);
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	}
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	return 0;
}

static int omap_i2c_init(struct omap_i2c_dev *dev)
{
	u16 psc = 0, scll = 0, sclh = 0;
	u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
	unsigned long fclk_rate = 12000000;
	unsigned long internal_clk = 0;
	struct clk *fclk;

	if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) {
		/*
		 * Enabling all wakup sources to stop I2C freezing on
		 * WFI instruction.
		 * REVISIT: Some wkup sources might not be needed.
		 */
		dev->westate = OMAP_I2C_WE_ALL;
	}
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	if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
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		/*
		 * The I2C functional clock is the armxor_ck, so there's
		 * no need to get "armxor_ck" separately.  Now, if OMAP2420
		 * always returns 12MHz for the functional clock, we can
		 * do this bit unconditionally.
		 */
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		fclk = clk_get(dev->dev, "fck");
		fclk_rate = clk_get_rate(fclk);
		clk_put(fclk);
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		/* TRM for 5912 says the I2C clock must be prescaled to be
		 * between 7 - 12 MHz. The XOR input clock is typically
		 * 12, 13 or 19.2 MHz. So we should have code that produces:
		 *
		 * XOR MHz	Divider		Prescaler
		 * 12		1		0
		 * 13		2		1
		 * 19.2		2		1
		 */
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		if (fclk_rate > 12000000)
			psc = fclk_rate / 12000000;
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	}

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	if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
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		/*
		 * HSI2C controller internal clk rate should be 19.2 Mhz for
		 * HS and for all modes on 2430. On 34xx we can use lower rate
		 * to get longer filter period for better noise suppression.
		 * The filter is iclk (fclk for HS) period.
		 */
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		if (dev->speed > 400 ||
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			       dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
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			internal_clk = 19200;
		else if (dev->speed > 100)
			internal_clk = 9600;
		else
			internal_clk = 4000;
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		fclk = clk_get(dev->dev, "fck");
		fclk_rate = clk_get_rate(fclk) / 1000;
		clk_put(fclk);
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		/* Compute prescaler divisor */
		psc = fclk_rate / internal_clk;
		psc = psc - 1;

		/* If configured for High Speed */
		if (dev->speed > 400) {
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			unsigned long scl;

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			/* For first phase of HS mode */
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			scl = internal_clk / 400;
			fsscll = scl - (scl / 3) - 7;
			fssclh = (scl / 3) - 5;
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			/* For second phase of HS mode */
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			scl = fclk_rate / dev->speed;
			hsscll = scl - (scl / 3) - 7;
			hssclh = (scl / 3) - 5;
		} else if (dev->speed > 100) {
			unsigned long scl;

			/* Fast mode */
			scl = internal_clk / dev->speed;
			fsscll = scl - (scl / 3) - 7;
			fssclh = (scl / 3) - 5;
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		} else {
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			/* Standard mode */
			fsscll = internal_clk / (dev->speed * 2) - 7;
			fssclh = internal_clk / (dev->speed * 2) - 5;
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		}
		scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
		sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
	} else {
		/* Program desired operating rate */
		fclk_rate /= (psc + 1) * 1000;
		if (psc > 2)
			psc = 2;
		scll = fclk_rate / (dev->speed * 2) - 7 + psc;
		sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
	}

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	dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
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			OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
			OMAP_I2C_IE_AL)  | ((dev->fifo_size) ?
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				(OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
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	dev->pscstate = psc;
	dev->scllstate = scll;
	dev->sclhstate = sclh;

	__omap_i2c_init(dev);

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	return 0;
}

/*
 * Waiting on Bus Busy
 */
static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
{
	unsigned long timeout;

	timeout = jiffies + OMAP_I2C_TIMEOUT;
	while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
		if (time_after(jiffies, timeout)) {
			dev_warn(dev->dev, "timeout waiting for bus ready\n");
			return -ETIMEDOUT;
		}
		msleep(1);
	}

	return 0;
}

473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502
static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx)
{
	u16		buf;

	if (dev->flags & OMAP_I2C_FLAG_NO_FIFO)
		return;

	/*
	 * Set up notification threshold based on message size. We're doing
	 * this to try and avoid draining feature as much as possible. Whenever
	 * we have big messages to transfer (bigger than our total fifo size)
	 * then we might use draining feature to transfer the remaining bytes.
	 */

	dev->threshold = clamp(size, (u8) 1, dev->fifo_size);

	buf = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);

	if (is_rx) {
		/* Clear RX Threshold */
		buf &= ~(0x3f << 8);
		buf |= ((dev->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;
	} else {
		/* Clear TX Threshold */
		buf &= ~0x3f;
		buf |= (dev->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;
	}

	omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);

503
	if (dev->rev < OMAP_I2C_REV_ON_3630)
504 505 506
		dev->b_hw = 1; /* Enable hardware fixes */

	/* calculate wakeup latency constraint for MPU */
507 508 509
	if (dev->set_mpu_wkup_lat != NULL)
		dev->latency = (1000000 * dev->threshold) /
			(1000 * dev->speed / 8);
510 511
}

512 513 514 515 516 517 518
/*
 * Low level master read/write transaction.
 */
static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
			     struct i2c_msg *msg, int stop)
{
	struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
519
	unsigned long timeout;
520 521 522 523 524 525 526 527
	u16 w;

	dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
		msg->addr, msg->len, msg->flags, stop);

	if (msg->len == 0)
		return -EINVAL;

528 529 530
	dev->receiver = !!(msg->flags & I2C_M_RD);
	omap_i2c_resize_fifo(dev, msg->len, dev->receiver);

531 532 533 534 535 536
	omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);

	/* REVISIT: Could the STB bit of I2C_CON be used with probing? */
	dev->buf = msg->buf;
	dev->buf_len = msg->len;

537 538 539
	/* make sure writes to dev->buf_len are ordered */
	barrier();

540 541
	omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);

542 543 544 545 546
	/* Clear the FIFO Buffers */
	w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
	w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
	omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);

547
	INIT_COMPLETION(dev->cmd_complete);
548 549 550
	dev->cmd_err = 0;

	w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
551 552 553

	/* High speed configuration */
	if (dev->speed > 400)
554
		w |= OMAP_I2C_CON_OPMODE_HS;
555

556 557
	if (msg->flags & I2C_M_STOP)
		stop = 1;
558 559 560 561
	if (msg->flags & I2C_M_TEN)
		w |= OMAP_I2C_CON_XA;
	if (!(msg->flags & I2C_M_RD))
		w |= OMAP_I2C_CON_TRX;
T
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562

563
	if (!dev->b_hw && stop)
564
		w |= OMAP_I2C_CON_STP;
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565

566 567
	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);

568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590
	/*
	 * Don't write stt and stp together on some hardware.
	 */
	if (dev->b_hw && stop) {
		unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
		u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
		while (con & OMAP_I2C_CON_STT) {
			con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);

			/* Let the user know if i2c is in a bad state */
			if (time_after(jiffies, delay)) {
				dev_err(dev->dev, "controller timed out "
				"waiting for start condition to finish\n");
				return -ETIMEDOUT;
			}
			cpu_relax();
		}

		w |= OMAP_I2C_CON_STP;
		w &= ~OMAP_I2C_CON_STT;
		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
	}

591 592 593 594
	/*
	 * REVISIT: We should abort the transfer on signals, but the bus goes
	 * into arbitration and we're currently unable to recover from it.
	 */
595 596 597
	timeout = wait_for_completion_timeout(&dev->cmd_complete,
						OMAP_I2C_TIMEOUT);
	if (timeout == 0) {
598
		dev_err(dev->dev, "controller timed out\n");
599 600
		omap_i2c_reset(dev);
		__omap_i2c_init(dev);
601 602 603 604 605 606 607 608 609
		return -ETIMEDOUT;
	}

	if (likely(!dev->cmd_err))
		return 0;

	/* We have an error */
	if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
			    OMAP_I2C_STAT_XUDF)) {
610 611
		omap_i2c_reset(dev);
		__omap_i2c_init(dev);
612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639
		return -EIO;
	}

	if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
		if (msg->flags & I2C_M_IGNORE_NAK)
			return 0;
		if (stop) {
			w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
			w |= OMAP_I2C_CON_STP;
			omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
		}
		return -EREMOTEIO;
	}
	return -EIO;
}


/*
 * Prepare controller for a transaction and call omap_i2c_xfer_msg
 * to do the work during IRQ processing.
 */
static int
omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
{
	struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
	int i;
	int r;

640 641
	r = pm_runtime_get_sync(dev->dev);
	if (IS_ERR_VALUE(r))
642
		goto out;
643

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Tony Lindgren 已提交
644 645
	r = omap_i2c_wait_for_bb(dev);
	if (r < 0)
646 647
		goto out;

648 649
	if (dev->set_mpu_wkup_lat != NULL)
		dev->set_mpu_wkup_lat(dev->dev, dev->latency);
650

651 652 653 654 655 656 657 658
	for (i = 0; i < num; i++) {
		r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
		if (r != 0)
			break;
	}

	if (r == 0)
		r = num;
659 660

	omap_i2c_wait_for_bb(dev);
661 662 663 664

	if (dev->set_mpu_wkup_lat != NULL)
		dev->set_mpu_wkup_lat(dev->dev, -1);

665
out:
666 667
	pm_runtime_mark_last_busy(dev->dev);
	pm_runtime_put_autosuspend(dev->dev);
668 669 670 671 672 673
	return r;
}

static u32
omap_i2c_func(struct i2c_adapter *adap)
{
674 675
	return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
	       I2C_FUNC_PROTOCOL_MANGLING;
676 677 678 679 680 681 682 683 684 685 686 687 688 689 690
}

static inline void
omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
{
	dev->cmd_err |= err;
	complete(&dev->cmd_complete);
}

static inline void
omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
{
	omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
}

691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718
static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
{
	/*
	 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
	 * Not applicable for OMAP4.
	 * Under certain rare conditions, RDR could be set again
	 * when the bus is busy, then ignore the interrupt and
	 * clear the interrupt.
	 */
	if (stat & OMAP_I2C_STAT_RDR) {
		/* Step 1: If RDR is set, clear it */
		omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);

		/* Step 2: */
		if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
						& OMAP_I2C_STAT_BB)) {

			/* Step 3: */
			if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
						& OMAP_I2C_STAT_RDR) {
				omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
				dev_dbg(dev->dev, "RDR when bus is busy.\n");
			}

		}
	}
}

719 720 721
/* rev1 devices are apparently only on some 15xx */
#ifdef CONFIG_ARCH_OMAP15XX

722
static irqreturn_t
723
omap_i2c_omap1_isr(int this_irq, void *dev_id)
724 725 726 727
{
	struct omap_i2c_dev *dev = dev_id;
	u16 iv, w;

728
	if (pm_runtime_suspended(dev->dev))
T
Tony Lindgren 已提交
729 730
		return IRQ_NONE;

731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775
	iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
	switch (iv) {
	case 0x00:	/* None */
		break;
	case 0x01:	/* Arbitration lost */
		dev_err(dev->dev, "Arbitration lost\n");
		omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
		break;
	case 0x02:	/* No acknowledgement */
		omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
		break;
	case 0x03:	/* Register access ready */
		omap_i2c_complete_cmd(dev, 0);
		break;
	case 0x04:	/* Receive data ready */
		if (dev->buf_len) {
			w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
			*dev->buf++ = w;
			dev->buf_len--;
			if (dev->buf_len) {
				*dev->buf++ = w >> 8;
				dev->buf_len--;
			}
		} else
			dev_err(dev->dev, "RRDY IRQ while no data requested\n");
		break;
	case 0x05:	/* Transmit data ready */
		if (dev->buf_len) {
			w = *dev->buf++;
			dev->buf_len--;
			if (dev->buf_len) {
				w |= *dev->buf++ << 8;
				dev->buf_len--;
			}
			omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
		} else
			dev_err(dev->dev, "XRDY IRQ while no data to send\n");
		break;
	default:
		return IRQ_NONE;
	}

	return IRQ_HANDLED;
}
776
#else
777
#define omap_i2c_omap1_isr		NULL
778
#endif
779

780
/*
781
 * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing
782 783 784
 * data to DATA_REG. Otherwise some data bytes can be lost while transferring
 * them from the memory to the I2C interface.
 */
785
static int errata_omap3_i462(struct omap_i2c_dev *dev)
786
{
787
	unsigned long timeout = 10000;
788
	u16 stat;
789

790 791 792 793 794 795
	do {
		stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
		if (stat & OMAP_I2C_STAT_XUDF)
			break;

		if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
796
			omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY |
797
							OMAP_I2C_STAT_XDR));
798 799 800 801 802 803 804 805 806 807 808
			if (stat & OMAP_I2C_STAT_NACK) {
				dev->cmd_err |= OMAP_I2C_STAT_NACK;
				omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
			}

			if (stat & OMAP_I2C_STAT_AL) {
				dev_err(dev->dev, "Arbitration lost\n");
				dev->cmd_err |= OMAP_I2C_STAT_AL;
				omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
			}

809
			return -EIO;
810
		}
811

812
		cpu_relax();
813
	} while (--timeout);
814

815 816 817 818 819
	if (!timeout) {
		dev_err(dev->dev, "timeout waiting on XUDF bit\n");
		return 0;
	}

820 821 822
	return 0;
}

823 824 825 826 827 828 829 830 831 832 833 834 835 836 837
static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes,
		bool is_rdr)
{
	u16		w;

	while (num_bytes--) {
		w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
		*dev->buf++ = w;
		dev->buf_len--;

		/*
		 * Data reg in 2430, omap3 and
		 * omap4 is 8 bit wide
		 */
		if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
838 839
			*dev->buf++ = w >> 8;
			dev->buf_len--;
840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857
		}
	}
}

static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes,
		bool is_xdr)
{
	u16		w;

	while (num_bytes--) {
		w = *dev->buf++;
		dev->buf_len--;

		/*
		 * Data reg in 2430, omap3 and
		 * omap4 is 8 bit wide
		 */
		if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
858 859
			w |= *dev->buf++ << 8;
			dev->buf_len--;
860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875
		}

		if (dev->errata & I2C_OMAP_ERRATA_I462) {
			int ret;

			ret = errata_omap3_i462(dev);
			if (ret < 0)
				return ret;
		}

		omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
	}

	return 0;
}

876
static irqreturn_t
877
omap_i2c_isr(int irq, void *dev_id)
878 879
{
	struct omap_i2c_dev *dev = dev_id;
880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895
	irqreturn_t ret = IRQ_HANDLED;
	u16 mask;
	u16 stat;

	spin_lock(&dev->lock);
	mask = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
	stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);

	if (stat & mask)
		ret = IRQ_WAKE_THREAD;

	spin_unlock(&dev->lock);

	return ret;
}

896
static irqreturn_t
897
omap_i2c_isr_thread(int this_irq, void *dev_id)
898 899
{
	struct omap_i2c_dev *dev = dev_id;
900
	unsigned long flags;
901
	u16 bits;
902
	u16 stat;
903
	int err = 0, count = 0;
904

905
	spin_lock_irqsave(&dev->lock, flags);
906 907 908 909 910
	do {
		bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
		stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
		stat &= bits;

911 912 913 914 915
		/* If we're in receiver mode, ignore XDR/XRDY */
		if (dev->receiver)
			stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY);
		else
			stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY);
916

917 918
		if (!stat) {
			/* my work here is done */
F
Felipe Balbi 已提交
919
			goto out;
920
		}
T
Tony Lindgren 已提交
921

922 923 924 925 926 927
		dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
		if (count++ == 100) {
			dev_warn(dev->dev, "Too much work in one IRQ\n");
			break;
		}

F
Felipe Balbi 已提交
928
		if (stat & OMAP_I2C_STAT_NACK) {
929
			err |= OMAP_I2C_STAT_NACK;
F
Felipe Balbi 已提交
930
			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
F
Felipe Balbi 已提交
931
			break;
F
Felipe Balbi 已提交
932
		}
J
Jan Weitzel 已提交
933

934 935 936
		if (stat & OMAP_I2C_STAT_AL) {
			dev_err(dev->dev, "Arbitration lost\n");
			err |= OMAP_I2C_STAT_AL;
F
Felipe Balbi 已提交
937
			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
F
Felipe Balbi 已提交
938
			break;
939
		}
F
Felipe Balbi 已提交
940

941
		/*
942
		 * ProDB0017052: Clear ARDY bit twice
943
		 */
944
		if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
945
					OMAP_I2C_STAT_AL)) {
946 947 948 949 950
			omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY |
						OMAP_I2C_STAT_RDR |
						OMAP_I2C_STAT_XRDY |
						OMAP_I2C_STAT_XDR |
						OMAP_I2C_STAT_ARDY));
F
Felipe Balbi 已提交
951
			break;
952
		}
F
Felipe Balbi 已提交
953

954
		if (stat & OMAP_I2C_STAT_RDR) {
955
			u8 num_bytes = 1;
956

957 958 959
			if (dev->fifo_size)
				num_bytes = dev->buf_len;

960
			omap_i2c_receive_data(dev, num_bytes, true);
961

962 963 964
			if (dev->errata & I2C_OMAP_ERRATA_I207)
				i2c_omap_errata_i207(dev, stat);

965
			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
F
Felipe Balbi 已提交
966
			break;
967 968 969 970 971
		}

		if (stat & OMAP_I2C_STAT_RRDY) {
			u8 num_bytes = 1;

972 973
			if (dev->threshold)
				num_bytes = dev->threshold;
974

975
			omap_i2c_receive_data(dev, num_bytes, false);
976
			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
977 978
			continue;
		}
F
Felipe Balbi 已提交
979

980
		if (stat & OMAP_I2C_STAT_XDR) {
981
			u8 num_bytes = 1;
982
			int ret;
983 984 985 986

			if (dev->fifo_size)
				num_bytes = dev->buf_len;

987 988
			ret = omap_i2c_transmit_data(dev, num_bytes, true);
			if (ret < 0)
F
Felipe Balbi 已提交
989
				break;
990 991

			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR);
F
Felipe Balbi 已提交
992
			break;
993 994 995 996
		}

		if (stat & OMAP_I2C_STAT_XRDY) {
			u8 num_bytes = 1;
997
			int ret;
998

999 1000
			if (dev->threshold)
				num_bytes = dev->threshold;
1001

1002 1003
			ret = omap_i2c_transmit_data(dev, num_bytes, false);
			if (ret < 0)
F
Felipe Balbi 已提交
1004
				break;
1005 1006

			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
1007 1008
			continue;
		}
F
Felipe Balbi 已提交
1009

1010 1011
		if (stat & OMAP_I2C_STAT_ROVR) {
			dev_err(dev->dev, "Receive overrun\n");
F
Felipe Balbi 已提交
1012 1013
			err |= OMAP_I2C_STAT_ROVR;
			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR);
F
Felipe Balbi 已提交
1014
			break;
1015
		}
F
Felipe Balbi 已提交
1016

1017
		if (stat & OMAP_I2C_STAT_XUDF) {
1018
			dev_err(dev->dev, "Transmit underflow\n");
F
Felipe Balbi 已提交
1019 1020
			err |= OMAP_I2C_STAT_XUDF;
			omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF);
F
Felipe Balbi 已提交
1021
			break;
1022
		}
1023
	} while (stat);
1024

F
Felipe Balbi 已提交
1025
	omap_i2c_complete_cmd(dev, err);
F
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1026 1027

out:
1028
	spin_unlock_irqrestore(&dev->lock, flags);
1029

1030
	return IRQ_HANDLED;
1031 1032
}

1033
static const struct i2c_algorithm omap_i2c_algo = {
1034 1035 1036 1037
	.master_xfer	= omap_i2c_xfer,
	.functionality	= omap_i2c_func,
};

1038 1039 1040
#ifdef CONFIG_OF
static struct omap_i2c_bus_platform_data omap3_pdata = {
	.rev = OMAP_I2C_IP_VERSION_1,
1041
	.flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061
};

static struct omap_i2c_bus_platform_data omap4_pdata = {
	.rev = OMAP_I2C_IP_VERSION_2,
};

static const struct of_device_id omap_i2c_of_match[] = {
	{
		.compatible = "ti,omap4-i2c",
		.data = &omap4_pdata,
	},
	{
		.compatible = "ti,omap3-i2c",
		.data = &omap3_pdata,
	},
	{ },
};
MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
#endif

1062 1063 1064 1065 1066 1067 1068 1069 1070 1071
#define OMAP_I2C_SCHEME(rev)		((rev & 0xc000) >> 14)

#define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4)
#define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf)

#define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7)
#define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f)
#define OMAP_I2C_SCHEME_0		0
#define OMAP_I2C_SCHEME_1		1

1072
static int
1073 1074 1075 1076
omap_i2c_probe(struct platform_device *pdev)
{
	struct omap_i2c_dev	*dev;
	struct i2c_adapter	*adap;
1077
	struct resource		*mem;
1078 1079
	const struct omap_i2c_bus_platform_data *pdata =
		pdev->dev.platform_data;
1080 1081
	struct device_node	*node = pdev->dev.of_node;
	const struct of_device_id *match;
1082
	int irq;
1083
	int r;
1084
	u32 rev;
S
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1085
	u16 minor, major, scheme;
1086 1087 1088 1089 1090 1091 1092

	/* NOTE: driver uses the static register mapping */
	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem) {
		dev_err(&pdev->dev, "no mem resource?\n");
		return -ENODEV;
	}
1093 1094 1095

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
1096
		dev_err(&pdev->dev, "no irq resource?\n");
1097
		return irq;
1098 1099
	}

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1100 1101 1102 1103
	dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
	if (!dev) {
		dev_err(&pdev->dev, "Menory allocation failed\n");
		return -ENOMEM;
1104 1105
	}

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1106 1107 1108 1109
	dev->base = devm_request_and_ioremap(&pdev->dev, mem);
	if (!dev->base) {
		dev_err(&pdev->dev, "I2C region already claimed\n");
		return -ENOMEM;
1110 1111
	}

1112
	match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124
	if (match) {
		u32 freq = 100000; /* default to 100000 Hz */

		pdata = match->data;
		dev->flags = pdata->flags;

		of_property_read_u32(node, "clock-frequency", &freq);
		/* convert DT freq value in Hz into kHz for speed */
		dev->speed = freq / 1000;
	} else if (pdata != NULL) {
		dev->speed = pdata->clkrate;
		dev->flags = pdata->flags;
1125
		dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
1126
	}
1127

1128 1129 1130 1131 1132 1133 1134 1135 1136 1137
	dev->pins = devm_pinctrl_get_select_default(&pdev->dev);
	if (IS_ERR(dev->pins)) {
		if (PTR_ERR(dev->pins) == -EPROBE_DEFER)
			return -EPROBE_DEFER;

		dev_warn(&pdev->dev, "did not get pins for i2c error: %li\n",
			 PTR_ERR(dev->pins));
		dev->pins = NULL;
	}

1138
	dev->dev = &pdev->dev;
1139
	dev->irq = irq;
1140

1141
	spin_lock_init(&dev->lock);
1142

1143
	platform_set_drvdata(pdev, dev);
1144
	init_completion(&dev->cmd_complete);
1145

1146
	dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
1147

1148
	pm_runtime_enable(dev->dev);
1149 1150 1151
	pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT);
	pm_runtime_use_autosuspend(dev->dev);

1152 1153 1154
	r = pm_runtime_get_sync(dev->dev);
	if (IS_ERR_VALUE(r))
		goto err_free_mem;
1155

1156 1157 1158 1159 1160 1161 1162 1163
	/*
	 * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2.
	 * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset.
	 * Also since the omap_i2c_read_reg uses reg_map_ip_* a
	 * raw_readw is done.
	 */
	rev = __raw_readw(dev->base + 0x04);

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1164 1165
	scheme = OMAP_I2C_SCHEME(rev);
	switch (scheme) {
1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181
	case OMAP_I2C_SCHEME_0:
		dev->regs = (u8 *)reg_map_ip_v1;
		dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG);
		minor = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
		major = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
		break;
	case OMAP_I2C_SCHEME_1:
		/* FALLTHROUGH */
	default:
		dev->regs = (u8 *)reg_map_ip_v2;
		rev = (rev << 16) |
			omap_i2c_read_reg(dev, OMAP_I2C_IP_V2_REVNB_LO);
		minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev);
		major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev);
		dev->rev = rev;
	}
1182

1183 1184
	dev->errata = 0;

1185 1186
	if (dev->rev >= OMAP_I2C_REV_ON_2430 &&
			dev->rev < OMAP_I2C_REV_ON_4430_PLUS)
1187 1188
		dev->errata |= I2C_OMAP_ERRATA_I207;

1189
	if (dev->rev <= OMAP_I2C_REV_ON_3430_3530)
1190
		dev->errata |= I2C_OMAP_ERRATA_I462;
1191

1192
	if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) {
1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203
		u16 s;

		/* Set up the fifo size - Get total size */
		s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
		dev->fifo_size = 0x8 << s;

		/*
		 * Set up notification threshold as half the total available
		 * size. This is to ensure that we can handle the status on int
		 * call back latencies.
		 */
1204 1205 1206

		dev->fifo_size = (dev->fifo_size / 2);

1207
		if (dev->rev < OMAP_I2C_REV_ON_3630)
1208
			dev->b_hw = 1; /* Enable hardware fixes */
1209

1210
		/* calculate wakeup latency constraint for MPU */
1211 1212 1213
		if (dev->set_mpu_wkup_lat != NULL)
			dev->latency = (1000000 * dev->fifo_size) /
				       (1000 * dev->speed / 8);
1214 1215
	}

1216 1217 1218
	/* reset ASAP, clearing any IRQs */
	omap_i2c_init(dev);

1219 1220 1221 1222 1223 1224 1225 1226
	if (dev->rev < OMAP_I2C_OMAP1_REV_2)
		r = devm_request_irq(&pdev->dev, dev->irq, omap_i2c_omap1_isr,
				IRQF_NO_SUSPEND, pdev->name, dev);
	else
		r = devm_request_threaded_irq(&pdev->dev, dev->irq,
				omap_i2c_isr, omap_i2c_isr_thread,
				IRQF_NO_SUSPEND | IRQF_ONESHOT,
				pdev->name, dev);
1227 1228 1229 1230 1231

	if (r) {
		dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
		goto err_unuse_clocks;
	}
1232

1233 1234 1235 1236
	adap = &dev->adapter;
	i2c_set_adapdata(adap, dev);
	adap->owner = THIS_MODULE;
	adap->class = I2C_CLASS_HWMON;
1237
	strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
1238 1239
	adap->algo = &omap_i2c_algo;
	adap->dev.parent = &pdev->dev;
1240
	adap->dev.of_node = pdev->dev.of_node;
1241 1242

	/* i2c device drivers may be active on return from add_adapter() */
1243 1244
	adap->nr = pdev->id;
	r = i2c_add_numbered_adapter(adap);
1245 1246
	if (r) {
		dev_err(dev->dev, "failure adding adapter\n");
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1247
		goto err_unuse_clocks;
1248 1249
	}

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1250 1251
	dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr,
		 major, minor, dev->speed);
1252

1253 1254
	of_i2c_register_devices(adap);

1255 1256
	pm_runtime_mark_last_busy(dev->dev);
	pm_runtime_put_autosuspend(dev->dev);
1257

1258 1259 1260
	return 0;

err_unuse_clocks:
1261
	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1262
	pm_runtime_put(dev->dev);
1263
	pm_runtime_disable(&pdev->dev);
1264 1265 1266 1267 1268 1269
err_free_mem:
	platform_set_drvdata(pdev, NULL);

	return r;
}

1270
static int omap_i2c_remove(struct platform_device *pdev)
1271 1272
{
	struct omap_i2c_dev	*dev = platform_get_drvdata(pdev);
1273
	int ret;
1274 1275 1276 1277

	platform_set_drvdata(pdev, NULL);

	i2c_del_adapter(&dev->adapter);
1278 1279 1280 1281
	ret = pm_runtime_get_sync(&pdev->dev);
	if (IS_ERR_VALUE(ret))
		return ret;

1282
	omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1283
	pm_runtime_put(&pdev->dev);
1284
	pm_runtime_disable(&pdev->dev);
1285 1286 1287
	return 0;
}

1288
#ifdef CONFIG_PM
1289 1290 1291 1292 1293
#ifdef CONFIG_PM_RUNTIME
static int omap_i2c_runtime_suspend(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
1294 1295

	_dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG);
1296 1297

	omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);
1298

1299
	if (_dev->rev < OMAP_I2C_OMAP1_REV_2) {
1300
		omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */
1301 1302
	} else {
		omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate);
1303

1304 1305 1306
		/* Flush posted write */
		omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG);
	}
1307 1308 1309 1310 1311 1312 1313 1314 1315

	return 0;
}

static int omap_i2c_runtime_resume(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);

1316 1317 1318
	if (!_dev->regs)
		return 0;

1319
	__omap_i2c_init(_dev);
1320 1321 1322

	return 0;
}
1323
#endif /* CONFIG_PM_RUNTIME */
1324 1325

static struct dev_pm_ops omap_i2c_pm_ops = {
1326 1327
	SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend,
			   omap_i2c_runtime_resume, NULL)
1328 1329 1330 1331
};
#define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops)
#else
#define OMAP_I2C_PM_OPS NULL
1332
#endif /* CONFIG_PM */
1333

1334 1335
static struct platform_driver omap_i2c_driver = {
	.probe		= omap_i2c_probe,
1336
	.remove		= omap_i2c_remove,
1337
	.driver		= {
1338
		.name	= "omap_i2c",
1339
		.owner	= THIS_MODULE,
1340
		.pm	= OMAP_I2C_PM_OPS,
1341
		.of_match_table = of_match_ptr(omap_i2c_of_match),
1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361
	},
};

/* I2C may be needed to bring up other drivers */
static int __init
omap_i2c_init_driver(void)
{
	return platform_driver_register(&omap_i2c_driver);
}
subsys_initcall(omap_i2c_init_driver);

static void __exit omap_i2c_exit_driver(void)
{
	platform_driver_unregister(&omap_i2c_driver);
}
module_exit(omap_i2c_exit_driver);

MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
MODULE_LICENSE("GPL");
1362
MODULE_ALIAS("platform:omap_i2c");