dsi.c 122.8 KB
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/*
 * linux/drivers/video/omap2/dss/dsi.c
 *
 * Copyright (C) 2009 Nokia Corporation
 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#define DSS_SUBSYS_NAME "DSI"

#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/mutex.h>
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#include <linux/module.h>
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#include <linux/semaphore.h>
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#include <linux/seq_file.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/wait.h>
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#include <linux/workqueue.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/debugfs.h>
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#include <linux/pm_runtime.h>
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#include <video/omapdss.h>
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#include <video/mipi_display.h>
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#include <plat/clock.h>

#include "dss.h"
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#include "dss_features.h"
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/*#define VERBOSE_IRQ*/
#define DSI_CATCH_MISSING_TE

struct dsi_reg { u16 idx; };

#define DSI_REG(idx)		((const struct dsi_reg) { idx })

#define DSI_SZ_REGS		SZ_1K
/* DSI Protocol Engine */

#define DSI_REVISION			DSI_REG(0x0000)
#define DSI_SYSCONFIG			DSI_REG(0x0010)
#define DSI_SYSSTATUS			DSI_REG(0x0014)
#define DSI_IRQSTATUS			DSI_REG(0x0018)
#define DSI_IRQENABLE			DSI_REG(0x001C)
#define DSI_CTRL			DSI_REG(0x0040)
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#define DSI_GNQ				DSI_REG(0x0044)
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#define DSI_COMPLEXIO_CFG1		DSI_REG(0x0048)
#define DSI_COMPLEXIO_IRQ_STATUS	DSI_REG(0x004C)
#define DSI_COMPLEXIO_IRQ_ENABLE	DSI_REG(0x0050)
#define DSI_CLK_CTRL			DSI_REG(0x0054)
#define DSI_TIMING1			DSI_REG(0x0058)
#define DSI_TIMING2			DSI_REG(0x005C)
#define DSI_VM_TIMING1			DSI_REG(0x0060)
#define DSI_VM_TIMING2			DSI_REG(0x0064)
#define DSI_VM_TIMING3			DSI_REG(0x0068)
#define DSI_CLK_TIMING			DSI_REG(0x006C)
#define DSI_TX_FIFO_VC_SIZE		DSI_REG(0x0070)
#define DSI_RX_FIFO_VC_SIZE		DSI_REG(0x0074)
#define DSI_COMPLEXIO_CFG2		DSI_REG(0x0078)
#define DSI_RX_FIFO_VC_FULLNESS		DSI_REG(0x007C)
#define DSI_VM_TIMING4			DSI_REG(0x0080)
#define DSI_TX_FIFO_VC_EMPTINESS	DSI_REG(0x0084)
#define DSI_VM_TIMING5			DSI_REG(0x0088)
#define DSI_VM_TIMING6			DSI_REG(0x008C)
#define DSI_VM_TIMING7			DSI_REG(0x0090)
#define DSI_STOPCLK_TIMING		DSI_REG(0x0094)
#define DSI_VC_CTRL(n)			DSI_REG(0x0100 + (n * 0x20))
#define DSI_VC_TE(n)			DSI_REG(0x0104 + (n * 0x20))
#define DSI_VC_LONG_PACKET_HEADER(n)	DSI_REG(0x0108 + (n * 0x20))
#define DSI_VC_LONG_PACKET_PAYLOAD(n)	DSI_REG(0x010C + (n * 0x20))
#define DSI_VC_SHORT_PACKET_HEADER(n)	DSI_REG(0x0110 + (n * 0x20))
#define DSI_VC_IRQSTATUS(n)		DSI_REG(0x0118 + (n * 0x20))
#define DSI_VC_IRQENABLE(n)		DSI_REG(0x011C + (n * 0x20))

/* DSIPHY_SCP */

#define DSI_DSIPHY_CFG0			DSI_REG(0x200 + 0x0000)
#define DSI_DSIPHY_CFG1			DSI_REG(0x200 + 0x0004)
#define DSI_DSIPHY_CFG2			DSI_REG(0x200 + 0x0008)
#define DSI_DSIPHY_CFG5			DSI_REG(0x200 + 0x0014)
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#define DSI_DSIPHY_CFG10		DSI_REG(0x200 + 0x0028)
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/* DSI_PLL_CTRL_SCP */

#define DSI_PLL_CONTROL			DSI_REG(0x300 + 0x0000)
#define DSI_PLL_STATUS			DSI_REG(0x300 + 0x0004)
#define DSI_PLL_GO			DSI_REG(0x300 + 0x0008)
#define DSI_PLL_CONFIGURATION1		DSI_REG(0x300 + 0x000C)
#define DSI_PLL_CONFIGURATION2		DSI_REG(0x300 + 0x0010)

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#define REG_GET(dsidev, idx, start, end) \
	FLD_GET(dsi_read_reg(dsidev, idx), start, end)
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#define REG_FLD_MOD(dsidev, idx, val, start, end) \
	dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
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/* Global interrupts */
#define DSI_IRQ_VC0		(1 << 0)
#define DSI_IRQ_VC1		(1 << 1)
#define DSI_IRQ_VC2		(1 << 2)
#define DSI_IRQ_VC3		(1 << 3)
#define DSI_IRQ_WAKEUP		(1 << 4)
#define DSI_IRQ_RESYNC		(1 << 5)
#define DSI_IRQ_PLL_LOCK	(1 << 7)
#define DSI_IRQ_PLL_UNLOCK	(1 << 8)
#define DSI_IRQ_PLL_RECALL	(1 << 9)
#define DSI_IRQ_COMPLEXIO_ERR	(1 << 10)
#define DSI_IRQ_HS_TX_TIMEOUT	(1 << 14)
#define DSI_IRQ_LP_RX_TIMEOUT	(1 << 15)
#define DSI_IRQ_TE_TRIGGER	(1 << 16)
#define DSI_IRQ_ACK_TRIGGER	(1 << 17)
#define DSI_IRQ_SYNC_LOST	(1 << 18)
#define DSI_IRQ_LDO_POWER_GOOD	(1 << 19)
#define DSI_IRQ_TA_TIMEOUT	(1 << 20)
#define DSI_IRQ_ERROR_MASK \
	(DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
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	DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST)
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#define DSI_IRQ_CHANNEL_MASK	0xf

/* Virtual channel interrupts */
#define DSI_VC_IRQ_CS		(1 << 0)
#define DSI_VC_IRQ_ECC_CORR	(1 << 1)
#define DSI_VC_IRQ_PACKET_SENT	(1 << 2)
#define DSI_VC_IRQ_FIFO_TX_OVF	(1 << 3)
#define DSI_VC_IRQ_FIFO_RX_OVF	(1 << 4)
#define DSI_VC_IRQ_BTA		(1 << 5)
#define DSI_VC_IRQ_ECC_NO_CORR	(1 << 6)
#define DSI_VC_IRQ_FIFO_TX_UDF	(1 << 7)
#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
#define DSI_VC_IRQ_ERROR_MASK \
	(DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
	DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
	DSI_VC_IRQ_FIFO_TX_UDF)

/* ComplexIO interrupts */
#define DSI_CIO_IRQ_ERRSYNCESC1		(1 << 0)
#define DSI_CIO_IRQ_ERRSYNCESC2		(1 << 1)
#define DSI_CIO_IRQ_ERRSYNCESC3		(1 << 2)
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#define DSI_CIO_IRQ_ERRSYNCESC4		(1 << 3)
#define DSI_CIO_IRQ_ERRSYNCESC5		(1 << 4)
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#define DSI_CIO_IRQ_ERRESC1		(1 << 5)
#define DSI_CIO_IRQ_ERRESC2		(1 << 6)
#define DSI_CIO_IRQ_ERRESC3		(1 << 7)
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#define DSI_CIO_IRQ_ERRESC4		(1 << 8)
#define DSI_CIO_IRQ_ERRESC5		(1 << 9)
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#define DSI_CIO_IRQ_ERRCONTROL1		(1 << 10)
#define DSI_CIO_IRQ_ERRCONTROL2		(1 << 11)
#define DSI_CIO_IRQ_ERRCONTROL3		(1 << 12)
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#define DSI_CIO_IRQ_ERRCONTROL4		(1 << 13)
#define DSI_CIO_IRQ_ERRCONTROL5		(1 << 14)
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#define DSI_CIO_IRQ_STATEULPS1		(1 << 15)
#define DSI_CIO_IRQ_STATEULPS2		(1 << 16)
#define DSI_CIO_IRQ_STATEULPS3		(1 << 17)
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#define DSI_CIO_IRQ_STATEULPS4		(1 << 18)
#define DSI_CIO_IRQ_STATEULPS5		(1 << 19)
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#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1	(1 << 20)
#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1	(1 << 21)
#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2	(1 << 22)
#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2	(1 << 23)
#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3	(1 << 24)
#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3	(1 << 25)
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#define DSI_CIO_IRQ_ERRCONTENTIONLP0_4	(1 << 26)
#define DSI_CIO_IRQ_ERRCONTENTIONLP1_4	(1 << 27)
#define DSI_CIO_IRQ_ERRCONTENTIONLP0_5	(1 << 28)
#define DSI_CIO_IRQ_ERRCONTENTIONLP1_5	(1 << 29)
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#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0	(1 << 30)
#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1	(1 << 31)
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#define DSI_CIO_IRQ_ERROR_MASK \
	(DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
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	 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
	 DSI_CIO_IRQ_ERRSYNCESC5 | \
	 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
	 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
	 DSI_CIO_IRQ_ERRESC5 | \
	 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
	 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
	 DSI_CIO_IRQ_ERRCONTROL5 | \
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	 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
	 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
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	 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
	 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
	 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
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typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);

#define DSI_MAX_NR_ISRS                2
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#define DSI_MAX_NR_LANES	5

enum dsi_lane_function {
	DSI_LANE_UNUSED	= 0,
	DSI_LANE_CLK,
	DSI_LANE_DATA1,
	DSI_LANE_DATA2,
	DSI_LANE_DATA3,
	DSI_LANE_DATA4,
};

struct dsi_lane_config {
	enum dsi_lane_function function;
	u8 polarity;
};
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struct dsi_isr_data {
	omap_dsi_isr_t	isr;
	void		*arg;
	u32		mask;
};

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enum fifo_size {
	DSI_FIFO_SIZE_0		= 0,
	DSI_FIFO_SIZE_32	= 1,
	DSI_FIFO_SIZE_64	= 2,
	DSI_FIFO_SIZE_96	= 3,
	DSI_FIFO_SIZE_128	= 4,
};

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enum dsi_vc_source {
	DSI_VC_SOURCE_L4 = 0,
	DSI_VC_SOURCE_VP,
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};

struct dsi_update_region {
	u16 x, y, w, h;
	struct omap_dss_device *device;
};

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struct dsi_irq_stats {
	unsigned long last_reset;
	unsigned irq_count;
	unsigned dsi_irqs[32];
	unsigned vc_irqs[4][32];
	unsigned cio_irqs[32];
};

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struct dsi_isr_tables {
	struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
	struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
	struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
};

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struct dsi_data {
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	struct platform_device *pdev;
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	void __iomem	*base;
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	int irq;
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	struct clk *dss_clk;
	struct clk *sys_clk;

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	int (*enable_pads)(int dsi_id, unsigned lane_mask);
	void (*disable_pads)(int dsi_id, unsigned lane_mask);
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	struct dsi_clock_info current_cinfo;

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	bool vdds_dsi_enabled;
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	struct regulator *vdds_dsi_reg;

	struct {
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		enum dsi_vc_source source;
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		struct omap_dss_device *dssdev;
		enum fifo_size fifo_size;
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		int vc_id;
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	} vc[4];

	struct mutex lock;
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	struct semaphore bus_lock;
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	unsigned pll_locked;

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	spinlock_t irq_lock;
	struct dsi_isr_tables isr_tables;
	/* space for a copy used by the interrupt handler */
	struct dsi_isr_tables isr_tables_copy;

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	int update_channel;
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	struct dsi_update_region update_region;

	bool te_enabled;
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	bool ulps_enabled;
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	void (*framedone_callback)(int, void *);
	void *framedone_data;

	struct delayed_work framedone_timeout_work;

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#ifdef DSI_CATCH_MISSING_TE
	struct timer_list te_timer;
#endif

	unsigned long cache_req_pck;
	unsigned long cache_clk_freq;
	struct dsi_clock_info cache_cinfo;

	u32		errors;
	spinlock_t	errors_lock;
#ifdef DEBUG
	ktime_t perf_setup_time;
	ktime_t perf_start_time;
#endif
	int debug_read;
	int debug_write;
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#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
	spinlock_t irq_stats_lock;
	struct dsi_irq_stats irq_stats;
#endif
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	/* DSI PLL Parameter Ranges */
	unsigned long regm_max, regn_max;
	unsigned long  regm_dispc_max, regm_dsi_max;
	unsigned long  fint_min, fint_max;
	unsigned long lpdiv_max;
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	unsigned num_lanes_supported;
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	struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
	unsigned num_lanes_used;

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	unsigned scp_clk_refcount;
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};
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struct dsi_packet_sent_handler_data {
	struct platform_device *dsidev;
	struct completion *completion;
};

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static struct platform_device *dsi_pdev_map[MAX_NUM_DSI];

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#ifdef DEBUG
static unsigned int dsi_perf;
module_param_named(dsi_perf, dsi_perf, bool, 0644);
#endif

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static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
{
	return dev_get_drvdata(&dsidev->dev);
}

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static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
{
	return dsi_pdev_map[dssdev->phy.dsi.module];
}

struct platform_device *dsi_get_dsidev_from_id(int module)
{
	return dsi_pdev_map[module];
}

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static inline int dsi_get_dsidev_id(struct platform_device *dsidev)
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{
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	return dsidev->id;
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}

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static inline void dsi_write_reg(struct platform_device *dsidev,
		const struct dsi_reg idx, u32 val)
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{
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	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	__raw_writel(val, dsi->base + idx.idx);
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}

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static inline u32 dsi_read_reg(struct platform_device *dsidev,
		const struct dsi_reg idx)
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{
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	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	return __raw_readl(dsi->base + idx.idx);
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}

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void dsi_bus_lock(struct omap_dss_device *dssdev)
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{
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	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	down(&dsi->bus_lock);
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}
EXPORT_SYMBOL(dsi_bus_lock);

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void dsi_bus_unlock(struct omap_dss_device *dssdev)
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{
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	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	up(&dsi->bus_lock);
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}
EXPORT_SYMBOL(dsi_bus_unlock);

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static bool dsi_bus_is_locked(struct platform_device *dsidev)
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{
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	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	return dsi->bus_lock.count == 0;
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}

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static void dsi_completion_handler(void *data, u32 mask)
{
	complete((struct completion *)data);
}

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static inline int wait_for_bit_change(struct platform_device *dsidev,
		const struct dsi_reg idx, int bitnum, int value)
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{
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	unsigned long timeout;
	ktime_t wait;
	int t;

	/* first busyloop to see if the bit changes right away */
	t = 100;
	while (t-- > 0) {
		if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
			return value;
	}

	/* then loop for 500ms, sleeping for 1ms in between */
	timeout = jiffies + msecs_to_jiffies(500);
	while (time_before(jiffies, timeout)) {
		if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
			return value;
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		wait = ns_to_ktime(1000 * 1000);
		set_current_state(TASK_UNINTERRUPTIBLE);
		schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
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	}

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	return !value;
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}

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u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
{
	switch (fmt) {
	case OMAP_DSS_DSI_FMT_RGB888:
	case OMAP_DSS_DSI_FMT_RGB666:
		return 24;
	case OMAP_DSS_DSI_FMT_RGB666_PACKED:
		return 18;
	case OMAP_DSS_DSI_FMT_RGB565:
		return 16;
	default:
		BUG();
	}
}

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#ifdef DEBUG
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static void dsi_perf_mark_setup(struct platform_device *dsidev)
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{
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	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
	dsi->perf_setup_time = ktime_get();
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}

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static void dsi_perf_mark_start(struct platform_device *dsidev)
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{
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	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
	dsi->perf_start_time = ktime_get();
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}

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static void dsi_perf_show(struct platform_device *dsidev, const char *name)
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{
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	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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	struct omap_dss_device *dssdev = dsi->update_region.device;
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	ktime_t t, setup_time, trans_time;
	u32 total_bytes;
	u32 setup_us, trans_us, total_us;

	if (!dsi_perf)
		return;

	t = ktime_get();

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	setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
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	setup_us = (u32)ktime_to_us(setup_time);
	if (setup_us == 0)
		setup_us = 1;

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	trans_time = ktime_sub(t, dsi->perf_start_time);
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	trans_us = (u32)ktime_to_us(trans_time);
	if (trans_us == 0)
		trans_us = 1;

	total_us = setup_us + trans_us;

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	total_bytes = dsi->update_region.w *
		dsi->update_region.h *
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		dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8;
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	printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
			"%u bytes, %u kbytes/sec\n",
			name,
			setup_us,
			trans_us,
			total_us,
			1000*1000 / total_us,
			total_bytes,
			total_bytes * 1000 / total_us);
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}
#else
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static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
{
}

static inline void dsi_perf_mark_start(struct platform_device *dsidev)
{
}

static inline void dsi_perf_show(struct platform_device *dsidev,
		const char *name)
{
}
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#endif

static void print_irq_status(u32 status)
{
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	if (status == 0)
		return;

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#ifndef VERBOSE_IRQ
	if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
		return;
#endif
	printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);

#define PIS(x) \
	if (status & DSI_IRQ_##x) \
		printk(#x " ");
#ifdef VERBOSE_IRQ
	PIS(VC0);
	PIS(VC1);
	PIS(VC2);
	PIS(VC3);
#endif
	PIS(WAKEUP);
	PIS(RESYNC);
	PIS(PLL_LOCK);
	PIS(PLL_UNLOCK);
	PIS(PLL_RECALL);
	PIS(COMPLEXIO_ERR);
	PIS(HS_TX_TIMEOUT);
	PIS(LP_RX_TIMEOUT);
	PIS(TE_TRIGGER);
	PIS(ACK_TRIGGER);
	PIS(SYNC_LOST);
	PIS(LDO_POWER_GOOD);
	PIS(TA_TIMEOUT);
#undef PIS

	printk("\n");
}

static void print_irq_status_vc(int channel, u32 status)
{
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	if (status == 0)
		return;

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#ifndef VERBOSE_IRQ
	if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
		return;
#endif
	printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);

#define PIS(x) \
	if (status & DSI_VC_IRQ_##x) \
		printk(#x " ");
	PIS(CS);
	PIS(ECC_CORR);
#ifdef VERBOSE_IRQ
	PIS(PACKET_SENT);
#endif
	PIS(FIFO_TX_OVF);
	PIS(FIFO_RX_OVF);
	PIS(BTA);
	PIS(ECC_NO_CORR);
	PIS(FIFO_TX_UDF);
	PIS(PP_BUSY_CHANGE);
#undef PIS
	printk("\n");
}

static void print_irq_status_cio(u32 status)
{
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	if (status == 0)
		return;

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	printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);

#define PIS(x) \
	if (status & DSI_CIO_IRQ_##x) \
		printk(#x " ");
	PIS(ERRSYNCESC1);
	PIS(ERRSYNCESC2);
	PIS(ERRSYNCESC3);
	PIS(ERRESC1);
	PIS(ERRESC2);
	PIS(ERRESC3);
	PIS(ERRCONTROL1);
	PIS(ERRCONTROL2);
	PIS(ERRCONTROL3);
	PIS(STATEULPS1);
	PIS(STATEULPS2);
	PIS(STATEULPS3);
	PIS(ERRCONTENTIONLP0_1);
	PIS(ERRCONTENTIONLP1_1);
	PIS(ERRCONTENTIONLP0_2);
	PIS(ERRCONTENTIONLP1_2);
	PIS(ERRCONTENTIONLP0_3);
	PIS(ERRCONTENTIONLP1_3);
	PIS(ULPSACTIVENOT_ALL0);
	PIS(ULPSACTIVENOT_ALL1);
#undef PIS

	printk("\n");
}

630
#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
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static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
		u32 *vcstatus, u32 ciostatus)
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{
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	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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	int i;

637
	spin_lock(&dsi->irq_stats_lock);
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	dsi->irq_stats.irq_count++;
	dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
641 642

	for (i = 0; i < 4; ++i)
643
		dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
644

645
	dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
646

647
	spin_unlock(&dsi->irq_stats_lock);
648 649
}
#else
650
#define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
651 652
#endif

653 654
static int debug_irq;

655 656
static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
		u32 *vcstatus, u32 ciostatus)
657
{
658
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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	int i;

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	if (irqstatus & DSI_IRQ_ERROR_MASK) {
		DSSERR("DSI error, irqstatus %x\n", irqstatus);
		print_irq_status(irqstatus);
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		spin_lock(&dsi->errors_lock);
		dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
		spin_unlock(&dsi->errors_lock);
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	} else if (debug_irq) {
		print_irq_status(irqstatus);
	}

	for (i = 0; i < 4; ++i) {
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		if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
			DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
				       i, vcstatus[i]);
			print_irq_status_vc(i, vcstatus[i]);
		} else if (debug_irq) {
			print_irq_status_vc(i, vcstatus[i]);
		}
	}
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	if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
		DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
		print_irq_status_cio(ciostatus);
	} else if (debug_irq) {
		print_irq_status_cio(ciostatus);
	}
}
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static void dsi_call_isrs(struct dsi_isr_data *isr_array,
		unsigned isr_array_size, u32 irqstatus)
{
	struct dsi_isr_data *isr_data;
	int i;

	for (i = 0; i < isr_array_size; i++) {
		isr_data = &isr_array[i];
		if (isr_data->isr && isr_data->mask & irqstatus)
			isr_data->isr(isr_data->arg, irqstatus);
	}
}

static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
		u32 irqstatus, u32 *vcstatus, u32 ciostatus)
{
	int i;

	dsi_call_isrs(isr_tables->isr_table,
			ARRAY_SIZE(isr_tables->isr_table),
			irqstatus);

	for (i = 0; i < 4; ++i) {
		if (vcstatus[i] == 0)
			continue;
		dsi_call_isrs(isr_tables->isr_table_vc[i],
				ARRAY_SIZE(isr_tables->isr_table_vc[i]),
				vcstatus[i]);
	}

	if (ciostatus != 0)
		dsi_call_isrs(isr_tables->isr_table_cio,
				ARRAY_SIZE(isr_tables->isr_table_cio),
				ciostatus);
}

725 726
static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
{
727
	struct platform_device *dsidev;
728
	struct dsi_data *dsi;
729 730
	u32 irqstatus, vcstatus[4], ciostatus;
	int i;
731

732
	dsidev = (struct platform_device *) arg;
733
	dsi = dsi_get_dsidrv_data(dsidev);
734

735
	spin_lock(&dsi->irq_lock);
736

737
	irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
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739
	/* IRQ is not for us */
740
	if (!irqstatus) {
741
		spin_unlock(&dsi->irq_lock);
742
		return IRQ_NONE;
743
	}
744

745
	dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
746
	/* flush posted write */
747
	dsi_read_reg(dsidev, DSI_IRQSTATUS);
748 749 750 751 752

	for (i = 0; i < 4; ++i) {
		if ((irqstatus & (1 << i)) == 0) {
			vcstatus[i] = 0;
			continue;
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		}

755
		vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
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757
		dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
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		/* flush posted write */
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		dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
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	}

	if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
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		ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
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		dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
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		/* flush posted write */
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		dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
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	} else {
		ciostatus = 0;
	}
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#ifdef DSI_CATCH_MISSING_TE
	if (irqstatus & DSI_IRQ_TE_TRIGGER)
774
		del_timer(&dsi->te_timer);
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#endif

777 778
	/* make a copy and unlock, so that isrs can unregister
	 * themselves */
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	memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
		sizeof(dsi->isr_tables));
781

782
	spin_unlock(&dsi->irq_lock);
783

784
	dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
785

786
	dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
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788
	dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
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790
	return IRQ_HANDLED;
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}

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/* dsi->irq_lock has to be locked by the caller */
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static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
		struct dsi_isr_data *isr_array,
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		unsigned isr_array_size, u32 default_mask,
		const struct dsi_reg enable_reg,
		const struct dsi_reg status_reg)
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{
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	struct dsi_isr_data *isr_data;
	u32 mask;
	u32 old_mask;
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	int i;

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	mask = default_mask;
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	for (i = 0; i < isr_array_size; i++) {
		isr_data = &isr_array[i];
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		if (isr_data->isr == NULL)
			continue;

		mask |= isr_data->mask;
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	}

816
	old_mask = dsi_read_reg(dsidev, enable_reg);
817
	/* clear the irqstatus for newly enabled irqs */
818 819
	dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
	dsi_write_reg(dsidev, enable_reg, mask);
820 821

	/* flush posted writes */
822 823
	dsi_read_reg(dsidev, enable_reg);
	dsi_read_reg(dsidev, status_reg);
824
}
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826
/* dsi->irq_lock has to be locked by the caller */
827
static void _omap_dsi_set_irqs(struct platform_device *dsidev)
828
{
829
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
830
	u32 mask = DSI_IRQ_ERROR_MASK;
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#ifdef DSI_CATCH_MISSING_TE
832
	mask |= DSI_IRQ_TE_TRIGGER;
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#endif
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	_omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
			ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
836 837
			DSI_IRQENABLE, DSI_IRQSTATUS);
}
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839
/* dsi->irq_lock has to be locked by the caller */
840
static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
841
{
842 843 844 845
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	_omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
			ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
846 847 848 849
			DSI_VC_IRQ_ERROR_MASK,
			DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
}

850
/* dsi->irq_lock has to be locked by the caller */
851
static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
852
{
853 854 855 856
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	_omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
			ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
857 858 859 860
			DSI_CIO_IRQ_ERROR_MASK,
			DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
}

861
static void _dsi_initialize_irq(struct platform_device *dsidev)
862
{
863
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
864 865 866
	unsigned long flags;
	int vc;

867
	spin_lock_irqsave(&dsi->irq_lock, flags);
868

869
	memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
870

871
	_omap_dsi_set_irqs(dsidev);
872
	for (vc = 0; vc < 4; ++vc)
873 874
		_omap_dsi_set_irqs_vc(dsidev, vc);
	_omap_dsi_set_irqs_cio(dsidev);
875

876
	spin_unlock_irqrestore(&dsi->irq_lock, flags);
877
}
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static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
		struct dsi_isr_data *isr_array, unsigned isr_array_size)
{
	struct dsi_isr_data *isr_data;
	int free_idx;
	int i;

	BUG_ON(isr == NULL);

	/* check for duplicate entry and find a free slot */
	free_idx = -1;
	for (i = 0; i < isr_array_size; i++) {
		isr_data = &isr_array[i];

		if (isr_data->isr == isr && isr_data->arg == arg &&
				isr_data->mask == mask) {
			return -EINVAL;
		}

		if (isr_data->isr == NULL && free_idx == -1)
			free_idx = i;
	}

	if (free_idx == -1)
		return -EBUSY;

	isr_data = &isr_array[free_idx];
	isr_data->isr = isr;
	isr_data->arg = arg;
	isr_data->mask = mask;

	return 0;
}

static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
		struct dsi_isr_data *isr_array, unsigned isr_array_size)
{
	struct dsi_isr_data *isr_data;
	int i;

	for (i = 0; i < isr_array_size; i++) {
		isr_data = &isr_array[i];
		if (isr_data->isr != isr || isr_data->arg != arg ||
				isr_data->mask != mask)
			continue;

		isr_data->isr = NULL;
		isr_data->arg = NULL;
		isr_data->mask = 0;

		return 0;
	}

	return -EINVAL;
}

935 936
static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
		void *arg, u32 mask)
937
{
938
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
939 940 941
	unsigned long flags;
	int r;

942
	spin_lock_irqsave(&dsi->irq_lock, flags);
943

944 945
	r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
			ARRAY_SIZE(dsi->isr_tables.isr_table));
946 947

	if (r == 0)
948
		_omap_dsi_set_irqs(dsidev);
949

950
	spin_unlock_irqrestore(&dsi->irq_lock, flags);
951 952 953 954

	return r;
}

955 956
static int dsi_unregister_isr(struct platform_device *dsidev,
		omap_dsi_isr_t isr, void *arg, u32 mask)
957
{
958
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
959 960 961
	unsigned long flags;
	int r;

962
	spin_lock_irqsave(&dsi->irq_lock, flags);
963

964 965
	r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
			ARRAY_SIZE(dsi->isr_tables.isr_table));
966 967

	if (r == 0)
968
		_omap_dsi_set_irqs(dsidev);
969

970
	spin_unlock_irqrestore(&dsi->irq_lock, flags);
971 972 973 974

	return r;
}

975 976
static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
		omap_dsi_isr_t isr, void *arg, u32 mask)
977
{
978
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
979 980 981
	unsigned long flags;
	int r;

982
	spin_lock_irqsave(&dsi->irq_lock, flags);
983 984

	r = _dsi_register_isr(isr, arg, mask,
985 986
			dsi->isr_tables.isr_table_vc[channel],
			ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
987 988

	if (r == 0)
989
		_omap_dsi_set_irqs_vc(dsidev, channel);
990

991
	spin_unlock_irqrestore(&dsi->irq_lock, flags);
992 993 994 995

	return r;
}

996 997
static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
		omap_dsi_isr_t isr, void *arg, u32 mask)
998
{
999
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1000 1001 1002
	unsigned long flags;
	int r;

1003
	spin_lock_irqsave(&dsi->irq_lock, flags);
1004 1005

	r = _dsi_unregister_isr(isr, arg, mask,
1006 1007
			dsi->isr_tables.isr_table_vc[channel],
			ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1008 1009

	if (r == 0)
1010
		_omap_dsi_set_irqs_vc(dsidev, channel);
1011

1012
	spin_unlock_irqrestore(&dsi->irq_lock, flags);
1013 1014 1015 1016

	return r;
}

1017 1018
static int dsi_register_isr_cio(struct platform_device *dsidev,
		omap_dsi_isr_t isr, void *arg, u32 mask)
1019
{
1020
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1021 1022 1023
	unsigned long flags;
	int r;

1024
	spin_lock_irqsave(&dsi->irq_lock, flags);
1025

1026 1027
	r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
			ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1028 1029

	if (r == 0)
1030
		_omap_dsi_set_irqs_cio(dsidev);
1031

1032
	spin_unlock_irqrestore(&dsi->irq_lock, flags);
1033 1034 1035 1036

	return r;
}

1037 1038
static int dsi_unregister_isr_cio(struct platform_device *dsidev,
		omap_dsi_isr_t isr, void *arg, u32 mask)
1039
{
1040
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1041 1042 1043
	unsigned long flags;
	int r;

1044
	spin_lock_irqsave(&dsi->irq_lock, flags);
1045

1046 1047
	r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
			ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1048 1049

	if (r == 0)
1050
		_omap_dsi_set_irqs_cio(dsidev);
1051

1052
	spin_unlock_irqrestore(&dsi->irq_lock, flags);
1053 1054

	return r;
T
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}

1057
static u32 dsi_get_errors(struct platform_device *dsidev)
T
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1058
{
1059
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
T
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1060 1061
	unsigned long flags;
	u32 e;
1062 1063 1064 1065
	spin_lock_irqsave(&dsi->errors_lock, flags);
	e = dsi->errors;
	dsi->errors = 0;
	spin_unlock_irqrestore(&dsi->errors_lock, flags);
T
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1066 1067 1068
	return e;
}

1069
int dsi_runtime_get(struct platform_device *dsidev)
T
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{
1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089
	int r;
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	DSSDBG("dsi_runtime_get\n");

	r = pm_runtime_get_sync(&dsi->pdev->dev);
	WARN_ON(r < 0);
	return r < 0 ? r : 0;
}

void dsi_runtime_put(struct platform_device *dsidev)
{
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
	int r;

	DSSDBG("dsi_runtime_put\n");

	r = pm_runtime_put(&dsi->pdev->dev);
	WARN_ON(r < 0);
T
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}

/* source clock for DSI PLL. this could also be PCLKFREE */
1093 1094
static inline void dsi_enable_pll_clock(struct platform_device *dsidev,
		bool enable)
T
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1095
{
1096 1097
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

T
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1098
	if (enable)
1099
		clk_enable(dsi->sys_clk);
T
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1100
	else
1101
		clk_disable(dsi->sys_clk);
T
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1102

1103
	if (enable && dsi->pll_locked) {
1104
		if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1)
T
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1105 1106 1107 1108 1109
			DSSERR("cannot lock PLL when enabling clocks\n");
	}
}

#ifdef DEBUG
1110
static void _dsi_print_reset_status(struct platform_device *dsidev)
T
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1111 1112
{
	u32 l;
1113
	int b0, b1, b2;
T
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1114 1115 1116 1117 1118 1119 1120

	if (!dss_debug)
		return;

	/* A dummy read using the SCP interface to any DSIPHY register is
	 * required after DSIPHY reset to complete the reset of the DSI complex
	 * I/O. */
1121
	l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
T
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1122 1123 1124

	printk(KERN_DEBUG "DSI resets: ");

1125
	l = dsi_read_reg(dsidev, DSI_PLL_STATUS);
T
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	printk("PLL (%d) ", FLD_GET(l, 0, 0));

1128
	l = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
T
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	printk("CIO (%d) ", FLD_GET(l, 29, 29));

1131 1132 1133 1134 1135 1136 1137 1138 1139 1140
	if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
		b0 = 28;
		b1 = 27;
		b2 = 26;
	} else {
		b0 = 24;
		b1 = 25;
		b2 = 26;
	}

1141
	l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1142 1143 1144 1145
	printk("PHY (%x%x%x, %d, %d, %d)\n",
			FLD_GET(l, b0, b0),
			FLD_GET(l, b1, b1),
			FLD_GET(l, b2, b2),
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			FLD_GET(l, 29, 29),
			FLD_GET(l, 30, 30),
			FLD_GET(l, 31, 31));
}
#else
1151
#define _dsi_print_reset_status(x)
T
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#endif

1154
static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
T
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1155 1156 1157 1158
{
	DSSDBG("dsi_if_enable(%d)\n", enable);

	enable = enable ? 1 : 0;
1159
	REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
T
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1160

1161
	if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
T
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			DSSERR("Failed to set dsi_if_enable to %d\n", enable);
			return -EIO;
	}

	return 0;
}

1169
unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
T
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1170
{
1171 1172 1173
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk;
T
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}

1176
static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
T
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1177
{
1178 1179 1180
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk;
T
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1181 1182
}

1183
static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
T
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1184
{
1185 1186 1187
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	return dsi->current_cinfo.clkin4ddr / 16;
T
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1188 1189
}

1190
static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
T
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1191 1192
{
	unsigned long r;
1193
	int dsi_module = dsi_get_dsidev_id(dsidev);
1194
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
T
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1195

1196
	if (dss_get_dsi_clk_source(dsi_module) == OMAP_DSS_CLK_SRC_FCK) {
1197
		/* DSI FCLK source is DSS_CLK_FCK */
1198
		r = clk_get_rate(dsi->dss_clk);
T
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1199
	} else {
1200
		/* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1201
		r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
T
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1202 1203 1204 1205 1206 1207 1208
	}

	return r;
}

static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
{
1209
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
1210
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
T
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1211 1212 1213 1214
	unsigned long dsi_fclk;
	unsigned lp_clk_div;
	unsigned long lp_clk;

1215
	lp_clk_div = dssdev->clocks.dsi.lp_clk_div;
T
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1216

1217
	if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max)
T
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1218 1219
		return -EINVAL;

1220
	dsi_fclk = dsi_fclk_rate(dsidev);
T
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1221 1222 1223 1224

	lp_clk = dsi_fclk / 2 / lp_clk_div;

	DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1225 1226
	dsi->current_cinfo.lp_clk = lp_clk;
	dsi->current_cinfo.lp_clk_div = lp_clk_div;
T
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1227

1228 1229
	/* LP_CLK_DIVISOR */
	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
T
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1231 1232
	/* LP_RX_SYNCHRO_ENABLE */
	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
T
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1233 1234 1235 1236

	return 0;
}

1237
static void dsi_enable_scp_clk(struct platform_device *dsidev)
1238
{
1239 1240 1241
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	if (dsi->scp_clk_refcount++ == 0)
1242
		REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1243 1244
}

1245
static void dsi_disable_scp_clk(struct platform_device *dsidev)
1246
{
1247 1248 1249 1250
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	WARN_ON(dsi->scp_clk_refcount == 0);
	if (--dsi->scp_clk_refcount == 0)
1251
		REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1252
}
T
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1253 1254 1255 1256 1257 1258 1259 1260

enum dsi_pll_power_state {
	DSI_PLL_POWER_OFF	= 0x0,
	DSI_PLL_POWER_ON_HSCLK	= 0x1,
	DSI_PLL_POWER_ON_ALL	= 0x2,
	DSI_PLL_POWER_ON_DIV	= 0x3,
};

1261 1262
static int dsi_pll_power(struct platform_device *dsidev,
		enum dsi_pll_power_state state)
T
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1263 1264 1265
{
	int t = 0;

1266 1267 1268 1269 1270
	/* DSI-PLL power command 0x3 is not working */
	if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
			state == DSI_PLL_POWER_ON_DIV)
		state = DSI_PLL_POWER_ON_ALL;

1271 1272
	/* PLL_PWR_CMD */
	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
T
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1273 1274

	/* PLL_PWR_STATUS */
1275
	while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1276
		if (++t > 1000) {
T
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			DSSERR("Failed to set DSI PLL power mode to %d\n",
					state);
			return -ENODEV;
		}
1281
		udelay(1);
T
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1282 1283 1284 1285 1286 1287
	}

	return 0;
}

/* calculate clock rates using dividers in cinfo */
1288 1289
static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
		struct dsi_clock_info *cinfo)
T
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1290
{
1291 1292 1293 1294
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)
T
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1295 1296
		return -EINVAL;

1297
	if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max)
T
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1298 1299
		return -EINVAL;

1300
	if (cinfo->regm_dispc > dsi->regm_dispc_max)
T
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1301 1302
		return -EINVAL;

1303
	if (cinfo->regm_dsi > dsi->regm_dsi_max)
T
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1304 1305
		return -EINVAL;

1306
	if (cinfo->use_sys_clk) {
1307
		cinfo->clkin = clk_get_rate(dsi->sys_clk);
T
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1308
		/* XXX it is unclear if highfreq should be used
1309
		 * with DSS_SYS_CLK source also */
T
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1310 1311
		cinfo->highfreq = 0;
	} else {
1312
		cinfo->clkin = dispc_mgr_pclk_rate(dssdev->manager->id);
T
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1313 1314 1315 1316 1317 1318 1319 1320 1321

		if (cinfo->clkin < 32000000)
			cinfo->highfreq = 0;
		else
			cinfo->highfreq = 1;
	}

	cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1));

1322
	if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min)
T
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1323 1324 1325 1326 1327 1328 1329
		return -EINVAL;

	cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;

	if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
		return -EINVAL;

1330 1331 1332
	if (cinfo->regm_dispc > 0)
		cinfo->dsi_pll_hsdiv_dispc_clk =
			cinfo->clkin4ddr / cinfo->regm_dispc;
T
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1333
	else
1334
		cinfo->dsi_pll_hsdiv_dispc_clk = 0;
T
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1335

1336 1337 1338
	if (cinfo->regm_dsi > 0)
		cinfo->dsi_pll_hsdiv_dsi_clk =
			cinfo->clkin4ddr / cinfo->regm_dsi;
T
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1339
	else
1340
		cinfo->dsi_pll_hsdiv_dsi_clk = 0;
T
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1341 1342 1343 1344

	return 0;
}

1345 1346
int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
		unsigned long req_pck, struct dsi_clock_info *dsi_cinfo,
T
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1347 1348
		struct dispc_clock_info *dispc_cinfo)
{
1349
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
T
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1350 1351 1352 1353
	struct dsi_clock_info cur, best;
	struct dispc_clock_info best_dispc;
	int min_fck_per_pck;
	int match = 0;
1354
	unsigned long dss_sys_clk, max_dss_fck;
T
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1355

1356
	dss_sys_clk = clk_get_rate(dsi->sys_clk);
T
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1357

1358
	max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1359

1360 1361
	if (req_pck == dsi->cache_req_pck &&
			dsi->cache_cinfo.clkin == dss_sys_clk) {
T
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1362
		DSSDBG("DSI clock info found from cache\n");
1363
		*dsi_cinfo = dsi->cache_cinfo;
1364 1365
		dispc_find_clk_divs(is_tft, req_pck,
			dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo);
T
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1366 1367 1368 1369 1370 1371
		return 0;
	}

	min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;

	if (min_fck_per_pck &&
1372
		req_pck * min_fck_per_pck > max_dss_fck) {
T
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1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385
		DSSERR("Requested pixel clock not possible with the current "
				"OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
				"the constraint off.\n");
		min_fck_per_pck = 0;
	}

	DSSDBG("dsi_pll_calc\n");

retry:
	memset(&best, 0, sizeof(best));
	memset(&best_dispc, 0, sizeof(best_dispc));

	memset(&cur, 0, sizeof(cur));
1386 1387
	cur.clkin = dss_sys_clk;
	cur.use_sys_clk = 1;
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1388 1389 1390 1391 1392
	cur.highfreq = 0;

	/* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
	/* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
	/* To reduce PLL lock time, keep Fint high (around 2 MHz) */
1393
	for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
T
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1394 1395 1396 1397 1398
		if (cur.highfreq == 0)
			cur.fint = cur.clkin / cur.regn;
		else
			cur.fint = cur.clkin / (2 * cur.regn);

1399
		if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
T
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1400 1401 1402
			continue;

		/* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
1403
		for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
T
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1404 1405 1406 1407 1408 1409 1410 1411 1412
			unsigned long a, b;

			a = 2 * cur.regm * (cur.clkin/1000);
			b = cur.regn * (cur.highfreq + 1);
			cur.clkin4ddr = a / b * 1000;

			if (cur.clkin4ddr > 1800 * 1000 * 1000)
				break;

1413 1414
			/* dsi_pll_hsdiv_dispc_clk(MHz) =
			 * DSIPHY(MHz) / regm_dispc  < 173MHz/186Mhz */
1415 1416
			for (cur.regm_dispc = 1; cur.regm_dispc <
					dsi->regm_dispc_max; ++cur.regm_dispc) {
T
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				struct dispc_clock_info cur_dispc;
1418 1419
				cur.dsi_pll_hsdiv_dispc_clk =
					cur.clkin4ddr / cur.regm_dispc;
T
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1420 1421 1422 1423

				/* this will narrow down the search a bit,
				 * but still give pixclocks below what was
				 * requested */
1424
				if (cur.dsi_pll_hsdiv_dispc_clk  < req_pck)
T
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1425 1426
					break;

1427
				if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck)
T
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1428 1429 1430
					continue;

				if (min_fck_per_pck &&
1431
					cur.dsi_pll_hsdiv_dispc_clk <
T
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1432 1433 1434 1435 1436 1437
						req_pck * min_fck_per_pck)
					continue;

				match = 1;

				dispc_find_clk_divs(is_tft, req_pck,
1438
						cur.dsi_pll_hsdiv_dispc_clk,
T
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1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466
						&cur_dispc);

				if (abs(cur_dispc.pck - req_pck) <
						abs(best_dispc.pck - req_pck)) {
					best = cur;
					best_dispc = cur_dispc;

					if (cur_dispc.pck == req_pck)
						goto found;
				}
			}
		}
	}
found:
	if (!match) {
		if (min_fck_per_pck) {
			DSSERR("Could not find suitable clock settings.\n"
					"Turning FCK/PCK constraint off and"
					"trying again.\n");
			min_fck_per_pck = 0;
			goto retry;
		}

		DSSERR("Could not find suitable clock settings.\n");

		return -EINVAL;
	}

1467 1468 1469
	/* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
	best.regm_dsi = 0;
	best.dsi_pll_hsdiv_dsi_clk = 0;
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1470 1471 1472 1473 1474 1475

	if (dsi_cinfo)
		*dsi_cinfo = best;
	if (dispc_cinfo)
		*dispc_cinfo = best_dispc;

1476 1477 1478
	dsi->cache_req_pck = req_pck;
	dsi->cache_clk_freq = 0;
	dsi->cache_cinfo = best;
T
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	return 0;
}

1483 1484
int dsi_pll_set_clock_div(struct platform_device *dsidev,
		struct dsi_clock_info *cinfo)
T
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1485
{
1486
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
T
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1487 1488
	int r = 0;
	u32 l;
1489
	int f = 0;
1490 1491
	u8 regn_start, regn_end, regm_start, regm_end;
	u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
T
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	DSSDBGF();

1495 1496
	dsi->current_cinfo.use_sys_clk = cinfo->use_sys_clk;
	dsi->current_cinfo.highfreq = cinfo->highfreq;
1497

1498 1499 1500
	dsi->current_cinfo.fint = cinfo->fint;
	dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
	dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk =
1501
			cinfo->dsi_pll_hsdiv_dispc_clk;
1502
	dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk =
1503
			cinfo->dsi_pll_hsdiv_dsi_clk;
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1505 1506 1507 1508
	dsi->current_cinfo.regn = cinfo->regn;
	dsi->current_cinfo.regm = cinfo->regm;
	dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
	dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
T
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1509 1510 1511 1512

	DSSDBG("DSI Fint %ld\n", cinfo->fint);

	DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
1513
			cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree",
T
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1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529
			cinfo->clkin,
			cinfo->highfreq);

	/* DSIPHY == CLKIN4DDR */
	DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n",
			cinfo->regm,
			cinfo->regn,
			cinfo->clkin,
			cinfo->highfreq + 1,
			cinfo->clkin4ddr);

	DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
			cinfo->clkin4ddr / 1000 / 1000 / 2);

	DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);

1530
	DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1531 1532
		dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
		dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1533 1534
		cinfo->dsi_pll_hsdiv_dispc_clk);
	DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1535 1536
		dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
		dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1537
		cinfo->dsi_pll_hsdiv_dsi_clk);
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1538

1539 1540 1541 1542 1543 1544 1545
	dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, &regn_start, &regn_end);
	dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, &regm_start, &regm_end);
	dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, &regm_dispc_start,
			&regm_dispc_end);
	dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, &regm_dsi_start,
			&regm_dsi_end);

1546 1547
	/* DSI_PLL_AUTOMODE = manual */
	REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0);
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1548

1549
	l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1);
T
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1550
	l = FLD_MOD(l, 1, 0, 0);		/* DSI_PLL_STOPMODE */
1551 1552 1553 1554 1555
	/* DSI_PLL_REGN */
	l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
	/* DSI_PLL_REGM */
	l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
	/* DSI_CLOCK_DIV */
1556
	l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1557 1558
			regm_dispc_start, regm_dispc_end);
	/* DSIPROTO_CLOCK_DIV */
1559
	l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1560
			regm_dsi_start, regm_dsi_end);
1561
	dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l);
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1562

1563
	BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
1564 1565 1566 1567 1568 1569 1570 1571

	if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
		f = cinfo->fint < 1000000 ? 0x3 :
			cinfo->fint < 1250000 ? 0x4 :
			cinfo->fint < 1500000 ? 0x5 :
			cinfo->fint < 1750000 ? 0x6 :
			0x7;
	}
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1572

1573
	l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1574 1575 1576

	if (dss_has_feature(FEAT_DSI_PLL_FREQSEL))
		l = FLD_MOD(l, f, 4, 1);	/* DSI_PLL_FREQSEL */
1577
	l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1,
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1578 1579 1580 1581 1582 1583
			11, 11);		/* DSI_PLL_CLKSEL */
	l = FLD_MOD(l, cinfo->highfreq,
			12, 12);		/* DSI_PLL_HIGHFREQ */
	l = FLD_MOD(l, 1, 13, 13);		/* DSI_PLL_REFEN */
	l = FLD_MOD(l, 0, 14, 14);		/* DSIPHY_CLKINEN */
	l = FLD_MOD(l, 1, 20, 20);		/* DSI_HSDIVBYPASS */
1584
	dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
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1585

1586
	REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0);	/* DSI_PLL_GO */
T
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1587

1588
	if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) {
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1589 1590 1591 1592 1593
		DSSERR("dsi pll go bit not going down.\n");
		r = -EIO;
		goto err;
	}

1594
	if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) {
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1595 1596 1597 1598 1599
		DSSERR("cannot lock PLL\n");
		r = -EIO;
		goto err;
	}

1600
	dsi->pll_locked = 1;
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1601

1602
	l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
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1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616
	l = FLD_MOD(l, 0, 0, 0);	/* DSI_PLL_IDLE */
	l = FLD_MOD(l, 0, 5, 5);	/* DSI_PLL_PLLLPMODE */
	l = FLD_MOD(l, 0, 6, 6);	/* DSI_PLL_LOWCURRSTBY */
	l = FLD_MOD(l, 0, 7, 7);	/* DSI_PLL_TIGHTPHASELOCK */
	l = FLD_MOD(l, 0, 8, 8);	/* DSI_PLL_DRIFTGUARDEN */
	l = FLD_MOD(l, 0, 10, 9);	/* DSI_PLL_LOCKSEL */
	l = FLD_MOD(l, 1, 13, 13);	/* DSI_PLL_REFEN */
	l = FLD_MOD(l, 1, 14, 14);	/* DSIPHY_CLKINEN */
	l = FLD_MOD(l, 0, 15, 15);	/* DSI_BYPASSEN */
	l = FLD_MOD(l, 1, 16, 16);	/* DSS_CLOCK_EN */
	l = FLD_MOD(l, 0, 17, 17);	/* DSS_CLOCK_PWDN */
	l = FLD_MOD(l, 1, 18, 18);	/* DSI_PROTO_CLOCK_EN */
	l = FLD_MOD(l, 0, 19, 19);	/* DSI_PROTO_CLOCK_PWDN */
	l = FLD_MOD(l, 0, 20, 20);	/* DSI_HSDIVBYPASS */
1617
	dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
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1618 1619 1620 1621 1622 1623

	DSSDBG("PLL config done\n");
err:
	return r;
}

1624 1625
int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
		bool enable_hsdiv)
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1626
{
1627
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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1628 1629 1630 1631 1632
	int r = 0;
	enum dsi_pll_power_state pwstate;

	DSSDBG("PLL init\n");

1633
	if (dsi->vdds_dsi_reg == NULL) {
1634 1635
		struct regulator *vdds_dsi;

1636
		vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
1637 1638 1639 1640 1641 1642

		if (IS_ERR(vdds_dsi)) {
			DSSERR("can't get VDDS_DSI regulator\n");
			return PTR_ERR(vdds_dsi);
		}

1643
		dsi->vdds_dsi_reg = vdds_dsi;
1644 1645
	}

1646
	dsi_enable_pll_clock(dsidev, 1);
1647 1648 1649
	/*
	 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
	 */
1650
	dsi_enable_scp_clk(dsidev);
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1651

1652 1653
	if (!dsi->vdds_dsi_enabled) {
		r = regulator_enable(dsi->vdds_dsi_reg);
1654 1655
		if (r)
			goto err0;
1656
		dsi->vdds_dsi_enabled = true;
1657
	}
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1658 1659 1660 1661

	/* XXX PLL does not come out of reset without this... */
	dispc_pck_free_enable(1);

1662
	if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
T
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1663 1664
		DSSERR("PLL not coming out of reset.\n");
		r = -ENODEV;
1665
		dispc_pck_free_enable(0);
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1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681
		goto err1;
	}

	/* XXX ... but if left on, we get problems when planes do not
	 * fill the whole display. No idea about this */
	dispc_pck_free_enable(0);

	if (enable_hsclk && enable_hsdiv)
		pwstate = DSI_PLL_POWER_ON_ALL;
	else if (enable_hsclk)
		pwstate = DSI_PLL_POWER_ON_HSCLK;
	else if (enable_hsdiv)
		pwstate = DSI_PLL_POWER_ON_DIV;
	else
		pwstate = DSI_PLL_POWER_OFF;

1682
	r = dsi_pll_power(dsidev, pwstate);
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1683 1684 1685 1686 1687 1688 1689 1690

	if (r)
		goto err1;

	DSSDBG("PLL init done\n");

	return 0;
err1:
1691 1692 1693
	if (dsi->vdds_dsi_enabled) {
		regulator_disable(dsi->vdds_dsi_reg);
		dsi->vdds_dsi_enabled = false;
1694
	}
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1695
err0:
1696 1697
	dsi_disable_scp_clk(dsidev);
	dsi_enable_pll_clock(dsidev, 0);
T
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1698 1699 1700
	return r;
}

1701
void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
T
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1702
{
1703 1704 1705
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	dsi->pll_locked = 0;
1706
	dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1707
	if (disconnect_lanes) {
1708 1709 1710
		WARN_ON(!dsi->vdds_dsi_enabled);
		regulator_disable(dsi->vdds_dsi_reg);
		dsi->vdds_dsi_enabled = false;
1711
	}
1712

1713 1714
	dsi_disable_scp_clk(dsidev);
	dsi_enable_pll_clock(dsidev, 0);
1715

T
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1716 1717 1718
	DSSDBG("PLL uninit done\n");
}

1719 1720
static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
		struct seq_file *s)
T
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1721
{
1722 1723
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
	struct dsi_clock_info *cinfo = &dsi->current_cinfo;
1724
	enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1725
	int dsi_module = dsi_get_dsidev_id(dsidev);
1726 1727

	dispc_clk_src = dss_get_dispc_clk_source();
1728
	dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
T
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1729

1730 1731
	if (dsi_runtime_get(dsidev))
		return;
T
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1732

1733
	seq_printf(s,	"- DSI%d PLL -\n", dsi_module + 1);
T
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1734 1735

	seq_printf(s,	"dsi pll source = %s\n",
1736
			cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree");
T
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1737 1738 1739 1740 1741 1742

	seq_printf(s,	"Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);

	seq_printf(s,	"CLKIN4DDR\t%-16luregm %u\n",
			cinfo->clkin4ddr, cinfo->regm);

1743
	seq_printf(s,	"%s (%s)\t%-16luregm_dispc %u\t(%s)\n",
1744 1745
			dss_get_generic_clk_source_name(dispc_clk_src),
			dss_feat_get_clk_source_name(dispc_clk_src),
1746 1747
			cinfo->dsi_pll_hsdiv_dispc_clk,
			cinfo->regm_dispc,
1748
			dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1749
			"off" : "on");
T
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1750

1751
	seq_printf(s,	"%s (%s)\t%-16luregm_dsi %u\t(%s)\n",
1752 1753
			dss_get_generic_clk_source_name(dsi_clk_src),
			dss_feat_get_clk_source_name(dsi_clk_src),
1754 1755
			cinfo->dsi_pll_hsdiv_dsi_clk,
			cinfo->regm_dsi,
1756
			dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1757
			"off" : "on");
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1758

1759
	seq_printf(s,	"- DSI%d -\n", dsi_module + 1);
T
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1760

1761 1762 1763
	seq_printf(s,	"dsi fclk source = %s (%s)\n",
			dss_get_generic_clk_source_name(dsi_clk_src),
			dss_feat_get_clk_source_name(dsi_clk_src));
T
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1764

1765
	seq_printf(s,	"DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
T
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1766 1767 1768 1769

	seq_printf(s,	"DDR_CLK\t\t%lu\n",
			cinfo->clkin4ddr / 4);

1770
	seq_printf(s,	"TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
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1771 1772 1773

	seq_printf(s,	"LP_CLK\t\t%lu\n", cinfo->lp_clk);

1774
	dsi_runtime_put(dsidev);
T
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1775 1776
}

1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788
void dsi_dump_clocks(struct seq_file *s)
{
	struct platform_device *dsidev;
	int i;

	for  (i = 0; i < MAX_NUM_DSI; i++) {
		dsidev = dsi_get_dsidev_from_id(i);
		if (dsidev)
			dsi_dump_dsidev_clocks(dsidev, s);
	}
}

1789
#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1790 1791
static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
		struct seq_file *s)
1792
{
1793
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1794 1795
	unsigned long flags;
	struct dsi_irq_stats stats;
1796
	int dsi_module = dsi_get_dsidev_id(dsidev);
1797

1798
	spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1799

1800 1801 1802
	stats = dsi->irq_stats;
	memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
	dsi->irq_stats.last_reset = jiffies;
1803

1804
	spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1805 1806 1807 1808 1809 1810 1811 1812

	seq_printf(s, "period %u ms\n",
			jiffies_to_msecs(jiffies - stats.last_reset));

	seq_printf(s, "irqs %d\n", stats.irq_count);
#define PIS(x) \
	seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);

1813
	seq_printf(s, "-- DSI%d interrupts --\n", dsi_module + 1);
1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879
	PIS(VC0);
	PIS(VC1);
	PIS(VC2);
	PIS(VC3);
	PIS(WAKEUP);
	PIS(RESYNC);
	PIS(PLL_LOCK);
	PIS(PLL_UNLOCK);
	PIS(PLL_RECALL);
	PIS(COMPLEXIO_ERR);
	PIS(HS_TX_TIMEOUT);
	PIS(LP_RX_TIMEOUT);
	PIS(TE_TRIGGER);
	PIS(ACK_TRIGGER);
	PIS(SYNC_LOST);
	PIS(LDO_POWER_GOOD);
	PIS(TA_TIMEOUT);
#undef PIS

#define PIS(x) \
	seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
			stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
			stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
			stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
			stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);

	seq_printf(s, "-- VC interrupts --\n");
	PIS(CS);
	PIS(ECC_CORR);
	PIS(PACKET_SENT);
	PIS(FIFO_TX_OVF);
	PIS(FIFO_RX_OVF);
	PIS(BTA);
	PIS(ECC_NO_CORR);
	PIS(FIFO_TX_UDF);
	PIS(PP_BUSY_CHANGE);
#undef PIS

#define PIS(x) \
	seq_printf(s, "%-20s %10d\n", #x, \
			stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);

	seq_printf(s, "-- CIO interrupts --\n");
	PIS(ERRSYNCESC1);
	PIS(ERRSYNCESC2);
	PIS(ERRSYNCESC3);
	PIS(ERRESC1);
	PIS(ERRESC2);
	PIS(ERRESC3);
	PIS(ERRCONTROL1);
	PIS(ERRCONTROL2);
	PIS(ERRCONTROL3);
	PIS(STATEULPS1);
	PIS(STATEULPS2);
	PIS(STATEULPS3);
	PIS(ERRCONTENTIONLP0_1);
	PIS(ERRCONTENTIONLP1_1);
	PIS(ERRCONTENTIONLP0_2);
	PIS(ERRCONTENTIONLP1_2);
	PIS(ERRCONTENTIONLP0_3);
	PIS(ERRCONTENTIONLP1_3);
	PIS(ULPSACTIVENOT_ALL0);
	PIS(ULPSACTIVENOT_ALL1);
#undef PIS
}

1880
static void dsi1_dump_irqs(struct seq_file *s)
T
Tomi Valkeinen 已提交
1881
{
1882 1883
	struct platform_device *dsidev = dsi_get_dsidev_from_id(0);

1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913
	dsi_dump_dsidev_irqs(dsidev, s);
}

static void dsi2_dump_irqs(struct seq_file *s)
{
	struct platform_device *dsidev = dsi_get_dsidev_from_id(1);

	dsi_dump_dsidev_irqs(dsidev, s);
}

void dsi_create_debugfs_files_irq(struct dentry *debugfs_dir,
		const struct file_operations *debug_fops)
{
	struct platform_device *dsidev;

	dsidev = dsi_get_dsidev_from_id(0);
	if (dsidev)
		debugfs_create_file("dsi1_irqs", S_IRUGO, debugfs_dir,
			&dsi1_dump_irqs, debug_fops);

	dsidev = dsi_get_dsidev_from_id(1);
	if (dsidev)
		debugfs_create_file("dsi2_irqs", S_IRUGO, debugfs_dir,
			&dsi2_dump_irqs, debug_fops);
}
#endif

static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
		struct seq_file *s)
{
1914
#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
T
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1915

1916 1917
	if (dsi_runtime_get(dsidev))
		return;
1918
	dsi_enable_scp_clk(dsidev);
T
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1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989

	DUMPREG(DSI_REVISION);
	DUMPREG(DSI_SYSCONFIG);
	DUMPREG(DSI_SYSSTATUS);
	DUMPREG(DSI_IRQSTATUS);
	DUMPREG(DSI_IRQENABLE);
	DUMPREG(DSI_CTRL);
	DUMPREG(DSI_COMPLEXIO_CFG1);
	DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
	DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
	DUMPREG(DSI_CLK_CTRL);
	DUMPREG(DSI_TIMING1);
	DUMPREG(DSI_TIMING2);
	DUMPREG(DSI_VM_TIMING1);
	DUMPREG(DSI_VM_TIMING2);
	DUMPREG(DSI_VM_TIMING3);
	DUMPREG(DSI_CLK_TIMING);
	DUMPREG(DSI_TX_FIFO_VC_SIZE);
	DUMPREG(DSI_RX_FIFO_VC_SIZE);
	DUMPREG(DSI_COMPLEXIO_CFG2);
	DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
	DUMPREG(DSI_VM_TIMING4);
	DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
	DUMPREG(DSI_VM_TIMING5);
	DUMPREG(DSI_VM_TIMING6);
	DUMPREG(DSI_VM_TIMING7);
	DUMPREG(DSI_STOPCLK_TIMING);

	DUMPREG(DSI_VC_CTRL(0));
	DUMPREG(DSI_VC_TE(0));
	DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
	DUMPREG(DSI_VC_IRQSTATUS(0));
	DUMPREG(DSI_VC_IRQENABLE(0));

	DUMPREG(DSI_VC_CTRL(1));
	DUMPREG(DSI_VC_TE(1));
	DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
	DUMPREG(DSI_VC_IRQSTATUS(1));
	DUMPREG(DSI_VC_IRQENABLE(1));

	DUMPREG(DSI_VC_CTRL(2));
	DUMPREG(DSI_VC_TE(2));
	DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
	DUMPREG(DSI_VC_IRQSTATUS(2));
	DUMPREG(DSI_VC_IRQENABLE(2));

	DUMPREG(DSI_VC_CTRL(3));
	DUMPREG(DSI_VC_TE(3));
	DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
	DUMPREG(DSI_VC_IRQSTATUS(3));
	DUMPREG(DSI_VC_IRQENABLE(3));

	DUMPREG(DSI_DSIPHY_CFG0);
	DUMPREG(DSI_DSIPHY_CFG1);
	DUMPREG(DSI_DSIPHY_CFG2);
	DUMPREG(DSI_DSIPHY_CFG5);

	DUMPREG(DSI_PLL_CONTROL);
	DUMPREG(DSI_PLL_STATUS);
	DUMPREG(DSI_PLL_GO);
	DUMPREG(DSI_PLL_CONFIGURATION1);
	DUMPREG(DSI_PLL_CONFIGURATION2);

1990
	dsi_disable_scp_clk(dsidev);
1991
	dsi_runtime_put(dsidev);
T
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1992 1993 1994
#undef DUMPREG
}

1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023
static void dsi1_dump_regs(struct seq_file *s)
{
	struct platform_device *dsidev = dsi_get_dsidev_from_id(0);

	dsi_dump_dsidev_regs(dsidev, s);
}

static void dsi2_dump_regs(struct seq_file *s)
{
	struct platform_device *dsidev = dsi_get_dsidev_from_id(1);

	dsi_dump_dsidev_regs(dsidev, s);
}

void dsi_create_debugfs_files_reg(struct dentry *debugfs_dir,
		const struct file_operations *debug_fops)
{
	struct platform_device *dsidev;

	dsidev = dsi_get_dsidev_from_id(0);
	if (dsidev)
		debugfs_create_file("dsi1_regs", S_IRUGO, debugfs_dir,
			&dsi1_dump_regs, debug_fops);

	dsidev = dsi_get_dsidev_from_id(1);
	if (dsidev)
		debugfs_create_file("dsi2_regs", S_IRUGO, debugfs_dir,
			&dsi2_dump_regs, debug_fops);
}
2024
enum dsi_cio_power_state {
T
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2025 2026 2027 2028 2029
	DSI_COMPLEXIO_POWER_OFF		= 0x0,
	DSI_COMPLEXIO_POWER_ON		= 0x1,
	DSI_COMPLEXIO_POWER_ULPS	= 0x2,
};

2030 2031
static int dsi_cio_power(struct platform_device *dsidev,
		enum dsi_cio_power_state state)
T
Tomi Valkeinen 已提交
2032 2033 2034 2035
{
	int t = 0;

	/* PWR_CMD */
2036
	REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
T
Tomi Valkeinen 已提交
2037 2038

	/* PWR_STATUS */
2039 2040
	while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
			26, 25) != state) {
2041
		if (++t > 1000) {
T
Tomi Valkeinen 已提交
2042 2043 2044 2045
			DSSERR("failed to set complexio power state to "
					"%d\n", state);
			return -ENODEV;
		}
2046
		udelay(1);
T
Tomi Valkeinen 已提交
2047 2048 2049 2050 2051
	}

	return 0;
}

2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082
static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
{
	int val;

	/* line buffer on OMAP3 is 1024 x 24bits */
	/* XXX: for some reason using full buffer size causes
	 * considerable TX slowdown with update sizes that fill the
	 * whole buffer */
	if (!dss_has_feature(FEAT_DSI_GNQ))
		return 1023 * 3;

	val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */

	switch (val) {
	case 1:
		return 512 * 3;		/* 512x24 bits */
	case 2:
		return 682 * 3;		/* 682x24 bits */
	case 3:
		return 853 * 3;		/* 853x24 bits */
	case 4:
		return 1024 * 3;	/* 1024x24 bits */
	case 5:
		return 1194 * 3;	/* 1194x24 bits */
	case 6:
		return 1365 * 3;	/* 1365x24 bits */
	default:
		BUG();
	}
}

T
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2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141
static int dsi_parse_lane_config(struct omap_dss_device *dssdev)
{
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
	u8 lanes[DSI_MAX_NR_LANES];
	u8 polarities[DSI_MAX_NR_LANES];
	int num_lanes, i;

	static const enum dsi_lane_function functions[] = {
		DSI_LANE_CLK,
		DSI_LANE_DATA1,
		DSI_LANE_DATA2,
		DSI_LANE_DATA3,
		DSI_LANE_DATA4,
	};

	lanes[0] = dssdev->phy.dsi.clk_lane;
	lanes[1] = dssdev->phy.dsi.data1_lane;
	lanes[2] = dssdev->phy.dsi.data2_lane;
	lanes[3] = dssdev->phy.dsi.data3_lane;
	lanes[4] = dssdev->phy.dsi.data4_lane;
	polarities[0] = dssdev->phy.dsi.clk_pol;
	polarities[1] = dssdev->phy.dsi.data1_pol;
	polarities[2] = dssdev->phy.dsi.data2_pol;
	polarities[3] = dssdev->phy.dsi.data3_pol;
	polarities[4] = dssdev->phy.dsi.data4_pol;

	num_lanes = 0;

	for (i = 0; i < dsi->num_lanes_supported; ++i)
		dsi->lanes[i].function = DSI_LANE_UNUSED;

	for (i = 0; i < dsi->num_lanes_supported; ++i) {
		int num;

		if (lanes[i] == DSI_LANE_UNUSED)
			break;

		num = lanes[i] - 1;

		if (num >= dsi->num_lanes_supported)
			return -EINVAL;

		if (dsi->lanes[num].function != DSI_LANE_UNUSED)
			return -EINVAL;

		dsi->lanes[num].function = functions[i];
		dsi->lanes[num].polarity = polarities[i];
		num_lanes++;
	}

	if (num_lanes < 2 || num_lanes > dsi->num_lanes_supported)
		return -EINVAL;

	dsi->num_lanes_used = num_lanes;

	return 0;
}

2142
static int dsi_set_lane_config(struct omap_dss_device *dssdev)
T
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2143
{
2144
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2145 2146 2147 2148 2149 2150 2151 2152 2153
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
	static const u8 offsets[] = { 0, 4, 8, 12, 16 };
	static const enum dsi_lane_function functions[] = {
		DSI_LANE_CLK,
		DSI_LANE_DATA1,
		DSI_LANE_DATA2,
		DSI_LANE_DATA3,
		DSI_LANE_DATA4,
	};
T
Tomi Valkeinen 已提交
2154
	u32 r;
2155
	int i;
T
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2156

2157
	r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175

	for (i = 0; i < dsi->num_lanes_used; ++i) {
		unsigned offset = offsets[i];
		unsigned polarity, lane_number;
		unsigned t;

		for (t = 0; t < dsi->num_lanes_supported; ++t)
			if (dsi->lanes[t].function == functions[i])
				break;

		if (t == dsi->num_lanes_supported)
			return -EINVAL;

		lane_number = t;
		polarity = dsi->lanes[t].polarity;

		r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
		r = FLD_MOD(r, polarity, offset + 3, offset + 3);
2176 2177
	}

2178 2179 2180 2181 2182 2183
	/* clear the unused lanes */
	for (; i < dsi->num_lanes_supported; ++i) {
		unsigned offset = offsets[i];

		r = FLD_MOD(r, 0, offset + 2, offset);
		r = FLD_MOD(r, 0, offset + 3, offset + 3);
2184
	}
T
Tomi Valkeinen 已提交
2185

2186
	dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
T
Tomi Valkeinen 已提交
2187

2188
	return 0;
T
Tomi Valkeinen 已提交
2189 2190
}

2191
static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
T
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2192
{
2193 2194
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

T
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2195
	/* convert time in ns to ddr ticks, rounding up */
2196
	unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
T
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2197 2198 2199
	return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
}

2200
static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
T
Tomi Valkeinen 已提交
2201
{
2202 2203 2204
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
T
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2205 2206 2207
	return ddr * 1000 * 1000 / (ddr_clk / 1000);
}

2208
static void dsi_cio_timings(struct platform_device *dsidev)
T
Tomi Valkeinen 已提交
2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219
{
	u32 r;
	u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
	u32 tlpx_half, tclk_trail, tclk_zero;
	u32 tclk_prepare;

	/* calculate timings */

	/* 1 * DDR_CLK = 2 * UI */

	/* min 40ns + 4*UI	max 85ns + 6*UI */
2220
	ths_prepare = ns2ddr(dsidev, 70) + 2;
T
Tomi Valkeinen 已提交
2221 2222

	/* min 145ns + 10*UI */
2223
	ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
T
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2224 2225

	/* min max(8*UI, 60ns+4*UI) */
2226
	ths_trail = ns2ddr(dsidev, 60) + 5;
T
Tomi Valkeinen 已提交
2227 2228

	/* min 100ns */
2229
	ths_exit = ns2ddr(dsidev, 145);
T
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2230 2231

	/* tlpx min 50n */
2232
	tlpx_half = ns2ddr(dsidev, 25);
T
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2233 2234

	/* min 60ns */
2235
	tclk_trail = ns2ddr(dsidev, 60) + 2;
T
Tomi Valkeinen 已提交
2236 2237

	/* min 38ns, max 95ns */
2238
	tclk_prepare = ns2ddr(dsidev, 65);
T
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2239 2240

	/* min tclk-prepare + tclk-zero = 300ns */
2241
	tclk_zero = ns2ddr(dsidev, 260);
T
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2242 2243

	DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2244 2245
		ths_prepare, ddr2ns(dsidev, ths_prepare),
		ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
T
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2246
	DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2247 2248
			ths_trail, ddr2ns(dsidev, ths_trail),
			ths_exit, ddr2ns(dsidev, ths_exit));
T
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2249 2250 2251

	DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
			"tclk_zero %u (%uns)\n",
2252 2253 2254
			tlpx_half, ddr2ns(dsidev, tlpx_half),
			tclk_trail, ddr2ns(dsidev, tclk_trail),
			tclk_zero, ddr2ns(dsidev, tclk_zero));
T
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2255
	DSSDBG("tclk_prepare %u (%uns)\n",
2256
			tclk_prepare, ddr2ns(dsidev, tclk_prepare));
T
Tomi Valkeinen 已提交
2257 2258 2259

	/* program timings */

2260
	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
T
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2261 2262 2263 2264
	r = FLD_MOD(r, ths_prepare, 31, 24);
	r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
	r = FLD_MOD(r, ths_trail, 15, 8);
	r = FLD_MOD(r, ths_exit, 7, 0);
2265
	dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
T
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2266

2267
	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
T
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2268 2269 2270
	r = FLD_MOD(r, tlpx_half, 22, 16);
	r = FLD_MOD(r, tclk_trail, 15, 8);
	r = FLD_MOD(r, tclk_zero, 7, 0);
2271
	dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
T
Tomi Valkeinen 已提交
2272

2273
	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
T
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2274
	r = FLD_MOD(r, tclk_prepare, 7, 0);
2275
	dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
T
Tomi Valkeinen 已提交
2276 2277
}

2278
/* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
2279
static void dsi_cio_enable_lane_override(struct omap_dss_device *dssdev,
2280
		unsigned mask_p, unsigned mask_n)
2281
{
2282
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2283
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2284 2285
	int i;
	u32 l;
2286
	u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
2287

2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299
	l = 0;

	for (i = 0; i < dsi->num_lanes_supported; ++i) {
		unsigned p = dsi->lanes[i].polarity;

		if (mask_p & (1 << i))
			l |= 1 << (i * 2 + (p ? 0 : 1));

		if (mask_n & (1 << i))
			l |= 1 << (i * 2 + (p ? 1 : 0));
	}

2300 2301 2302 2303 2304
	/*
	 * Bits in REGLPTXSCPDAT4TO0DXDY:
	 * 17: DY0 18: DX0
	 * 19: DY1 20: DX1
	 * 21: DY2 22: DX2
2305 2306
	 * 23: DY3 24: DX3
	 * 25: DY4 26: DX4
2307 2308 2309
	 */

	/* Set the lane override configuration */
2310 2311

	/* REGLPTXSCPDAT4TO0DXDY */
2312
	REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
2313 2314

	/* Enable lane override */
2315 2316 2317

	/* ENLPTXSCPDAT */
	REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
2318 2319
}

2320
static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
2321 2322
{
	/* Disable lane override */
2323
	REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
2324
	/* Reset the lane override configuration */
2325 2326
	/* REGLPTXSCPDAT4TO0DXDY */
	REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
2327
}
T
Tomi Valkeinen 已提交
2328

2329 2330
static int dsi_cio_wait_tx_clk_esc_reset(struct omap_dss_device *dssdev)
{
2331
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
	int t, i;
	bool in_use[DSI_MAX_NR_LANES];
	static const u8 offsets_old[] = { 28, 27, 26 };
	static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
	const u8 *offsets;

	if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC))
		offsets = offsets_old;
	else
		offsets = offsets_new;
2343

2344 2345
	for (i = 0; i < dsi->num_lanes_supported; ++i)
		in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
2346 2347 2348 2349 2350 2351

	t = 100000;
	while (true) {
		u32 l;
		int ok;

2352
		l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2353 2354

		ok = 0;
2355 2356
		for (i = 0; i < dsi->num_lanes_supported; ++i) {
			if (!in_use[i] || (l & (1 << offsets[i])))
2357 2358 2359
				ok++;
		}

2360
		if (ok == dsi->num_lanes_supported)
2361 2362 2363
			break;

		if (--t == 0) {
2364 2365
			for (i = 0; i < dsi->num_lanes_supported; ++i) {
				if (!in_use[i] || (l & (1 << offsets[i])))
2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377
					continue;

				DSSERR("CIO TXCLKESC%d domain not coming " \
						"out of reset\n", i);
			}
			return -EIO;
		}
	}

	return 0;
}

2378
/* return bitmask of enabled lanes, lane0 being the lsb */
2379 2380
static unsigned dsi_get_lane_mask(struct omap_dss_device *dssdev)
{
2381 2382 2383 2384
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
	unsigned mask = 0;
	int i;
2385

2386 2387 2388 2389
	for (i = 0; i < dsi->num_lanes_supported; ++i) {
		if (dsi->lanes[i].function != DSI_LANE_UNUSED)
			mask |= 1 << i;
	}
2390

2391
	return mask;
2392 2393
}

2394
static int dsi_cio_init(struct omap_dss_device *dssdev)
T
Tomi Valkeinen 已提交
2395
{
2396
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2397
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2398
	int r;
2399
	u32 l;
T
Tomi Valkeinen 已提交
2400

2401
	DSSDBGF();
T
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2402

2403 2404 2405
	r = dsi->enable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
	if (r)
		return r;
2406

2407
	dsi_enable_scp_clk(dsidev);
2408

T
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2409 2410 2411
	/* A dummy read using the SCP interface to any DSIPHY register is
	 * required after DSIPHY reset to complete the reset of the DSI complex
	 * I/O. */
2412
	dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
T
Tomi Valkeinen 已提交
2413

2414
	if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2415 2416 2417
		DSSERR("CIO SCP Clock domain not coming out of reset.\n");
		r = -EIO;
		goto err_scp_clk_dom;
T
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2418 2419
	}

2420 2421 2422
	r = dsi_set_lane_config(dssdev);
	if (r)
		goto err_scp_clk_dom;
T
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2423

2424
	/* set TX STOP MODE timer to maximum for this operation */
2425
	l = dsi_read_reg(dsidev, DSI_TIMING1);
2426 2427 2428 2429
	l = FLD_MOD(l, 1, 15, 15);	/* FORCE_TX_STOP_MODE_IO */
	l = FLD_MOD(l, 1, 14, 14);	/* STOP_STATE_X16_IO */
	l = FLD_MOD(l, 1, 13, 13);	/* STOP_STATE_X4_IO */
	l = FLD_MOD(l, 0x1fff, 12, 0);	/* STOP_STATE_COUNTER_IO */
2430
	dsi_write_reg(dsidev, DSI_TIMING1, l);
2431

2432
	if (dsi->ulps_enabled) {
2433 2434
		unsigned mask_p;
		int i;
2435

2436 2437
		DSSDBG("manual ulps exit\n");

2438 2439 2440 2441 2442
		/* ULPS is exited by Mark-1 state for 1ms, followed by
		 * stop state. DSS HW cannot do this via the normal
		 * ULPS exit sequence, as after reset the DSS HW thinks
		 * that we are not in ULPS mode, and refuses to send the
		 * sequence. So we need to send the ULPS exit sequence
2443 2444
		 * manually by setting positive lines high and negative lines
		 * low for 1ms.
2445 2446
		 */

2447
		mask_p = 0;
2448

2449 2450 2451 2452 2453
		for (i = 0; i < dsi->num_lanes_supported; ++i) {
			if (dsi->lanes[i].function == DSI_LANE_UNUSED)
				continue;
			mask_p |= 1 << i;
		}
2454

2455
		dsi_cio_enable_lane_override(dssdev, mask_p, 0);
2456
	}
T
Tomi Valkeinen 已提交
2457

2458
	r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
T
Tomi Valkeinen 已提交
2459
	if (r)
2460 2461
		goto err_cio_pwr;

2462
	if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2463 2464 2465 2466 2467
		DSSERR("CIO PWR clock domain not coming out of reset.\n");
		r = -ENODEV;
		goto err_cio_pwr_dom;
	}

2468 2469 2470
	dsi_if_enable(dsidev, true);
	dsi_if_enable(dsidev, false);
	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
T
Tomi Valkeinen 已提交
2471

2472 2473 2474 2475
	r = dsi_cio_wait_tx_clk_esc_reset(dssdev);
	if (r)
		goto err_tx_clk_esc_rst;

2476
	if (dsi->ulps_enabled) {
2477 2478 2479 2480 2481 2482 2483
		/* Keep Mark-1 state for 1ms (as per DSI spec) */
		ktime_t wait = ns_to_ktime(1000 * 1000);
		set_current_state(TASK_UNINTERRUPTIBLE);
		schedule_hrtimeout(&wait, HRTIMER_MODE_REL);

		/* Disable the override. The lanes should be set to Mark-11
		 * state by the HW */
2484
		dsi_cio_disable_lane_override(dsidev);
2485 2486 2487
	}

	/* FORCE_TX_STOP_MODE_IO */
2488
	REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2489

2490
	dsi_cio_timings(dsidev);
T
Tomi Valkeinen 已提交
2491

2492 2493 2494 2495 2496 2497
	if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
		/* DDR_CLK_ALWAYS_ON */
		REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
			dssdev->panel.dsi_vm_data.ddr_clk_always_on, 13, 13);
	}

2498
	dsi->ulps_enabled = false;
T
Tomi Valkeinen 已提交
2499 2500

	DSSDBG("CIO init done\n");
2501 2502 2503

	return 0;

2504
err_tx_clk_esc_rst:
2505
	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2506
err_cio_pwr_dom:
2507
	dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2508
err_cio_pwr:
2509
	if (dsi->ulps_enabled)
2510
		dsi_cio_disable_lane_override(dsidev);
2511
err_scp_clk_dom:
2512
	dsi_disable_scp_clk(dsidev);
2513
	dsi->disable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
T
Tomi Valkeinen 已提交
2514 2515 2516
	return r;
}

2517
static void dsi_cio_uninit(struct omap_dss_device *dssdev)
T
Tomi Valkeinen 已提交
2518
{
2519
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2520 2521
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

2522 2523 2524
	/* DDR_CLK_ALWAYS_ON */
	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);

2525 2526
	dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
	dsi_disable_scp_clk(dsidev);
2527
	dsi->disable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
T
Tomi Valkeinen 已提交
2528 2529
}

2530 2531
static void dsi_config_tx_fifo(struct platform_device *dsidev,
		enum fifo_size size1, enum fifo_size size2,
T
Tomi Valkeinen 已提交
2532 2533
		enum fifo_size size3, enum fifo_size size4)
{
2534
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
T
Tomi Valkeinen 已提交
2535 2536 2537 2538
	u32 r = 0;
	int add = 0;
	int i;

2539 2540 2541 2542
	dsi->vc[0].fifo_size = size1;
	dsi->vc[1].fifo_size = size2;
	dsi->vc[2].fifo_size = size3;
	dsi->vc[3].fifo_size = size4;
T
Tomi Valkeinen 已提交
2543 2544 2545

	for (i = 0; i < 4; i++) {
		u8 v;
2546
		int size = dsi->vc[i].fifo_size;
T
Tomi Valkeinen 已提交
2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558

		if (add + size > 4) {
			DSSERR("Illegal FIFO configuration\n");
			BUG();
		}

		v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
		r |= v << (8 * i);
		/*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
		add += size;
	}

2559
	dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
T
Tomi Valkeinen 已提交
2560 2561
}

2562 2563
static void dsi_config_rx_fifo(struct platform_device *dsidev,
		enum fifo_size size1, enum fifo_size size2,
T
Tomi Valkeinen 已提交
2564 2565
		enum fifo_size size3, enum fifo_size size4)
{
2566
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
T
Tomi Valkeinen 已提交
2567 2568 2569 2570
	u32 r = 0;
	int add = 0;
	int i;

2571 2572 2573 2574
	dsi->vc[0].fifo_size = size1;
	dsi->vc[1].fifo_size = size2;
	dsi->vc[2].fifo_size = size3;
	dsi->vc[3].fifo_size = size4;
T
Tomi Valkeinen 已提交
2575 2576 2577

	for (i = 0; i < 4; i++) {
		u8 v;
2578
		int size = dsi->vc[i].fifo_size;
T
Tomi Valkeinen 已提交
2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590

		if (add + size > 4) {
			DSSERR("Illegal FIFO configuration\n");
			BUG();
		}

		v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
		r |= v << (8 * i);
		/*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
		add += size;
	}

2591
	dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
T
Tomi Valkeinen 已提交
2592 2593
}

2594
static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
T
Tomi Valkeinen 已提交
2595 2596 2597
{
	u32 r;

2598
	r = dsi_read_reg(dsidev, DSI_TIMING1);
T
Tomi Valkeinen 已提交
2599
	r = FLD_MOD(r, 1, 15, 15);	/* FORCE_TX_STOP_MODE_IO */
2600
	dsi_write_reg(dsidev, DSI_TIMING1, r);
T
Tomi Valkeinen 已提交
2601

2602
	if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
T
Tomi Valkeinen 已提交
2603 2604 2605 2606 2607 2608 2609
		DSSERR("TX_STOP bit not going down\n");
		return -EIO;
	}

	return 0;
}

2610
static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2611
{
2612
	return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2613 2614 2615 2616
}

static void dsi_packet_sent_handler_vp(void *data, u32 mask)
{
2617 2618 2619
	struct dsi_packet_sent_handler_data *vp_data =
		(struct dsi_packet_sent_handler_data *) data;
	struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2620 2621
	const int channel = dsi->update_channel;
	u8 bit = dsi->te_enabled ? 30 : 31;
2622

2623 2624
	if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
		complete(vp_data->completion);
2625 2626
}

2627
static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2628
{
2629
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2630 2631
	DECLARE_COMPLETION_ONSTACK(completion);
	struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion };
2632 2633 2634
	int r = 0;
	u8 bit;

2635
	bit = dsi->te_enabled ? 30 : 31;
2636

2637
	r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2638
		&vp_data, DSI_VC_IRQ_PACKET_SENT);
2639 2640 2641 2642
	if (r)
		goto err0;

	/* Wait for completion only if TE_EN/TE_START is still set */
2643
	if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2644 2645 2646 2647 2648 2649 2650 2651
		if (wait_for_completion_timeout(&completion,
				msecs_to_jiffies(10)) == 0) {
			DSSERR("Failed to complete previous frame transfer\n");
			r = -EIO;
			goto err1;
		}
	}

2652
	dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2653
		&vp_data, DSI_VC_IRQ_PACKET_SENT);
2654 2655 2656

	return 0;
err1:
2657
	dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2658
		&vp_data, DSI_VC_IRQ_PACKET_SENT);
2659 2660 2661 2662 2663 2664
err0:
	return r;
}

static void dsi_packet_sent_handler_l4(void *data, u32 mask)
{
2665 2666 2667
	struct dsi_packet_sent_handler_data *l4_data =
		(struct dsi_packet_sent_handler_data *) data;
	struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2668
	const int channel = dsi->update_channel;
2669

2670 2671
	if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
		complete(l4_data->completion);
2672 2673
}

2674
static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2675 2676
{
	DECLARE_COMPLETION_ONSTACK(completion);
2677 2678
	struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion };
	int r = 0;
2679

2680
	r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2681
		&l4_data, DSI_VC_IRQ_PACKET_SENT);
2682 2683 2684 2685
	if (r)
		goto err0;

	/* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2686
	if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2687 2688 2689 2690 2691 2692 2693 2694
		if (wait_for_completion_timeout(&completion,
				msecs_to_jiffies(10)) == 0) {
			DSSERR("Failed to complete previous l4 transfer\n");
			r = -EIO;
			goto err1;
		}
	}

2695
	dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2696
		&l4_data, DSI_VC_IRQ_PACKET_SENT);
2697 2698 2699

	return 0;
err1:
2700
	dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2701
		&l4_data, DSI_VC_IRQ_PACKET_SENT);
2702 2703 2704 2705
err0:
	return r;
}

2706
static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2707
{
2708 2709
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

2710
	WARN_ON(!dsi_bus_is_locked(dsidev));
2711 2712 2713

	WARN_ON(in_interrupt());

2714
	if (!dsi_vc_is_enabled(dsidev, channel))
2715 2716
		return 0;

2717 2718
	switch (dsi->vc[channel].source) {
	case DSI_VC_SOURCE_VP:
2719
		return dsi_sync_vc_vp(dsidev, channel);
2720
	case DSI_VC_SOURCE_L4:
2721
		return dsi_sync_vc_l4(dsidev, channel);
2722 2723 2724 2725 2726
	default:
		BUG();
	}
}

2727 2728
static int dsi_vc_enable(struct platform_device *dsidev, int channel,
		bool enable)
T
Tomi Valkeinen 已提交
2729
{
2730 2731
	DSSDBG("dsi_vc_enable channel %d, enable %d\n",
			channel, enable);
T
Tomi Valkeinen 已提交
2732 2733 2734

	enable = enable ? 1 : 0;

2735
	REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
T
Tomi Valkeinen 已提交
2736

2737 2738
	if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
		0, enable) != enable) {
T
Tomi Valkeinen 已提交
2739 2740 2741 2742 2743 2744 2745
			DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
			return -EIO;
	}

	return 0;
}

2746
static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
T
Tomi Valkeinen 已提交
2747 2748 2749 2750 2751
{
	u32 r;

	DSSDBGF("%d", channel);

2752
	r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
T
Tomi Valkeinen 已提交
2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764

	if (FLD_GET(r, 15, 15)) /* VC_BUSY */
		DSSERR("VC(%d) busy when trying to configure it!\n",
				channel);

	r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
	r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN  */
	r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
	r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
	r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
	r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
	r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2765 2766
	if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
		r = FLD_MOD(r, 3, 11, 10);	/* OCP_WIDTH = 32 bit */
T
Tomi Valkeinen 已提交
2767 2768 2769 2770

	r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
	r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */

2771
	dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
T
Tomi Valkeinen 已提交
2772 2773
}

2774 2775
static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
		enum dsi_vc_source source)
T
Tomi Valkeinen 已提交
2776
{
2777 2778
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

2779
	if (dsi->vc[channel].source == source)
2780
		return 0;
T
Tomi Valkeinen 已提交
2781 2782 2783

	DSSDBGF("%d", channel);

2784
	dsi_sync_vc(dsidev, channel);
2785

2786
	dsi_vc_enable(dsidev, channel, 0);
T
Tomi Valkeinen 已提交
2787

2788
	/* VC_BUSY */
2789
	if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
T
Tomi Valkeinen 已提交
2790
		DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2791 2792
		return -EIO;
	}
T
Tomi Valkeinen 已提交
2793

2794 2795
	/* SOURCE, 0 = L4, 1 = video port */
	REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
T
Tomi Valkeinen 已提交
2796

2797
	/* DCS_CMD_ENABLE */
2798 2799 2800 2801
	if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
		bool enable = source == DSI_VC_SOURCE_VP;
		REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
	}
2802

2803
	dsi_vc_enable(dsidev, channel, 1);
T
Tomi Valkeinen 已提交
2804

2805
	dsi->vc[channel].source = source;
2806 2807

	return 0;
T
Tomi Valkeinen 已提交
2808 2809
}

2810 2811
void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
		bool enable)
T
Tomi Valkeinen 已提交
2812
{
2813 2814
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);

T
Tomi Valkeinen 已提交
2815 2816
	DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);

2817
	WARN_ON(!dsi_bus_is_locked(dsidev));
2818

2819 2820
	dsi_vc_enable(dsidev, channel, 0);
	dsi_if_enable(dsidev, 0);
T
Tomi Valkeinen 已提交
2821

2822
	REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
T
Tomi Valkeinen 已提交
2823

2824 2825
	dsi_vc_enable(dsidev, channel, 1);
	dsi_if_enable(dsidev, 1);
T
Tomi Valkeinen 已提交
2826

2827
	dsi_force_tx_stop_mode_io(dsidev);
2828 2829 2830 2831

	/* start the DDR clock by sending a NULL packet */
	if (dssdev->panel.dsi_vm_data.ddr_clk_always_on && enable)
		dsi_vc_send_null(dssdev, channel);
T
Tomi Valkeinen 已提交
2832
}
2833
EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
T
Tomi Valkeinen 已提交
2834

2835
static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
T
Tomi Valkeinen 已提交
2836
{
2837
	while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
T
Tomi Valkeinen 已提交
2838
		u32 val;
2839
		val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
T
Tomi Valkeinen 已提交
2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884
		DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
				(val >> 0) & 0xff,
				(val >> 8) & 0xff,
				(val >> 16) & 0xff,
				(val >> 24) & 0xff);
	}
}

static void dsi_show_rx_ack_with_err(u16 err)
{
	DSSERR("\tACK with ERROR (%#x):\n", err);
	if (err & (1 << 0))
		DSSERR("\t\tSoT Error\n");
	if (err & (1 << 1))
		DSSERR("\t\tSoT Sync Error\n");
	if (err & (1 << 2))
		DSSERR("\t\tEoT Sync Error\n");
	if (err & (1 << 3))
		DSSERR("\t\tEscape Mode Entry Command Error\n");
	if (err & (1 << 4))
		DSSERR("\t\tLP Transmit Sync Error\n");
	if (err & (1 << 5))
		DSSERR("\t\tHS Receive Timeout Error\n");
	if (err & (1 << 6))
		DSSERR("\t\tFalse Control Error\n");
	if (err & (1 << 7))
		DSSERR("\t\t(reserved7)\n");
	if (err & (1 << 8))
		DSSERR("\t\tECC Error, single-bit (corrected)\n");
	if (err & (1 << 9))
		DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
	if (err & (1 << 10))
		DSSERR("\t\tChecksum Error\n");
	if (err & (1 << 11))
		DSSERR("\t\tData type not recognized\n");
	if (err & (1 << 12))
		DSSERR("\t\tInvalid VC ID\n");
	if (err & (1 << 13))
		DSSERR("\t\tInvalid Transmission Length\n");
	if (err & (1 << 14))
		DSSERR("\t\t(reserved14)\n");
	if (err & (1 << 15))
		DSSERR("\t\tDSI Protocol Violation\n");
}

2885 2886
static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
		int channel)
T
Tomi Valkeinen 已提交
2887 2888
{
	/* RX_FIFO_NOT_EMPTY */
2889
	while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
T
Tomi Valkeinen 已提交
2890 2891
		u32 val;
		u8 dt;
2892
		val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2893
		DSSERR("\trawval %#08x\n", val);
T
Tomi Valkeinen 已提交
2894
		dt = FLD_GET(val, 5, 0);
2895
		if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
T
Tomi Valkeinen 已提交
2896 2897
			u16 err = FLD_GET(val, 23, 8);
			dsi_show_rx_ack_with_err(err);
2898
		} else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2899
			DSSERR("\tDCS short response, 1 byte: %#x\n",
T
Tomi Valkeinen 已提交
2900
					FLD_GET(val, 23, 8));
2901
		} else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2902
			DSSERR("\tDCS short response, 2 byte: %#x\n",
T
Tomi Valkeinen 已提交
2903
					FLD_GET(val, 23, 8));
2904
		} else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2905
			DSSERR("\tDCS long response, len %d\n",
T
Tomi Valkeinen 已提交
2906
					FLD_GET(val, 23, 8));
2907
			dsi_vc_flush_long_data(dsidev, channel);
T
Tomi Valkeinen 已提交
2908 2909 2910 2911 2912 2913 2914
		} else {
			DSSERR("\tunknown datatype 0x%02x\n", dt);
		}
	}
	return 0;
}

2915
static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
T
Tomi Valkeinen 已提交
2916
{
2917 2918 2919
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	if (dsi->debug_write || dsi->debug_read)
T
Tomi Valkeinen 已提交
2920 2921
		DSSDBG("dsi_vc_send_bta %d\n", channel);

2922
	WARN_ON(!dsi_bus_is_locked(dsidev));
T
Tomi Valkeinen 已提交
2923

2924 2925
	/* RX_FIFO_NOT_EMPTY */
	if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
T
Tomi Valkeinen 已提交
2926
		DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2927
		dsi_vc_flush_receive_data(dsidev, channel);
T
Tomi Valkeinen 已提交
2928 2929
	}

2930
	REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
T
Tomi Valkeinen 已提交
2931

2932 2933 2934
	/* flush posted write */
	dsi_read_reg(dsidev, DSI_VC_CTRL(channel));

T
Tomi Valkeinen 已提交
2935 2936 2937
	return 0;
}

2938
int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
T
Tomi Valkeinen 已提交
2939
{
2940
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2941
	DECLARE_COMPLETION_ONSTACK(completion);
T
Tomi Valkeinen 已提交
2942 2943 2944
	int r = 0;
	u32 err;

2945
	r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2946 2947 2948
			&completion, DSI_VC_IRQ_BTA);
	if (r)
		goto err0;
T
Tomi Valkeinen 已提交
2949

2950
	r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2951
			DSI_IRQ_ERROR_MASK);
T
Tomi Valkeinen 已提交
2952
	if (r)
2953
		goto err1;
T
Tomi Valkeinen 已提交
2954

2955
	r = dsi_vc_send_bta(dsidev, channel);
2956 2957 2958
	if (r)
		goto err2;

2959
	if (wait_for_completion_timeout(&completion,
T
Tomi Valkeinen 已提交
2960 2961 2962
				msecs_to_jiffies(500)) == 0) {
		DSSERR("Failed to receive BTA\n");
		r = -EIO;
2963
		goto err2;
T
Tomi Valkeinen 已提交
2964 2965
	}

2966
	err = dsi_get_errors(dsidev);
T
Tomi Valkeinen 已提交
2967 2968 2969
	if (err) {
		DSSERR("Error while sending BTA: %x\n", err);
		r = -EIO;
2970
		goto err2;
T
Tomi Valkeinen 已提交
2971
	}
2972
err2:
2973
	dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
2974
			DSI_IRQ_ERROR_MASK);
2975
err1:
2976
	dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
2977 2978
			&completion, DSI_VC_IRQ_BTA);
err0:
T
Tomi Valkeinen 已提交
2979 2980 2981 2982
	return r;
}
EXPORT_SYMBOL(dsi_vc_send_bta_sync);

2983 2984
static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
		int channel, u8 data_type, u16 len, u8 ecc)
T
Tomi Valkeinen 已提交
2985
{
2986
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
T
Tomi Valkeinen 已提交
2987 2988 2989
	u32 val;
	u8 data_id;

2990
	WARN_ON(!dsi_bus_is_locked(dsidev));
T
Tomi Valkeinen 已提交
2991

2992
	data_id = data_type | dsi->vc[channel].vc_id << 6;
T
Tomi Valkeinen 已提交
2993 2994 2995 2996

	val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
		FLD_VAL(ecc, 31, 24);

2997
	dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
T
Tomi Valkeinen 已提交
2998 2999
}

3000 3001
static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
		int channel, u8 b1, u8 b2, u8 b3, u8 b4)
T
Tomi Valkeinen 已提交
3002 3003 3004 3005 3006 3007 3008 3009
{
	u32 val;

	val = b4 << 24 | b3 << 16 | b2 << 8  | b1 << 0;

/*	DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
			b1, b2, b3, b4, val); */

3010
	dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
T
Tomi Valkeinen 已提交
3011 3012
}

3013 3014
static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
		u8 data_type, u8 *data, u16 len, u8 ecc)
T
Tomi Valkeinen 已提交
3015 3016
{
	/*u32 val; */
3017
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
T
Tomi Valkeinen 已提交
3018 3019 3020 3021 3022
	int i;
	u8 *p;
	int r = 0;
	u8 b1, b2, b3, b4;

3023
	if (dsi->debug_write)
T
Tomi Valkeinen 已提交
3024 3025 3026
		DSSDBG("dsi_vc_send_long, %d bytes\n", len);

	/* len + header */
3027
	if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) {
T
Tomi Valkeinen 已提交
3028 3029 3030 3031
		DSSERR("unable to send long packet: packet too long.\n");
		return -EINVAL;
	}

3032
	dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
T
Tomi Valkeinen 已提交
3033

3034
	dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
T
Tomi Valkeinen 已提交
3035 3036 3037

	p = data;
	for (i = 0; i < len >> 2; i++) {
3038
		if (dsi->debug_write)
T
Tomi Valkeinen 已提交
3039 3040 3041 3042 3043 3044 3045
			DSSDBG("\tsending full packet %d\n", i);

		b1 = *p++;
		b2 = *p++;
		b3 = *p++;
		b4 = *p++;

3046
		dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
T
Tomi Valkeinen 已提交
3047 3048 3049 3050 3051 3052
	}

	i = len % 4;
	if (i) {
		b1 = 0; b2 = 0; b3 = 0;

3053
		if (dsi->debug_write)
T
Tomi Valkeinen 已提交
3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070
			DSSDBG("\tsending remainder bytes %d\n", i);

		switch (i) {
		case 3:
			b1 = *p++;
			b2 = *p++;
			b3 = *p++;
			break;
		case 2:
			b1 = *p++;
			b2 = *p++;
			break;
		case 1:
			b1 = *p++;
			break;
		}

3071
		dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
T
Tomi Valkeinen 已提交
3072 3073 3074 3075 3076
	}

	return r;
}

3077 3078
static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
		u8 data_type, u16 data, u8 ecc)
T
Tomi Valkeinen 已提交
3079
{
3080
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
T
Tomi Valkeinen 已提交
3081 3082 3083
	u32 r;
	u8 data_id;

3084
	WARN_ON(!dsi_bus_is_locked(dsidev));
T
Tomi Valkeinen 已提交
3085

3086
	if (dsi->debug_write)
T
Tomi Valkeinen 已提交
3087 3088 3089 3090
		DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
				channel,
				data_type, data & 0xff, (data >> 8) & 0xff);

3091
	dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
T
Tomi Valkeinen 已提交
3092

3093
	if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
T
Tomi Valkeinen 已提交
3094 3095 3096 3097
		DSSERR("ERROR FIFO FULL, aborting transfer\n");
		return -EINVAL;
	}

3098
	data_id = data_type | dsi->vc[channel].vc_id << 6;
T
Tomi Valkeinen 已提交
3099 3100 3101

	r = (data_id << 0) | (data << 8) | (ecc << 24);

3102
	dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
T
Tomi Valkeinen 已提交
3103 3104 3105 3106

	return 0;
}

3107
int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
T
Tomi Valkeinen 已提交
3108
{
3109 3110
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);

3111 3112
	return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
		0, 0);
T
Tomi Valkeinen 已提交
3113 3114 3115
}
EXPORT_SYMBOL(dsi_vc_send_null);

3116 3117
static int dsi_vc_write_nosync_common(struct omap_dss_device *dssdev,
		int channel, u8 *data, int len, enum dss_dsi_content_type type)
T
Tomi Valkeinen 已提交
3118
{
3119
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
T
Tomi Valkeinen 已提交
3120 3121
	int r;

3122 3123
	if (len == 0) {
		BUG_ON(type == DSS_DSI_CONTENT_DCS);
3124
		r = dsi_vc_send_short(dsidev, channel,
3125 3126 3127 3128 3129
				MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
	} else if (len == 1) {
		r = dsi_vc_send_short(dsidev, channel,
				type == DSS_DSI_CONTENT_GENERIC ?
				MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
3130
				MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
T
Tomi Valkeinen 已提交
3131
	} else if (len == 2) {
3132
		r = dsi_vc_send_short(dsidev, channel,
3133 3134
				type == DSS_DSI_CONTENT_GENERIC ?
				MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
3135
				MIPI_DSI_DCS_SHORT_WRITE_PARAM,
T
Tomi Valkeinen 已提交
3136 3137
				data[0] | (data[1] << 8), 0);
	} else {
3138 3139 3140 3141
		r = dsi_vc_send_long(dsidev, channel,
				type == DSS_DSI_CONTENT_GENERIC ?
				MIPI_DSI_GENERIC_LONG_WRITE :
				MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
T
Tomi Valkeinen 已提交
3142 3143 3144 3145
	}

	return r;
}
3146 3147 3148 3149 3150 3151 3152

int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
		u8 *data, int len)
{
	return dsi_vc_write_nosync_common(dssdev, channel, data, len,
			DSS_DSI_CONTENT_DCS);
}
T
Tomi Valkeinen 已提交
3153 3154
EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);

3155 3156 3157 3158 3159 3160 3161 3162 3163 3164
int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
		u8 *data, int len)
{
	return dsi_vc_write_nosync_common(dssdev, channel, data, len,
			DSS_DSI_CONTENT_GENERIC);
}
EXPORT_SYMBOL(dsi_vc_generic_write_nosync);

static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
		u8 *data, int len, enum dss_dsi_content_type type)
T
Tomi Valkeinen 已提交
3165
{
3166
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
T
Tomi Valkeinen 已提交
3167 3168
	int r;

3169
	r = dsi_vc_write_nosync_common(dssdev, channel, data, len, type);
T
Tomi Valkeinen 已提交
3170
	if (r)
3171
		goto err;
T
Tomi Valkeinen 已提交
3172

3173
	r = dsi_vc_send_bta_sync(dssdev, channel);
3174 3175
	if (r)
		goto err;
T
Tomi Valkeinen 已提交
3176

3177 3178
	/* RX_FIFO_NOT_EMPTY */
	if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
3179
		DSSERR("rx fifo not empty after write, dumping data:\n");
3180
		dsi_vc_flush_receive_data(dsidev, channel);
3181 3182 3183 3184
		r = -EIO;
		goto err;
	}

3185 3186
	return 0;
err:
3187
	DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
3188
			channel, data[0], len);
T
Tomi Valkeinen 已提交
3189 3190
	return r;
}
3191 3192 3193 3194 3195 3196 3197

int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
		int len)
{
	return dsi_vc_write_common(dssdev, channel, data, len,
			DSS_DSI_CONTENT_DCS);
}
T
Tomi Valkeinen 已提交
3198 3199
EXPORT_SYMBOL(dsi_vc_dcs_write);

3200 3201 3202 3203 3204 3205 3206 3207
int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
		int len)
{
	return dsi_vc_write_common(dssdev, channel, data, len,
			DSS_DSI_CONTENT_GENERIC);
}
EXPORT_SYMBOL(dsi_vc_generic_write);

3208
int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd)
3209
{
3210
	return dsi_vc_dcs_write(dssdev, channel, &dcs_cmd, 1);
3211 3212 3213
}
EXPORT_SYMBOL(dsi_vc_dcs_write_0);

3214 3215 3216 3217 3218 3219
int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel)
{
	return dsi_vc_generic_write(dssdev, channel, NULL, 0);
}
EXPORT_SYMBOL(dsi_vc_generic_write_0);

3220 3221
int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
		u8 param)
3222 3223 3224 3225
{
	u8 buf[2];
	buf[0] = dcs_cmd;
	buf[1] = param;
3226
	return dsi_vc_dcs_write(dssdev, channel, buf, 2);
3227 3228 3229
}
EXPORT_SYMBOL(dsi_vc_dcs_write_1);

3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246
int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
		u8 param)
{
	return dsi_vc_generic_write(dssdev, channel, &param, 1);
}
EXPORT_SYMBOL(dsi_vc_generic_write_1);

int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
		u8 param1, u8 param2)
{
	u8 buf[2];
	buf[0] = param1;
	buf[1] = param2;
	return dsi_vc_generic_write(dssdev, channel, buf, 2);
}
EXPORT_SYMBOL(dsi_vc_generic_write_2);

3247 3248
static int dsi_vc_dcs_send_read_request(struct omap_dss_device *dssdev,
		int channel, u8 dcs_cmd)
T
Tomi Valkeinen 已提交
3249
{
3250
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3251
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
T
Tomi Valkeinen 已提交
3252 3253
	int r;

3254
	if (dsi->debug_read)
3255 3256
		DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
			channel, dcs_cmd);
T
Tomi Valkeinen 已提交
3257

3258
	r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
3259 3260 3261 3262 3263
	if (r) {
		DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
			" failed\n", channel, dcs_cmd);
		return r;
	}
T
Tomi Valkeinen 已提交
3264

3265 3266 3267
	return 0;
}

3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305
static int dsi_vc_generic_send_read_request(struct omap_dss_device *dssdev,
		int channel, u8 *reqdata, int reqlen)
{
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
	u16 data;
	u8 data_type;
	int r;

	if (dsi->debug_read)
		DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
			channel, reqlen);

	if (reqlen == 0) {
		data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
		data = 0;
	} else if (reqlen == 1) {
		data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
		data = reqdata[0];
	} else if (reqlen == 2) {
		data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
		data = reqdata[0] | (reqdata[1] << 8);
	} else {
		BUG();
	}

	r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
	if (r) {
		DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
			" failed\n", channel, reqlen);
		return r;
	}

	return 0;
}

static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
		u8 *buf, int buflen, enum dss_dsi_content_type type)
3306 3307 3308 3309 3310
{
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
	u32 val;
	u8 dt;
	int r;
T
Tomi Valkeinen 已提交
3311 3312

	/* RX_FIFO_NOT_EMPTY */
3313
	if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
T
Tomi Valkeinen 已提交
3314
		DSSERR("RX fifo empty when trying to read.\n");
3315 3316
		r = -EIO;
		goto err;
T
Tomi Valkeinen 已提交
3317 3318
	}

3319
	val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
3320
	if (dsi->debug_read)
T
Tomi Valkeinen 已提交
3321 3322
		DSSDBG("\theader: %08x\n", val);
	dt = FLD_GET(val, 5, 0);
3323
	if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
T
Tomi Valkeinen 已提交
3324 3325
		u16 err = FLD_GET(val, 23, 8);
		dsi_show_rx_ack_with_err(err);
3326 3327
		r = -EIO;
		goto err;
T
Tomi Valkeinen 已提交
3328

3329 3330 3331
	} else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
			MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
			MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
T
Tomi Valkeinen 已提交
3332
		u8 data = FLD_GET(val, 15, 8);
3333
		if (dsi->debug_read)
3334 3335 3336
			DSSDBG("\t%s short response, 1 byte: %02x\n",
				type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
				"DCS", data);
T
Tomi Valkeinen 已提交
3337

3338 3339 3340 3341
		if (buflen < 1) {
			r = -EIO;
			goto err;
		}
T
Tomi Valkeinen 已提交
3342 3343 3344 3345

		buf[0] = data;

		return 1;
3346 3347 3348
	} else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
			MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
			MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
T
Tomi Valkeinen 已提交
3349
		u16 data = FLD_GET(val, 23, 8);
3350
		if (dsi->debug_read)
3351 3352 3353
			DSSDBG("\t%s short response, 2 byte: %04x\n",
				type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
				"DCS", data);
T
Tomi Valkeinen 已提交
3354

3355 3356 3357 3358
		if (buflen < 2) {
			r = -EIO;
			goto err;
		}
T
Tomi Valkeinen 已提交
3359 3360 3361 3362 3363

		buf[0] = data & 0xff;
		buf[1] = (data >> 8) & 0xff;

		return 2;
3364 3365 3366
	} else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
			MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
			MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
T
Tomi Valkeinen 已提交
3367 3368
		int w;
		int len = FLD_GET(val, 23, 8);
3369
		if (dsi->debug_read)
3370 3371 3372
			DSSDBG("\t%s long response, len %d\n",
				type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
				"DCS", len);
T
Tomi Valkeinen 已提交
3373

3374 3375 3376 3377
		if (len > buflen) {
			r = -EIO;
			goto err;
		}
T
Tomi Valkeinen 已提交
3378 3379 3380 3381

		/* two byte checksum ends the packet, not included in len */
		for (w = 0; w < len + 2;) {
			int b;
3382 3383
			val = dsi_read_reg(dsidev,
				DSI_VC_SHORT_PACKET_HEADER(channel));
3384
			if (dsi->debug_read)
T
Tomi Valkeinen 已提交
3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396 3397 3398 3399 3400 3401
				DSSDBG("\t\t%02x %02x %02x %02x\n",
						(val >> 0) & 0xff,
						(val >> 8) & 0xff,
						(val >> 16) & 0xff,
						(val >> 24) & 0xff);

			for (b = 0; b < 4; ++b) {
				if (w < len)
					buf[w] = (val >> (b * 8)) & 0xff;
				/* we discard the 2 byte checksum */
				++w;
			}
		}

		return len;
	} else {
		DSSERR("\tunknown datatype 0x%02x\n", dt);
3402 3403
		r = -EIO;
		goto err;
T
Tomi Valkeinen 已提交
3404
	}
3405 3406 3407

	BUG();
err:
3408 3409
	DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
		type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3410

3411
	return r;
3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422
}

int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
		u8 *buf, int buflen)
{
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
	int r;

	r = dsi_vc_dcs_send_read_request(dssdev, channel, dcs_cmd);
	if (r)
		goto err;
3423

3424 3425 3426 3427
	r = dsi_vc_send_bta_sync(dssdev, channel);
	if (r)
		goto err;

3428 3429
	r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
		DSS_DSI_CONTENT_DCS);
3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441
	if (r < 0)
		goto err;

	if (r != buflen) {
		r = -EIO;
		goto err;
	}

	return 0;
err:
	DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
	return r;
T
Tomi Valkeinen 已提交
3442 3443 3444
}
EXPORT_SYMBOL(dsi_vc_dcs_read);

3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520
static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
		u8 *reqdata, int reqlen, u8 *buf, int buflen)
{
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
	int r;

	r = dsi_vc_generic_send_read_request(dssdev, channel, reqdata, reqlen);
	if (r)
		return r;

	r = dsi_vc_send_bta_sync(dssdev, channel);
	if (r)
		return r;

	r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
		DSS_DSI_CONTENT_GENERIC);
	if (r < 0)
		return r;

	if (r != buflen) {
		r = -EIO;
		return r;
	}

	return 0;
}

int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
		int buflen)
{
	int r;

	r = dsi_vc_generic_read(dssdev, channel, NULL, 0, buf, buflen);
	if (r) {
		DSSERR("dsi_vc_generic_read_0(ch %d) failed\n", channel);
		return r;
	}

	return 0;
}
EXPORT_SYMBOL(dsi_vc_generic_read_0);

int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
		u8 *buf, int buflen)
{
	int r;

	r = dsi_vc_generic_read(dssdev, channel, &param, 1, buf, buflen);
	if (r) {
		DSSERR("dsi_vc_generic_read_1(ch %d) failed\n", channel);
		return r;
	}

	return 0;
}
EXPORT_SYMBOL(dsi_vc_generic_read_1);

int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
		u8 param1, u8 param2, u8 *buf, int buflen)
{
	int r;
	u8 reqdata[2];

	reqdata[0] = param1;
	reqdata[1] = param2;

	r = dsi_vc_generic_read(dssdev, channel, reqdata, 2, buf, buflen);
	if (r) {
		DSSERR("dsi_vc_generic_read_2(ch %d) failed\n", channel);
		return r;
	}

	return 0;
}
EXPORT_SYMBOL(dsi_vc_generic_read_2);

3521 3522
int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
		u16 len)
T
Tomi Valkeinen 已提交
3523
{
3524 3525
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);

3526 3527
	return dsi_vc_send_short(dsidev, channel,
			MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
T
Tomi Valkeinen 已提交
3528 3529 3530
}
EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);

3531
static int dsi_enter_ulps(struct platform_device *dsidev)
3532
{
3533
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3534
	DECLARE_COMPLETION_ONSTACK(completion);
3535 3536
	int r, i;
	unsigned mask;
3537 3538 3539

	DSSDBGF();

3540
	WARN_ON(!dsi_bus_is_locked(dsidev));
3541

3542
	WARN_ON(dsi->ulps_enabled);
3543

3544
	if (dsi->ulps_enabled)
3545 3546
		return 0;

3547
	if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3548 3549 3550 3551
		DSSERR("DDR_CLK_ALWAYS_ON enabled when entering ULPS\n");
		return -EIO;
	}

3552 3553 3554 3555
	dsi_sync_vc(dsidev, 0);
	dsi_sync_vc(dsidev, 1);
	dsi_sync_vc(dsidev, 2);
	dsi_sync_vc(dsidev, 3);
3556

3557
	dsi_force_tx_stop_mode_io(dsidev);
3558

3559 3560 3561 3562
	dsi_vc_enable(dsidev, 0, false);
	dsi_vc_enable(dsidev, 1, false);
	dsi_vc_enable(dsidev, 2, false);
	dsi_vc_enable(dsidev, 3, false);
3563

3564
	if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) {	/* HS_BUSY */
3565 3566 3567 3568
		DSSERR("HS busy when enabling ULPS\n");
		return -EIO;
	}

3569
	if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) {	/* LP_BUSY */
3570 3571 3572 3573
		DSSERR("LP busy when enabling ULPS\n");
		return -EIO;
	}

3574
	r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3575 3576 3577 3578
			DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
	if (r)
		return r;

3579 3580 3581 3582 3583 3584 3585
	mask = 0;

	for (i = 0; i < dsi->num_lanes_supported; ++i) {
		if (dsi->lanes[i].function == DSI_LANE_UNUSED)
			continue;
		mask |= 1 << i;
	}
3586 3587
	/* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
	/* LANEx_ULPS_SIG2 */
3588
	REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5);
3589

3590 3591 3592
	/* flush posted write and wait for SCP interface to finish the write */
	dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);

3593 3594 3595 3596 3597 3598 3599
	if (wait_for_completion_timeout(&completion,
				msecs_to_jiffies(1000)) == 0) {
		DSSERR("ULPS enable timeout\n");
		r = -EIO;
		goto err;
	}

3600
	dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3601 3602
			DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);

3603
	/* Reset LANEx_ULPS_SIG2 */
3604
	REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5);
3605

3606 3607 3608
	/* flush posted write and wait for SCP interface to finish the write */
	dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);

3609
	dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3610

3611
	dsi_if_enable(dsidev, false);
3612

3613
	dsi->ulps_enabled = true;
3614 3615 3616 3617

	return 0;

err:
3618
	dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3619 3620 3621 3622
			DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
	return r;
}

3623 3624
static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
		unsigned ticks, bool x4, bool x16)
T
Tomi Valkeinen 已提交
3625 3626
{
	unsigned long fck;
3627 3628
	unsigned long total_ticks;
	u32 r;
T
Tomi Valkeinen 已提交
3629

3630
	BUG_ON(ticks > 0x1fff);
T
Tomi Valkeinen 已提交
3631

3632
	/* ticks in DSI_FCK */
3633
	fck = dsi_fclk_rate(dsidev);
T
Tomi Valkeinen 已提交
3634

3635
	r = dsi_read_reg(dsidev, DSI_TIMING2);
T
Tomi Valkeinen 已提交
3636
	r = FLD_MOD(r, 1, 15, 15);	/* LP_RX_TO */
3637 3638
	r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);	/* LP_RX_TO_X16 */
	r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);	/* LP_RX_TO_X4 */
T
Tomi Valkeinen 已提交
3639
	r = FLD_MOD(r, ticks, 12, 0);	/* LP_RX_COUNTER */
3640
	dsi_write_reg(dsidev, DSI_TIMING2, r);
T
Tomi Valkeinen 已提交
3641

3642 3643 3644 3645 3646 3647
	total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);

	DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
			total_ticks,
			ticks, x4 ? " x4" : "", x16 ? " x16" : "",
			(total_ticks * 1000) / (fck / 1000 / 1000));
T
Tomi Valkeinen 已提交
3648 3649
}

3650 3651
static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
		bool x8, bool x16)
T
Tomi Valkeinen 已提交
3652 3653
{
	unsigned long fck;
3654 3655 3656 3657
	unsigned long total_ticks;
	u32 r;

	BUG_ON(ticks > 0x1fff);
T
Tomi Valkeinen 已提交
3658 3659

	/* ticks in DSI_FCK */
3660
	fck = dsi_fclk_rate(dsidev);
T
Tomi Valkeinen 已提交
3661

3662
	r = dsi_read_reg(dsidev, DSI_TIMING1);
T
Tomi Valkeinen 已提交
3663
	r = FLD_MOD(r, 1, 31, 31);	/* TA_TO */
3664 3665
	r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);	/* TA_TO_X16 */
	r = FLD_MOD(r, x8 ? 1 : 0, 29, 29);	/* TA_TO_X8 */
T
Tomi Valkeinen 已提交
3666
	r = FLD_MOD(r, ticks, 28, 16);	/* TA_TO_COUNTER */
3667
	dsi_write_reg(dsidev, DSI_TIMING1, r);
T
Tomi Valkeinen 已提交
3668

3669 3670 3671 3672 3673 3674
	total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);

	DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
			total_ticks,
			ticks, x8 ? " x8" : "", x16 ? " x16" : "",
			(total_ticks * 1000) / (fck / 1000 / 1000));
T
Tomi Valkeinen 已提交
3675 3676
}

3677 3678
static void dsi_set_stop_state_counter(struct platform_device *dsidev,
		unsigned ticks, bool x4, bool x16)
T
Tomi Valkeinen 已提交
3679 3680
{
	unsigned long fck;
3681 3682
	unsigned long total_ticks;
	u32 r;
T
Tomi Valkeinen 已提交
3683

3684
	BUG_ON(ticks > 0x1fff);
T
Tomi Valkeinen 已提交
3685

3686
	/* ticks in DSI_FCK */
3687
	fck = dsi_fclk_rate(dsidev);
T
Tomi Valkeinen 已提交
3688

3689
	r = dsi_read_reg(dsidev, DSI_TIMING1);
T
Tomi Valkeinen 已提交
3690
	r = FLD_MOD(r, 1, 15, 15);	/* FORCE_TX_STOP_MODE_IO */
3691 3692
	r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);	/* STOP_STATE_X16_IO */
	r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);	/* STOP_STATE_X4_IO */
T
Tomi Valkeinen 已提交
3693
	r = FLD_MOD(r, ticks, 12, 0);	/* STOP_STATE_COUNTER_IO */
3694
	dsi_write_reg(dsidev, DSI_TIMING1, r);
T
Tomi Valkeinen 已提交
3695

3696 3697 3698 3699 3700 3701
	total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);

	DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
			total_ticks,
			ticks, x4 ? " x4" : "", x16 ? " x16" : "",
			(total_ticks * 1000) / (fck / 1000 / 1000));
T
Tomi Valkeinen 已提交
3702 3703
}

3704 3705
static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
		unsigned ticks, bool x4, bool x16)
T
Tomi Valkeinen 已提交
3706 3707
{
	unsigned long fck;
3708 3709
	unsigned long total_ticks;
	u32 r;
T
Tomi Valkeinen 已提交
3710

3711
	BUG_ON(ticks > 0x1fff);
T
Tomi Valkeinen 已提交
3712

3713
	/* ticks in TxByteClkHS */
3714
	fck = dsi_get_txbyteclkhs(dsidev);
T
Tomi Valkeinen 已提交
3715

3716
	r = dsi_read_reg(dsidev, DSI_TIMING2);
T
Tomi Valkeinen 已提交
3717
	r = FLD_MOD(r, 1, 31, 31);	/* HS_TX_TO */
3718 3719
	r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);	/* HS_TX_TO_X16 */
	r = FLD_MOD(r, x4 ? 1 : 0, 29, 29);	/* HS_TX_TO_X8 (4 really) */
T
Tomi Valkeinen 已提交
3720
	r = FLD_MOD(r, ticks, 28, 16);	/* HS_TX_TO_COUNTER */
3721
	dsi_write_reg(dsidev, DSI_TIMING2, r);
T
Tomi Valkeinen 已提交
3722

3723 3724 3725 3726 3727 3728
	total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);

	DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
			total_ticks,
			ticks, x4 ? " x4" : "", x16 ? " x16" : "",
			(total_ticks * 1000) / (fck / 1000 / 1000));
T
Tomi Valkeinen 已提交
3729
}
3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741 3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790 3791 3792 3793 3794 3795 3796 3797 3798

static void dsi_config_vp_num_line_buffers(struct omap_dss_device *dssdev)
{
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
	int num_line_buffers;

	if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
		int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
		unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
		struct omap_video_timings *timings = &dssdev->panel.timings;
		/*
		 * Don't use line buffers if width is greater than the video
		 * port's line buffer size
		 */
		if (line_buf_size <= timings->x_res * bpp / 8)
			num_line_buffers = 0;
		else
			num_line_buffers = 2;
	} else {
		/* Use maximum number of line buffers in command mode */
		num_line_buffers = 2;
	}

	/* LINE_BUFFER */
	REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
}

static void dsi_config_vp_sync_events(struct omap_dss_device *dssdev)
{
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
	int de_pol = dssdev->panel.dsi_vm_data.vp_de_pol;
	int hsync_pol = dssdev->panel.dsi_vm_data.vp_hsync_pol;
	int vsync_pol = dssdev->panel.dsi_vm_data.vp_vsync_pol;
	bool vsync_end = dssdev->panel.dsi_vm_data.vp_vsync_end;
	bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
	u32 r;

	r = dsi_read_reg(dsidev, DSI_CTRL);
	r = FLD_MOD(r, de_pol, 9, 9);		/* VP_DE_POL */
	r = FLD_MOD(r, hsync_pol, 10, 10);	/* VP_HSYNC_POL */
	r = FLD_MOD(r, vsync_pol, 11, 11);	/* VP_VSYNC_POL */
	r = FLD_MOD(r, 1, 15, 15);		/* VP_VSYNC_START */
	r = FLD_MOD(r, vsync_end, 16, 16);	/* VP_VSYNC_END */
	r = FLD_MOD(r, 1, 17, 17);		/* VP_HSYNC_START */
	r = FLD_MOD(r, hsync_end, 18, 18);	/* VP_HSYNC_END */
	dsi_write_reg(dsidev, DSI_CTRL, r);
}

static void dsi_config_blanking_modes(struct omap_dss_device *dssdev)
{
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
	int blanking_mode = dssdev->panel.dsi_vm_data.blanking_mode;
	int hfp_blanking_mode = dssdev->panel.dsi_vm_data.hfp_blanking_mode;
	int hbp_blanking_mode = dssdev->panel.dsi_vm_data.hbp_blanking_mode;
	int hsa_blanking_mode = dssdev->panel.dsi_vm_data.hsa_blanking_mode;
	u32 r;

	/*
	 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
	 * 1 = Long blanking packets are sent in corresponding blanking periods
	 */
	r = dsi_read_reg(dsidev, DSI_CTRL);
	r = FLD_MOD(r, blanking_mode, 20, 20);		/* BLANKING_MODE */
	r = FLD_MOD(r, hfp_blanking_mode, 21, 21);	/* HFP_BLANKING */
	r = FLD_MOD(r, hbp_blanking_mode, 22, 22);	/* HBP_BLANKING */
	r = FLD_MOD(r, hsa_blanking_mode, 23, 23);	/* HSA_BLANKING */
	dsi_write_reg(dsidev, DSI_CTRL, r);
}

T
Tomi Valkeinen 已提交
3799 3800
static int dsi_proto_config(struct omap_dss_device *dssdev)
{
3801
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
T
Tomi Valkeinen 已提交
3802 3803 3804
	u32 r;
	int buswidth = 0;

3805
	dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
3806 3807 3808
			DSI_FIFO_SIZE_32,
			DSI_FIFO_SIZE_32,
			DSI_FIFO_SIZE_32);
T
Tomi Valkeinen 已提交
3809

3810
	dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
3811 3812 3813
			DSI_FIFO_SIZE_32,
			DSI_FIFO_SIZE_32,
			DSI_FIFO_SIZE_32);
T
Tomi Valkeinen 已提交
3814 3815

	/* XXX what values for the timeouts? */
3816 3817 3818 3819
	dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
	dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
	dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
	dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
T
Tomi Valkeinen 已提交
3820

3821
	switch (dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt)) {
T
Tomi Valkeinen 已提交
3822 3823 3824 3825 3826 3827 3828 3829 3830 3831 3832 3833 3834
	case 16:
		buswidth = 0;
		break;
	case 18:
		buswidth = 1;
		break;
	case 24:
		buswidth = 2;
		break;
	default:
		BUG();
	}

3835
	r = dsi_read_reg(dsidev, DSI_CTRL);
T
Tomi Valkeinen 已提交
3836 3837 3838 3839 3840 3841 3842 3843
	r = FLD_MOD(r, 1, 1, 1);	/* CS_RX_EN */
	r = FLD_MOD(r, 1, 2, 2);	/* ECC_RX_EN */
	r = FLD_MOD(r, 1, 3, 3);	/* TX_FIFO_ARBITRATION */
	r = FLD_MOD(r, 1, 4, 4);	/* VP_CLK_RATIO, always 1, see errata*/
	r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
	r = FLD_MOD(r, 0, 8, 8);	/* VP_CLK_POL */
	r = FLD_MOD(r, 1, 14, 14);	/* TRIGGER_RESET_MODE */
	r = FLD_MOD(r, 1, 19, 19);	/* EOT_ENABLE */
3844 3845 3846 3847 3848
	if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
		r = FLD_MOD(r, 1, 24, 24);	/* DCS_CMD_ENABLE */
		/* DCS_CMD_CODE, 1=start, 0=continue */
		r = FLD_MOD(r, 0, 25, 25);
	}
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3849

3850
	dsi_write_reg(dsidev, DSI_CTRL, r);
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3851

3852 3853 3854 3855 3856 3857 3858
	dsi_config_vp_num_line_buffers(dssdev);

	if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
		dsi_config_vp_sync_events(dssdev);
		dsi_config_blanking_modes(dssdev);
	}

3859 3860 3861 3862
	dsi_vc_initial_config(dsidev, 0);
	dsi_vc_initial_config(dsidev, 1);
	dsi_vc_initial_config(dsidev, 2);
	dsi_vc_initial_config(dsidev, 3);
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3863 3864 3865 3866 3867 3868

	return 0;
}

static void dsi_proto_timings(struct omap_dss_device *dssdev)
{
3869
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3870
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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	unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
	unsigned tclk_pre, tclk_post;
	unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
	unsigned ths_trail, ths_exit;
	unsigned ddr_clk_pre, ddr_clk_post;
	unsigned enter_hs_mode_lat, exit_hs_mode_lat;
	unsigned ths_eot;
3878
	int ndl = dsi->num_lanes_used - 1;
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3879 3880
	u32 r;

3881
	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
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3882 3883 3884 3885 3886 3887
	ths_prepare = FLD_GET(r, 31, 24);
	ths_prepare_ths_zero = FLD_GET(r, 23, 16);
	ths_zero = ths_prepare_ths_zero - ths_prepare;
	ths_trail = FLD_GET(r, 15, 8);
	ths_exit = FLD_GET(r, 7, 0);

3888
	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
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3889 3890 3891 3892
	tlpx = FLD_GET(r, 22, 16) * 2;
	tclk_trail = FLD_GET(r, 15, 8);
	tclk_zero = FLD_GET(r, 7, 0);

3893
	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
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3894 3895 3896 3897 3898
	tclk_prepare = FLD_GET(r, 7, 0);

	/* min 8*UI */
	tclk_pre = 20;
	/* min 60ns + 52*UI */
3899
	tclk_post = ns2ddr(dsidev, 60) + 26;
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3900

3901
	ths_eot = DIV_ROUND_UP(4, ndl);
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3902 3903 3904 3905 3906 3907 3908 3909

	ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
			4);
	ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;

	BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
	BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);

3910
	r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
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3911 3912
	r = FLD_MOD(r, ddr_clk_pre, 15, 8);
	r = FLD_MOD(r, ddr_clk_post, 7, 0);
3913
	dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
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3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924 3925 3926

	DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
			ddr_clk_pre,
			ddr_clk_post);

	enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
		DIV_ROUND_UP(ths_prepare, 4) +
		DIV_ROUND_UP(ths_zero + 3, 4);

	exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;

	r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
		FLD_VAL(exit_hs_mode_lat, 15, 0);
3927
	dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
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3928 3929 3930

	DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
			enter_hs_mode_lat, exit_hs_mode_lat);
3931 3932 3933 3934 3935 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952 3953 3954 3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031 4032 4033 4034 4035 4036

	 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
		/* TODO: Implement a video mode check_timings function */
		int hsa = dssdev->panel.dsi_vm_data.hsa;
		int hfp = dssdev->panel.dsi_vm_data.hfp;
		int hbp = dssdev->panel.dsi_vm_data.hbp;
		int vsa = dssdev->panel.dsi_vm_data.vsa;
		int vfp = dssdev->panel.dsi_vm_data.vfp;
		int vbp = dssdev->panel.dsi_vm_data.vbp;
		int window_sync = dssdev->panel.dsi_vm_data.window_sync;
		bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
		struct omap_video_timings *timings = &dssdev->panel.timings;
		int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
		int tl, t_he, width_bytes;

		t_he = hsync_end ?
			((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;

		width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);

		/* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
		tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
			DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;

		DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
			hfp, hsync_end ? hsa : 0, tl);
		DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
			vsa, timings->y_res);

		r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
		r = FLD_MOD(r, hbp, 11, 0);	/* HBP */
		r = FLD_MOD(r, hfp, 23, 12);	/* HFP */
		r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24);	/* HSA */
		dsi_write_reg(dsidev, DSI_VM_TIMING1, r);

		r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
		r = FLD_MOD(r, vbp, 7, 0);	/* VBP */
		r = FLD_MOD(r, vfp, 15, 8);	/* VFP */
		r = FLD_MOD(r, vsa, 23, 16);	/* VSA */
		r = FLD_MOD(r, window_sync, 27, 24);	/* WINDOW_SYNC */
		dsi_write_reg(dsidev, DSI_VM_TIMING2, r);

		r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
		r = FLD_MOD(r, timings->y_res, 14, 0);	/* VACT */
		r = FLD_MOD(r, tl, 31, 16);		/* TL */
		dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
	}
}

int dsi_video_mode_enable(struct omap_dss_device *dssdev, int channel)
{
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
	int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
	u8 data_type;
	u16 word_count;

	switch (dssdev->panel.dsi_pix_fmt) {
	case OMAP_DSS_DSI_FMT_RGB888:
		data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
		break;
	case OMAP_DSS_DSI_FMT_RGB666:
		data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
		break;
	case OMAP_DSS_DSI_FMT_RGB666_PACKED:
		data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
		break;
	case OMAP_DSS_DSI_FMT_RGB565:
		data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
		break;
	default:
		BUG();
	};

	dsi_if_enable(dsidev, false);
	dsi_vc_enable(dsidev, channel, false);

	/* MODE, 1 = video mode */
	REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);

	word_count = DIV_ROUND_UP(dssdev->panel.timings.x_res * bpp, 8);

	dsi_vc_write_long_header(dsidev, channel, data_type, word_count, 0);

	dsi_vc_enable(dsidev, channel, true);
	dsi_if_enable(dsidev, true);

	dssdev->manager->enable(dssdev->manager);

	return 0;
}
EXPORT_SYMBOL(dsi_video_mode_enable);

void dsi_video_mode_disable(struct omap_dss_device *dssdev, int channel)
{
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);

	dsi_if_enable(dsidev, false);
	dsi_vc_enable(dsidev, channel, false);

	/* MODE, 0 = command mode */
	REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);

	dsi_vc_enable(dsidev, channel, true);
	dsi_if_enable(dsidev, true);

	dssdev->manager->disable(dssdev->manager);
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4037
}
4038
EXPORT_SYMBOL(dsi_video_mode_disable);
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4039 4040 4041 4042

static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
		u16 x, u16 y, u16 w, u16 h)
{
4043
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4044
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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4045 4046 4047 4048 4049 4050 4051
	unsigned bytespp;
	unsigned bytespl;
	unsigned bytespf;
	unsigned total_len;
	unsigned packet_payload;
	unsigned packet_len;
	u32 l;
4052
	int r;
4053
	const unsigned channel = dsi->update_channel;
4054
	const unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
T
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4055

4056 4057
	DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
			x, y, w, h);
T
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4058

4059
	dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
4060

4061
	bytespp	= dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8;
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4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079
	bytespl = w * bytespp;
	bytespf = bytespl * h;

	/* NOTE: packet_payload has to be equal to N * bytespl, where N is
	 * number of lines in a packet.  See errata about VP_CLK_RATIO */

	if (bytespf < line_buf_size)
		packet_payload = bytespf;
	else
		packet_payload = (line_buf_size) / bytespl * bytespl;

	packet_len = packet_payload + 1;	/* 1 byte for DCS cmd */
	total_len = (bytespf / packet_payload) * packet_len;

	if (bytespf % packet_payload)
		total_len += (bytespf % packet_payload) + 1;

	l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
4080
	dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
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4081

4082
	dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
4083
		packet_len, 0);
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4084

4085
	if (dsi->te_enabled)
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4086 4087 4088
		l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
	else
		l = FLD_MOD(l, 1, 31, 31); /* TE_START */
4089
	dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
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4090 4091 4092 4093 4094 4095 4096 4097 4098

	/* We put SIDLEMODE to no-idle for the duration of the transfer,
	 * because DSS interrupts are not capable of waking up the CPU and the
	 * framedone interrupt could be delayed for quite a long time. I think
	 * the same goes for any DSS interrupts, but for some reason I have not
	 * seen the problem anywhere else than here.
	 */
	dispc_disable_sidle();

4099
	dsi_perf_mark_start(dsidev);
4100

4101 4102
	r = schedule_delayed_work(&dsi->framedone_timeout_work,
		msecs_to_jiffies(250));
4103
	BUG_ON(r == 0);
4104

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4105 4106
	dss_start_update(dssdev);

4107
	if (dsi->te_enabled) {
T
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4108 4109
		/* disable LP_RX_TO, so that we can receive TE.  Time to wait
		 * for TE is longer than the timer allows */
4110
		REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
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4111

4112
		dsi_vc_send_bta(dsidev, channel);
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4113 4114

#ifdef DSI_CATCH_MISSING_TE
4115
		mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
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4116 4117 4118 4119 4120 4121 4122 4123 4124 4125 4126
#endif
	}
}

#ifdef DSI_CATCH_MISSING_TE
static void dsi_te_timeout(unsigned long arg)
{
	DSSERR("TE not received for 250ms!\n");
}
#endif

4127
static void dsi_handle_framedone(struct platform_device *dsidev, int error)
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4128
{
4129 4130
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

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4131 4132 4133
	/* SIDLEMODE back to smart-idle */
	dispc_enable_sidle();

4134
	if (dsi->te_enabled) {
4135
		/* enable LP_RX_TO again after the TE */
4136
		REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
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4137 4138
	}

4139
	dsi->framedone_callback(error, dsi->framedone_data);
4140 4141

	if (!error)
4142
		dsi_perf_show(dsidev, "DISPC");
4143
}
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4144

4145
static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4146
{
4147 4148
	struct dsi_data *dsi = container_of(work, struct dsi_data,
			framedone_timeout_work.work);
4149 4150 4151 4152 4153 4154
	/* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
	 * 250ms which would conflict with this timeout work. What should be
	 * done is first cancel the transfer on the HW, and then cancel the
	 * possibly scheduled framedone work. However, cancelling the transfer
	 * on the HW is buggy, and would probably require resetting the whole
	 * DSI */
4155

4156
	DSSERR("Framedone not received for 250ms!\n");
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4157

4158
	dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
T
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4159 4160
}

4161
static void dsi_framedone_irq_callback(void *data, u32 mask)
T
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4162
{
4163 4164
	struct omap_dss_device *dssdev = (struct omap_dss_device *) data;
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4165 4166
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

4167 4168 4169 4170
	/* Note: We get FRAMEDONE when DISPC has finished sending pixels and
	 * turns itself off. However, DSI still has the pixels in its buffers,
	 * and is sending the data.
	 */
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4171

4172
	__cancel_delayed_work(&dsi->framedone_timeout_work);
T
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4173

4174
	dsi_handle_framedone(dsidev, 0);
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4175

4176 4177 4178
#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
	dispc_fake_vsync_irq();
#endif
4179
}
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4180

4181
int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
4182 4183
				    u16 *x, u16 *y, u16 *w, u16 *h,
				    bool enlarge_update_area)
4184
{
4185
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4186
	u16 dw, dh;
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4187

4188
	dssdev->driver->get_resolution(dssdev, &dw, &dh);
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4189

4190 4191
	if  (*x > dw || *y > dh)
		return -EINVAL;
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4192

4193 4194
	if (*x + *w > dw)
		return -EINVAL;
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4195

4196 4197
	if (*y + *h > dh)
		return -EINVAL;
T
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4198

4199 4200
	if (*w == 1)
		return -EINVAL;
T
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4201

4202 4203
	if (*w == 0 || *h == 0)
		return -EINVAL;
T
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4204

4205
	dsi_perf_mark_setup(dsidev);
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4206

4207 4208
	dss_setup_partial_planes(dssdev, x, y, w, h,
			enlarge_update_area);
4209
	dispc_mgr_set_lcd_size(dssdev->manager->id, *w, *h);
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4211 4212 4213
	return 0;
}
EXPORT_SYMBOL(omap_dsi_prepare_update);
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4214

4215 4216 4217 4218 4219
int omap_dsi_update(struct omap_dss_device *dssdev,
		int channel,
		u16 x, u16 y, u16 w, u16 h,
		void (*callback)(int, void *), void *data)
{
4220
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4221
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4222

4223
	dsi->update_channel = channel;
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4224

4225 4226 4227 4228 4229 4230
	/* OMAP DSS cannot send updates of odd widths.
	 * omap_dsi_prepare_update() makes the widths even, but add a BUG_ON
	 * here to make sure we catch erroneous updates. Otherwise we'll only
	 * see rather obscure HW error happening, as DSS halts. */
	BUG_ON(x % 2 == 1);

4231 4232
	dsi->framedone_callback = callback;
	dsi->framedone_data = data;
4233

4234 4235 4236 4237 4238
	dsi->update_region.x = x;
	dsi->update_region.y = y;
	dsi->update_region.w = w;
	dsi->update_region.h = h;
	dsi->update_region.device = dssdev;
4239

4240
	dsi_update_screen_dispc(dssdev, x, y, w, h);
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4241 4242 4243

	return 0;
}
4244
EXPORT_SYMBOL(omap_dsi_update);
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4245 4246 4247 4248 4249 4250 4251

/* Display funcs */

static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
{
	int r;

4252 4253
	if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
		u32 irq;
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4254 4255 4256 4257 4258 4259 4260 4261 4262
		struct omap_video_timings timings = {
			.hsw		= 1,
			.hfp		= 1,
			.hbp		= 1,
			.vsw		= 1,
			.vfp		= 0,
			.vbp		= 0,
		};

4263 4264 4265 4266 4267 4268 4269 4270 4271 4272 4273 4274 4275
		irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
			DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;

		r = omap_dispc_register_isr(dsi_framedone_irq_callback,
			(void *) dssdev, irq);
		if (r) {
			DSSERR("can't get FRAMEDONE irq\n");
			return r;
		}

		dispc_mgr_enable_stallmode(dssdev->manager->id, true);
		dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 1);

4276
		dispc_mgr_set_lcd_timings(dssdev->manager->id, &timings);
4277 4278 4279 4280 4281 4282
	} else {
		dispc_mgr_enable_stallmode(dssdev->manager->id, false);
		dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 0);

		dispc_mgr_set_lcd_timings(dssdev->manager->id,
			&dssdev->panel.timings);
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4283 4284
	}

4285 4286 4287 4288
		dispc_mgr_set_lcd_display_type(dssdev->manager->id,
			OMAP_DSS_LCD_DISPLAY_TFT);
		dispc_mgr_set_tft_data_lines(dssdev->manager->id,
			dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt));
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4289 4290 4291 4292 4293
	return 0;
}

static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
{
4294 4295
	if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
		u32 irq;
4296

4297 4298
		irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
			DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
4299

4300 4301 4302
		omap_dispc_unregister_isr(dsi_framedone_irq_callback,
			(void *) dssdev, irq);
	}
T
Tomi Valkeinen 已提交
4303 4304 4305 4306
}

static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
{
4307
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
T
Tomi Valkeinen 已提交
4308 4309 4310
	struct dsi_clock_info cinfo;
	int r;

4311 4312
	/* we always use DSS_CLK_SYSCK as input clock */
	cinfo.use_sys_clk = true;
4313 4314 4315 4316
	cinfo.regn  = dssdev->clocks.dsi.regn;
	cinfo.regm  = dssdev->clocks.dsi.regm;
	cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc;
	cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi;
4317
	r = dsi_calc_clock_rates(dssdev, &cinfo);
4318 4319
	if (r) {
		DSSERR("Failed to calc dsi clocks\n");
T
Tomi Valkeinen 已提交
4320
		return r;
4321
	}
T
Tomi Valkeinen 已提交
4322

4323
	r = dsi_pll_set_clock_div(dsidev, &cinfo);
T
Tomi Valkeinen 已提交
4324 4325 4326 4327 4328 4329 4330 4331 4332 4333
	if (r) {
		DSSERR("Failed to set dsi clocks\n");
		return r;
	}

	return 0;
}

static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
{
4334
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
T
Tomi Valkeinen 已提交
4335 4336 4337 4338
	struct dispc_clock_info dispc_cinfo;
	int r;
	unsigned long long fck;

4339
	fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
T
Tomi Valkeinen 已提交
4340

4341 4342
	dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div;
	dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div;
T
Tomi Valkeinen 已提交
4343 4344 4345 4346 4347 4348 4349

	r = dispc_calc_clock_rates(fck, &dispc_cinfo);
	if (r) {
		DSSERR("Failed to calc dispc clocks\n");
		return r;
	}

4350
	r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
T
Tomi Valkeinen 已提交
4351 4352 4353 4354 4355 4356 4357 4358 4359 4360
	if (r) {
		DSSERR("Failed to set dispc clocks\n");
		return r;
	}

	return 0;
}

static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
{
4361
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4362
	int dsi_module = dsi_get_dsidev_id(dsidev);
T
Tomi Valkeinen 已提交
4363 4364
	int r;

T
Tomi Valkeinen 已提交
4365 4366 4367 4368 4369 4370
	r = dsi_parse_lane_config(dssdev);
	if (r) {
		DSSERR("illegal lane config");
		goto err0;
	}

4371
	r = dsi_pll_init(dsidev, true, true);
T
Tomi Valkeinen 已提交
4372 4373 4374 4375 4376 4377 4378
	if (r)
		goto err0;

	r = dsi_configure_dsi_clocks(dssdev);
	if (r)
		goto err1;

4379
	dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
4380
	dss_select_dsi_clk_source(dsi_module, dssdev->clocks.dsi.dsi_fclk_src);
4381
	dss_select_lcd_clk_source(dssdev->manager->id,
4382
			dssdev->clocks.dispc.channel.lcd_clk_src);
T
Tomi Valkeinen 已提交
4383 4384 4385 4386 4387 4388 4389

	DSSDBG("PLL OK\n");

	r = dsi_configure_dispc_clocks(dssdev);
	if (r)
		goto err2;

4390
	r = dsi_cio_init(dssdev);
T
Tomi Valkeinen 已提交
4391 4392 4393
	if (r)
		goto err2;

4394
	_dsi_print_reset_status(dsidev);
T
Tomi Valkeinen 已提交
4395 4396 4397 4398 4399

	dsi_proto_timings(dssdev);
	dsi_set_lp_clk_divisor(dssdev);

	if (1)
4400
		_dsi_print_reset_status(dsidev);
T
Tomi Valkeinen 已提交
4401 4402 4403 4404 4405 4406

	r = dsi_proto_config(dssdev);
	if (r)
		goto err3;

	/* enable interface */
4407 4408 4409 4410 4411 4412
	dsi_vc_enable(dsidev, 0, 1);
	dsi_vc_enable(dsidev, 1, 1);
	dsi_vc_enable(dsidev, 2, 1);
	dsi_vc_enable(dsidev, 3, 1);
	dsi_if_enable(dsidev, 1);
	dsi_force_tx_stop_mode_io(dsidev);
T
Tomi Valkeinen 已提交
4413 4414 4415

	return 0;
err3:
4416
	dsi_cio_uninit(dssdev);
T
Tomi Valkeinen 已提交
4417
err2:
4418
	dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4419
	dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
4420 4421
	dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK);

T
Tomi Valkeinen 已提交
4422
err1:
4423
	dsi_pll_uninit(dsidev, true);
T
Tomi Valkeinen 已提交
4424 4425 4426 4427
err0:
	return r;
}

4428
static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev,
4429
		bool disconnect_lanes, bool enter_ulps)
T
Tomi Valkeinen 已提交
4430
{
4431
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4432
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4433
	int dsi_module = dsi_get_dsidev_id(dsidev);
4434

4435
	if (enter_ulps && !dsi->ulps_enabled)
4436
		dsi_enter_ulps(dsidev);
4437

4438
	/* disable interface */
4439 4440 4441 4442 4443
	dsi_if_enable(dsidev, 0);
	dsi_vc_enable(dsidev, 0, 0);
	dsi_vc_enable(dsidev, 1, 0);
	dsi_vc_enable(dsidev, 2, 0);
	dsi_vc_enable(dsidev, 3, 0);
4444

4445
	dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4446
	dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
4447
	dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK);
4448
	dsi_cio_uninit(dssdev);
4449
	dsi_pll_uninit(dsidev, disconnect_lanes);
T
Tomi Valkeinen 已提交
4450 4451
}

4452
int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
T
Tomi Valkeinen 已提交
4453
{
4454
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4455
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
T
Tomi Valkeinen 已提交
4456 4457 4458 4459
	int r = 0;

	DSSDBG("dsi_display_enable\n");

4460
	WARN_ON(!dsi_bus_is_locked(dsidev));
4461

4462
	mutex_lock(&dsi->lock);
T
Tomi Valkeinen 已提交
4463

4464 4465 4466 4467 4468 4469
	if (dssdev->manager == NULL) {
		DSSERR("failed to enable display: no manager\n");
		r = -ENODEV;
		goto err_start_dev;
	}

T
Tomi Valkeinen 已提交
4470 4471 4472
	r = omap_dss_start_device(dssdev);
	if (r) {
		DSSERR("failed to start device\n");
4473
		goto err_start_dev;
T
Tomi Valkeinen 已提交
4474 4475
	}

4476
	r = dsi_runtime_get(dsidev);
T
Tomi Valkeinen 已提交
4477
	if (r)
4478 4479 4480
		goto err_get_dsi;

	dsi_enable_pll_clock(dsidev, 1);
T
Tomi Valkeinen 已提交
4481

4482
	_dsi_initialize_irq(dsidev);
T
Tomi Valkeinen 已提交
4483 4484 4485

	r = dsi_display_init_dispc(dssdev);
	if (r)
4486
		goto err_init_dispc;
T
Tomi Valkeinen 已提交
4487 4488 4489

	r = dsi_display_init_dsi(dssdev);
	if (r)
4490
		goto err_init_dsi;
T
Tomi Valkeinen 已提交
4491

4492
	mutex_unlock(&dsi->lock);
T
Tomi Valkeinen 已提交
4493 4494 4495

	return 0;

4496
err_init_dsi:
4497
	dsi_display_uninit_dispc(dssdev);
4498
err_init_dispc:
4499
	dsi_enable_pll_clock(dsidev, 0);
4500 4501
	dsi_runtime_put(dsidev);
err_get_dsi:
T
Tomi Valkeinen 已提交
4502
	omap_dss_stop_device(dssdev);
4503
err_start_dev:
4504
	mutex_unlock(&dsi->lock);
T
Tomi Valkeinen 已提交
4505 4506 4507
	DSSDBG("dsi_display_enable FAILED\n");
	return r;
}
4508
EXPORT_SYMBOL(omapdss_dsi_display_enable);
T
Tomi Valkeinen 已提交
4509

4510
void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
4511
		bool disconnect_lanes, bool enter_ulps)
T
Tomi Valkeinen 已提交
4512
{
4513
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4514
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4515

T
Tomi Valkeinen 已提交
4516 4517
	DSSDBG("dsi_display_disable\n");

4518
	WARN_ON(!dsi_bus_is_locked(dsidev));
T
Tomi Valkeinen 已提交
4519

4520
	mutex_lock(&dsi->lock);
T
Tomi Valkeinen 已提交
4521

4522 4523 4524 4525 4526
	dsi_sync_vc(dsidev, 0);
	dsi_sync_vc(dsidev, 1);
	dsi_sync_vc(dsidev, 2);
	dsi_sync_vc(dsidev, 3);

T
Tomi Valkeinen 已提交
4527 4528
	dsi_display_uninit_dispc(dssdev);

4529
	dsi_display_uninit_dsi(dssdev, disconnect_lanes, enter_ulps);
T
Tomi Valkeinen 已提交
4530

4531
	dsi_runtime_put(dsidev);
4532
	dsi_enable_pll_clock(dsidev, 0);
T
Tomi Valkeinen 已提交
4533

4534
	omap_dss_stop_device(dssdev);
T
Tomi Valkeinen 已提交
4535

4536
	mutex_unlock(&dsi->lock);
T
Tomi Valkeinen 已提交
4537
}
4538
EXPORT_SYMBOL(omapdss_dsi_display_disable);
T
Tomi Valkeinen 已提交
4539

4540
int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
T
Tomi Valkeinen 已提交
4541
{
4542 4543 4544 4545
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	dsi->te_enabled = enable;
4546
	return 0;
T
Tomi Valkeinen 已提交
4547
}
4548
EXPORT_SYMBOL(omapdss_dsi_enable_te);
T
Tomi Valkeinen 已提交
4549 4550

void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
4551
		u32 fifo_size, u32 burst_size,
T
Tomi Valkeinen 已提交
4552 4553
		u32 *fifo_low, u32 *fifo_high)
{
4554 4555
	*fifo_high = fifo_size - burst_size;
	*fifo_low = fifo_size - burst_size * 2;
T
Tomi Valkeinen 已提交
4556 4557 4558 4559
}

int dsi_init_display(struct omap_dss_device *dssdev)
{
4560 4561 4562
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

T
Tomi Valkeinen 已提交
4563 4564
	DSSDBG("DSI init\n");

4565 4566 4567 4568
	if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
		dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
			OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
	}
T
Tomi Valkeinen 已提交
4569

4570
	if (dsi->vdds_dsi_reg == NULL) {
4571 4572
		struct regulator *vdds_dsi;

4573
		vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
4574 4575 4576 4577 4578 4579

		if (IS_ERR(vdds_dsi)) {
			DSSERR("can't get VDDS_DSI regulator\n");
			return PTR_ERR(vdds_dsi);
		}

4580
		dsi->vdds_dsi_reg = vdds_dsi;
4581 4582
	}

T
Tomi Valkeinen 已提交
4583 4584 4585
	return 0;
}

4586 4587
int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
{
4588 4589
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4590 4591
	int i;

4592 4593 4594
	for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
		if (!dsi->vc[i].dssdev) {
			dsi->vc[i].dssdev = dssdev;
4595 4596 4597 4598 4599 4600 4601 4602 4603 4604 4605 4606
			*channel = i;
			return 0;
		}
	}

	DSSERR("cannot get VC for display %s", dssdev->name);
	return -ENOSPC;
}
EXPORT_SYMBOL(omap_dsi_request_vc);

int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
{
4607 4608 4609
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

4610 4611 4612 4613 4614 4615 4616 4617 4618 4619
	if (vc_id < 0 || vc_id > 3) {
		DSSERR("VC ID out of range\n");
		return -EINVAL;
	}

	if (channel < 0 || channel > 3) {
		DSSERR("Virtual Channel out of range\n");
		return -EINVAL;
	}

4620
	if (dsi->vc[channel].dssdev != dssdev) {
4621 4622 4623 4624 4625
		DSSERR("Virtual Channel not allocated to display %s\n",
			dssdev->name);
		return -EINVAL;
	}

4626
	dsi->vc[channel].vc_id = vc_id;
4627 4628 4629 4630 4631 4632 4633

	return 0;
}
EXPORT_SYMBOL(omap_dsi_set_vc_id);

void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel)
{
4634 4635 4636
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

4637
	if ((channel >= 0 && channel <= 3) &&
4638 4639 4640
		dsi->vc[channel].dssdev == dssdev) {
		dsi->vc[channel].dssdev = NULL;
		dsi->vc[channel].vc_id = 0;
4641 4642 4643 4644
	}
}
EXPORT_SYMBOL(omap_dsi_release_vc);

4645
void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
4646
{
4647
	if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1)
4648
		DSSERR("%s (%s) not active\n",
4649 4650
			dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
			dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
4651 4652
}

4653
void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
4654
{
4655
	if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1)
4656
		DSSERR("%s (%s) not active\n",
4657 4658
			dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
			dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
4659 4660
}

4661
static void dsi_calc_clock_param_ranges(struct platform_device *dsidev)
4662
{
4663 4664 4665 4666 4667 4668 4669 4670 4671 4672
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
	dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
	dsi->regm_dispc_max =
		dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
	dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
	dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
	dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
	dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
4673 4674
}

4675 4676 4677 4678 4679 4680 4681 4682 4683 4684 4685 4686 4687
static int dsi_get_clocks(struct platform_device *dsidev)
{
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
	struct clk *clk;

	clk = clk_get(&dsidev->dev, "fck");
	if (IS_ERR(clk)) {
		DSSERR("can't get fck\n");
		return PTR_ERR(clk);
	}

	dsi->dss_clk = clk;

4688
	clk = clk_get(&dsidev->dev, "sys_clk");
4689 4690 4691 4692 4693 4694 4695 4696 4697 4698 4699 4700 4701 4702 4703 4704 4705 4706 4707 4708 4709 4710
	if (IS_ERR(clk)) {
		DSSERR("can't get sys_clk\n");
		clk_put(dsi->dss_clk);
		dsi->dss_clk = NULL;
		return PTR_ERR(clk);
	}

	dsi->sys_clk = clk;

	return 0;
}

static void dsi_put_clocks(struct platform_device *dsidev)
{
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	if (dsi->dss_clk)
		clk_put(dsi->dss_clk);
	if (dsi->sys_clk)
		clk_put(dsi->sys_clk);
}

4711
/* DSI1 HW IP initialisation */
4712
static int omap_dsihw_probe(struct platform_device *dsidev)
T
Tomi Valkeinen 已提交
4713
{
4714 4715
	struct omap_display_platform_data *dss_plat_data;
	struct omap_dss_board_info *board_info;
T
Tomi Valkeinen 已提交
4716
	u32 rev;
4717
	int r, i, dsi_module = dsi_get_dsidev_id(dsidev);
4718
	struct resource *dsi_mem;
4719 4720 4721 4722 4723
	struct dsi_data *dsi;

	dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
	if (!dsi) {
		r = -ENOMEM;
4724
		goto err_alloc;
4725
	}
T
Tomi Valkeinen 已提交
4726

4727 4728 4729
	dsi->pdev = dsidev;
	dsi_pdev_map[dsi_module] = dsidev;
	dev_set_drvdata(&dsidev->dev, dsi);
4730 4731

	dss_plat_data = dsidev->dev.platform_data;
4732
	board_info = dss_plat_data->board_data;
4733 4734
	dsi->enable_pads = board_info->dsi_enable_pads;
	dsi->disable_pads = board_info->dsi_disable_pads;
4735

4736 4737 4738
	spin_lock_init(&dsi->irq_lock);
	spin_lock_init(&dsi->errors_lock);
	dsi->errors = 0;
T
Tomi Valkeinen 已提交
4739

4740
#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4741 4742
	spin_lock_init(&dsi->irq_stats_lock);
	dsi->irq_stats.last_reset = jiffies;
4743 4744
#endif

4745 4746
	mutex_init(&dsi->lock);
	sema_init(&dsi->bus_lock, 1);
T
Tomi Valkeinen 已提交
4747

4748 4749 4750 4751 4752 4753
	r = dsi_get_clocks(dsidev);
	if (r)
		goto err_get_clk;

	pm_runtime_enable(&dsidev->dev);

4754
	INIT_DELAYED_WORK_DEFERRABLE(&dsi->framedone_timeout_work,
4755 4756
			dsi_framedone_timeout_work_callback);

T
Tomi Valkeinen 已提交
4757
#ifdef DSI_CATCH_MISSING_TE
4758 4759 4760
	init_timer(&dsi->te_timer);
	dsi->te_timer.function = dsi_te_timeout;
	dsi->te_timer.data = 0;
T
Tomi Valkeinen 已提交
4761
#endif
4762
	dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0);
4763 4764 4765
	if (!dsi_mem) {
		DSSERR("can't get IORESOURCE_MEM DSI\n");
		r = -EINVAL;
4766
		goto err_ioremap;
4767
	}
4768 4769
	dsi->base = ioremap(dsi_mem->start, resource_size(dsi_mem));
	if (!dsi->base) {
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4770 4771
		DSSERR("can't ioremap DSI\n");
		r = -ENOMEM;
4772
		goto err_ioremap;
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4773
	}
4774 4775
	dsi->irq = platform_get_irq(dsi->pdev, 0);
	if (dsi->irq < 0) {
4776 4777
		DSSERR("platform_get_irq failed\n");
		r = -ENODEV;
4778
		goto err_get_irq;
4779 4780
	}

4781 4782
	r = request_irq(dsi->irq, omap_dsi_irq_handler, IRQF_SHARED,
		dev_name(&dsidev->dev), dsi->pdev);
4783 4784
	if (r < 0) {
		DSSERR("request_irq failed\n");
4785
		goto err_get_irq;
4786
	}
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4787

4788
	/* DSI VCs initialization */
4789
	for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4790
		dsi->vc[i].source = DSI_VC_SOURCE_L4;
4791 4792
		dsi->vc[i].dssdev = NULL;
		dsi->vc[i].vc_id = 0;
4793 4794
	}

4795
	dsi_calc_clock_param_ranges(dsidev);
4796

4797 4798 4799
	r = dsi_runtime_get(dsidev);
	if (r)
		goto err_get_dsi;
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4800

4801 4802
	rev = dsi_read_reg(dsidev, DSI_REVISION);
	dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
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4803 4804
	       FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));

4805 4806 4807 4808 4809 4810 4811
	/* DSI on OMAP3 doesn't have register DSI_GNQ, set number
	 * of data to 3 by default */
	if (dss_has_feature(FEAT_DSI_GNQ))
		/* NB_DATA_LANES */
		dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9);
	else
		dsi->num_lanes_supported = 3;
4812

4813
	dsi_runtime_put(dsidev);
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4814 4815

	return 0;
4816 4817 4818 4819

err_get_dsi:
	free_irq(dsi->irq, dsi->pdev);
err_get_irq:
4820
	iounmap(dsi->base);
4821 4822 4823
err_ioremap:
	pm_runtime_disable(&dsidev->dev);
err_get_clk:
4824
	kfree(dsi);
4825
err_alloc:
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4826 4827 4828
	return r;
}

4829
static int omap_dsihw_remove(struct platform_device *dsidev)
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4830
{
4831 4832
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

4833 4834
	WARN_ON(dsi->scp_clk_refcount > 0);

4835 4836 4837 4838
	pm_runtime_disable(&dsidev->dev);

	dsi_put_clocks(dsidev);

4839 4840 4841 4842
	if (dsi->vdds_dsi_reg != NULL) {
		if (dsi->vdds_dsi_enabled) {
			regulator_disable(dsi->vdds_dsi_reg);
			dsi->vdds_dsi_enabled = false;
4843 4844
		}

4845 4846
		regulator_put(dsi->vdds_dsi_reg);
		dsi->vdds_dsi_reg = NULL;
4847 4848
	}

4849 4850
	free_irq(dsi->irq, dsi->pdev);
	iounmap(dsi->base);
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4851

4852
	kfree(dsi);
4853

4854 4855 4856
	return 0;
}

4857 4858 4859 4860 4861 4862 4863 4864 4865 4866 4867 4868 4869 4870 4871 4872 4873 4874 4875 4876 4877 4878 4879 4880 4881 4882 4883 4884 4885 4886 4887 4888 4889
static int dsi_runtime_suspend(struct device *dev)
{
	dispc_runtime_put();
	dss_runtime_put();

	return 0;
}

static int dsi_runtime_resume(struct device *dev)
{
	int r;

	r = dss_runtime_get();
	if (r)
		goto err_get_dss;

	r = dispc_runtime_get();
	if (r)
		goto err_get_dispc;

	return 0;

err_get_dispc:
	dss_runtime_put();
err_get_dss:
	return r;
}

static const struct dev_pm_ops dsi_pm_ops = {
	.runtime_suspend = dsi_runtime_suspend,
	.runtime_resume = dsi_runtime_resume,
};

4890 4891 4892
static struct platform_driver omap_dsihw_driver = {
	.probe          = omap_dsihw_probe,
	.remove         = omap_dsihw_remove,
4893
	.driver         = {
4894
		.name   = "omapdss_dsi",
4895
		.owner  = THIS_MODULE,
4896
		.pm	= &dsi_pm_ops,
4897 4898 4899 4900 4901
	},
};

int dsi_init_platform_driver(void)
{
4902
	return platform_driver_register(&omap_dsihw_driver);
4903 4904 4905 4906
}

void dsi_uninit_platform_driver(void)
{
4907
	return platform_driver_unregister(&omap_dsihw_driver);
4908
}