dsi.c 116.3 KB
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/*
 * linux/drivers/video/omap2/dss/dsi.c
 *
 * Copyright (C) 2009 Nokia Corporation
 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#define DSS_SUBSYS_NAME "DSI"

#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/mutex.h>
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#include <linux/semaphore.h>
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#include <linux/seq_file.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/wait.h>
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#include <linux/workqueue.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/debugfs.h>
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#include <linux/pm_runtime.h>
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#include <video/omapdss.h>
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#include <video/mipi_display.h>
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#include <plat/clock.h>

#include "dss.h"
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#include "dss_features.h"
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/*#define VERBOSE_IRQ*/
#define DSI_CATCH_MISSING_TE

struct dsi_reg { u16 idx; };

#define DSI_REG(idx)		((const struct dsi_reg) { idx })

#define DSI_SZ_REGS		SZ_1K
/* DSI Protocol Engine */

#define DSI_REVISION			DSI_REG(0x0000)
#define DSI_SYSCONFIG			DSI_REG(0x0010)
#define DSI_SYSSTATUS			DSI_REG(0x0014)
#define DSI_IRQSTATUS			DSI_REG(0x0018)
#define DSI_IRQENABLE			DSI_REG(0x001C)
#define DSI_CTRL			DSI_REG(0x0040)
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#define DSI_GNQ				DSI_REG(0x0044)
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#define DSI_COMPLEXIO_CFG1		DSI_REG(0x0048)
#define DSI_COMPLEXIO_IRQ_STATUS	DSI_REG(0x004C)
#define DSI_COMPLEXIO_IRQ_ENABLE	DSI_REG(0x0050)
#define DSI_CLK_CTRL			DSI_REG(0x0054)
#define DSI_TIMING1			DSI_REG(0x0058)
#define DSI_TIMING2			DSI_REG(0x005C)
#define DSI_VM_TIMING1			DSI_REG(0x0060)
#define DSI_VM_TIMING2			DSI_REG(0x0064)
#define DSI_VM_TIMING3			DSI_REG(0x0068)
#define DSI_CLK_TIMING			DSI_REG(0x006C)
#define DSI_TX_FIFO_VC_SIZE		DSI_REG(0x0070)
#define DSI_RX_FIFO_VC_SIZE		DSI_REG(0x0074)
#define DSI_COMPLEXIO_CFG2		DSI_REG(0x0078)
#define DSI_RX_FIFO_VC_FULLNESS		DSI_REG(0x007C)
#define DSI_VM_TIMING4			DSI_REG(0x0080)
#define DSI_TX_FIFO_VC_EMPTINESS	DSI_REG(0x0084)
#define DSI_VM_TIMING5			DSI_REG(0x0088)
#define DSI_VM_TIMING6			DSI_REG(0x008C)
#define DSI_VM_TIMING7			DSI_REG(0x0090)
#define DSI_STOPCLK_TIMING		DSI_REG(0x0094)
#define DSI_VC_CTRL(n)			DSI_REG(0x0100 + (n * 0x20))
#define DSI_VC_TE(n)			DSI_REG(0x0104 + (n * 0x20))
#define DSI_VC_LONG_PACKET_HEADER(n)	DSI_REG(0x0108 + (n * 0x20))
#define DSI_VC_LONG_PACKET_PAYLOAD(n)	DSI_REG(0x010C + (n * 0x20))
#define DSI_VC_SHORT_PACKET_HEADER(n)	DSI_REG(0x0110 + (n * 0x20))
#define DSI_VC_IRQSTATUS(n)		DSI_REG(0x0118 + (n * 0x20))
#define DSI_VC_IRQENABLE(n)		DSI_REG(0x011C + (n * 0x20))

/* DSIPHY_SCP */

#define DSI_DSIPHY_CFG0			DSI_REG(0x200 + 0x0000)
#define DSI_DSIPHY_CFG1			DSI_REG(0x200 + 0x0004)
#define DSI_DSIPHY_CFG2			DSI_REG(0x200 + 0x0008)
#define DSI_DSIPHY_CFG5			DSI_REG(0x200 + 0x0014)
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#define DSI_DSIPHY_CFG10		DSI_REG(0x200 + 0x0028)
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/* DSI_PLL_CTRL_SCP */

#define DSI_PLL_CONTROL			DSI_REG(0x300 + 0x0000)
#define DSI_PLL_STATUS			DSI_REG(0x300 + 0x0004)
#define DSI_PLL_GO			DSI_REG(0x300 + 0x0008)
#define DSI_PLL_CONFIGURATION1		DSI_REG(0x300 + 0x000C)
#define DSI_PLL_CONFIGURATION2		DSI_REG(0x300 + 0x0010)

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#define REG_GET(dsidev, idx, start, end) \
	FLD_GET(dsi_read_reg(dsidev, idx), start, end)
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#define REG_FLD_MOD(dsidev, idx, val, start, end) \
	dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
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/* Global interrupts */
#define DSI_IRQ_VC0		(1 << 0)
#define DSI_IRQ_VC1		(1 << 1)
#define DSI_IRQ_VC2		(1 << 2)
#define DSI_IRQ_VC3		(1 << 3)
#define DSI_IRQ_WAKEUP		(1 << 4)
#define DSI_IRQ_RESYNC		(1 << 5)
#define DSI_IRQ_PLL_LOCK	(1 << 7)
#define DSI_IRQ_PLL_UNLOCK	(1 << 8)
#define DSI_IRQ_PLL_RECALL	(1 << 9)
#define DSI_IRQ_COMPLEXIO_ERR	(1 << 10)
#define DSI_IRQ_HS_TX_TIMEOUT	(1 << 14)
#define DSI_IRQ_LP_RX_TIMEOUT	(1 << 15)
#define DSI_IRQ_TE_TRIGGER	(1 << 16)
#define DSI_IRQ_ACK_TRIGGER	(1 << 17)
#define DSI_IRQ_SYNC_LOST	(1 << 18)
#define DSI_IRQ_LDO_POWER_GOOD	(1 << 19)
#define DSI_IRQ_TA_TIMEOUT	(1 << 20)
#define DSI_IRQ_ERROR_MASK \
	(DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
	DSI_IRQ_TA_TIMEOUT)
#define DSI_IRQ_CHANNEL_MASK	0xf

/* Virtual channel interrupts */
#define DSI_VC_IRQ_CS		(1 << 0)
#define DSI_VC_IRQ_ECC_CORR	(1 << 1)
#define DSI_VC_IRQ_PACKET_SENT	(1 << 2)
#define DSI_VC_IRQ_FIFO_TX_OVF	(1 << 3)
#define DSI_VC_IRQ_FIFO_RX_OVF	(1 << 4)
#define DSI_VC_IRQ_BTA		(1 << 5)
#define DSI_VC_IRQ_ECC_NO_CORR	(1 << 6)
#define DSI_VC_IRQ_FIFO_TX_UDF	(1 << 7)
#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
#define DSI_VC_IRQ_ERROR_MASK \
	(DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
	DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
	DSI_VC_IRQ_FIFO_TX_UDF)

/* ComplexIO interrupts */
#define DSI_CIO_IRQ_ERRSYNCESC1		(1 << 0)
#define DSI_CIO_IRQ_ERRSYNCESC2		(1 << 1)
#define DSI_CIO_IRQ_ERRSYNCESC3		(1 << 2)
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#define DSI_CIO_IRQ_ERRSYNCESC4		(1 << 3)
#define DSI_CIO_IRQ_ERRSYNCESC5		(1 << 4)
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#define DSI_CIO_IRQ_ERRESC1		(1 << 5)
#define DSI_CIO_IRQ_ERRESC2		(1 << 6)
#define DSI_CIO_IRQ_ERRESC3		(1 << 7)
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#define DSI_CIO_IRQ_ERRESC4		(1 << 8)
#define DSI_CIO_IRQ_ERRESC5		(1 << 9)
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#define DSI_CIO_IRQ_ERRCONTROL1		(1 << 10)
#define DSI_CIO_IRQ_ERRCONTROL2		(1 << 11)
#define DSI_CIO_IRQ_ERRCONTROL3		(1 << 12)
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#define DSI_CIO_IRQ_ERRCONTROL4		(1 << 13)
#define DSI_CIO_IRQ_ERRCONTROL5		(1 << 14)
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#define DSI_CIO_IRQ_STATEULPS1		(1 << 15)
#define DSI_CIO_IRQ_STATEULPS2		(1 << 16)
#define DSI_CIO_IRQ_STATEULPS3		(1 << 17)
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#define DSI_CIO_IRQ_STATEULPS4		(1 << 18)
#define DSI_CIO_IRQ_STATEULPS5		(1 << 19)
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#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1	(1 << 20)
#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1	(1 << 21)
#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2	(1 << 22)
#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2	(1 << 23)
#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3	(1 << 24)
#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3	(1 << 25)
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#define DSI_CIO_IRQ_ERRCONTENTIONLP0_4	(1 << 26)
#define DSI_CIO_IRQ_ERRCONTENTIONLP1_4	(1 << 27)
#define DSI_CIO_IRQ_ERRCONTENTIONLP0_5	(1 << 28)
#define DSI_CIO_IRQ_ERRCONTENTIONLP1_5	(1 << 29)
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#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0	(1 << 30)
#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1	(1 << 31)
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#define DSI_CIO_IRQ_ERROR_MASK \
	(DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
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	 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
	 DSI_CIO_IRQ_ERRSYNCESC5 | \
	 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
	 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
	 DSI_CIO_IRQ_ERRESC5 | \
	 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
	 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
	 DSI_CIO_IRQ_ERRCONTROL5 | \
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	 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
	 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
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	 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
	 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
	 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
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typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);

#define DSI_MAX_NR_ISRS                2

struct dsi_isr_data {
	omap_dsi_isr_t	isr;
	void		*arg;
	u32		mask;
};

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enum fifo_size {
	DSI_FIFO_SIZE_0		= 0,
	DSI_FIFO_SIZE_32	= 1,
	DSI_FIFO_SIZE_64	= 2,
	DSI_FIFO_SIZE_96	= 3,
	DSI_FIFO_SIZE_128	= 4,
};

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enum dsi_vc_source {
	DSI_VC_SOURCE_L4 = 0,
	DSI_VC_SOURCE_VP,
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};

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enum dsi_lane {
	DSI_CLK_P	= 1 << 0,
	DSI_CLK_N	= 1 << 1,
	DSI_DATA1_P	= 1 << 2,
	DSI_DATA1_N	= 1 << 3,
	DSI_DATA2_P	= 1 << 4,
	DSI_DATA2_N	= 1 << 5,
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	DSI_DATA3_P	= 1 << 6,
	DSI_DATA3_N	= 1 << 7,
	DSI_DATA4_P	= 1 << 8,
	DSI_DATA4_N	= 1 << 9,
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};

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struct dsi_update_region {
	u16 x, y, w, h;
	struct omap_dss_device *device;
};

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struct dsi_irq_stats {
	unsigned long last_reset;
	unsigned irq_count;
	unsigned dsi_irqs[32];
	unsigned vc_irqs[4][32];
	unsigned cio_irqs[32];
};

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struct dsi_isr_tables {
	struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
	struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
	struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
};

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struct dsi_data {
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	struct platform_device *pdev;
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	void __iomem	*base;
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	int irq;
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	struct clk *dss_clk;
	struct clk *sys_clk;

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	int (*enable_pads)(int dsi_id, unsigned lane_mask);
	void (*disable_pads)(int dsi_id, unsigned lane_mask);
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	struct dsi_clock_info current_cinfo;

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	bool vdds_dsi_enabled;
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	struct regulator *vdds_dsi_reg;

	struct {
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		enum dsi_vc_source source;
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		struct omap_dss_device *dssdev;
		enum fifo_size fifo_size;
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		int vc_id;
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	} vc[4];

	struct mutex lock;
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	struct semaphore bus_lock;
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	unsigned pll_locked;

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	spinlock_t irq_lock;
	struct dsi_isr_tables isr_tables;
	/* space for a copy used by the interrupt handler */
	struct dsi_isr_tables isr_tables_copy;

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	int update_channel;
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	struct dsi_update_region update_region;

	bool te_enabled;
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	bool ulps_enabled;
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	void (*framedone_callback)(int, void *);
	void *framedone_data;

	struct delayed_work framedone_timeout_work;

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#ifdef DSI_CATCH_MISSING_TE
	struct timer_list te_timer;
#endif

	unsigned long cache_req_pck;
	unsigned long cache_clk_freq;
	struct dsi_clock_info cache_cinfo;

	u32		errors;
	spinlock_t	errors_lock;
#ifdef DEBUG
	ktime_t perf_setup_time;
	ktime_t perf_start_time;
#endif
	int debug_read;
	int debug_write;
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#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
	spinlock_t irq_stats_lock;
	struct dsi_irq_stats irq_stats;
#endif
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	/* DSI PLL Parameter Ranges */
	unsigned long regm_max, regn_max;
	unsigned long  regm_dispc_max, regm_dsi_max;
	unsigned long  fint_min, fint_max;
	unsigned long lpdiv_max;
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	int num_data_lanes;

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	unsigned scp_clk_refcount;
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};
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struct dsi_packet_sent_handler_data {
	struct platform_device *dsidev;
	struct completion *completion;
};

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static struct platform_device *dsi_pdev_map[MAX_NUM_DSI];

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#ifdef DEBUG
static unsigned int dsi_perf;
module_param_named(dsi_perf, dsi_perf, bool, 0644);
#endif

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static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
{
	return dev_get_drvdata(&dsidev->dev);
}

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static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
{
	return dsi_pdev_map[dssdev->phy.dsi.module];
}

struct platform_device *dsi_get_dsidev_from_id(int module)
{
	return dsi_pdev_map[module];
}

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static inline int dsi_get_dsidev_id(struct platform_device *dsidev)
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{
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	return dsidev->id;
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}

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static inline void dsi_write_reg(struct platform_device *dsidev,
		const struct dsi_reg idx, u32 val)
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{
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	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	__raw_writel(val, dsi->base + idx.idx);
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}

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static inline u32 dsi_read_reg(struct platform_device *dsidev,
		const struct dsi_reg idx)
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{
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	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	return __raw_readl(dsi->base + idx.idx);
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}

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void dsi_bus_lock(struct omap_dss_device *dssdev)
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{
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	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	down(&dsi->bus_lock);
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}
EXPORT_SYMBOL(dsi_bus_lock);

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void dsi_bus_unlock(struct omap_dss_device *dssdev)
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{
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	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	up(&dsi->bus_lock);
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}
EXPORT_SYMBOL(dsi_bus_unlock);

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static bool dsi_bus_is_locked(struct platform_device *dsidev)
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{
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	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	return dsi->bus_lock.count == 0;
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}

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static void dsi_completion_handler(void *data, u32 mask)
{
	complete((struct completion *)data);
}

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static inline int wait_for_bit_change(struct platform_device *dsidev,
		const struct dsi_reg idx, int bitnum, int value)
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{
	int t = 100000;

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	while (REG_GET(dsidev, idx, bitnum, bitnum) != value) {
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		if (--t == 0)
			return !value;
	}

	return value;
}

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u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
{
	switch (fmt) {
	case OMAP_DSS_DSI_FMT_RGB888:
	case OMAP_DSS_DSI_FMT_RGB666:
		return 24;
	case OMAP_DSS_DSI_FMT_RGB666_PACKED:
		return 18;
	case OMAP_DSS_DSI_FMT_RGB565:
		return 16;
	default:
		BUG();
	}
}

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#ifdef DEBUG
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static void dsi_perf_mark_setup(struct platform_device *dsidev)
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{
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	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
	dsi->perf_setup_time = ktime_get();
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}

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static void dsi_perf_mark_start(struct platform_device *dsidev)
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{
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	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
	dsi->perf_start_time = ktime_get();
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}

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static void dsi_perf_show(struct platform_device *dsidev, const char *name)
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{
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	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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	struct omap_dss_device *dssdev = dsi->update_region.device;
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	ktime_t t, setup_time, trans_time;
	u32 total_bytes;
	u32 setup_us, trans_us, total_us;

	if (!dsi_perf)
		return;

	t = ktime_get();

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	setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
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	setup_us = (u32)ktime_to_us(setup_time);
	if (setup_us == 0)
		setup_us = 1;

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	trans_time = ktime_sub(t, dsi->perf_start_time);
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	trans_us = (u32)ktime_to_us(trans_time);
	if (trans_us == 0)
		trans_us = 1;

	total_us = setup_us + trans_us;

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	total_bytes = dsi->update_region.w *
		dsi->update_region.h *
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		dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8;
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	printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
			"%u bytes, %u kbytes/sec\n",
			name,
			setup_us,
			trans_us,
			total_us,
			1000*1000 / total_us,
			total_bytes,
			total_bytes * 1000 / total_us);
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}
#else
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static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
{
}

static inline void dsi_perf_mark_start(struct platform_device *dsidev)
{
}

static inline void dsi_perf_show(struct platform_device *dsidev,
		const char *name)
{
}
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#endif

static void print_irq_status(u32 status)
{
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	if (status == 0)
		return;

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#ifndef VERBOSE_IRQ
	if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
		return;
#endif
	printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);

#define PIS(x) \
	if (status & DSI_IRQ_##x) \
		printk(#x " ");
#ifdef VERBOSE_IRQ
	PIS(VC0);
	PIS(VC1);
	PIS(VC2);
	PIS(VC3);
#endif
	PIS(WAKEUP);
	PIS(RESYNC);
	PIS(PLL_LOCK);
	PIS(PLL_UNLOCK);
	PIS(PLL_RECALL);
	PIS(COMPLEXIO_ERR);
	PIS(HS_TX_TIMEOUT);
	PIS(LP_RX_TIMEOUT);
	PIS(TE_TRIGGER);
	PIS(ACK_TRIGGER);
	PIS(SYNC_LOST);
	PIS(LDO_POWER_GOOD);
	PIS(TA_TIMEOUT);
#undef PIS

	printk("\n");
}

static void print_irq_status_vc(int channel, u32 status)
{
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	if (status == 0)
		return;

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#ifndef VERBOSE_IRQ
	if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
		return;
#endif
	printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);

#define PIS(x) \
	if (status & DSI_VC_IRQ_##x) \
		printk(#x " ");
	PIS(CS);
	PIS(ECC_CORR);
#ifdef VERBOSE_IRQ
	PIS(PACKET_SENT);
#endif
	PIS(FIFO_TX_OVF);
	PIS(FIFO_RX_OVF);
	PIS(BTA);
	PIS(ECC_NO_CORR);
	PIS(FIFO_TX_UDF);
	PIS(PP_BUSY_CHANGE);
#undef PIS
	printk("\n");
}

static void print_irq_status_cio(u32 status)
{
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	if (status == 0)
		return;

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	printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);

#define PIS(x) \
	if (status & DSI_CIO_IRQ_##x) \
		printk(#x " ");
	PIS(ERRSYNCESC1);
	PIS(ERRSYNCESC2);
	PIS(ERRSYNCESC3);
	PIS(ERRESC1);
	PIS(ERRESC2);
	PIS(ERRESC3);
	PIS(ERRCONTROL1);
	PIS(ERRCONTROL2);
	PIS(ERRCONTROL3);
	PIS(STATEULPS1);
	PIS(STATEULPS2);
	PIS(STATEULPS3);
	PIS(ERRCONTENTIONLP0_1);
	PIS(ERRCONTENTIONLP1_1);
	PIS(ERRCONTENTIONLP0_2);
	PIS(ERRCONTENTIONLP1_2);
	PIS(ERRCONTENTIONLP0_3);
	PIS(ERRCONTENTIONLP1_3);
	PIS(ULPSACTIVENOT_ALL0);
	PIS(ULPSACTIVENOT_ALL1);
#undef PIS

	printk("\n");
}

609
#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
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static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
		u32 *vcstatus, u32 ciostatus)
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{
613
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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	int i;

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	spin_lock(&dsi->irq_stats_lock);
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618 619
	dsi->irq_stats.irq_count++;
	dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
620 621

	for (i = 0; i < 4; ++i)
622
		dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
623

624
	dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
625

626
	spin_unlock(&dsi->irq_stats_lock);
627 628
}
#else
629
#define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
630 631
#endif

632 633
static int debug_irq;

634 635
static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
		u32 *vcstatus, u32 ciostatus)
636
{
637
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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	int i;

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	if (irqstatus & DSI_IRQ_ERROR_MASK) {
		DSSERR("DSI error, irqstatus %x\n", irqstatus);
		print_irq_status(irqstatus);
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		spin_lock(&dsi->errors_lock);
		dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
		spin_unlock(&dsi->errors_lock);
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	} else if (debug_irq) {
		print_irq_status(irqstatus);
	}

	for (i = 0; i < 4; ++i) {
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		if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
			DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
				       i, vcstatus[i]);
			print_irq_status_vc(i, vcstatus[i]);
		} else if (debug_irq) {
			print_irq_status_vc(i, vcstatus[i]);
		}
	}
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	if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
		DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
		print_irq_status_cio(ciostatus);
	} else if (debug_irq) {
		print_irq_status_cio(ciostatus);
	}
}
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static void dsi_call_isrs(struct dsi_isr_data *isr_array,
		unsigned isr_array_size, u32 irqstatus)
{
	struct dsi_isr_data *isr_data;
	int i;

	for (i = 0; i < isr_array_size; i++) {
		isr_data = &isr_array[i];
		if (isr_data->isr && isr_data->mask & irqstatus)
			isr_data->isr(isr_data->arg, irqstatus);
	}
}

static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
		u32 irqstatus, u32 *vcstatus, u32 ciostatus)
{
	int i;

	dsi_call_isrs(isr_tables->isr_table,
			ARRAY_SIZE(isr_tables->isr_table),
			irqstatus);

	for (i = 0; i < 4; ++i) {
		if (vcstatus[i] == 0)
			continue;
		dsi_call_isrs(isr_tables->isr_table_vc[i],
				ARRAY_SIZE(isr_tables->isr_table_vc[i]),
				vcstatus[i]);
	}

	if (ciostatus != 0)
		dsi_call_isrs(isr_tables->isr_table_cio,
				ARRAY_SIZE(isr_tables->isr_table_cio),
				ciostatus);
}

704 705
static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
{
706
	struct platform_device *dsidev;
707
	struct dsi_data *dsi;
708 709
	u32 irqstatus, vcstatus[4], ciostatus;
	int i;
710

711
	dsidev = (struct platform_device *) arg;
712
	dsi = dsi_get_dsidrv_data(dsidev);
713

714
	spin_lock(&dsi->irq_lock);
715

716
	irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
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718
	/* IRQ is not for us */
719
	if (!irqstatus) {
720
		spin_unlock(&dsi->irq_lock);
721
		return IRQ_NONE;
722
	}
723

724
	dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
725
	/* flush posted write */
726
	dsi_read_reg(dsidev, DSI_IRQSTATUS);
727 728 729 730 731

	for (i = 0; i < 4; ++i) {
		if ((irqstatus & (1 << i)) == 0) {
			vcstatus[i] = 0;
			continue;
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		}

734
		vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
735

736
		dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
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		/* flush posted write */
738
		dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
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	}

	if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
742
		ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
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744
		dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
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		/* flush posted write */
746
		dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
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	} else {
		ciostatus = 0;
	}
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#ifdef DSI_CATCH_MISSING_TE
	if (irqstatus & DSI_IRQ_TE_TRIGGER)
753
		del_timer(&dsi->te_timer);
754 755
#endif

756 757
	/* make a copy and unlock, so that isrs can unregister
	 * themselves */
758 759
	memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
		sizeof(dsi->isr_tables));
760

761
	spin_unlock(&dsi->irq_lock);
762

763
	dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
764

765
	dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
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767
	dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
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769
	return IRQ_HANDLED;
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}

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/* dsi->irq_lock has to be locked by the caller */
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static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
		struct dsi_isr_data *isr_array,
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		unsigned isr_array_size, u32 default_mask,
		const struct dsi_reg enable_reg,
		const struct dsi_reg status_reg)
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{
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	struct dsi_isr_data *isr_data;
	u32 mask;
	u32 old_mask;
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	int i;

784
	mask = default_mask;
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	for (i = 0; i < isr_array_size; i++) {
		isr_data = &isr_array[i];
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		if (isr_data->isr == NULL)
			continue;

		mask |= isr_data->mask;
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	}

795
	old_mask = dsi_read_reg(dsidev, enable_reg);
796
	/* clear the irqstatus for newly enabled irqs */
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	dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
	dsi_write_reg(dsidev, enable_reg, mask);
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	/* flush posted writes */
801 802
	dsi_read_reg(dsidev, enable_reg);
	dsi_read_reg(dsidev, status_reg);
803
}
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805
/* dsi->irq_lock has to be locked by the caller */
806
static void _omap_dsi_set_irqs(struct platform_device *dsidev)
807
{
808
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
809
	u32 mask = DSI_IRQ_ERROR_MASK;
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#ifdef DSI_CATCH_MISSING_TE
811
	mask |= DSI_IRQ_TE_TRIGGER;
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#endif
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	_omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
			ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
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			DSI_IRQENABLE, DSI_IRQSTATUS);
}
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818
/* dsi->irq_lock has to be locked by the caller */
819
static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
820
{
821 822 823 824
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	_omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
			ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
825 826 827 828
			DSI_VC_IRQ_ERROR_MASK,
			DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
}

829
/* dsi->irq_lock has to be locked by the caller */
830
static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
831
{
832 833 834 835
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	_omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
			ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
836 837 838 839
			DSI_CIO_IRQ_ERROR_MASK,
			DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
}

840
static void _dsi_initialize_irq(struct platform_device *dsidev)
841
{
842
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
843 844 845
	unsigned long flags;
	int vc;

846
	spin_lock_irqsave(&dsi->irq_lock, flags);
847

848
	memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
849

850
	_omap_dsi_set_irqs(dsidev);
851
	for (vc = 0; vc < 4; ++vc)
852 853
		_omap_dsi_set_irqs_vc(dsidev, vc);
	_omap_dsi_set_irqs_cio(dsidev);
854

855
	spin_unlock_irqrestore(&dsi->irq_lock, flags);
856
}
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static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
		struct dsi_isr_data *isr_array, unsigned isr_array_size)
{
	struct dsi_isr_data *isr_data;
	int free_idx;
	int i;

	BUG_ON(isr == NULL);

	/* check for duplicate entry and find a free slot */
	free_idx = -1;
	for (i = 0; i < isr_array_size; i++) {
		isr_data = &isr_array[i];

		if (isr_data->isr == isr && isr_data->arg == arg &&
				isr_data->mask == mask) {
			return -EINVAL;
		}

		if (isr_data->isr == NULL && free_idx == -1)
			free_idx = i;
	}

	if (free_idx == -1)
		return -EBUSY;

	isr_data = &isr_array[free_idx];
	isr_data->isr = isr;
	isr_data->arg = arg;
	isr_data->mask = mask;

	return 0;
}

static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
		struct dsi_isr_data *isr_array, unsigned isr_array_size)
{
	struct dsi_isr_data *isr_data;
	int i;

	for (i = 0; i < isr_array_size; i++) {
		isr_data = &isr_array[i];
		if (isr_data->isr != isr || isr_data->arg != arg ||
				isr_data->mask != mask)
			continue;

		isr_data->isr = NULL;
		isr_data->arg = NULL;
		isr_data->mask = 0;

		return 0;
	}

	return -EINVAL;
}

914 915
static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
		void *arg, u32 mask)
916
{
917
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
918 919 920
	unsigned long flags;
	int r;

921
	spin_lock_irqsave(&dsi->irq_lock, flags);
922

923 924
	r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
			ARRAY_SIZE(dsi->isr_tables.isr_table));
925 926

	if (r == 0)
927
		_omap_dsi_set_irqs(dsidev);
928

929
	spin_unlock_irqrestore(&dsi->irq_lock, flags);
930 931 932 933

	return r;
}

934 935
static int dsi_unregister_isr(struct platform_device *dsidev,
		omap_dsi_isr_t isr, void *arg, u32 mask)
936
{
937
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
938 939 940
	unsigned long flags;
	int r;

941
	spin_lock_irqsave(&dsi->irq_lock, flags);
942

943 944
	r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
			ARRAY_SIZE(dsi->isr_tables.isr_table));
945 946

	if (r == 0)
947
		_omap_dsi_set_irqs(dsidev);
948

949
	spin_unlock_irqrestore(&dsi->irq_lock, flags);
950 951 952 953

	return r;
}

954 955
static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
		omap_dsi_isr_t isr, void *arg, u32 mask)
956
{
957
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
958 959 960
	unsigned long flags;
	int r;

961
	spin_lock_irqsave(&dsi->irq_lock, flags);
962 963

	r = _dsi_register_isr(isr, arg, mask,
964 965
			dsi->isr_tables.isr_table_vc[channel],
			ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
966 967

	if (r == 0)
968
		_omap_dsi_set_irqs_vc(dsidev, channel);
969

970
	spin_unlock_irqrestore(&dsi->irq_lock, flags);
971 972 973 974

	return r;
}

975 976
static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
		omap_dsi_isr_t isr, void *arg, u32 mask)
977
{
978
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
979 980 981
	unsigned long flags;
	int r;

982
	spin_lock_irqsave(&dsi->irq_lock, flags);
983 984

	r = _dsi_unregister_isr(isr, arg, mask,
985 986
			dsi->isr_tables.isr_table_vc[channel],
			ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
987 988

	if (r == 0)
989
		_omap_dsi_set_irqs_vc(dsidev, channel);
990

991
	spin_unlock_irqrestore(&dsi->irq_lock, flags);
992 993 994 995

	return r;
}

996 997
static int dsi_register_isr_cio(struct platform_device *dsidev,
		omap_dsi_isr_t isr, void *arg, u32 mask)
998
{
999
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1000 1001 1002
	unsigned long flags;
	int r;

1003
	spin_lock_irqsave(&dsi->irq_lock, flags);
1004

1005 1006
	r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
			ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1007 1008

	if (r == 0)
1009
		_omap_dsi_set_irqs_cio(dsidev);
1010

1011
	spin_unlock_irqrestore(&dsi->irq_lock, flags);
1012 1013 1014 1015

	return r;
}

1016 1017
static int dsi_unregister_isr_cio(struct platform_device *dsidev,
		omap_dsi_isr_t isr, void *arg, u32 mask)
1018
{
1019
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1020 1021 1022
	unsigned long flags;
	int r;

1023
	spin_lock_irqsave(&dsi->irq_lock, flags);
1024

1025 1026
	r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
			ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1027 1028

	if (r == 0)
1029
		_omap_dsi_set_irqs_cio(dsidev);
1030

1031
	spin_unlock_irqrestore(&dsi->irq_lock, flags);
1032 1033

	return r;
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}

1036
static u32 dsi_get_errors(struct platform_device *dsidev)
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{
1038
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
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	unsigned long flags;
	u32 e;
1041 1042 1043 1044
	spin_lock_irqsave(&dsi->errors_lock, flags);
	e = dsi->errors;
	dsi->errors = 0;
	spin_unlock_irqrestore(&dsi->errors_lock, flags);
T
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	return e;
}

1048
int dsi_runtime_get(struct platform_device *dsidev)
T
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1049
{
1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068
	int r;
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	DSSDBG("dsi_runtime_get\n");

	r = pm_runtime_get_sync(&dsi->pdev->dev);
	WARN_ON(r < 0);
	return r < 0 ? r : 0;
}

void dsi_runtime_put(struct platform_device *dsidev)
{
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
	int r;

	DSSDBG("dsi_runtime_put\n");

	r = pm_runtime_put(&dsi->pdev->dev);
	WARN_ON(r < 0);
T
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}

/* source clock for DSI PLL. this could also be PCLKFREE */
1072 1073
static inline void dsi_enable_pll_clock(struct platform_device *dsidev,
		bool enable)
T
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1074
{
1075 1076
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

T
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1077
	if (enable)
1078
		clk_enable(dsi->sys_clk);
T
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1079
	else
1080
		clk_disable(dsi->sys_clk);
T
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1081

1082
	if (enable && dsi->pll_locked) {
1083
		if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1)
T
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1084 1085 1086 1087 1088
			DSSERR("cannot lock PLL when enabling clocks\n");
	}
}

#ifdef DEBUG
1089
static void _dsi_print_reset_status(struct platform_device *dsidev)
T
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1090 1091
{
	u32 l;
1092
	int b0, b1, b2;
T
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1093 1094 1095 1096 1097 1098 1099

	if (!dss_debug)
		return;

	/* A dummy read using the SCP interface to any DSIPHY register is
	 * required after DSIPHY reset to complete the reset of the DSI complex
	 * I/O. */
1100
	l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
T
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1101 1102 1103

	printk(KERN_DEBUG "DSI resets: ");

1104
	l = dsi_read_reg(dsidev, DSI_PLL_STATUS);
T
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1105 1106
	printk("PLL (%d) ", FLD_GET(l, 0, 0));

1107
	l = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
T
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1108 1109
	printk("CIO (%d) ", FLD_GET(l, 29, 29));

1110 1111 1112 1113 1114 1115 1116 1117 1118 1119
	if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
		b0 = 28;
		b1 = 27;
		b2 = 26;
	} else {
		b0 = 24;
		b1 = 25;
		b2 = 26;
	}

1120
	l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1121 1122 1123 1124
	printk("PHY (%x%x%x, %d, %d, %d)\n",
			FLD_GET(l, b0, b0),
			FLD_GET(l, b1, b1),
			FLD_GET(l, b2, b2),
T
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1125 1126 1127 1128 1129
			FLD_GET(l, 29, 29),
			FLD_GET(l, 30, 30),
			FLD_GET(l, 31, 31));
}
#else
1130
#define _dsi_print_reset_status(x)
T
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#endif

1133
static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
T
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1134 1135 1136 1137
{
	DSSDBG("dsi_if_enable(%d)\n", enable);

	enable = enable ? 1 : 0;
1138
	REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
T
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1139

1140
	if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
T
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1141 1142 1143 1144 1145 1146 1147
			DSSERR("Failed to set dsi_if_enable to %d\n", enable);
			return -EIO;
	}

	return 0;
}

1148
unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
T
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1149
{
1150 1151 1152
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk;
T
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}

1155
static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
T
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1156
{
1157 1158 1159
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk;
T
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}

1162
static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
T
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1163
{
1164 1165 1166
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	return dsi->current_cinfo.clkin4ddr / 16;
T
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1167 1168
}

1169
static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
T
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1170 1171
{
	unsigned long r;
1172
	int dsi_module = dsi_get_dsidev_id(dsidev);
1173
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
T
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1174

1175
	if (dss_get_dsi_clk_source(dsi_module) == OMAP_DSS_CLK_SRC_FCK) {
1176
		/* DSI FCLK source is DSS_CLK_FCK */
1177
		r = clk_get_rate(dsi->dss_clk);
T
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1178
	} else {
1179
		/* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1180
		r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
T
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1181 1182 1183 1184 1185 1186 1187
	}

	return r;
}

static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
{
1188
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
1189
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
T
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1190 1191 1192 1193
	unsigned long dsi_fclk;
	unsigned lp_clk_div;
	unsigned long lp_clk;

1194
	lp_clk_div = dssdev->clocks.dsi.lp_clk_div;
T
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1195

1196
	if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max)
T
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1197 1198
		return -EINVAL;

1199
	dsi_fclk = dsi_fclk_rate(dsidev);
T
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1200 1201 1202 1203

	lp_clk = dsi_fclk / 2 / lp_clk_div;

	DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1204 1205
	dsi->current_cinfo.lp_clk = lp_clk;
	dsi->current_cinfo.lp_clk_div = lp_clk_div;
T
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1206

1207 1208
	/* LP_CLK_DIVISOR */
	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
T
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1210 1211
	/* LP_RX_SYNCHRO_ENABLE */
	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
T
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1212 1213 1214 1215

	return 0;
}

1216
static void dsi_enable_scp_clk(struct platform_device *dsidev)
1217
{
1218 1219 1220
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	if (dsi->scp_clk_refcount++ == 0)
1221
		REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1222 1223
}

1224
static void dsi_disable_scp_clk(struct platform_device *dsidev)
1225
{
1226 1227 1228 1229
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	WARN_ON(dsi->scp_clk_refcount == 0);
	if (--dsi->scp_clk_refcount == 0)
1230
		REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1231
}
T
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1232 1233 1234 1235 1236 1237 1238 1239

enum dsi_pll_power_state {
	DSI_PLL_POWER_OFF	= 0x0,
	DSI_PLL_POWER_ON_HSCLK	= 0x1,
	DSI_PLL_POWER_ON_ALL	= 0x2,
	DSI_PLL_POWER_ON_DIV	= 0x3,
};

1240 1241
static int dsi_pll_power(struct platform_device *dsidev,
		enum dsi_pll_power_state state)
T
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1242 1243 1244
{
	int t = 0;

1245 1246 1247 1248 1249
	/* DSI-PLL power command 0x3 is not working */
	if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
			state == DSI_PLL_POWER_ON_DIV)
		state = DSI_PLL_POWER_ON_ALL;

1250 1251
	/* PLL_PWR_CMD */
	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
T
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1252 1253

	/* PLL_PWR_STATUS */
1254
	while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1255
		if (++t > 1000) {
T
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			DSSERR("Failed to set DSI PLL power mode to %d\n",
					state);
			return -ENODEV;
		}
1260
		udelay(1);
T
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1261 1262 1263 1264 1265 1266
	}

	return 0;
}

/* calculate clock rates using dividers in cinfo */
1267 1268
static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
		struct dsi_clock_info *cinfo)
T
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1269
{
1270 1271 1272 1273
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)
T
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1274 1275
		return -EINVAL;

1276
	if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max)
T
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1277 1278
		return -EINVAL;

1279
	if (cinfo->regm_dispc > dsi->regm_dispc_max)
T
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1280 1281
		return -EINVAL;

1282
	if (cinfo->regm_dsi > dsi->regm_dsi_max)
T
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1283 1284
		return -EINVAL;

1285
	if (cinfo->use_sys_clk) {
1286
		cinfo->clkin = clk_get_rate(dsi->sys_clk);
T
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1287
		/* XXX it is unclear if highfreq should be used
1288
		 * with DSS_SYS_CLK source also */
T
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1289 1290
		cinfo->highfreq = 0;
	} else {
1291
		cinfo->clkin = dispc_mgr_pclk_rate(dssdev->manager->id);
T
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1292 1293 1294 1295 1296 1297 1298 1299 1300

		if (cinfo->clkin < 32000000)
			cinfo->highfreq = 0;
		else
			cinfo->highfreq = 1;
	}

	cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1));

1301
	if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min)
T
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1302 1303 1304 1305 1306 1307 1308
		return -EINVAL;

	cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;

	if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
		return -EINVAL;

1309 1310 1311
	if (cinfo->regm_dispc > 0)
		cinfo->dsi_pll_hsdiv_dispc_clk =
			cinfo->clkin4ddr / cinfo->regm_dispc;
T
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1312
	else
1313
		cinfo->dsi_pll_hsdiv_dispc_clk = 0;
T
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1314

1315 1316 1317
	if (cinfo->regm_dsi > 0)
		cinfo->dsi_pll_hsdiv_dsi_clk =
			cinfo->clkin4ddr / cinfo->regm_dsi;
T
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1318
	else
1319
		cinfo->dsi_pll_hsdiv_dsi_clk = 0;
T
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1320 1321 1322 1323

	return 0;
}

1324 1325
int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
		unsigned long req_pck, struct dsi_clock_info *dsi_cinfo,
T
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1326 1327
		struct dispc_clock_info *dispc_cinfo)
{
1328
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
T
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1329 1330 1331 1332
	struct dsi_clock_info cur, best;
	struct dispc_clock_info best_dispc;
	int min_fck_per_pck;
	int match = 0;
1333
	unsigned long dss_sys_clk, max_dss_fck;
T
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1334

1335
	dss_sys_clk = clk_get_rate(dsi->sys_clk);
T
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1336

1337
	max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1338

1339 1340
	if (req_pck == dsi->cache_req_pck &&
			dsi->cache_cinfo.clkin == dss_sys_clk) {
T
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1341
		DSSDBG("DSI clock info found from cache\n");
1342
		*dsi_cinfo = dsi->cache_cinfo;
1343 1344
		dispc_find_clk_divs(is_tft, req_pck,
			dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo);
T
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1345 1346 1347 1348 1349 1350
		return 0;
	}

	min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;

	if (min_fck_per_pck &&
1351
		req_pck * min_fck_per_pck > max_dss_fck) {
T
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1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364
		DSSERR("Requested pixel clock not possible with the current "
				"OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
				"the constraint off.\n");
		min_fck_per_pck = 0;
	}

	DSSDBG("dsi_pll_calc\n");

retry:
	memset(&best, 0, sizeof(best));
	memset(&best_dispc, 0, sizeof(best_dispc));

	memset(&cur, 0, sizeof(cur));
1365 1366
	cur.clkin = dss_sys_clk;
	cur.use_sys_clk = 1;
T
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1367 1368 1369 1370 1371
	cur.highfreq = 0;

	/* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
	/* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
	/* To reduce PLL lock time, keep Fint high (around 2 MHz) */
1372
	for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
T
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1373 1374 1375 1376 1377
		if (cur.highfreq == 0)
			cur.fint = cur.clkin / cur.regn;
		else
			cur.fint = cur.clkin / (2 * cur.regn);

1378
		if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
T
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1379 1380 1381
			continue;

		/* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
1382
		for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
T
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1383 1384 1385 1386 1387 1388 1389 1390 1391
			unsigned long a, b;

			a = 2 * cur.regm * (cur.clkin/1000);
			b = cur.regn * (cur.highfreq + 1);
			cur.clkin4ddr = a / b * 1000;

			if (cur.clkin4ddr > 1800 * 1000 * 1000)
				break;

1392 1393
			/* dsi_pll_hsdiv_dispc_clk(MHz) =
			 * DSIPHY(MHz) / regm_dispc  < 173MHz/186Mhz */
1394 1395
			for (cur.regm_dispc = 1; cur.regm_dispc <
					dsi->regm_dispc_max; ++cur.regm_dispc) {
T
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1396
				struct dispc_clock_info cur_dispc;
1397 1398
				cur.dsi_pll_hsdiv_dispc_clk =
					cur.clkin4ddr / cur.regm_dispc;
T
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1399 1400 1401 1402

				/* this will narrow down the search a bit,
				 * but still give pixclocks below what was
				 * requested */
1403
				if (cur.dsi_pll_hsdiv_dispc_clk  < req_pck)
T
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1404 1405
					break;

1406
				if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck)
T
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1407 1408 1409
					continue;

				if (min_fck_per_pck &&
1410
					cur.dsi_pll_hsdiv_dispc_clk <
T
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1411 1412 1413 1414 1415 1416
						req_pck * min_fck_per_pck)
					continue;

				match = 1;

				dispc_find_clk_divs(is_tft, req_pck,
1417
						cur.dsi_pll_hsdiv_dispc_clk,
T
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1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445
						&cur_dispc);

				if (abs(cur_dispc.pck - req_pck) <
						abs(best_dispc.pck - req_pck)) {
					best = cur;
					best_dispc = cur_dispc;

					if (cur_dispc.pck == req_pck)
						goto found;
				}
			}
		}
	}
found:
	if (!match) {
		if (min_fck_per_pck) {
			DSSERR("Could not find suitable clock settings.\n"
					"Turning FCK/PCK constraint off and"
					"trying again.\n");
			min_fck_per_pck = 0;
			goto retry;
		}

		DSSERR("Could not find suitable clock settings.\n");

		return -EINVAL;
	}

1446 1447 1448
	/* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
	best.regm_dsi = 0;
	best.dsi_pll_hsdiv_dsi_clk = 0;
T
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1449 1450 1451 1452 1453 1454

	if (dsi_cinfo)
		*dsi_cinfo = best;
	if (dispc_cinfo)
		*dispc_cinfo = best_dispc;

1455 1456 1457
	dsi->cache_req_pck = req_pck;
	dsi->cache_clk_freq = 0;
	dsi->cache_cinfo = best;
T
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1458 1459 1460 1461

	return 0;
}

1462 1463
int dsi_pll_set_clock_div(struct platform_device *dsidev,
		struct dsi_clock_info *cinfo)
T
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1464
{
1465
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
T
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1466 1467
	int r = 0;
	u32 l;
1468
	int f = 0;
1469 1470
	u8 regn_start, regn_end, regm_start, regm_end;
	u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
T
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1471 1472 1473

	DSSDBGF();

1474 1475
	dsi->current_cinfo.use_sys_clk = cinfo->use_sys_clk;
	dsi->current_cinfo.highfreq = cinfo->highfreq;
1476

1477 1478 1479
	dsi->current_cinfo.fint = cinfo->fint;
	dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
	dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk =
1480
			cinfo->dsi_pll_hsdiv_dispc_clk;
1481
	dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk =
1482
			cinfo->dsi_pll_hsdiv_dsi_clk;
T
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1484 1485 1486 1487
	dsi->current_cinfo.regn = cinfo->regn;
	dsi->current_cinfo.regm = cinfo->regm;
	dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
	dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
T
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1488 1489 1490 1491

	DSSDBG("DSI Fint %ld\n", cinfo->fint);

	DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
1492
			cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree",
T
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1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508
			cinfo->clkin,
			cinfo->highfreq);

	/* DSIPHY == CLKIN4DDR */
	DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n",
			cinfo->regm,
			cinfo->regn,
			cinfo->clkin,
			cinfo->highfreq + 1,
			cinfo->clkin4ddr);

	DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
			cinfo->clkin4ddr / 1000 / 1000 / 2);

	DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);

1509
	DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1510 1511
		dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
		dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1512 1513
		cinfo->dsi_pll_hsdiv_dispc_clk);
	DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1514 1515
		dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
		dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1516
		cinfo->dsi_pll_hsdiv_dsi_clk);
T
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1517

1518 1519 1520 1521 1522 1523 1524
	dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, &regn_start, &regn_end);
	dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, &regm_start, &regm_end);
	dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, &regm_dispc_start,
			&regm_dispc_end);
	dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, &regm_dsi_start,
			&regm_dsi_end);

1525 1526
	/* DSI_PLL_AUTOMODE = manual */
	REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0);
T
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1527

1528
	l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1);
T
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1529
	l = FLD_MOD(l, 1, 0, 0);		/* DSI_PLL_STOPMODE */
1530 1531 1532 1533 1534
	/* DSI_PLL_REGN */
	l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
	/* DSI_PLL_REGM */
	l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
	/* DSI_CLOCK_DIV */
1535
	l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1536 1537
			regm_dispc_start, regm_dispc_end);
	/* DSIPROTO_CLOCK_DIV */
1538
	l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1539
			regm_dsi_start, regm_dsi_end);
1540
	dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l);
T
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1541

1542
	BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
1543 1544 1545 1546 1547 1548 1549 1550

	if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
		f = cinfo->fint < 1000000 ? 0x3 :
			cinfo->fint < 1250000 ? 0x4 :
			cinfo->fint < 1500000 ? 0x5 :
			cinfo->fint < 1750000 ? 0x6 :
			0x7;
	}
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1551

1552
	l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1553 1554 1555

	if (dss_has_feature(FEAT_DSI_PLL_FREQSEL))
		l = FLD_MOD(l, f, 4, 1);	/* DSI_PLL_FREQSEL */
1556
	l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1,
T
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1557 1558 1559 1560 1561 1562
			11, 11);		/* DSI_PLL_CLKSEL */
	l = FLD_MOD(l, cinfo->highfreq,
			12, 12);		/* DSI_PLL_HIGHFREQ */
	l = FLD_MOD(l, 1, 13, 13);		/* DSI_PLL_REFEN */
	l = FLD_MOD(l, 0, 14, 14);		/* DSIPHY_CLKINEN */
	l = FLD_MOD(l, 1, 20, 20);		/* DSI_HSDIVBYPASS */
1563
	dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
T
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1564

1565
	REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0);	/* DSI_PLL_GO */
T
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1566

1567
	if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) {
T
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1568 1569 1570 1571 1572
		DSSERR("dsi pll go bit not going down.\n");
		r = -EIO;
		goto err;
	}

1573
	if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) {
T
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1574 1575 1576 1577 1578
		DSSERR("cannot lock PLL\n");
		r = -EIO;
		goto err;
	}

1579
	dsi->pll_locked = 1;
T
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1580

1581
	l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
T
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1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595
	l = FLD_MOD(l, 0, 0, 0);	/* DSI_PLL_IDLE */
	l = FLD_MOD(l, 0, 5, 5);	/* DSI_PLL_PLLLPMODE */
	l = FLD_MOD(l, 0, 6, 6);	/* DSI_PLL_LOWCURRSTBY */
	l = FLD_MOD(l, 0, 7, 7);	/* DSI_PLL_TIGHTPHASELOCK */
	l = FLD_MOD(l, 0, 8, 8);	/* DSI_PLL_DRIFTGUARDEN */
	l = FLD_MOD(l, 0, 10, 9);	/* DSI_PLL_LOCKSEL */
	l = FLD_MOD(l, 1, 13, 13);	/* DSI_PLL_REFEN */
	l = FLD_MOD(l, 1, 14, 14);	/* DSIPHY_CLKINEN */
	l = FLD_MOD(l, 0, 15, 15);	/* DSI_BYPASSEN */
	l = FLD_MOD(l, 1, 16, 16);	/* DSS_CLOCK_EN */
	l = FLD_MOD(l, 0, 17, 17);	/* DSS_CLOCK_PWDN */
	l = FLD_MOD(l, 1, 18, 18);	/* DSI_PROTO_CLOCK_EN */
	l = FLD_MOD(l, 0, 19, 19);	/* DSI_PROTO_CLOCK_PWDN */
	l = FLD_MOD(l, 0, 20, 20);	/* DSI_HSDIVBYPASS */
1596
	dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
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1597 1598 1599 1600 1601 1602

	DSSDBG("PLL config done\n");
err:
	return r;
}

1603 1604
int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
		bool enable_hsdiv)
T
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1605
{
1606
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
T
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1607 1608 1609 1610 1611
	int r = 0;
	enum dsi_pll_power_state pwstate;

	DSSDBG("PLL init\n");

1612
	if (dsi->vdds_dsi_reg == NULL) {
1613 1614
		struct regulator *vdds_dsi;

1615
		vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
1616 1617 1618 1619 1620 1621

		if (IS_ERR(vdds_dsi)) {
			DSSERR("can't get VDDS_DSI regulator\n");
			return PTR_ERR(vdds_dsi);
		}

1622
		dsi->vdds_dsi_reg = vdds_dsi;
1623 1624
	}

1625
	dsi_enable_pll_clock(dsidev, 1);
1626 1627 1628
	/*
	 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
	 */
1629
	dsi_enable_scp_clk(dsidev);
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1630

1631 1632
	if (!dsi->vdds_dsi_enabled) {
		r = regulator_enable(dsi->vdds_dsi_reg);
1633 1634
		if (r)
			goto err0;
1635
		dsi->vdds_dsi_enabled = true;
1636
	}
T
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1637 1638 1639 1640

	/* XXX PLL does not come out of reset without this... */
	dispc_pck_free_enable(1);

1641
	if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
T
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1642 1643
		DSSERR("PLL not coming out of reset.\n");
		r = -ENODEV;
1644
		dispc_pck_free_enable(0);
T
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1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660
		goto err1;
	}

	/* XXX ... but if left on, we get problems when planes do not
	 * fill the whole display. No idea about this */
	dispc_pck_free_enable(0);

	if (enable_hsclk && enable_hsdiv)
		pwstate = DSI_PLL_POWER_ON_ALL;
	else if (enable_hsclk)
		pwstate = DSI_PLL_POWER_ON_HSCLK;
	else if (enable_hsdiv)
		pwstate = DSI_PLL_POWER_ON_DIV;
	else
		pwstate = DSI_PLL_POWER_OFF;

1661
	r = dsi_pll_power(dsidev, pwstate);
T
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1662 1663 1664 1665 1666 1667 1668 1669

	if (r)
		goto err1;

	DSSDBG("PLL init done\n");

	return 0;
err1:
1670 1671 1672
	if (dsi->vdds_dsi_enabled) {
		regulator_disable(dsi->vdds_dsi_reg);
		dsi->vdds_dsi_enabled = false;
1673
	}
T
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1674
err0:
1675 1676
	dsi_disable_scp_clk(dsidev);
	dsi_enable_pll_clock(dsidev, 0);
T
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1677 1678 1679
	return r;
}

1680
void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
T
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1681
{
1682 1683 1684
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	dsi->pll_locked = 0;
1685
	dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1686
	if (disconnect_lanes) {
1687 1688 1689
		WARN_ON(!dsi->vdds_dsi_enabled);
		regulator_disable(dsi->vdds_dsi_reg);
		dsi->vdds_dsi_enabled = false;
1690
	}
1691

1692 1693
	dsi_disable_scp_clk(dsidev);
	dsi_enable_pll_clock(dsidev, 0);
1694

T
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1695 1696 1697
	DSSDBG("PLL uninit done\n");
}

1698 1699
static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
		struct seq_file *s)
T
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1700
{
1701 1702
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
	struct dsi_clock_info *cinfo = &dsi->current_cinfo;
1703
	enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1704
	int dsi_module = dsi_get_dsidev_id(dsidev);
1705 1706

	dispc_clk_src = dss_get_dispc_clk_source();
1707
	dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
T
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1708

1709 1710
	if (dsi_runtime_get(dsidev))
		return;
T
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1711

1712
	seq_printf(s,	"- DSI%d PLL -\n", dsi_module + 1);
T
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1713 1714

	seq_printf(s,	"dsi pll source = %s\n",
1715
			cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree");
T
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1716 1717 1718 1719 1720 1721

	seq_printf(s,	"Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);

	seq_printf(s,	"CLKIN4DDR\t%-16luregm %u\n",
			cinfo->clkin4ddr, cinfo->regm);

1722
	seq_printf(s,	"%s (%s)\t%-16luregm_dispc %u\t(%s)\n",
1723 1724
			dss_get_generic_clk_source_name(dispc_clk_src),
			dss_feat_get_clk_source_name(dispc_clk_src),
1725 1726
			cinfo->dsi_pll_hsdiv_dispc_clk,
			cinfo->regm_dispc,
1727
			dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1728
			"off" : "on");
T
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1729

1730
	seq_printf(s,	"%s (%s)\t%-16luregm_dsi %u\t(%s)\n",
1731 1732
			dss_get_generic_clk_source_name(dsi_clk_src),
			dss_feat_get_clk_source_name(dsi_clk_src),
1733 1734
			cinfo->dsi_pll_hsdiv_dsi_clk,
			cinfo->regm_dsi,
1735
			dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1736
			"off" : "on");
T
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1737

1738
	seq_printf(s,	"- DSI%d -\n", dsi_module + 1);
T
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1739

1740 1741 1742
	seq_printf(s,	"dsi fclk source = %s (%s)\n",
			dss_get_generic_clk_source_name(dsi_clk_src),
			dss_feat_get_clk_source_name(dsi_clk_src));
T
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1743

1744
	seq_printf(s,	"DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
T
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1745 1746 1747 1748

	seq_printf(s,	"DDR_CLK\t\t%lu\n",
			cinfo->clkin4ddr / 4);

1749
	seq_printf(s,	"TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
T
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1750 1751 1752

	seq_printf(s,	"LP_CLK\t\t%lu\n", cinfo->lp_clk);

1753
	dsi_runtime_put(dsidev);
T
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1754 1755
}

1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767
void dsi_dump_clocks(struct seq_file *s)
{
	struct platform_device *dsidev;
	int i;

	for  (i = 0; i < MAX_NUM_DSI; i++) {
		dsidev = dsi_get_dsidev_from_id(i);
		if (dsidev)
			dsi_dump_dsidev_clocks(dsidev, s);
	}
}

1768
#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1769 1770
static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
		struct seq_file *s)
1771
{
1772
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1773 1774
	unsigned long flags;
	struct dsi_irq_stats stats;
1775
	int dsi_module = dsi_get_dsidev_id(dsidev);
1776

1777
	spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1778

1779 1780 1781
	stats = dsi->irq_stats;
	memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
	dsi->irq_stats.last_reset = jiffies;
1782

1783
	spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1784 1785 1786 1787 1788 1789 1790 1791

	seq_printf(s, "period %u ms\n",
			jiffies_to_msecs(jiffies - stats.last_reset));

	seq_printf(s, "irqs %d\n", stats.irq_count);
#define PIS(x) \
	seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);

1792
	seq_printf(s, "-- DSI%d interrupts --\n", dsi_module + 1);
1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858
	PIS(VC0);
	PIS(VC1);
	PIS(VC2);
	PIS(VC3);
	PIS(WAKEUP);
	PIS(RESYNC);
	PIS(PLL_LOCK);
	PIS(PLL_UNLOCK);
	PIS(PLL_RECALL);
	PIS(COMPLEXIO_ERR);
	PIS(HS_TX_TIMEOUT);
	PIS(LP_RX_TIMEOUT);
	PIS(TE_TRIGGER);
	PIS(ACK_TRIGGER);
	PIS(SYNC_LOST);
	PIS(LDO_POWER_GOOD);
	PIS(TA_TIMEOUT);
#undef PIS

#define PIS(x) \
	seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
			stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
			stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
			stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
			stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);

	seq_printf(s, "-- VC interrupts --\n");
	PIS(CS);
	PIS(ECC_CORR);
	PIS(PACKET_SENT);
	PIS(FIFO_TX_OVF);
	PIS(FIFO_RX_OVF);
	PIS(BTA);
	PIS(ECC_NO_CORR);
	PIS(FIFO_TX_UDF);
	PIS(PP_BUSY_CHANGE);
#undef PIS

#define PIS(x) \
	seq_printf(s, "%-20s %10d\n", #x, \
			stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);

	seq_printf(s, "-- CIO interrupts --\n");
	PIS(ERRSYNCESC1);
	PIS(ERRSYNCESC2);
	PIS(ERRSYNCESC3);
	PIS(ERRESC1);
	PIS(ERRESC2);
	PIS(ERRESC3);
	PIS(ERRCONTROL1);
	PIS(ERRCONTROL2);
	PIS(ERRCONTROL3);
	PIS(STATEULPS1);
	PIS(STATEULPS2);
	PIS(STATEULPS3);
	PIS(ERRCONTENTIONLP0_1);
	PIS(ERRCONTENTIONLP1_1);
	PIS(ERRCONTENTIONLP0_2);
	PIS(ERRCONTENTIONLP1_2);
	PIS(ERRCONTENTIONLP0_3);
	PIS(ERRCONTENTIONLP1_3);
	PIS(ULPSACTIVENOT_ALL0);
	PIS(ULPSACTIVENOT_ALL1);
#undef PIS
}

1859
static void dsi1_dump_irqs(struct seq_file *s)
T
Tomi Valkeinen 已提交
1860
{
1861 1862
	struct platform_device *dsidev = dsi_get_dsidev_from_id(0);

1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892
	dsi_dump_dsidev_irqs(dsidev, s);
}

static void dsi2_dump_irqs(struct seq_file *s)
{
	struct platform_device *dsidev = dsi_get_dsidev_from_id(1);

	dsi_dump_dsidev_irqs(dsidev, s);
}

void dsi_create_debugfs_files_irq(struct dentry *debugfs_dir,
		const struct file_operations *debug_fops)
{
	struct platform_device *dsidev;

	dsidev = dsi_get_dsidev_from_id(0);
	if (dsidev)
		debugfs_create_file("dsi1_irqs", S_IRUGO, debugfs_dir,
			&dsi1_dump_irqs, debug_fops);

	dsidev = dsi_get_dsidev_from_id(1);
	if (dsidev)
		debugfs_create_file("dsi2_irqs", S_IRUGO, debugfs_dir,
			&dsi2_dump_irqs, debug_fops);
}
#endif

static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
		struct seq_file *s)
{
1893
#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
T
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1894

1895 1896
	if (dsi_runtime_get(dsidev))
		return;
1897
	dsi_enable_scp_clk(dsidev);
T
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1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968

	DUMPREG(DSI_REVISION);
	DUMPREG(DSI_SYSCONFIG);
	DUMPREG(DSI_SYSSTATUS);
	DUMPREG(DSI_IRQSTATUS);
	DUMPREG(DSI_IRQENABLE);
	DUMPREG(DSI_CTRL);
	DUMPREG(DSI_COMPLEXIO_CFG1);
	DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
	DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
	DUMPREG(DSI_CLK_CTRL);
	DUMPREG(DSI_TIMING1);
	DUMPREG(DSI_TIMING2);
	DUMPREG(DSI_VM_TIMING1);
	DUMPREG(DSI_VM_TIMING2);
	DUMPREG(DSI_VM_TIMING3);
	DUMPREG(DSI_CLK_TIMING);
	DUMPREG(DSI_TX_FIFO_VC_SIZE);
	DUMPREG(DSI_RX_FIFO_VC_SIZE);
	DUMPREG(DSI_COMPLEXIO_CFG2);
	DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
	DUMPREG(DSI_VM_TIMING4);
	DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
	DUMPREG(DSI_VM_TIMING5);
	DUMPREG(DSI_VM_TIMING6);
	DUMPREG(DSI_VM_TIMING7);
	DUMPREG(DSI_STOPCLK_TIMING);

	DUMPREG(DSI_VC_CTRL(0));
	DUMPREG(DSI_VC_TE(0));
	DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
	DUMPREG(DSI_VC_IRQSTATUS(0));
	DUMPREG(DSI_VC_IRQENABLE(0));

	DUMPREG(DSI_VC_CTRL(1));
	DUMPREG(DSI_VC_TE(1));
	DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
	DUMPREG(DSI_VC_IRQSTATUS(1));
	DUMPREG(DSI_VC_IRQENABLE(1));

	DUMPREG(DSI_VC_CTRL(2));
	DUMPREG(DSI_VC_TE(2));
	DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
	DUMPREG(DSI_VC_IRQSTATUS(2));
	DUMPREG(DSI_VC_IRQENABLE(2));

	DUMPREG(DSI_VC_CTRL(3));
	DUMPREG(DSI_VC_TE(3));
	DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
	DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
	DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
	DUMPREG(DSI_VC_IRQSTATUS(3));
	DUMPREG(DSI_VC_IRQENABLE(3));

	DUMPREG(DSI_DSIPHY_CFG0);
	DUMPREG(DSI_DSIPHY_CFG1);
	DUMPREG(DSI_DSIPHY_CFG2);
	DUMPREG(DSI_DSIPHY_CFG5);

	DUMPREG(DSI_PLL_CONTROL);
	DUMPREG(DSI_PLL_STATUS);
	DUMPREG(DSI_PLL_GO);
	DUMPREG(DSI_PLL_CONFIGURATION1);
	DUMPREG(DSI_PLL_CONFIGURATION2);

1969
	dsi_disable_scp_clk(dsidev);
1970
	dsi_runtime_put(dsidev);
T
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1971 1972 1973
#undef DUMPREG
}

1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002
static void dsi1_dump_regs(struct seq_file *s)
{
	struct platform_device *dsidev = dsi_get_dsidev_from_id(0);

	dsi_dump_dsidev_regs(dsidev, s);
}

static void dsi2_dump_regs(struct seq_file *s)
{
	struct platform_device *dsidev = dsi_get_dsidev_from_id(1);

	dsi_dump_dsidev_regs(dsidev, s);
}

void dsi_create_debugfs_files_reg(struct dentry *debugfs_dir,
		const struct file_operations *debug_fops)
{
	struct platform_device *dsidev;

	dsidev = dsi_get_dsidev_from_id(0);
	if (dsidev)
		debugfs_create_file("dsi1_regs", S_IRUGO, debugfs_dir,
			&dsi1_dump_regs, debug_fops);

	dsidev = dsi_get_dsidev_from_id(1);
	if (dsidev)
		debugfs_create_file("dsi2_regs", S_IRUGO, debugfs_dir,
			&dsi2_dump_regs, debug_fops);
}
2003
enum dsi_cio_power_state {
T
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2004 2005 2006 2007 2008
	DSI_COMPLEXIO_POWER_OFF		= 0x0,
	DSI_COMPLEXIO_POWER_ON		= 0x1,
	DSI_COMPLEXIO_POWER_ULPS	= 0x2,
};

2009 2010
static int dsi_cio_power(struct platform_device *dsidev,
		enum dsi_cio_power_state state)
T
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2011 2012 2013 2014
{
	int t = 0;

	/* PWR_CMD */
2015
	REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
T
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2016 2017

	/* PWR_STATUS */
2018 2019
	while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
			26, 25) != state) {
2020
		if (++t > 1000) {
T
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2021 2022 2023 2024
			DSSERR("failed to set complexio power state to "
					"%d\n", state);
			return -ENODEV;
		}
2025
		udelay(1);
T
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2026 2027 2028 2029 2030
	}

	return 0;
}

2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058
/* Number of data lanes present on DSI interface */
static inline int dsi_get_num_data_lanes(struct platform_device *dsidev)
{
	/* DSI on OMAP3 doesn't have register DSI_GNQ, set number
	 * of data lanes as 2 by default */
	if (dss_has_feature(FEAT_DSI_GNQ))
		return REG_GET(dsidev, DSI_GNQ, 11, 9);	/* NB_DATA_LANES */
	else
		return 2;
}

/* Number of data lanes used by the dss device */
static inline int dsi_get_num_data_lanes_dssdev(struct omap_dss_device *dssdev)
{
	int num_data_lanes = 0;

	if (dssdev->phy.dsi.data1_lane != 0)
		num_data_lanes++;
	if (dssdev->phy.dsi.data2_lane != 0)
		num_data_lanes++;
	if (dssdev->phy.dsi.data3_lane != 0)
		num_data_lanes++;
	if (dssdev->phy.dsi.data4_lane != 0)
		num_data_lanes++;

	return num_data_lanes;
}

2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089
static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
{
	int val;

	/* line buffer on OMAP3 is 1024 x 24bits */
	/* XXX: for some reason using full buffer size causes
	 * considerable TX slowdown with update sizes that fill the
	 * whole buffer */
	if (!dss_has_feature(FEAT_DSI_GNQ))
		return 1023 * 3;

	val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */

	switch (val) {
	case 1:
		return 512 * 3;		/* 512x24 bits */
	case 2:
		return 682 * 3;		/* 682x24 bits */
	case 3:
		return 853 * 3;		/* 853x24 bits */
	case 4:
		return 1024 * 3;	/* 1024x24 bits */
	case 5:
		return 1194 * 3;	/* 1194x24 bits */
	case 6:
		return 1365 * 3;	/* 1365x24 bits */
	default:
		BUG();
	}
}

2090
static void dsi_set_lane_config(struct omap_dss_device *dssdev)
T
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2091
{
2092
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
T
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2093
	u32 r;
2094
	int num_data_lanes_dssdev = dsi_get_num_data_lanes_dssdev(dssdev);
T
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2095 2096 2097 2098 2099 2100 2101 2102

	int clk_lane   = dssdev->phy.dsi.clk_lane;
	int data1_lane = dssdev->phy.dsi.data1_lane;
	int data2_lane = dssdev->phy.dsi.data2_lane;
	int clk_pol    = dssdev->phy.dsi.clk_pol;
	int data1_pol  = dssdev->phy.dsi.data1_pol;
	int data2_pol  = dssdev->phy.dsi.data2_pol;

2103
	r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
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2104 2105 2106 2107 2108 2109
	r = FLD_MOD(r, clk_lane, 2, 0);
	r = FLD_MOD(r, clk_pol, 3, 3);
	r = FLD_MOD(r, data1_lane, 6, 4);
	r = FLD_MOD(r, data1_pol, 7, 7);
	r = FLD_MOD(r, data2_lane, 10, 8);
	r = FLD_MOD(r, data2_pol, 11, 11);
2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123
	if (num_data_lanes_dssdev > 2) {
		int data3_lane  = dssdev->phy.dsi.data3_lane;
		int data3_pol  = dssdev->phy.dsi.data3_pol;

		r = FLD_MOD(r, data3_lane, 14, 12);
		r = FLD_MOD(r, data3_pol, 15, 15);
	}
	if (num_data_lanes_dssdev > 3) {
		int data4_lane  = dssdev->phy.dsi.data4_lane;
		int data4_pol  = dssdev->phy.dsi.data4_pol;

		r = FLD_MOD(r, data4_lane, 18, 16);
		r = FLD_MOD(r, data4_pol, 19, 19);
	}
2124
	dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
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2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137

	/* The configuration of the DSI complex I/O (number of data lanes,
	   position, differential order) should not be changed while
	   DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
	   the hardware to take into account a new configuration of the complex
	   I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
	   follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
	   then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
	   DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
	   DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
	   DSI complex I/O configuration is unknown. */

	/*
2138 2139 2140 2141
	REG_FLD_MOD(dsidev, DSI_CTRL, 1, 0, 0);
	REG_FLD_MOD(dsidev, DSI_CTRL, 0, 0, 0);
	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20);
	REG_FLD_MOD(dsidev, DSI_CTRL, 1, 0, 0);
T
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2142 2143 2144
	*/
}

2145
static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
T
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2146
{
2147 2148
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

T
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2149
	/* convert time in ns to ddr ticks, rounding up */
2150
	unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
T
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2151 2152 2153
	return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
}

2154
static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
T
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2155
{
2156 2157 2158
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
T
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2159 2160 2161
	return ddr * 1000 * 1000 / (ddr_clk / 1000);
}

2162
static void dsi_cio_timings(struct platform_device *dsidev)
T
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2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173
{
	u32 r;
	u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
	u32 tlpx_half, tclk_trail, tclk_zero;
	u32 tclk_prepare;

	/* calculate timings */

	/* 1 * DDR_CLK = 2 * UI */

	/* min 40ns + 4*UI	max 85ns + 6*UI */
2174
	ths_prepare = ns2ddr(dsidev, 70) + 2;
T
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2175 2176

	/* min 145ns + 10*UI */
2177
	ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
T
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2178 2179

	/* min max(8*UI, 60ns+4*UI) */
2180
	ths_trail = ns2ddr(dsidev, 60) + 5;
T
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2181 2182

	/* min 100ns */
2183
	ths_exit = ns2ddr(dsidev, 145);
T
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2184 2185

	/* tlpx min 50n */
2186
	tlpx_half = ns2ddr(dsidev, 25);
T
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2187 2188

	/* min 60ns */
2189
	tclk_trail = ns2ddr(dsidev, 60) + 2;
T
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2190 2191

	/* min 38ns, max 95ns */
2192
	tclk_prepare = ns2ddr(dsidev, 65);
T
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2193 2194

	/* min tclk-prepare + tclk-zero = 300ns */
2195
	tclk_zero = ns2ddr(dsidev, 260);
T
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2196 2197

	DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2198 2199
		ths_prepare, ddr2ns(dsidev, ths_prepare),
		ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
T
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2200
	DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2201 2202
			ths_trail, ddr2ns(dsidev, ths_trail),
			ths_exit, ddr2ns(dsidev, ths_exit));
T
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2203 2204 2205

	DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
			"tclk_zero %u (%uns)\n",
2206 2207 2208
			tlpx_half, ddr2ns(dsidev, tlpx_half),
			tclk_trail, ddr2ns(dsidev, tclk_trail),
			tclk_zero, ddr2ns(dsidev, tclk_zero));
T
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2209
	DSSDBG("tclk_prepare %u (%uns)\n",
2210
			tclk_prepare, ddr2ns(dsidev, tclk_prepare));
T
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2211 2212 2213

	/* program timings */

2214
	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
T
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2215 2216 2217 2218
	r = FLD_MOD(r, ths_prepare, 31, 24);
	r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
	r = FLD_MOD(r, ths_trail, 15, 8);
	r = FLD_MOD(r, ths_exit, 7, 0);
2219
	dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
T
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2220

2221
	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
T
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2222 2223 2224
	r = FLD_MOD(r, tlpx_half, 22, 16);
	r = FLD_MOD(r, tclk_trail, 15, 8);
	r = FLD_MOD(r, tclk_zero, 7, 0);
2225
	dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
T
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2226

2227
	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
T
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2228
	r = FLD_MOD(r, tclk_prepare, 7, 0);
2229
	dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
T
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2230 2231
}

2232
static void dsi_cio_enable_lane_override(struct omap_dss_device *dssdev,
2233 2234
		enum dsi_lane lanes)
{
2235
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2236
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2237 2238 2239
	int clk_lane   = dssdev->phy.dsi.clk_lane;
	int data1_lane = dssdev->phy.dsi.data1_lane;
	int data2_lane = dssdev->phy.dsi.data2_lane;
2240 2241
	int data3_lane = dssdev->phy.dsi.data3_lane;
	int data4_lane = dssdev->phy.dsi.data4_lane;
2242 2243 2244
	int clk_pol    = dssdev->phy.dsi.clk_pol;
	int data1_pol  = dssdev->phy.dsi.data1_pol;
	int data2_pol  = dssdev->phy.dsi.data2_pol;
2245 2246
	int data3_pol  = dssdev->phy.dsi.data3_pol;
	int data4_pol  = dssdev->phy.dsi.data4_pol;
2247 2248

	u32 l = 0;
2249
	u8 lptxscp_start = dsi->num_data_lanes == 2 ? 22 : 26;
2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265

	if (lanes & DSI_CLK_P)
		l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 0 : 1));
	if (lanes & DSI_CLK_N)
		l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 1 : 0));

	if (lanes & DSI_DATA1_P)
		l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 0 : 1));
	if (lanes & DSI_DATA1_N)
		l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 1 : 0));

	if (lanes & DSI_DATA2_P)
		l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 0 : 1));
	if (lanes & DSI_DATA2_N)
		l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 1 : 0));

2266 2267 2268 2269 2270 2271 2272 2273 2274
	if (lanes & DSI_DATA3_P)
		l |= 1 << ((data3_lane - 1) * 2 + (data3_pol ? 0 : 1));
	if (lanes & DSI_DATA3_N)
		l |= 1 << ((data3_lane - 1) * 2 + (data3_pol ? 1 : 0));

	if (lanes & DSI_DATA4_P)
		l |= 1 << ((data4_lane - 1) * 2 + (data4_pol ? 0 : 1));
	if (lanes & DSI_DATA4_N)
		l |= 1 << ((data4_lane - 1) * 2 + (data4_pol ? 1 : 0));
2275 2276 2277 2278 2279
	/*
	 * Bits in REGLPTXSCPDAT4TO0DXDY:
	 * 17: DY0 18: DX0
	 * 19: DY1 20: DX1
	 * 21: DY2 22: DX2
2280 2281
	 * 23: DY3 24: DX3
	 * 25: DY4 26: DX4
2282 2283 2284
	 */

	/* Set the lane override configuration */
2285 2286

	/* REGLPTXSCPDAT4TO0DXDY */
2287
	REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
2288 2289

	/* Enable lane override */
2290 2291 2292

	/* ENLPTXSCPDAT */
	REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
2293 2294
}

2295
static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
2296 2297
{
	/* Disable lane override */
2298
	REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
2299
	/* Reset the lane override configuration */
2300 2301
	/* REGLPTXSCPDAT4TO0DXDY */
	REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
2302
}
T
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2303

2304 2305
static int dsi_cio_wait_tx_clk_esc_reset(struct omap_dss_device *dssdev)
{
2306
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337
	int t;
	int bits[3];
	bool in_use[3];

	if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
		bits[0] = 28;
		bits[1] = 27;
		bits[2] = 26;
	} else {
		bits[0] = 24;
		bits[1] = 25;
		bits[2] = 26;
	}

	in_use[0] = false;
	in_use[1] = false;
	in_use[2] = false;

	if (dssdev->phy.dsi.clk_lane != 0)
		in_use[dssdev->phy.dsi.clk_lane - 1] = true;
	if (dssdev->phy.dsi.data1_lane != 0)
		in_use[dssdev->phy.dsi.data1_lane - 1] = true;
	if (dssdev->phy.dsi.data2_lane != 0)
		in_use[dssdev->phy.dsi.data2_lane - 1] = true;

	t = 100000;
	while (true) {
		u32 l;
		int i;
		int ok;

2338
		l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363

		ok = 0;
		for (i = 0; i < 3; ++i) {
			if (!in_use[i] || (l & (1 << bits[i])))
				ok++;
		}

		if (ok == 3)
			break;

		if (--t == 0) {
			for (i = 0; i < 3; ++i) {
				if (!in_use[i] || (l & (1 << bits[i])))
					continue;

				DSSERR("CIO TXCLKESC%d domain not coming " \
						"out of reset\n", i);
			}
			return -EIO;
		}
	}

	return 0;
}

2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381
static unsigned dsi_get_lane_mask(struct omap_dss_device *dssdev)
{
	unsigned lanes = 0;

	if (dssdev->phy.dsi.clk_lane != 0)
		lanes |= 1 << (dssdev->phy.dsi.clk_lane - 1);
	if (dssdev->phy.dsi.data1_lane != 0)
		lanes |= 1 << (dssdev->phy.dsi.data1_lane - 1);
	if (dssdev->phy.dsi.data2_lane != 0)
		lanes |= 1 << (dssdev->phy.dsi.data2_lane - 1);
	if (dssdev->phy.dsi.data3_lane != 0)
		lanes |= 1 << (dssdev->phy.dsi.data3_lane - 1);
	if (dssdev->phy.dsi.data4_lane != 0)
		lanes |= 1 << (dssdev->phy.dsi.data4_lane - 1);

	return lanes;
}

2382
static int dsi_cio_init(struct omap_dss_device *dssdev)
T
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2383
{
2384
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2385
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2386
	int r;
2387
	int num_data_lanes_dssdev = dsi_get_num_data_lanes_dssdev(dssdev);
2388
	u32 l;
T
Tomi Valkeinen 已提交
2389

2390
	DSSDBGF();
T
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2391

2392 2393 2394
	r = dsi->enable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
	if (r)
		return r;
2395

2396
	dsi_enable_scp_clk(dsidev);
2397

T
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2398 2399 2400
	/* A dummy read using the SCP interface to any DSIPHY register is
	 * required after DSIPHY reset to complete the reset of the DSI complex
	 * I/O. */
2401
	dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
T
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2402

2403
	if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2404 2405 2406
		DSSERR("CIO SCP Clock domain not coming out of reset.\n");
		r = -EIO;
		goto err_scp_clk_dom;
T
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2407 2408
	}

2409
	dsi_set_lane_config(dssdev);
T
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2410

2411
	/* set TX STOP MODE timer to maximum for this operation */
2412
	l = dsi_read_reg(dsidev, DSI_TIMING1);
2413 2414 2415 2416
	l = FLD_MOD(l, 1, 15, 15);	/* FORCE_TX_STOP_MODE_IO */
	l = FLD_MOD(l, 1, 14, 14);	/* STOP_STATE_X16_IO */
	l = FLD_MOD(l, 1, 13, 13);	/* STOP_STATE_X4_IO */
	l = FLD_MOD(l, 0x1fff, 12, 0);	/* STOP_STATE_COUNTER_IO */
2417
	dsi_write_reg(dsidev, DSI_TIMING1, l);
2418

2419
	if (dsi->ulps_enabled) {
2420 2421
		u32 lane_mask = DSI_CLK_P | DSI_DATA1_P | DSI_DATA2_P;

2422 2423
		DSSDBG("manual ulps exit\n");

2424 2425 2426 2427 2428 2429 2430 2431
		/* ULPS is exited by Mark-1 state for 1ms, followed by
		 * stop state. DSS HW cannot do this via the normal
		 * ULPS exit sequence, as after reset the DSS HW thinks
		 * that we are not in ULPS mode, and refuses to send the
		 * sequence. So we need to send the ULPS exit sequence
		 * manually.
		 */

2432 2433 2434 2435 2436 2437 2438
		if (num_data_lanes_dssdev > 2)
			lane_mask |= DSI_DATA3_P;

		if (num_data_lanes_dssdev > 3)
			lane_mask |= DSI_DATA4_P;

		dsi_cio_enable_lane_override(dssdev, lane_mask);
2439
	}
T
Tomi Valkeinen 已提交
2440

2441
	r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
T
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2442
	if (r)
2443 2444
		goto err_cio_pwr;

2445
	if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2446 2447 2448 2449 2450
		DSSERR("CIO PWR clock domain not coming out of reset.\n");
		r = -ENODEV;
		goto err_cio_pwr_dom;
	}

2451 2452 2453
	dsi_if_enable(dsidev, true);
	dsi_if_enable(dsidev, false);
	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
T
Tomi Valkeinen 已提交
2454

2455 2456 2457 2458
	r = dsi_cio_wait_tx_clk_esc_reset(dssdev);
	if (r)
		goto err_tx_clk_esc_rst;

2459
	if (dsi->ulps_enabled) {
2460 2461 2462 2463 2464 2465 2466
		/* Keep Mark-1 state for 1ms (as per DSI spec) */
		ktime_t wait = ns_to_ktime(1000 * 1000);
		set_current_state(TASK_UNINTERRUPTIBLE);
		schedule_hrtimeout(&wait, HRTIMER_MODE_REL);

		/* Disable the override. The lanes should be set to Mark-11
		 * state by the HW */
2467
		dsi_cio_disable_lane_override(dsidev);
2468 2469 2470
	}

	/* FORCE_TX_STOP_MODE_IO */
2471
	REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2472

2473
	dsi_cio_timings(dsidev);
T
Tomi Valkeinen 已提交
2474

2475
	dsi->ulps_enabled = false;
T
Tomi Valkeinen 已提交
2476 2477

	DSSDBG("CIO init done\n");
2478 2479 2480

	return 0;

2481
err_tx_clk_esc_rst:
2482
	REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2483
err_cio_pwr_dom:
2484
	dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2485
err_cio_pwr:
2486
	if (dsi->ulps_enabled)
2487
		dsi_cio_disable_lane_override(dsidev);
2488
err_scp_clk_dom:
2489
	dsi_disable_scp_clk(dsidev);
2490
	dsi->disable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
T
Tomi Valkeinen 已提交
2491 2492 2493
	return r;
}

2494
static void dsi_cio_uninit(struct omap_dss_device *dssdev)
T
Tomi Valkeinen 已提交
2495
{
2496
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2497 2498
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

2499 2500
	dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
	dsi_disable_scp_clk(dsidev);
2501
	dsi->disable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
T
Tomi Valkeinen 已提交
2502 2503
}

2504 2505
static void dsi_config_tx_fifo(struct platform_device *dsidev,
		enum fifo_size size1, enum fifo_size size2,
T
Tomi Valkeinen 已提交
2506 2507
		enum fifo_size size3, enum fifo_size size4)
{
2508
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
T
Tomi Valkeinen 已提交
2509 2510 2511 2512
	u32 r = 0;
	int add = 0;
	int i;

2513 2514 2515 2516
	dsi->vc[0].fifo_size = size1;
	dsi->vc[1].fifo_size = size2;
	dsi->vc[2].fifo_size = size3;
	dsi->vc[3].fifo_size = size4;
T
Tomi Valkeinen 已提交
2517 2518 2519

	for (i = 0; i < 4; i++) {
		u8 v;
2520
		int size = dsi->vc[i].fifo_size;
T
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2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532

		if (add + size > 4) {
			DSSERR("Illegal FIFO configuration\n");
			BUG();
		}

		v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
		r |= v << (8 * i);
		/*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
		add += size;
	}

2533
	dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
T
Tomi Valkeinen 已提交
2534 2535
}

2536 2537
static void dsi_config_rx_fifo(struct platform_device *dsidev,
		enum fifo_size size1, enum fifo_size size2,
T
Tomi Valkeinen 已提交
2538 2539
		enum fifo_size size3, enum fifo_size size4)
{
2540
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
T
Tomi Valkeinen 已提交
2541 2542 2543 2544
	u32 r = 0;
	int add = 0;
	int i;

2545 2546 2547 2548
	dsi->vc[0].fifo_size = size1;
	dsi->vc[1].fifo_size = size2;
	dsi->vc[2].fifo_size = size3;
	dsi->vc[3].fifo_size = size4;
T
Tomi Valkeinen 已提交
2549 2550 2551

	for (i = 0; i < 4; i++) {
		u8 v;
2552
		int size = dsi->vc[i].fifo_size;
T
Tomi Valkeinen 已提交
2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564

		if (add + size > 4) {
			DSSERR("Illegal FIFO configuration\n");
			BUG();
		}

		v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
		r |= v << (8 * i);
		/*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
		add += size;
	}

2565
	dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
T
Tomi Valkeinen 已提交
2566 2567
}

2568
static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
T
Tomi Valkeinen 已提交
2569 2570 2571
{
	u32 r;

2572
	r = dsi_read_reg(dsidev, DSI_TIMING1);
T
Tomi Valkeinen 已提交
2573
	r = FLD_MOD(r, 1, 15, 15);	/* FORCE_TX_STOP_MODE_IO */
2574
	dsi_write_reg(dsidev, DSI_TIMING1, r);
T
Tomi Valkeinen 已提交
2575

2576
	if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
T
Tomi Valkeinen 已提交
2577 2578 2579 2580 2581 2582 2583
		DSSERR("TX_STOP bit not going down\n");
		return -EIO;
	}

	return 0;
}

2584
static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2585
{
2586
	return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2587 2588 2589 2590
}

static void dsi_packet_sent_handler_vp(void *data, u32 mask)
{
2591 2592 2593
	struct dsi_packet_sent_handler_data *vp_data =
		(struct dsi_packet_sent_handler_data *) data;
	struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2594 2595
	const int channel = dsi->update_channel;
	u8 bit = dsi->te_enabled ? 30 : 31;
2596

2597 2598
	if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
		complete(vp_data->completion);
2599 2600
}

2601
static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2602
{
2603
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2604 2605
	DECLARE_COMPLETION_ONSTACK(completion);
	struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion };
2606 2607 2608
	int r = 0;
	u8 bit;

2609
	bit = dsi->te_enabled ? 30 : 31;
2610

2611
	r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2612
		&vp_data, DSI_VC_IRQ_PACKET_SENT);
2613 2614 2615 2616
	if (r)
		goto err0;

	/* Wait for completion only if TE_EN/TE_START is still set */
2617
	if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2618 2619 2620 2621 2622 2623 2624 2625
		if (wait_for_completion_timeout(&completion,
				msecs_to_jiffies(10)) == 0) {
			DSSERR("Failed to complete previous frame transfer\n");
			r = -EIO;
			goto err1;
		}
	}

2626
	dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2627
		&vp_data, DSI_VC_IRQ_PACKET_SENT);
2628 2629 2630

	return 0;
err1:
2631
	dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2632
		&vp_data, DSI_VC_IRQ_PACKET_SENT);
2633 2634 2635 2636 2637 2638
err0:
	return r;
}

static void dsi_packet_sent_handler_l4(void *data, u32 mask)
{
2639 2640 2641
	struct dsi_packet_sent_handler_data *l4_data =
		(struct dsi_packet_sent_handler_data *) data;
	struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2642
	const int channel = dsi->update_channel;
2643

2644 2645
	if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
		complete(l4_data->completion);
2646 2647
}

2648
static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2649 2650
{
	DECLARE_COMPLETION_ONSTACK(completion);
2651 2652
	struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion };
	int r = 0;
2653

2654
	r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2655
		&l4_data, DSI_VC_IRQ_PACKET_SENT);
2656 2657 2658 2659
	if (r)
		goto err0;

	/* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2660
	if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2661 2662 2663 2664 2665 2666 2667 2668
		if (wait_for_completion_timeout(&completion,
				msecs_to_jiffies(10)) == 0) {
			DSSERR("Failed to complete previous l4 transfer\n");
			r = -EIO;
			goto err1;
		}
	}

2669
	dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2670
		&l4_data, DSI_VC_IRQ_PACKET_SENT);
2671 2672 2673

	return 0;
err1:
2674
	dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2675
		&l4_data, DSI_VC_IRQ_PACKET_SENT);
2676 2677 2678 2679
err0:
	return r;
}

2680
static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2681
{
2682 2683
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

2684
	WARN_ON(!dsi_bus_is_locked(dsidev));
2685 2686 2687

	WARN_ON(in_interrupt());

2688
	if (!dsi_vc_is_enabled(dsidev, channel))
2689 2690
		return 0;

2691 2692
	switch (dsi->vc[channel].source) {
	case DSI_VC_SOURCE_VP:
2693
		return dsi_sync_vc_vp(dsidev, channel);
2694
	case DSI_VC_SOURCE_L4:
2695
		return dsi_sync_vc_l4(dsidev, channel);
2696 2697 2698 2699 2700
	default:
		BUG();
	}
}

2701 2702
static int dsi_vc_enable(struct platform_device *dsidev, int channel,
		bool enable)
T
Tomi Valkeinen 已提交
2703
{
2704 2705
	DSSDBG("dsi_vc_enable channel %d, enable %d\n",
			channel, enable);
T
Tomi Valkeinen 已提交
2706 2707 2708

	enable = enable ? 1 : 0;

2709
	REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
T
Tomi Valkeinen 已提交
2710

2711 2712
	if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
		0, enable) != enable) {
T
Tomi Valkeinen 已提交
2713 2714 2715 2716 2717 2718 2719
			DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
			return -EIO;
	}

	return 0;
}

2720
static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
T
Tomi Valkeinen 已提交
2721 2722 2723 2724 2725
{
	u32 r;

	DSSDBGF("%d", channel);

2726
	r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
T
Tomi Valkeinen 已提交
2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738

	if (FLD_GET(r, 15, 15)) /* VC_BUSY */
		DSSERR("VC(%d) busy when trying to configure it!\n",
				channel);

	r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
	r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN  */
	r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
	r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
	r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
	r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
	r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2739 2740
	if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
		r = FLD_MOD(r, 3, 11, 10);	/* OCP_WIDTH = 32 bit */
T
Tomi Valkeinen 已提交
2741 2742 2743 2744

	r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
	r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */

2745
	dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
T
Tomi Valkeinen 已提交
2746 2747
}

2748 2749
static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
		enum dsi_vc_source source)
T
Tomi Valkeinen 已提交
2750
{
2751 2752
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

2753
	if (dsi->vc[channel].source == source)
2754
		return 0;
T
Tomi Valkeinen 已提交
2755 2756 2757

	DSSDBGF("%d", channel);

2758
	dsi_sync_vc(dsidev, channel);
2759

2760
	dsi_vc_enable(dsidev, channel, 0);
T
Tomi Valkeinen 已提交
2761

2762
	/* VC_BUSY */
2763
	if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
T
Tomi Valkeinen 已提交
2764
		DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2765 2766
		return -EIO;
	}
T
Tomi Valkeinen 已提交
2767

2768 2769
	/* SOURCE, 0 = L4, 1 = video port */
	REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
T
Tomi Valkeinen 已提交
2770

2771
	/* DCS_CMD_ENABLE */
2772 2773 2774 2775
	if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
		bool enable = source == DSI_VC_SOURCE_VP;
		REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
	}
2776

2777
	dsi_vc_enable(dsidev, channel, 1);
T
Tomi Valkeinen 已提交
2778

2779
	dsi->vc[channel].source = source;
2780 2781

	return 0;
T
Tomi Valkeinen 已提交
2782 2783
}

2784 2785
void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
		bool enable)
T
Tomi Valkeinen 已提交
2786
{
2787 2788
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);

T
Tomi Valkeinen 已提交
2789 2790
	DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);

2791
	WARN_ON(!dsi_bus_is_locked(dsidev));
2792

2793 2794
	dsi_vc_enable(dsidev, channel, 0);
	dsi_if_enable(dsidev, 0);
T
Tomi Valkeinen 已提交
2795

2796
	REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
T
Tomi Valkeinen 已提交
2797

2798 2799
	dsi_vc_enable(dsidev, channel, 1);
	dsi_if_enable(dsidev, 1);
T
Tomi Valkeinen 已提交
2800

2801
	dsi_force_tx_stop_mode_io(dsidev);
T
Tomi Valkeinen 已提交
2802
}
2803
EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
T
Tomi Valkeinen 已提交
2804

2805
static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
T
Tomi Valkeinen 已提交
2806
{
2807
	while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
T
Tomi Valkeinen 已提交
2808
		u32 val;
2809
		val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
T
Tomi Valkeinen 已提交
2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854
		DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
				(val >> 0) & 0xff,
				(val >> 8) & 0xff,
				(val >> 16) & 0xff,
				(val >> 24) & 0xff);
	}
}

static void dsi_show_rx_ack_with_err(u16 err)
{
	DSSERR("\tACK with ERROR (%#x):\n", err);
	if (err & (1 << 0))
		DSSERR("\t\tSoT Error\n");
	if (err & (1 << 1))
		DSSERR("\t\tSoT Sync Error\n");
	if (err & (1 << 2))
		DSSERR("\t\tEoT Sync Error\n");
	if (err & (1 << 3))
		DSSERR("\t\tEscape Mode Entry Command Error\n");
	if (err & (1 << 4))
		DSSERR("\t\tLP Transmit Sync Error\n");
	if (err & (1 << 5))
		DSSERR("\t\tHS Receive Timeout Error\n");
	if (err & (1 << 6))
		DSSERR("\t\tFalse Control Error\n");
	if (err & (1 << 7))
		DSSERR("\t\t(reserved7)\n");
	if (err & (1 << 8))
		DSSERR("\t\tECC Error, single-bit (corrected)\n");
	if (err & (1 << 9))
		DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
	if (err & (1 << 10))
		DSSERR("\t\tChecksum Error\n");
	if (err & (1 << 11))
		DSSERR("\t\tData type not recognized\n");
	if (err & (1 << 12))
		DSSERR("\t\tInvalid VC ID\n");
	if (err & (1 << 13))
		DSSERR("\t\tInvalid Transmission Length\n");
	if (err & (1 << 14))
		DSSERR("\t\t(reserved14)\n");
	if (err & (1 << 15))
		DSSERR("\t\tDSI Protocol Violation\n");
}

2855 2856
static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
		int channel)
T
Tomi Valkeinen 已提交
2857 2858
{
	/* RX_FIFO_NOT_EMPTY */
2859
	while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
T
Tomi Valkeinen 已提交
2860 2861
		u32 val;
		u8 dt;
2862
		val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2863
		DSSERR("\trawval %#08x\n", val);
T
Tomi Valkeinen 已提交
2864
		dt = FLD_GET(val, 5, 0);
2865
		if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
T
Tomi Valkeinen 已提交
2866 2867
			u16 err = FLD_GET(val, 23, 8);
			dsi_show_rx_ack_with_err(err);
2868
		} else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2869
			DSSERR("\tDCS short response, 1 byte: %#x\n",
T
Tomi Valkeinen 已提交
2870
					FLD_GET(val, 23, 8));
2871
		} else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2872
			DSSERR("\tDCS short response, 2 byte: %#x\n",
T
Tomi Valkeinen 已提交
2873
					FLD_GET(val, 23, 8));
2874
		} else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2875
			DSSERR("\tDCS long response, len %d\n",
T
Tomi Valkeinen 已提交
2876
					FLD_GET(val, 23, 8));
2877
			dsi_vc_flush_long_data(dsidev, channel);
T
Tomi Valkeinen 已提交
2878 2879 2880 2881 2882 2883 2884
		} else {
			DSSERR("\tunknown datatype 0x%02x\n", dt);
		}
	}
	return 0;
}

2885
static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
T
Tomi Valkeinen 已提交
2886
{
2887 2888 2889
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	if (dsi->debug_write || dsi->debug_read)
T
Tomi Valkeinen 已提交
2890 2891
		DSSDBG("dsi_vc_send_bta %d\n", channel);

2892
	WARN_ON(!dsi_bus_is_locked(dsidev));
T
Tomi Valkeinen 已提交
2893

2894 2895
	/* RX_FIFO_NOT_EMPTY */
	if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
T
Tomi Valkeinen 已提交
2896
		DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2897
		dsi_vc_flush_receive_data(dsidev, channel);
T
Tomi Valkeinen 已提交
2898 2899
	}

2900
	REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
T
Tomi Valkeinen 已提交
2901 2902 2903 2904

	return 0;
}

2905
int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
T
Tomi Valkeinen 已提交
2906
{
2907
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2908
	DECLARE_COMPLETION_ONSTACK(completion);
T
Tomi Valkeinen 已提交
2909 2910 2911
	int r = 0;
	u32 err;

2912
	r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2913 2914 2915
			&completion, DSI_VC_IRQ_BTA);
	if (r)
		goto err0;
T
Tomi Valkeinen 已提交
2916

2917
	r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2918
			DSI_IRQ_ERROR_MASK);
T
Tomi Valkeinen 已提交
2919
	if (r)
2920
		goto err1;
T
Tomi Valkeinen 已提交
2921

2922
	r = dsi_vc_send_bta(dsidev, channel);
2923 2924 2925
	if (r)
		goto err2;

2926
	if (wait_for_completion_timeout(&completion,
T
Tomi Valkeinen 已提交
2927 2928 2929
				msecs_to_jiffies(500)) == 0) {
		DSSERR("Failed to receive BTA\n");
		r = -EIO;
2930
		goto err2;
T
Tomi Valkeinen 已提交
2931 2932
	}

2933
	err = dsi_get_errors(dsidev);
T
Tomi Valkeinen 已提交
2934 2935 2936
	if (err) {
		DSSERR("Error while sending BTA: %x\n", err);
		r = -EIO;
2937
		goto err2;
T
Tomi Valkeinen 已提交
2938
	}
2939
err2:
2940
	dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
2941
			DSI_IRQ_ERROR_MASK);
2942
err1:
2943
	dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
2944 2945
			&completion, DSI_VC_IRQ_BTA);
err0:
T
Tomi Valkeinen 已提交
2946 2947 2948 2949
	return r;
}
EXPORT_SYMBOL(dsi_vc_send_bta_sync);

2950 2951
static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
		int channel, u8 data_type, u16 len, u8 ecc)
T
Tomi Valkeinen 已提交
2952
{
2953
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
T
Tomi Valkeinen 已提交
2954 2955 2956
	u32 val;
	u8 data_id;

2957
	WARN_ON(!dsi_bus_is_locked(dsidev));
T
Tomi Valkeinen 已提交
2958

2959
	data_id = data_type | dsi->vc[channel].vc_id << 6;
T
Tomi Valkeinen 已提交
2960 2961 2962 2963

	val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
		FLD_VAL(ecc, 31, 24);

2964
	dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
T
Tomi Valkeinen 已提交
2965 2966
}

2967 2968
static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
		int channel, u8 b1, u8 b2, u8 b3, u8 b4)
T
Tomi Valkeinen 已提交
2969 2970 2971 2972 2973 2974 2975 2976
{
	u32 val;

	val = b4 << 24 | b3 << 16 | b2 << 8  | b1 << 0;

/*	DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
			b1, b2, b3, b4, val); */

2977
	dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
T
Tomi Valkeinen 已提交
2978 2979
}

2980 2981
static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
		u8 data_type, u8 *data, u16 len, u8 ecc)
T
Tomi Valkeinen 已提交
2982 2983
{
	/*u32 val; */
2984
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
T
Tomi Valkeinen 已提交
2985 2986 2987 2988 2989
	int i;
	u8 *p;
	int r = 0;
	u8 b1, b2, b3, b4;

2990
	if (dsi->debug_write)
T
Tomi Valkeinen 已提交
2991 2992 2993
		DSSDBG("dsi_vc_send_long, %d bytes\n", len);

	/* len + header */
2994
	if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) {
T
Tomi Valkeinen 已提交
2995 2996 2997 2998
		DSSERR("unable to send long packet: packet too long.\n");
		return -EINVAL;
	}

2999
	dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
T
Tomi Valkeinen 已提交
3000

3001
	dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
T
Tomi Valkeinen 已提交
3002 3003 3004

	p = data;
	for (i = 0; i < len >> 2; i++) {
3005
		if (dsi->debug_write)
T
Tomi Valkeinen 已提交
3006 3007 3008 3009 3010 3011 3012
			DSSDBG("\tsending full packet %d\n", i);

		b1 = *p++;
		b2 = *p++;
		b3 = *p++;
		b4 = *p++;

3013
		dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
T
Tomi Valkeinen 已提交
3014 3015 3016 3017 3018 3019
	}

	i = len % 4;
	if (i) {
		b1 = 0; b2 = 0; b3 = 0;

3020
		if (dsi->debug_write)
T
Tomi Valkeinen 已提交
3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037
			DSSDBG("\tsending remainder bytes %d\n", i);

		switch (i) {
		case 3:
			b1 = *p++;
			b2 = *p++;
			b3 = *p++;
			break;
		case 2:
			b1 = *p++;
			b2 = *p++;
			break;
		case 1:
			b1 = *p++;
			break;
		}

3038
		dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
T
Tomi Valkeinen 已提交
3039 3040 3041 3042 3043
	}

	return r;
}

3044 3045
static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
		u8 data_type, u16 data, u8 ecc)
T
Tomi Valkeinen 已提交
3046
{
3047
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
T
Tomi Valkeinen 已提交
3048 3049 3050
	u32 r;
	u8 data_id;

3051
	WARN_ON(!dsi_bus_is_locked(dsidev));
T
Tomi Valkeinen 已提交
3052

3053
	if (dsi->debug_write)
T
Tomi Valkeinen 已提交
3054 3055 3056 3057
		DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
				channel,
				data_type, data & 0xff, (data >> 8) & 0xff);

3058
	dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
T
Tomi Valkeinen 已提交
3059

3060
	if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
T
Tomi Valkeinen 已提交
3061 3062 3063 3064
		DSSERR("ERROR FIFO FULL, aborting transfer\n");
		return -EINVAL;
	}

3065
	data_id = data_type | dsi->vc[channel].vc_id << 6;
T
Tomi Valkeinen 已提交
3066 3067 3068

	r = (data_id << 0) | (data << 8) | (ecc << 24);

3069
	dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
T
Tomi Valkeinen 已提交
3070 3071 3072 3073

	return 0;
}

3074
int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
T
Tomi Valkeinen 已提交
3075
{
3076 3077
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);

3078 3079
	return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
		0, 0);
T
Tomi Valkeinen 已提交
3080 3081 3082
}
EXPORT_SYMBOL(dsi_vc_send_null);

3083 3084
static int dsi_vc_write_nosync_common(struct omap_dss_device *dssdev,
		int channel, u8 *data, int len, enum dss_dsi_content_type type)
T
Tomi Valkeinen 已提交
3085
{
3086
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
T
Tomi Valkeinen 已提交
3087 3088
	int r;

3089 3090
	if (len == 0) {
		BUG_ON(type == DSS_DSI_CONTENT_DCS);
3091
		r = dsi_vc_send_short(dsidev, channel,
3092 3093 3094 3095 3096
				MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
	} else if (len == 1) {
		r = dsi_vc_send_short(dsidev, channel,
				type == DSS_DSI_CONTENT_GENERIC ?
				MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
3097
				MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
T
Tomi Valkeinen 已提交
3098
	} else if (len == 2) {
3099
		r = dsi_vc_send_short(dsidev, channel,
3100 3101
				type == DSS_DSI_CONTENT_GENERIC ?
				MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
3102
				MIPI_DSI_DCS_SHORT_WRITE_PARAM,
T
Tomi Valkeinen 已提交
3103 3104
				data[0] | (data[1] << 8), 0);
	} else {
3105 3106 3107 3108
		r = dsi_vc_send_long(dsidev, channel,
				type == DSS_DSI_CONTENT_GENERIC ?
				MIPI_DSI_GENERIC_LONG_WRITE :
				MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
T
Tomi Valkeinen 已提交
3109 3110 3111 3112
	}

	return r;
}
3113 3114 3115 3116 3117 3118 3119

int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
		u8 *data, int len)
{
	return dsi_vc_write_nosync_common(dssdev, channel, data, len,
			DSS_DSI_CONTENT_DCS);
}
T
Tomi Valkeinen 已提交
3120 3121
EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);

3122 3123 3124 3125 3126 3127 3128 3129 3130 3131
int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
		u8 *data, int len)
{
	return dsi_vc_write_nosync_common(dssdev, channel, data, len,
			DSS_DSI_CONTENT_GENERIC);
}
EXPORT_SYMBOL(dsi_vc_generic_write_nosync);

static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
		u8 *data, int len, enum dss_dsi_content_type type)
T
Tomi Valkeinen 已提交
3132
{
3133
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
T
Tomi Valkeinen 已提交
3134 3135
	int r;

3136
	r = dsi_vc_write_nosync_common(dssdev, channel, data, len, type);
T
Tomi Valkeinen 已提交
3137
	if (r)
3138
		goto err;
T
Tomi Valkeinen 已提交
3139

3140
	r = dsi_vc_send_bta_sync(dssdev, channel);
3141 3142
	if (r)
		goto err;
T
Tomi Valkeinen 已提交
3143

3144 3145
	/* RX_FIFO_NOT_EMPTY */
	if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
3146
		DSSERR("rx fifo not empty after write, dumping data:\n");
3147
		dsi_vc_flush_receive_data(dsidev, channel);
3148 3149 3150 3151
		r = -EIO;
		goto err;
	}

3152 3153
	return 0;
err:
3154
	DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
3155
			channel, data[0], len);
T
Tomi Valkeinen 已提交
3156 3157
	return r;
}
3158 3159 3160 3161 3162 3163 3164

int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
		int len)
{
	return dsi_vc_write_common(dssdev, channel, data, len,
			DSS_DSI_CONTENT_DCS);
}
T
Tomi Valkeinen 已提交
3165 3166
EXPORT_SYMBOL(dsi_vc_dcs_write);

3167 3168 3169 3170 3171 3172 3173 3174
int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
		int len)
{
	return dsi_vc_write_common(dssdev, channel, data, len,
			DSS_DSI_CONTENT_GENERIC);
}
EXPORT_SYMBOL(dsi_vc_generic_write);

3175
int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd)
3176
{
3177
	return dsi_vc_dcs_write(dssdev, channel, &dcs_cmd, 1);
3178 3179 3180
}
EXPORT_SYMBOL(dsi_vc_dcs_write_0);

3181 3182 3183 3184 3185 3186
int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel)
{
	return dsi_vc_generic_write(dssdev, channel, NULL, 0);
}
EXPORT_SYMBOL(dsi_vc_generic_write_0);

3187 3188
int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
		u8 param)
3189 3190 3191 3192
{
	u8 buf[2];
	buf[0] = dcs_cmd;
	buf[1] = param;
3193
	return dsi_vc_dcs_write(dssdev, channel, buf, 2);
3194 3195 3196
}
EXPORT_SYMBOL(dsi_vc_dcs_write_1);

3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213
int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
		u8 param)
{
	return dsi_vc_generic_write(dssdev, channel, &param, 1);
}
EXPORT_SYMBOL(dsi_vc_generic_write_1);

int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
		u8 param1, u8 param2)
{
	u8 buf[2];
	buf[0] = param1;
	buf[1] = param2;
	return dsi_vc_generic_write(dssdev, channel, buf, 2);
}
EXPORT_SYMBOL(dsi_vc_generic_write_2);

3214 3215
static int dsi_vc_dcs_send_read_request(struct omap_dss_device *dssdev,
		int channel, u8 dcs_cmd)
T
Tomi Valkeinen 已提交
3216
{
3217
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3218
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
T
Tomi Valkeinen 已提交
3219 3220
	int r;

3221
	if (dsi->debug_read)
3222 3223
		DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
			channel, dcs_cmd);
T
Tomi Valkeinen 已提交
3224

3225
	r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
3226 3227 3228 3229 3230
	if (r) {
		DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
			" failed\n", channel, dcs_cmd);
		return r;
	}
T
Tomi Valkeinen 已提交
3231

3232 3233 3234
	return 0;
}

3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272
static int dsi_vc_generic_send_read_request(struct omap_dss_device *dssdev,
		int channel, u8 *reqdata, int reqlen)
{
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
	u16 data;
	u8 data_type;
	int r;

	if (dsi->debug_read)
		DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
			channel, reqlen);

	if (reqlen == 0) {
		data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
		data = 0;
	} else if (reqlen == 1) {
		data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
		data = reqdata[0];
	} else if (reqlen == 2) {
		data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
		data = reqdata[0] | (reqdata[1] << 8);
	} else {
		BUG();
	}

	r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
	if (r) {
		DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
			" failed\n", channel, reqlen);
		return r;
	}

	return 0;
}

static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
		u8 *buf, int buflen, enum dss_dsi_content_type type)
3273 3274 3275 3276 3277
{
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
	u32 val;
	u8 dt;
	int r;
T
Tomi Valkeinen 已提交
3278 3279

	/* RX_FIFO_NOT_EMPTY */
3280
	if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
T
Tomi Valkeinen 已提交
3281
		DSSERR("RX fifo empty when trying to read.\n");
3282 3283
		r = -EIO;
		goto err;
T
Tomi Valkeinen 已提交
3284 3285
	}

3286
	val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
3287
	if (dsi->debug_read)
T
Tomi Valkeinen 已提交
3288 3289
		DSSDBG("\theader: %08x\n", val);
	dt = FLD_GET(val, 5, 0);
3290
	if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
T
Tomi Valkeinen 已提交
3291 3292
		u16 err = FLD_GET(val, 23, 8);
		dsi_show_rx_ack_with_err(err);
3293 3294
		r = -EIO;
		goto err;
T
Tomi Valkeinen 已提交
3295

3296 3297 3298
	} else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
			MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
			MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
T
Tomi Valkeinen 已提交
3299
		u8 data = FLD_GET(val, 15, 8);
3300
		if (dsi->debug_read)
3301 3302 3303
			DSSDBG("\t%s short response, 1 byte: %02x\n",
				type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
				"DCS", data);
T
Tomi Valkeinen 已提交
3304

3305 3306 3307 3308
		if (buflen < 1) {
			r = -EIO;
			goto err;
		}
T
Tomi Valkeinen 已提交
3309 3310 3311 3312

		buf[0] = data;

		return 1;
3313 3314 3315
	} else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
			MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
			MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
T
Tomi Valkeinen 已提交
3316
		u16 data = FLD_GET(val, 23, 8);
3317
		if (dsi->debug_read)
3318 3319 3320
			DSSDBG("\t%s short response, 2 byte: %04x\n",
				type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
				"DCS", data);
T
Tomi Valkeinen 已提交
3321

3322 3323 3324 3325
		if (buflen < 2) {
			r = -EIO;
			goto err;
		}
T
Tomi Valkeinen 已提交
3326 3327 3328 3329 3330

		buf[0] = data & 0xff;
		buf[1] = (data >> 8) & 0xff;

		return 2;
3331 3332 3333
	} else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
			MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
			MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
T
Tomi Valkeinen 已提交
3334 3335
		int w;
		int len = FLD_GET(val, 23, 8);
3336
		if (dsi->debug_read)
3337 3338 3339
			DSSDBG("\t%s long response, len %d\n",
				type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
				"DCS", len);
T
Tomi Valkeinen 已提交
3340

3341 3342 3343 3344
		if (len > buflen) {
			r = -EIO;
			goto err;
		}
T
Tomi Valkeinen 已提交
3345 3346 3347 3348

		/* two byte checksum ends the packet, not included in len */
		for (w = 0; w < len + 2;) {
			int b;
3349 3350
			val = dsi_read_reg(dsidev,
				DSI_VC_SHORT_PACKET_HEADER(channel));
3351
			if (dsi->debug_read)
T
Tomi Valkeinen 已提交
3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368
				DSSDBG("\t\t%02x %02x %02x %02x\n",
						(val >> 0) & 0xff,
						(val >> 8) & 0xff,
						(val >> 16) & 0xff,
						(val >> 24) & 0xff);

			for (b = 0; b < 4; ++b) {
				if (w < len)
					buf[w] = (val >> (b * 8)) & 0xff;
				/* we discard the 2 byte checksum */
				++w;
			}
		}

		return len;
	} else {
		DSSERR("\tunknown datatype 0x%02x\n", dt);
3369 3370
		r = -EIO;
		goto err;
T
Tomi Valkeinen 已提交
3371
	}
3372 3373 3374

	BUG();
err:
3375 3376
	DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
		type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3377

3378
	return r;
3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389
}

int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
		u8 *buf, int buflen)
{
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
	int r;

	r = dsi_vc_dcs_send_read_request(dssdev, channel, dcs_cmd);
	if (r)
		goto err;
3390

3391 3392 3393 3394
	r = dsi_vc_send_bta_sync(dssdev, channel);
	if (r)
		goto err;

3395 3396
	r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
		DSS_DSI_CONTENT_DCS);
3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 3408
	if (r < 0)
		goto err;

	if (r != buflen) {
		r = -EIO;
		goto err;
	}

	return 0;
err:
	DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
	return r;
T
Tomi Valkeinen 已提交
3409 3410 3411
}
EXPORT_SYMBOL(dsi_vc_dcs_read);

3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487
static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
		u8 *reqdata, int reqlen, u8 *buf, int buflen)
{
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
	int r;

	r = dsi_vc_generic_send_read_request(dssdev, channel, reqdata, reqlen);
	if (r)
		return r;

	r = dsi_vc_send_bta_sync(dssdev, channel);
	if (r)
		return r;

	r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
		DSS_DSI_CONTENT_GENERIC);
	if (r < 0)
		return r;

	if (r != buflen) {
		r = -EIO;
		return r;
	}

	return 0;
}

int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
		int buflen)
{
	int r;

	r = dsi_vc_generic_read(dssdev, channel, NULL, 0, buf, buflen);
	if (r) {
		DSSERR("dsi_vc_generic_read_0(ch %d) failed\n", channel);
		return r;
	}

	return 0;
}
EXPORT_SYMBOL(dsi_vc_generic_read_0);

int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
		u8 *buf, int buflen)
{
	int r;

	r = dsi_vc_generic_read(dssdev, channel, &param, 1, buf, buflen);
	if (r) {
		DSSERR("dsi_vc_generic_read_1(ch %d) failed\n", channel);
		return r;
	}

	return 0;
}
EXPORT_SYMBOL(dsi_vc_generic_read_1);

int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
		u8 param1, u8 param2, u8 *buf, int buflen)
{
	int r;
	u8 reqdata[2];

	reqdata[0] = param1;
	reqdata[1] = param2;

	r = dsi_vc_generic_read(dssdev, channel, reqdata, 2, buf, buflen);
	if (r) {
		DSSERR("dsi_vc_generic_read_2(ch %d) failed\n", channel);
		return r;
	}

	return 0;
}
EXPORT_SYMBOL(dsi_vc_generic_read_2);

3488 3489
int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
		u16 len)
T
Tomi Valkeinen 已提交
3490
{
3491 3492
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);

3493 3494
	return dsi_vc_send_short(dsidev, channel,
			MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
T
Tomi Valkeinen 已提交
3495 3496 3497
}
EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);

3498
static int dsi_enter_ulps(struct platform_device *dsidev)
3499
{
3500
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3501 3502 3503 3504 3505
	DECLARE_COMPLETION_ONSTACK(completion);
	int r;

	DSSDBGF();

3506
	WARN_ON(!dsi_bus_is_locked(dsidev));
3507

3508
	WARN_ON(dsi->ulps_enabled);
3509

3510
	if (dsi->ulps_enabled)
3511 3512
		return 0;

3513
	if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3514 3515 3516 3517
		DSSERR("DDR_CLK_ALWAYS_ON enabled when entering ULPS\n");
		return -EIO;
	}

3518 3519 3520 3521
	dsi_sync_vc(dsidev, 0);
	dsi_sync_vc(dsidev, 1);
	dsi_sync_vc(dsidev, 2);
	dsi_sync_vc(dsidev, 3);
3522

3523
	dsi_force_tx_stop_mode_io(dsidev);
3524

3525 3526 3527 3528
	dsi_vc_enable(dsidev, 0, false);
	dsi_vc_enable(dsidev, 1, false);
	dsi_vc_enable(dsidev, 2, false);
	dsi_vc_enable(dsidev, 3, false);
3529

3530
	if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) {	/* HS_BUSY */
3531 3532 3533 3534
		DSSERR("HS busy when enabling ULPS\n");
		return -EIO;
	}

3535
	if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) {	/* LP_BUSY */
3536 3537 3538 3539
		DSSERR("LP busy when enabling ULPS\n");
		return -EIO;
	}

3540
	r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3541 3542 3543 3544 3545 3546
			DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
	if (r)
		return r;

	/* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
	/* LANEx_ULPS_SIG2 */
3547 3548
	REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, (1 << 0) | (1 << 1) | (1 << 2),
		7, 5);
3549 3550 3551 3552 3553 3554 3555 3556

	if (wait_for_completion_timeout(&completion,
				msecs_to_jiffies(1000)) == 0) {
		DSSERR("ULPS enable timeout\n");
		r = -EIO;
		goto err;
	}

3557
	dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3558 3559
			DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);

3560 3561 3562 3563
	/* Reset LANEx_ULPS_SIG2 */
	REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, (0 << 0) | (0 << 1) | (0 << 2),
		7, 5);

3564
	dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3565

3566
	dsi_if_enable(dsidev, false);
3567

3568
	dsi->ulps_enabled = true;
3569 3570 3571 3572

	return 0;

err:
3573
	dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3574 3575 3576 3577
			DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
	return r;
}

3578 3579
static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
		unsigned ticks, bool x4, bool x16)
T
Tomi Valkeinen 已提交
3580 3581
{
	unsigned long fck;
3582 3583
	unsigned long total_ticks;
	u32 r;
T
Tomi Valkeinen 已提交
3584

3585
	BUG_ON(ticks > 0x1fff);
T
Tomi Valkeinen 已提交
3586

3587
	/* ticks in DSI_FCK */
3588
	fck = dsi_fclk_rate(dsidev);
T
Tomi Valkeinen 已提交
3589

3590
	r = dsi_read_reg(dsidev, DSI_TIMING2);
T
Tomi Valkeinen 已提交
3591
	r = FLD_MOD(r, 1, 15, 15);	/* LP_RX_TO */
3592 3593
	r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);	/* LP_RX_TO_X16 */
	r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);	/* LP_RX_TO_X4 */
T
Tomi Valkeinen 已提交
3594
	r = FLD_MOD(r, ticks, 12, 0);	/* LP_RX_COUNTER */
3595
	dsi_write_reg(dsidev, DSI_TIMING2, r);
T
Tomi Valkeinen 已提交
3596

3597 3598 3599 3600 3601 3602
	total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);

	DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
			total_ticks,
			ticks, x4 ? " x4" : "", x16 ? " x16" : "",
			(total_ticks * 1000) / (fck / 1000 / 1000));
T
Tomi Valkeinen 已提交
3603 3604
}

3605 3606
static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
		bool x8, bool x16)
T
Tomi Valkeinen 已提交
3607 3608
{
	unsigned long fck;
3609 3610 3611 3612
	unsigned long total_ticks;
	u32 r;

	BUG_ON(ticks > 0x1fff);
T
Tomi Valkeinen 已提交
3613 3614

	/* ticks in DSI_FCK */
3615
	fck = dsi_fclk_rate(dsidev);
T
Tomi Valkeinen 已提交
3616

3617
	r = dsi_read_reg(dsidev, DSI_TIMING1);
T
Tomi Valkeinen 已提交
3618
	r = FLD_MOD(r, 1, 31, 31);	/* TA_TO */
3619 3620
	r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);	/* TA_TO_X16 */
	r = FLD_MOD(r, x8 ? 1 : 0, 29, 29);	/* TA_TO_X8 */
T
Tomi Valkeinen 已提交
3621
	r = FLD_MOD(r, ticks, 28, 16);	/* TA_TO_COUNTER */
3622
	dsi_write_reg(dsidev, DSI_TIMING1, r);
T
Tomi Valkeinen 已提交
3623

3624 3625 3626 3627 3628 3629
	total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);

	DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
			total_ticks,
			ticks, x8 ? " x8" : "", x16 ? " x16" : "",
			(total_ticks * 1000) / (fck / 1000 / 1000));
T
Tomi Valkeinen 已提交
3630 3631
}

3632 3633
static void dsi_set_stop_state_counter(struct platform_device *dsidev,
		unsigned ticks, bool x4, bool x16)
T
Tomi Valkeinen 已提交
3634 3635
{
	unsigned long fck;
3636 3637
	unsigned long total_ticks;
	u32 r;
T
Tomi Valkeinen 已提交
3638

3639
	BUG_ON(ticks > 0x1fff);
T
Tomi Valkeinen 已提交
3640

3641
	/* ticks in DSI_FCK */
3642
	fck = dsi_fclk_rate(dsidev);
T
Tomi Valkeinen 已提交
3643

3644
	r = dsi_read_reg(dsidev, DSI_TIMING1);
T
Tomi Valkeinen 已提交
3645
	r = FLD_MOD(r, 1, 15, 15);	/* FORCE_TX_STOP_MODE_IO */
3646 3647
	r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);	/* STOP_STATE_X16_IO */
	r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);	/* STOP_STATE_X4_IO */
T
Tomi Valkeinen 已提交
3648
	r = FLD_MOD(r, ticks, 12, 0);	/* STOP_STATE_COUNTER_IO */
3649
	dsi_write_reg(dsidev, DSI_TIMING1, r);
T
Tomi Valkeinen 已提交
3650

3651 3652 3653 3654 3655 3656
	total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);

	DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
			total_ticks,
			ticks, x4 ? " x4" : "", x16 ? " x16" : "",
			(total_ticks * 1000) / (fck / 1000 / 1000));
T
Tomi Valkeinen 已提交
3657 3658
}

3659 3660
static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
		unsigned ticks, bool x4, bool x16)
T
Tomi Valkeinen 已提交
3661 3662
{
	unsigned long fck;
3663 3664
	unsigned long total_ticks;
	u32 r;
T
Tomi Valkeinen 已提交
3665

3666
	BUG_ON(ticks > 0x1fff);
T
Tomi Valkeinen 已提交
3667

3668
	/* ticks in TxByteClkHS */
3669
	fck = dsi_get_txbyteclkhs(dsidev);
T
Tomi Valkeinen 已提交
3670

3671
	r = dsi_read_reg(dsidev, DSI_TIMING2);
T
Tomi Valkeinen 已提交
3672
	r = FLD_MOD(r, 1, 31, 31);	/* HS_TX_TO */
3673 3674
	r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);	/* HS_TX_TO_X16 */
	r = FLD_MOD(r, x4 ? 1 : 0, 29, 29);	/* HS_TX_TO_X8 (4 really) */
T
Tomi Valkeinen 已提交
3675
	r = FLD_MOD(r, ticks, 28, 16);	/* HS_TX_TO_COUNTER */
3676
	dsi_write_reg(dsidev, DSI_TIMING2, r);
T
Tomi Valkeinen 已提交
3677

3678 3679 3680 3681 3682 3683
	total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);

	DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
			total_ticks,
			ticks, x4 ? " x4" : "", x16 ? " x16" : "",
			(total_ticks * 1000) / (fck / 1000 / 1000));
T
Tomi Valkeinen 已提交
3684 3685 3686
}
static int dsi_proto_config(struct omap_dss_device *dssdev)
{
3687
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
T
Tomi Valkeinen 已提交
3688 3689 3690
	u32 r;
	int buswidth = 0;

3691
	dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
3692 3693 3694
			DSI_FIFO_SIZE_32,
			DSI_FIFO_SIZE_32,
			DSI_FIFO_SIZE_32);
T
Tomi Valkeinen 已提交
3695

3696
	dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
3697 3698 3699
			DSI_FIFO_SIZE_32,
			DSI_FIFO_SIZE_32,
			DSI_FIFO_SIZE_32);
T
Tomi Valkeinen 已提交
3700 3701

	/* XXX what values for the timeouts? */
3702 3703 3704 3705
	dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
	dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
	dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
	dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
T
Tomi Valkeinen 已提交
3706

3707
	switch (dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt)) {
T
Tomi Valkeinen 已提交
3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720
	case 16:
		buswidth = 0;
		break;
	case 18:
		buswidth = 1;
		break;
	case 24:
		buswidth = 2;
		break;
	default:
		BUG();
	}

3721
	r = dsi_read_reg(dsidev, DSI_CTRL);
T
Tomi Valkeinen 已提交
3722 3723 3724 3725 3726 3727 3728 3729 3730
	r = FLD_MOD(r, 1, 1, 1);	/* CS_RX_EN */
	r = FLD_MOD(r, 1, 2, 2);	/* ECC_RX_EN */
	r = FLD_MOD(r, 1, 3, 3);	/* TX_FIFO_ARBITRATION */
	r = FLD_MOD(r, 1, 4, 4);	/* VP_CLK_RATIO, always 1, see errata*/
	r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
	r = FLD_MOD(r, 0, 8, 8);	/* VP_CLK_POL */
	r = FLD_MOD(r, 2, 13, 12);	/* LINE_BUFFER, 2 lines */
	r = FLD_MOD(r, 1, 14, 14);	/* TRIGGER_RESET_MODE */
	r = FLD_MOD(r, 1, 19, 19);	/* EOT_ENABLE */
3731 3732 3733 3734 3735
	if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
		r = FLD_MOD(r, 1, 24, 24);	/* DCS_CMD_ENABLE */
		/* DCS_CMD_CODE, 1=start, 0=continue */
		r = FLD_MOD(r, 0, 25, 25);
	}
T
Tomi Valkeinen 已提交
3736

3737
	dsi_write_reg(dsidev, DSI_CTRL, r);
T
Tomi Valkeinen 已提交
3738

3739 3740 3741 3742
	dsi_vc_initial_config(dsidev, 0);
	dsi_vc_initial_config(dsidev, 1);
	dsi_vc_initial_config(dsidev, 2);
	dsi_vc_initial_config(dsidev, 3);
T
Tomi Valkeinen 已提交
3743 3744 3745 3746 3747 3748

	return 0;
}

static void dsi_proto_timings(struct omap_dss_device *dssdev)
{
3749
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
T
Tomi Valkeinen 已提交
3750 3751 3752 3753 3754 3755 3756 3757 3758
	unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
	unsigned tclk_pre, tclk_post;
	unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
	unsigned ths_trail, ths_exit;
	unsigned ddr_clk_pre, ddr_clk_post;
	unsigned enter_hs_mode_lat, exit_hs_mode_lat;
	unsigned ths_eot;
	u32 r;

3759
	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
T
Tomi Valkeinen 已提交
3760 3761 3762 3763 3764 3765
	ths_prepare = FLD_GET(r, 31, 24);
	ths_prepare_ths_zero = FLD_GET(r, 23, 16);
	ths_zero = ths_prepare_ths_zero - ths_prepare;
	ths_trail = FLD_GET(r, 15, 8);
	ths_exit = FLD_GET(r, 7, 0);

3766
	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
T
Tomi Valkeinen 已提交
3767 3768 3769 3770
	tlpx = FLD_GET(r, 22, 16) * 2;
	tclk_trail = FLD_GET(r, 15, 8);
	tclk_zero = FLD_GET(r, 7, 0);

3771
	r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
T
Tomi Valkeinen 已提交
3772 3773 3774 3775 3776
	tclk_prepare = FLD_GET(r, 7, 0);

	/* min 8*UI */
	tclk_pre = 20;
	/* min 60ns + 52*UI */
3777
	tclk_post = ns2ddr(dsidev, 60) + 26;
T
Tomi Valkeinen 已提交
3778

3779
	ths_eot = DIV_ROUND_UP(4, dsi_get_num_data_lanes_dssdev(dssdev));
T
Tomi Valkeinen 已提交
3780 3781 3782 3783 3784 3785 3786 3787

	ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
			4);
	ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;

	BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
	BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);

3788
	r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
T
Tomi Valkeinen 已提交
3789 3790
	r = FLD_MOD(r, ddr_clk_pre, 15, 8);
	r = FLD_MOD(r, ddr_clk_post, 7, 0);
3791
	dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
T
Tomi Valkeinen 已提交
3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803 3804

	DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
			ddr_clk_pre,
			ddr_clk_post);

	enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
		DIV_ROUND_UP(ths_prepare, 4) +
		DIV_ROUND_UP(ths_zero + 3, 4);

	exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;

	r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
		FLD_VAL(exit_hs_mode_lat, 15, 0);
3805
	dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
T
Tomi Valkeinen 已提交
3806 3807 3808 3809 3810 3811 3812 3813

	DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
			enter_hs_mode_lat, exit_hs_mode_lat);
}

static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
		u16 x, u16 y, u16 w, u16 h)
{
3814
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3815
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
T
Tomi Valkeinen 已提交
3816 3817 3818 3819 3820 3821 3822
	unsigned bytespp;
	unsigned bytespl;
	unsigned bytespf;
	unsigned total_len;
	unsigned packet_payload;
	unsigned packet_len;
	u32 l;
3823
	int r;
3824
	const unsigned channel = dsi->update_channel;
3825
	const unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
T
Tomi Valkeinen 已提交
3826

3827 3828
	DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
			x, y, w, h);
T
Tomi Valkeinen 已提交
3829

3830
	dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
3831

3832
	bytespp	= dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8;
T
Tomi Valkeinen 已提交
3833 3834 3835 3836 3837 3838 3839 3840 3841 3842 3843 3844 3845 3846 3847 3848 3849 3850
	bytespl = w * bytespp;
	bytespf = bytespl * h;

	/* NOTE: packet_payload has to be equal to N * bytespl, where N is
	 * number of lines in a packet.  See errata about VP_CLK_RATIO */

	if (bytespf < line_buf_size)
		packet_payload = bytespf;
	else
		packet_payload = (line_buf_size) / bytespl * bytespl;

	packet_len = packet_payload + 1;	/* 1 byte for DCS cmd */
	total_len = (bytespf / packet_payload) * packet_len;

	if (bytespf % packet_payload)
		total_len += (bytespf % packet_payload) + 1;

	l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
3851
	dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
T
Tomi Valkeinen 已提交
3852

3853
	dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
3854
		packet_len, 0);
T
Tomi Valkeinen 已提交
3855

3856
	if (dsi->te_enabled)
T
Tomi Valkeinen 已提交
3857 3858 3859
		l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
	else
		l = FLD_MOD(l, 1, 31, 31); /* TE_START */
3860
	dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
T
Tomi Valkeinen 已提交
3861 3862 3863 3864 3865 3866 3867 3868 3869

	/* We put SIDLEMODE to no-idle for the duration of the transfer,
	 * because DSS interrupts are not capable of waking up the CPU and the
	 * framedone interrupt could be delayed for quite a long time. I think
	 * the same goes for any DSS interrupts, but for some reason I have not
	 * seen the problem anywhere else than here.
	 */
	dispc_disable_sidle();

3870
	dsi_perf_mark_start(dsidev);
3871

3872 3873
	r = schedule_delayed_work(&dsi->framedone_timeout_work,
		msecs_to_jiffies(250));
3874
	BUG_ON(r == 0);
3875

T
Tomi Valkeinen 已提交
3876 3877
	dss_start_update(dssdev);

3878
	if (dsi->te_enabled) {
T
Tomi Valkeinen 已提交
3879 3880
		/* disable LP_RX_TO, so that we can receive TE.  Time to wait
		 * for TE is longer than the timer allows */
3881
		REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
T
Tomi Valkeinen 已提交
3882

3883
		dsi_vc_send_bta(dsidev, channel);
T
Tomi Valkeinen 已提交
3884 3885

#ifdef DSI_CATCH_MISSING_TE
3886
		mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
T
Tomi Valkeinen 已提交
3887 3888 3889 3890 3891 3892 3893 3894 3895 3896 3897
#endif
	}
}

#ifdef DSI_CATCH_MISSING_TE
static void dsi_te_timeout(unsigned long arg)
{
	DSSERR("TE not received for 250ms!\n");
}
#endif

3898
static void dsi_handle_framedone(struct platform_device *dsidev, int error)
T
Tomi Valkeinen 已提交
3899
{
3900 3901
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

T
Tomi Valkeinen 已提交
3902 3903 3904
	/* SIDLEMODE back to smart-idle */
	dispc_enable_sidle();

3905
	if (dsi->te_enabled) {
3906
		/* enable LP_RX_TO again after the TE */
3907
		REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
T
Tomi Valkeinen 已提交
3908 3909
	}

3910
	dsi->framedone_callback(error, dsi->framedone_data);
3911 3912

	if (!error)
3913
		dsi_perf_show(dsidev, "DISPC");
3914
}
T
Tomi Valkeinen 已提交
3915

3916
static void dsi_framedone_timeout_work_callback(struct work_struct *work)
3917
{
3918 3919
	struct dsi_data *dsi = container_of(work, struct dsi_data,
			framedone_timeout_work.work);
3920 3921 3922 3923 3924 3925
	/* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
	 * 250ms which would conflict with this timeout work. What should be
	 * done is first cancel the transfer on the HW, and then cancel the
	 * possibly scheduled framedone work. However, cancelling the transfer
	 * on the HW is buggy, and would probably require resetting the whole
	 * DSI */
3926

3927
	DSSERR("Framedone not received for 250ms!\n");
T
Tomi Valkeinen 已提交
3928

3929
	dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
T
Tomi Valkeinen 已提交
3930 3931
}

3932
static void dsi_framedone_irq_callback(void *data, u32 mask)
T
Tomi Valkeinen 已提交
3933
{
3934 3935
	struct omap_dss_device *dssdev = (struct omap_dss_device *) data;
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3936 3937
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

3938 3939 3940 3941
	/* Note: We get FRAMEDONE when DISPC has finished sending pixels and
	 * turns itself off. However, DSI still has the pixels in its buffers,
	 * and is sending the data.
	 */
T
Tomi Valkeinen 已提交
3942

3943
	__cancel_delayed_work(&dsi->framedone_timeout_work);
T
Tomi Valkeinen 已提交
3944

3945
	dsi_handle_framedone(dsidev, 0);
T
Tomi Valkeinen 已提交
3946

3947 3948 3949
#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
	dispc_fake_vsync_irq();
#endif
3950
}
T
Tomi Valkeinen 已提交
3951

3952
int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
3953 3954
				    u16 *x, u16 *y, u16 *w, u16 *h,
				    bool enlarge_update_area)
3955
{
3956
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3957
	u16 dw, dh;
T
Tomi Valkeinen 已提交
3958

3959
	dssdev->driver->get_resolution(dssdev, &dw, &dh);
T
Tomi Valkeinen 已提交
3960

3961 3962
	if  (*x > dw || *y > dh)
		return -EINVAL;
T
Tomi Valkeinen 已提交
3963

3964 3965
	if (*x + *w > dw)
		return -EINVAL;
T
Tomi Valkeinen 已提交
3966

3967 3968
	if (*y + *h > dh)
		return -EINVAL;
T
Tomi Valkeinen 已提交
3969

3970 3971
	if (*w == 1)
		return -EINVAL;
T
Tomi Valkeinen 已提交
3972

3973 3974
	if (*w == 0 || *h == 0)
		return -EINVAL;
T
Tomi Valkeinen 已提交
3975

3976
	dsi_perf_mark_setup(dsidev);
T
Tomi Valkeinen 已提交
3977

3978 3979
	dss_setup_partial_planes(dssdev, x, y, w, h,
			enlarge_update_area);
3980
	dispc_mgr_set_lcd_size(dssdev->manager->id, *w, *h);
T
Tomi Valkeinen 已提交
3981

3982 3983 3984
	return 0;
}
EXPORT_SYMBOL(omap_dsi_prepare_update);
T
Tomi Valkeinen 已提交
3985

3986 3987 3988 3989 3990
int omap_dsi_update(struct omap_dss_device *dssdev,
		int channel,
		u16 x, u16 y, u16 w, u16 h,
		void (*callback)(int, void *), void *data)
{
3991
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3992
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3993

3994
	dsi->update_channel = channel;
T
Tomi Valkeinen 已提交
3995

3996 3997 3998 3999 4000 4001
	/* OMAP DSS cannot send updates of odd widths.
	 * omap_dsi_prepare_update() makes the widths even, but add a BUG_ON
	 * here to make sure we catch erroneous updates. Otherwise we'll only
	 * see rather obscure HW error happening, as DSS halts. */
	BUG_ON(x % 2 == 1);

4002 4003
	dsi->framedone_callback = callback;
	dsi->framedone_data = data;
4004

4005 4006 4007 4008 4009
	dsi->update_region.x = x;
	dsi->update_region.y = y;
	dsi->update_region.w = w;
	dsi->update_region.h = h;
	dsi->update_region.device = dssdev;
4010

4011
	dsi_update_screen_dispc(dssdev, x, y, w, h);
T
Tomi Valkeinen 已提交
4012 4013 4014

	return 0;
}
4015
EXPORT_SYMBOL(omap_dsi_update);
T
Tomi Valkeinen 已提交
4016 4017 4018 4019 4020 4021

/* Display funcs */

static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
{
	int r;
4022 4023 4024 4025
	u32 irq;

	irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
		DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
T
Tomi Valkeinen 已提交
4026

4027
	r = omap_dispc_register_isr(dsi_framedone_irq_callback, (void *) dssdev,
4028
			irq);
T
Tomi Valkeinen 已提交
4029 4030 4031 4032 4033
	if (r) {
		DSSERR("can't get FRAMEDONE irq\n");
		return r;
	}

4034
	dispc_mgr_set_lcd_display_type(dssdev->manager->id,
4035
			OMAP_DSS_LCD_DISPLAY_TFT);
T
Tomi Valkeinen 已提交
4036

4037
	dispc_mgr_enable_stallmode(dssdev->manager->id, true);
4038
	dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 1);
T
Tomi Valkeinen 已提交
4039

4040
	dispc_mgr_set_tft_data_lines(dssdev->manager->id,
4041
			dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt));
T
Tomi Valkeinen 已提交
4042 4043 4044 4045 4046 4047 4048 4049 4050 4051 4052

	{
		struct omap_video_timings timings = {
			.hsw		= 1,
			.hfp		= 1,
			.hbp		= 1,
			.vsw		= 1,
			.vfp		= 0,
			.vbp		= 0,
		};

4053
		dispc_mgr_set_lcd_timings(dssdev->manager->id, &timings);
T
Tomi Valkeinen 已提交
4054 4055 4056 4057 4058 4059 4060
	}

	return 0;
}

static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
{
4061 4062 4063 4064 4065
	u32 irq;

	irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
		DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;

4066
	omap_dispc_unregister_isr(dsi_framedone_irq_callback, (void *) dssdev,
4067
			irq);
T
Tomi Valkeinen 已提交
4068 4069 4070 4071
}

static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
{
4072
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
T
Tomi Valkeinen 已提交
4073 4074 4075
	struct dsi_clock_info cinfo;
	int r;

4076 4077
	/* we always use DSS_CLK_SYSCK as input clock */
	cinfo.use_sys_clk = true;
4078 4079 4080 4081
	cinfo.regn  = dssdev->clocks.dsi.regn;
	cinfo.regm  = dssdev->clocks.dsi.regm;
	cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc;
	cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi;
4082
	r = dsi_calc_clock_rates(dssdev, &cinfo);
4083 4084
	if (r) {
		DSSERR("Failed to calc dsi clocks\n");
T
Tomi Valkeinen 已提交
4085
		return r;
4086
	}
T
Tomi Valkeinen 已提交
4087

4088
	r = dsi_pll_set_clock_div(dsidev, &cinfo);
T
Tomi Valkeinen 已提交
4089 4090 4091 4092 4093 4094 4095 4096 4097 4098
	if (r) {
		DSSERR("Failed to set dsi clocks\n");
		return r;
	}

	return 0;
}

static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
{
4099
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
T
Tomi Valkeinen 已提交
4100 4101 4102 4103
	struct dispc_clock_info dispc_cinfo;
	int r;
	unsigned long long fck;

4104
	fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
T
Tomi Valkeinen 已提交
4105

4106 4107
	dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div;
	dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div;
T
Tomi Valkeinen 已提交
4108 4109 4110 4111 4112 4113 4114

	r = dispc_calc_clock_rates(fck, &dispc_cinfo);
	if (r) {
		DSSERR("Failed to calc dispc clocks\n");
		return r;
	}

4115
	r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
T
Tomi Valkeinen 已提交
4116 4117 4118 4119 4120 4121 4122 4123 4124 4125
	if (r) {
		DSSERR("Failed to set dispc clocks\n");
		return r;
	}

	return 0;
}

static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
{
4126
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4127
	int dsi_module = dsi_get_dsidev_id(dsidev);
T
Tomi Valkeinen 已提交
4128 4129
	int r;

4130
	r = dsi_pll_init(dsidev, true, true);
T
Tomi Valkeinen 已提交
4131 4132 4133 4134 4135 4136 4137
	if (r)
		goto err0;

	r = dsi_configure_dsi_clocks(dssdev);
	if (r)
		goto err1;

4138
	dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
4139
	dss_select_dsi_clk_source(dsi_module, dssdev->clocks.dsi.dsi_fclk_src);
4140
	dss_select_lcd_clk_source(dssdev->manager->id,
4141
			dssdev->clocks.dispc.channel.lcd_clk_src);
T
Tomi Valkeinen 已提交
4142 4143 4144 4145 4146 4147 4148

	DSSDBG("PLL OK\n");

	r = dsi_configure_dispc_clocks(dssdev);
	if (r)
		goto err2;

4149
	r = dsi_cio_init(dssdev);
T
Tomi Valkeinen 已提交
4150 4151 4152
	if (r)
		goto err2;

4153
	_dsi_print_reset_status(dsidev);
T
Tomi Valkeinen 已提交
4154 4155 4156 4157 4158

	dsi_proto_timings(dssdev);
	dsi_set_lp_clk_divisor(dssdev);

	if (1)
4159
		_dsi_print_reset_status(dsidev);
T
Tomi Valkeinen 已提交
4160 4161 4162 4163 4164 4165

	r = dsi_proto_config(dssdev);
	if (r)
		goto err3;

	/* enable interface */
4166 4167 4168 4169 4170 4171
	dsi_vc_enable(dsidev, 0, 1);
	dsi_vc_enable(dsidev, 1, 1);
	dsi_vc_enable(dsidev, 2, 1);
	dsi_vc_enable(dsidev, 3, 1);
	dsi_if_enable(dsidev, 1);
	dsi_force_tx_stop_mode_io(dsidev);
T
Tomi Valkeinen 已提交
4172 4173 4174

	return 0;
err3:
4175
	dsi_cio_uninit(dssdev);
T
Tomi Valkeinen 已提交
4176
err2:
4177
	dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4178
	dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
4179 4180
	dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK);

T
Tomi Valkeinen 已提交
4181
err1:
4182
	dsi_pll_uninit(dsidev, true);
T
Tomi Valkeinen 已提交
4183 4184 4185 4186
err0:
	return r;
}

4187
static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev,
4188
		bool disconnect_lanes, bool enter_ulps)
T
Tomi Valkeinen 已提交
4189
{
4190
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4191
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4192
	int dsi_module = dsi_get_dsidev_id(dsidev);
4193

4194
	if (enter_ulps && !dsi->ulps_enabled)
4195
		dsi_enter_ulps(dsidev);
4196

4197
	/* disable interface */
4198 4199 4200 4201 4202
	dsi_if_enable(dsidev, 0);
	dsi_vc_enable(dsidev, 0, 0);
	dsi_vc_enable(dsidev, 1, 0);
	dsi_vc_enable(dsidev, 2, 0);
	dsi_vc_enable(dsidev, 3, 0);
4203

4204
	dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4205
	dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
4206
	dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK);
4207
	dsi_cio_uninit(dssdev);
4208
	dsi_pll_uninit(dsidev, disconnect_lanes);
T
Tomi Valkeinen 已提交
4209 4210
}

4211
int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
T
Tomi Valkeinen 已提交
4212
{
4213
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4214
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
T
Tomi Valkeinen 已提交
4215 4216 4217 4218
	int r = 0;

	DSSDBG("dsi_display_enable\n");

4219
	WARN_ON(!dsi_bus_is_locked(dsidev));
4220

4221
	mutex_lock(&dsi->lock);
T
Tomi Valkeinen 已提交
4222

4223 4224 4225 4226 4227 4228
	if (dssdev->manager == NULL) {
		DSSERR("failed to enable display: no manager\n");
		r = -ENODEV;
		goto err_start_dev;
	}

T
Tomi Valkeinen 已提交
4229 4230 4231
	r = omap_dss_start_device(dssdev);
	if (r) {
		DSSERR("failed to start device\n");
4232
		goto err_start_dev;
T
Tomi Valkeinen 已提交
4233 4234
	}

4235
	r = dsi_runtime_get(dsidev);
T
Tomi Valkeinen 已提交
4236
	if (r)
4237 4238 4239
		goto err_get_dsi;

	dsi_enable_pll_clock(dsidev, 1);
T
Tomi Valkeinen 已提交
4240

4241
	_dsi_initialize_irq(dsidev);
T
Tomi Valkeinen 已提交
4242 4243 4244

	r = dsi_display_init_dispc(dssdev);
	if (r)
4245
		goto err_init_dispc;
T
Tomi Valkeinen 已提交
4246 4247 4248

	r = dsi_display_init_dsi(dssdev);
	if (r)
4249
		goto err_init_dsi;
T
Tomi Valkeinen 已提交
4250

4251
	mutex_unlock(&dsi->lock);
T
Tomi Valkeinen 已提交
4252 4253 4254

	return 0;

4255
err_init_dsi:
4256
	dsi_display_uninit_dispc(dssdev);
4257
err_init_dispc:
4258
	dsi_enable_pll_clock(dsidev, 0);
4259 4260
	dsi_runtime_put(dsidev);
err_get_dsi:
T
Tomi Valkeinen 已提交
4261
	omap_dss_stop_device(dssdev);
4262
err_start_dev:
4263
	mutex_unlock(&dsi->lock);
T
Tomi Valkeinen 已提交
4264 4265 4266
	DSSDBG("dsi_display_enable FAILED\n");
	return r;
}
4267
EXPORT_SYMBOL(omapdss_dsi_display_enable);
T
Tomi Valkeinen 已提交
4268

4269
void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
4270
		bool disconnect_lanes, bool enter_ulps)
T
Tomi Valkeinen 已提交
4271
{
4272
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4273
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4274

T
Tomi Valkeinen 已提交
4275 4276
	DSSDBG("dsi_display_disable\n");

4277
	WARN_ON(!dsi_bus_is_locked(dsidev));
T
Tomi Valkeinen 已提交
4278

4279
	mutex_lock(&dsi->lock);
T
Tomi Valkeinen 已提交
4280

4281 4282 4283 4284 4285
	dsi_sync_vc(dsidev, 0);
	dsi_sync_vc(dsidev, 1);
	dsi_sync_vc(dsidev, 2);
	dsi_sync_vc(dsidev, 3);

T
Tomi Valkeinen 已提交
4286 4287
	dsi_display_uninit_dispc(dssdev);

4288
	dsi_display_uninit_dsi(dssdev, disconnect_lanes, enter_ulps);
T
Tomi Valkeinen 已提交
4289

4290
	dsi_runtime_put(dsidev);
4291
	dsi_enable_pll_clock(dsidev, 0);
T
Tomi Valkeinen 已提交
4292

4293
	omap_dss_stop_device(dssdev);
T
Tomi Valkeinen 已提交
4294

4295
	mutex_unlock(&dsi->lock);
T
Tomi Valkeinen 已提交
4296
}
4297
EXPORT_SYMBOL(omapdss_dsi_display_disable);
T
Tomi Valkeinen 已提交
4298

4299
int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
T
Tomi Valkeinen 已提交
4300
{
4301 4302 4303 4304
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	dsi->te_enabled = enable;
4305
	return 0;
T
Tomi Valkeinen 已提交
4306
}
4307
EXPORT_SYMBOL(omapdss_dsi_enable_te);
T
Tomi Valkeinen 已提交
4308 4309

void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
4310
		u32 fifo_size, u32 burst_size,
T
Tomi Valkeinen 已提交
4311 4312
		u32 *fifo_low, u32 *fifo_high)
{
4313 4314
	*fifo_high = fifo_size - burst_size;
	*fifo_low = fifo_size - burst_size * 2;
T
Tomi Valkeinen 已提交
4315 4316 4317 4318
}

int dsi_init_display(struct omap_dss_device *dssdev)
{
4319 4320
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4321
	int dsi_module = dsi_get_dsidev_id(dsidev);
4322

T
Tomi Valkeinen 已提交
4323 4324
	DSSDBG("DSI init\n");

4325 4326 4327 4328
	if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
		dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
			OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
	}
T
Tomi Valkeinen 已提交
4329

4330
	if (dsi->vdds_dsi_reg == NULL) {
4331 4332
		struct regulator *vdds_dsi;

4333
		vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
4334 4335 4336 4337 4338 4339

		if (IS_ERR(vdds_dsi)) {
			DSSERR("can't get VDDS_DSI regulator\n");
			return PTR_ERR(vdds_dsi);
		}

4340
		dsi->vdds_dsi_reg = vdds_dsi;
4341 4342
	}

4343 4344 4345 4346 4347 4348
	if (dsi_get_num_data_lanes_dssdev(dssdev) > dsi->num_data_lanes) {
		DSSERR("DSI%d can't support more than %d data lanes\n",
			dsi_module + 1, dsi->num_data_lanes);
		return -EINVAL;
	}

T
Tomi Valkeinen 已提交
4349 4350 4351
	return 0;
}

4352 4353
int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
{
4354 4355
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4356 4357
	int i;

4358 4359 4360
	for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
		if (!dsi->vc[i].dssdev) {
			dsi->vc[i].dssdev = dssdev;
4361 4362 4363 4364 4365 4366 4367 4368 4369 4370 4371 4372
			*channel = i;
			return 0;
		}
	}

	DSSERR("cannot get VC for display %s", dssdev->name);
	return -ENOSPC;
}
EXPORT_SYMBOL(omap_dsi_request_vc);

int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
{
4373 4374 4375
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

4376 4377 4378 4379 4380 4381 4382 4383 4384 4385
	if (vc_id < 0 || vc_id > 3) {
		DSSERR("VC ID out of range\n");
		return -EINVAL;
	}

	if (channel < 0 || channel > 3) {
		DSSERR("Virtual Channel out of range\n");
		return -EINVAL;
	}

4386
	if (dsi->vc[channel].dssdev != dssdev) {
4387 4388 4389 4390 4391
		DSSERR("Virtual Channel not allocated to display %s\n",
			dssdev->name);
		return -EINVAL;
	}

4392
	dsi->vc[channel].vc_id = vc_id;
4393 4394 4395 4396 4397 4398 4399

	return 0;
}
EXPORT_SYMBOL(omap_dsi_set_vc_id);

void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel)
{
4400 4401 4402
	struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

4403
	if ((channel >= 0 && channel <= 3) &&
4404 4405 4406
		dsi->vc[channel].dssdev == dssdev) {
		dsi->vc[channel].dssdev = NULL;
		dsi->vc[channel].vc_id = 0;
4407 4408 4409 4410
	}
}
EXPORT_SYMBOL(omap_dsi_release_vc);

4411
void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
4412
{
4413
	if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1)
4414
		DSSERR("%s (%s) not active\n",
4415 4416
			dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
			dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
4417 4418
}

4419
void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
4420
{
4421
	if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1)
4422
		DSSERR("%s (%s) not active\n",
4423 4424
			dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
			dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
4425 4426
}

4427
static void dsi_calc_clock_param_ranges(struct platform_device *dsidev)
4428
{
4429 4430 4431 4432 4433 4434 4435 4436 4437 4438
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
	dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
	dsi->regm_dispc_max =
		dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
	dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
	dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
	dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
	dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
4439 4440
}

4441 4442 4443 4444 4445 4446 4447 4448 4449 4450 4451 4452 4453
static int dsi_get_clocks(struct platform_device *dsidev)
{
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
	struct clk *clk;

	clk = clk_get(&dsidev->dev, "fck");
	if (IS_ERR(clk)) {
		DSSERR("can't get fck\n");
		return PTR_ERR(clk);
	}

	dsi->dss_clk = clk;

4454
	clk = clk_get(&dsidev->dev, "sys_clk");
4455 4456 4457 4458 4459 4460 4461 4462 4463 4464 4465 4466 4467 4468 4469 4470 4471 4472 4473 4474 4475 4476
	if (IS_ERR(clk)) {
		DSSERR("can't get sys_clk\n");
		clk_put(dsi->dss_clk);
		dsi->dss_clk = NULL;
		return PTR_ERR(clk);
	}

	dsi->sys_clk = clk;

	return 0;
}

static void dsi_put_clocks(struct platform_device *dsidev)
{
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

	if (dsi->dss_clk)
		clk_put(dsi->dss_clk);
	if (dsi->sys_clk)
		clk_put(dsi->sys_clk);
}

4477
/* DSI1 HW IP initialisation */
4478
static int omap_dsihw_probe(struct platform_device *dsidev)
T
Tomi Valkeinen 已提交
4479
{
4480 4481
	struct omap_display_platform_data *dss_plat_data;
	struct omap_dss_board_info *board_info;
T
Tomi Valkeinen 已提交
4482
	u32 rev;
4483
	int r, i, dsi_module = dsi_get_dsidev_id(dsidev);
4484
	struct resource *dsi_mem;
4485 4486 4487 4488 4489
	struct dsi_data *dsi;

	dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
	if (!dsi) {
		r = -ENOMEM;
4490
		goto err_alloc;
4491
	}
T
Tomi Valkeinen 已提交
4492

4493 4494 4495
	dsi->pdev = dsidev;
	dsi_pdev_map[dsi_module] = dsidev;
	dev_set_drvdata(&dsidev->dev, dsi);
4496 4497

	dss_plat_data = dsidev->dev.platform_data;
4498
	board_info = dss_plat_data->board_data;
4499 4500
	dsi->enable_pads = board_info->dsi_enable_pads;
	dsi->disable_pads = board_info->dsi_disable_pads;
4501

4502 4503 4504
	spin_lock_init(&dsi->irq_lock);
	spin_lock_init(&dsi->errors_lock);
	dsi->errors = 0;
T
Tomi Valkeinen 已提交
4505

4506
#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4507 4508
	spin_lock_init(&dsi->irq_stats_lock);
	dsi->irq_stats.last_reset = jiffies;
4509 4510
#endif

4511 4512
	mutex_init(&dsi->lock);
	sema_init(&dsi->bus_lock, 1);
T
Tomi Valkeinen 已提交
4513

4514 4515 4516 4517 4518 4519
	r = dsi_get_clocks(dsidev);
	if (r)
		goto err_get_clk;

	pm_runtime_enable(&dsidev->dev);

4520
	INIT_DELAYED_WORK_DEFERRABLE(&dsi->framedone_timeout_work,
4521 4522
			dsi_framedone_timeout_work_callback);

T
Tomi Valkeinen 已提交
4523
#ifdef DSI_CATCH_MISSING_TE
4524 4525 4526
	init_timer(&dsi->te_timer);
	dsi->te_timer.function = dsi_te_timeout;
	dsi->te_timer.data = 0;
T
Tomi Valkeinen 已提交
4527
#endif
4528
	dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0);
4529 4530 4531
	if (!dsi_mem) {
		DSSERR("can't get IORESOURCE_MEM DSI\n");
		r = -EINVAL;
4532
		goto err_ioremap;
4533
	}
4534 4535
	dsi->base = ioremap(dsi_mem->start, resource_size(dsi_mem));
	if (!dsi->base) {
T
Tomi Valkeinen 已提交
4536 4537
		DSSERR("can't ioremap DSI\n");
		r = -ENOMEM;
4538
		goto err_ioremap;
T
Tomi Valkeinen 已提交
4539
	}
4540 4541
	dsi->irq = platform_get_irq(dsi->pdev, 0);
	if (dsi->irq < 0) {
4542 4543
		DSSERR("platform_get_irq failed\n");
		r = -ENODEV;
4544
		goto err_get_irq;
4545 4546
	}

4547 4548
	r = request_irq(dsi->irq, omap_dsi_irq_handler, IRQF_SHARED,
		dev_name(&dsidev->dev), dsi->pdev);
4549 4550
	if (r < 0) {
		DSSERR("request_irq failed\n");
4551
		goto err_get_irq;
4552
	}
T
Tomi Valkeinen 已提交
4553

4554
	/* DSI VCs initialization */
4555
	for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4556
		dsi->vc[i].source = DSI_VC_SOURCE_L4;
4557 4558
		dsi->vc[i].dssdev = NULL;
		dsi->vc[i].vc_id = 0;
4559 4560
	}

4561
	dsi_calc_clock_param_ranges(dsidev);
4562

4563 4564 4565
	r = dsi_runtime_get(dsidev);
	if (r)
		goto err_get_dsi;
T
Tomi Valkeinen 已提交
4566

4567 4568
	rev = dsi_read_reg(dsidev, DSI_REVISION);
	dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
T
Tomi Valkeinen 已提交
4569 4570
	       FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));

4571 4572
	dsi->num_data_lanes = dsi_get_num_data_lanes(dsidev);

4573
	dsi_runtime_put(dsidev);
T
Tomi Valkeinen 已提交
4574 4575

	return 0;
4576 4577 4578 4579

err_get_dsi:
	free_irq(dsi->irq, dsi->pdev);
err_get_irq:
4580
	iounmap(dsi->base);
4581 4582 4583
err_ioremap:
	pm_runtime_disable(&dsidev->dev);
err_get_clk:
4584
	kfree(dsi);
4585
err_alloc:
T
Tomi Valkeinen 已提交
4586 4587 4588
	return r;
}

4589
static int omap_dsihw_remove(struct platform_device *dsidev)
T
Tomi Valkeinen 已提交
4590
{
4591 4592
	struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);

4593 4594
	WARN_ON(dsi->scp_clk_refcount > 0);

4595 4596 4597 4598
	pm_runtime_disable(&dsidev->dev);

	dsi_put_clocks(dsidev);

4599 4600 4601 4602
	if (dsi->vdds_dsi_reg != NULL) {
		if (dsi->vdds_dsi_enabled) {
			regulator_disable(dsi->vdds_dsi_reg);
			dsi->vdds_dsi_enabled = false;
4603 4604
		}

4605 4606
		regulator_put(dsi->vdds_dsi_reg);
		dsi->vdds_dsi_reg = NULL;
4607 4608
	}

4609 4610
	free_irq(dsi->irq, dsi->pdev);
	iounmap(dsi->base);
T
Tomi Valkeinen 已提交
4611

4612
	kfree(dsi);
4613

4614 4615 4616
	return 0;
}

4617 4618 4619 4620 4621 4622 4623 4624 4625 4626 4627 4628 4629 4630 4631 4632 4633 4634 4635 4636 4637 4638 4639 4640 4641 4642 4643 4644 4645 4646 4647 4648 4649
static int dsi_runtime_suspend(struct device *dev)
{
	dispc_runtime_put();
	dss_runtime_put();

	return 0;
}

static int dsi_runtime_resume(struct device *dev)
{
	int r;

	r = dss_runtime_get();
	if (r)
		goto err_get_dss;

	r = dispc_runtime_get();
	if (r)
		goto err_get_dispc;

	return 0;

err_get_dispc:
	dss_runtime_put();
err_get_dss:
	return r;
}

static const struct dev_pm_ops dsi_pm_ops = {
	.runtime_suspend = dsi_runtime_suspend,
	.runtime_resume = dsi_runtime_resume,
};

4650 4651 4652
static struct platform_driver omap_dsihw_driver = {
	.probe          = omap_dsihw_probe,
	.remove         = omap_dsihw_remove,
4653
	.driver         = {
4654
		.name   = "omapdss_dsi",
4655
		.owner  = THIS_MODULE,
4656
		.pm	= &dsi_pm_ops,
4657 4658 4659 4660 4661
	},
};

int dsi_init_platform_driver(void)
{
4662
	return platform_driver_register(&omap_dsihw_driver);
4663 4664 4665 4666
}

void dsi_uninit_platform_driver(void)
{
4667
	return platform_driver_unregister(&omap_dsihw_driver);
4668
}