mce_amd.c 34.1 KB
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/*
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 *  (c) 2005-2016 Advanced Micro Devices, Inc.
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 *  Your use of this code is subject to the terms and conditions of the
 *  GNU general public license version 2. See "COPYING" or
 *  http://www.gnu.org/licenses/gpl.html
 *
 *  Written by Jacob Shin - AMD, Inc.
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 *  Maintained by: Borislav Petkov <bp@alien8.de>
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 *
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 *  All MC4_MISCi registers are shared between cores on a node.
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 */
#include <linux/interrupt.h>
#include <linux/notifier.h>
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#include <linux/kobject.h>
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#include <linux/percpu.h>
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#include <linux/errno.h>
#include <linux/sched.h>
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#include <linux/sysfs.h>
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#include <linux/slab.h>
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#include <linux/init.h>
#include <linux/cpu.h>
#include <linux/smp.h>
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#include <linux/string.h>
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#include <asm/amd_nb.h>
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#include <asm/apic.h>
#include <asm/mce.h>
#include <asm/msr.h>
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#include <asm/trace/irq_vectors.h>
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#include "mce-internal.h"

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#define NR_BLOCKS         5
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#define THRESHOLD_MAX     0xFFF
#define INT_TYPE_APIC     0x00020000
#define MASK_VALID_HI     0x80000000
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#define MASK_CNTP_HI      0x40000000
#define MASK_LOCKED_HI    0x20000000
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#define MASK_LVTOFF_HI    0x00F00000
#define MASK_COUNT_EN_HI  0x00080000
#define MASK_INT_TYPE_HI  0x00060000
#define MASK_OVERFLOW_HI  0x00010000
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#define MASK_ERR_COUNT_HI 0x00000FFF
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#define MASK_BLKPTR_LO    0xFF000000
#define MCG_XBLK_ADDR     0xC0000400
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/* Deferred error settings */
#define MSR_CU_DEF_ERR		0xC0000410
#define MASK_DEF_LVTOFF		0x000000F0
#define MASK_DEF_INT_TYPE	0x00000006
#define DEF_LVT_OFF		0x2
#define DEF_INT_TYPE_APIC	0x2

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/* Scalable MCA: */

/* Threshold LVT offset is at MSR0xC0000410[15:12] */
#define SMCA_THR_LVT_OFF	0xF000

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static bool thresholding_irq_en;
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static const char * const th_names[] = {
	"load_store",
	"insn_fetch",
	"combined_unit",
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	"decode_unit",
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	"northbridge",
	"execution_unit",
};

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static const char * const smca_umc_block_names[] = {
	"dram_ecc",
	"misc_umc"
};

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struct smca_bank_name {
	const char *name;	/* Short name for sysfs */
	const char *long_name;	/* Long name for pretty-printing */
};

static struct smca_bank_name smca_names[] = {
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	[SMCA_LS]	= { "load_store",	"Load Store Unit" },
	[SMCA_IF]	= { "insn_fetch",	"Instruction Fetch Unit" },
	[SMCA_L2_CACHE]	= { "l2_cache",		"L2 Cache" },
	[SMCA_DE]	= { "decode_unit",	"Decode Unit" },
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	[SMCA_RESERVED]	= { "reserved",		"Reserved" },
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	[SMCA_EX]	= { "execution_unit",	"Execution Unit" },
	[SMCA_FP]	= { "floating_point",	"Floating Point Unit" },
	[SMCA_L3_CACHE]	= { "l3_cache",		"L3 Cache" },
	[SMCA_CS]	= { "coherent_slave",	"Coherent Slave" },
	[SMCA_PIE]	= { "pie",		"Power, Interrupts, etc." },
	[SMCA_UMC]	= { "umc",		"Unified Memory Controller" },
	[SMCA_PB]	= { "param_block",	"Parameter Block" },
	[SMCA_PSP]	= { "psp",		"Platform Security Processor" },
	[SMCA_SMU]	= { "smu",		"System Management Unit" },
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};
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static u32 smca_bank_addrs[MAX_NR_BANKS][NR_BLOCKS] __ro_after_init =
{
	[0 ... MAX_NR_BANKS - 1] = { [0 ... NR_BLOCKS - 1] = -1 }
};

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const char *smca_get_name(enum smca_bank_types t)
{
	if (t >= N_SMCA_BANK_TYPES)
		return NULL;

	return smca_names[t].name;
}

const char *smca_get_long_name(enum smca_bank_types t)
{
	if (t >= N_SMCA_BANK_TYPES)
		return NULL;

	return smca_names[t].long_name;
}
EXPORT_SYMBOL_GPL(smca_get_long_name);
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static enum smca_bank_types smca_get_bank_type(unsigned int bank)
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{
	struct smca_bank *b;

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	if (bank >= MAX_NR_BANKS)
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		return N_SMCA_BANK_TYPES;

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	b = &smca_banks[bank];
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	if (!b->hwid)
		return N_SMCA_BANK_TYPES;

	return b->hwid->bank_type;
}

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static struct smca_hwid smca_hwid_mcatypes[] = {
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	/* { bank_type, hwid_mcatype, xec_bitmap } */

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	/* Reserved type */
	{ SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0), 0x0 },

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	/* ZN Core (HWID=0xB0) MCA types */
	{ SMCA_LS,	 HWID_MCATYPE(0xB0, 0x0), 0x1FFFEF },
	{ SMCA_IF,	 HWID_MCATYPE(0xB0, 0x1), 0x3FFF },
	{ SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2), 0xF },
	{ SMCA_DE,	 HWID_MCATYPE(0xB0, 0x3), 0x1FF },
	/* HWID 0xB0 MCATYPE 0x4 is Reserved */
	{ SMCA_EX,	 HWID_MCATYPE(0xB0, 0x5), 0x7FF },
	{ SMCA_FP,	 HWID_MCATYPE(0xB0, 0x6), 0x7F },
	{ SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7), 0xFF },

	/* Data Fabric MCA types */
	{ SMCA_CS,	 HWID_MCATYPE(0x2E, 0x0), 0x1FF },
	{ SMCA_PIE,	 HWID_MCATYPE(0x2E, 0x1), 0xF },

	/* Unified Memory Controller MCA type */
	{ SMCA_UMC,	 HWID_MCATYPE(0x96, 0x0), 0x3F },

	/* Parameter Block MCA type */
	{ SMCA_PB,	 HWID_MCATYPE(0x05, 0x0), 0x1 },
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	/* Platform Security Processor MCA type */
	{ SMCA_PSP,	 HWID_MCATYPE(0xFF, 0x0), 0x1 },

	/* System Management Unit MCA type */
	{ SMCA_SMU,	 HWID_MCATYPE(0x01, 0x0), 0x1 },
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};
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struct smca_bank smca_banks[MAX_NR_BANKS];
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EXPORT_SYMBOL_GPL(smca_banks);
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/*
 * In SMCA enabled processors, we can have multiple banks for a given IP type.
 * So to define a unique name for each bank, we use a temp c-string to append
 * the MCA_IPID[InstanceId] to type's name in get_name().
 *
 * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN
 * is greater than 8 plus 1 (for underscore) plus length of longest type name.
 */
#define MAX_MCATYPE_NAME_LEN	30
static char buf_mcatype[MAX_MCATYPE_NAME_LEN];

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static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks);
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static DEFINE_PER_CPU(unsigned int, bank_map);	/* see which banks are on */
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static void amd_threshold_interrupt(void);
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static void amd_deferred_error_interrupt(void);

static void default_deferred_error_interrupt(void)
{
	pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR);
}
void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt;
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static void smca_configure(unsigned int bank, unsigned int cpu)
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{
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	unsigned int i, hwid_mcatype;
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	struct smca_hwid *s_hwid;
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	u32 high, low;
	u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank);

	/* Set appropriate bits in MCA_CONFIG */
	if (!rdmsr_safe(smca_config, &low, &high)) {
		/*
		 * OS is required to set the MCAX bit to acknowledge that it is
		 * now using the new MSR ranges and new registers under each
		 * bank. It also means that the OS will configure deferred
		 * errors in the new MCx_CONFIG register. If the bit is not set,
		 * uncorrectable errors will cause a system panic.
		 *
		 * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.)
		 */
		high |= BIT(0);

		/*
		 * SMCA sets the Deferred Error Interrupt type per bank.
		 *
		 * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us
		 * if the DeferredIntType bit field is available.
		 *
		 * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the
		 * high portion of the MSR). OS should set this to 0x1 to enable
		 * APIC based interrupt. First, check that no interrupt has been
		 * set.
		 */
		if ((low & BIT(5)) && !((high >> 5) & 0x3))
			high |= BIT(5);

		wrmsr(smca_config, low, high);
	}
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	/* Return early if this bank was already initialized. */
	if (smca_banks[bank].hwid)
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		return;

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	if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) {
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		pr_warn("Failed to read MCA_IPID for bank %d\n", bank);
		return;
	}

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	hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID,
				    (high & MCI_IPID_MCATYPE) >> 16);
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	for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) {
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		s_hwid = &smca_hwid_mcatypes[i];
		if (hwid_mcatype == s_hwid->hwid_mcatype) {
			smca_banks[bank].hwid = s_hwid;
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			smca_banks[bank].id = low;
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			smca_banks[bank].sysfs_id = s_hwid->count++;
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			break;
		}
	}
}

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struct thresh_restart {
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	struct threshold_block	*b;
	int			reset;
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	int			set_lvt_off;
	int			lvt_off;
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	u16			old_limit;
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};

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static inline bool is_shared_bank(int bank)
{
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	/*
	 * Scalable MCA provides for only one core to have access to the MSRs of
	 * a shared bank.
	 */
	if (mce_flags.smca)
		return false;

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	/* Bank 4 is for northbridge reporting and is thus shared */
	return (bank == 4);
}

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static const char *bank4_names(const struct threshold_block *b)
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{
	switch (b->address) {
	/* MSR4_MISC0 */
	case 0x00000413:
		return "dram";

	case 0xc0000408:
		return "ht_links";

	case 0xc0000409:
		return "l3_cache";

	default:
		WARN(1, "Funny MSR: 0x%08x\n", b->address);
		return "";
	}
};


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static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)
{
	/*
	 * bank 4 supports APIC LVT interrupts implicitly since forever.
	 */
	if (bank == 4)
		return true;

	/*
	 * IntP: interrupt present; if this bit is set, the thresholding
	 * bank can generate APIC LVT interrupts
	 */
	return msr_high_bits & BIT(28);
}

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static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
{
	int msr = (hi & MASK_LVTOFF_HI) >> 20;

	if (apic < 0) {
		pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt "
		       "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,
		       b->bank, b->block, b->address, hi, lo);
		return 0;
	}

	if (apic != msr) {
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		/*
		 * On SMCA CPUs, LVT offset is programmed at a different MSR, and
		 * the BIOS provides the value. The original field where LVT offset
		 * was set is reserved. Return early here:
		 */
		if (mce_flags.smca)
			return 0;

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		pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
		       "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
		       b->cpu, apic, b->bank, b->block, b->address, hi, lo);
		return 0;
	}

	return 1;
};

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/* Reprogram MCx_MISC MSR behind this threshold bank. */
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static void threshold_restart_bank(void *_tr)
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{
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	struct thresh_restart *tr = _tr;
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	u32 hi, lo;
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	rdmsr(tr->b->address, lo, hi);
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	if (tr->b->threshold_limit < (hi & THRESHOLD_MAX))
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		tr->reset = 1;	/* limit cannot be lower than err count */
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	if (tr->reset) {		/* reset err count and overflow bit */
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		hi =
		    (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
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		    (THRESHOLD_MAX - tr->b->threshold_limit);
	} else if (tr->old_limit) {	/* change limit w/o reset */
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		int new_count = (hi & THRESHOLD_MAX) +
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		    (tr->old_limit - tr->b->threshold_limit);
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		hi = (hi & ~MASK_ERR_COUNT_HI) |
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		    (new_count & THRESHOLD_MAX);
	}

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	/* clear IntType */
	hi &= ~MASK_INT_TYPE_HI;

	if (!tr->b->interrupt_capable)
		goto done;

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	if (tr->set_lvt_off) {
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		if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
			/* set new lvt offset */
			hi &= ~MASK_LVTOFF_HI;
			hi |= tr->lvt_off << 20;
		}
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	}

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	if (tr->b->interrupt_enable)
		hi |= INT_TYPE_APIC;

 done:
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	hi |= MASK_COUNT_EN_HI;
	wrmsr(tr->b->address, lo, hi);
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}

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static void mce_threshold_block_init(struct threshold_block *b, int offset)
{
	struct thresh_restart tr = {
		.b			= b,
		.set_lvt_off		= 1,
		.lvt_off		= offset,
	};

	b->threshold_limit		= THRESHOLD_MAX;
	threshold_restart_bank(&tr);
};

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static int setup_APIC_mce_threshold(int reserved, int new)
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{
	if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,
					      APIC_EILVT_MSG_FIX, 0))
		return new;

	return reserved;
}

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static int setup_APIC_deferred_error(int reserved, int new)
{
	if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR,
					      APIC_EILVT_MSG_FIX, 0))
		return new;

	return reserved;
}

static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
{
	u32 low = 0, high = 0;
	int def_offset = -1, def_new;

	if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high))
		return;

	def_new = (low & MASK_DEF_LVTOFF) >> 4;
	if (!(low & MASK_DEF_LVTOFF)) {
		pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n");
		def_new = DEF_LVT_OFF;
		low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4);
	}

	def_offset = setup_APIC_deferred_error(def_offset, def_new);
	if ((def_offset == def_new) &&
	    (deferred_error_int_vector != amd_deferred_error_interrupt))
		deferred_error_int_vector = amd_deferred_error_interrupt;

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	if (!mce_flags.smca)
		low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;

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	wrmsr(MSR_CU_DEF_ERR, low, high);
}

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static u32 smca_get_block_address(unsigned int bank, unsigned int block)
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{
	u32 low, high;
	u32 addr = 0;

	if (smca_get_bank_type(bank) == SMCA_RESERVED)
		return addr;

	if (!block)
		return MSR_AMD64_SMCA_MCx_MISC(bank);

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	/* Check our cache first: */
	if (smca_bank_addrs[bank][block] != -1)
		return smca_bank_addrs[bank][block];

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	/*
	 * For SMCA enabled processors, BLKPTR field of the first MISC register
	 * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4).
	 */
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	if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high))
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		goto out;
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	if (!(low & MCI_CONFIG_MCAX))
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		goto out;
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	if (!rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) &&
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	    (low & MASK_BLKPTR_LO))
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		addr = MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1);
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out:
	smca_bank_addrs[bank][block] = addr;
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	return addr;
}

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static u32 get_block_address(u32 current_addr, u32 low, u32 high,
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			     unsigned int bank, unsigned int block)
{
	u32 addr = 0, offset = 0;

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	if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS))
		return addr;

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	if (mce_flags.smca)
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		return smca_get_block_address(bank, block);
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	/* Fall back to method we used for older processors: */
	switch (block) {
	case 0:
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		addr = msr_ops.misc(bank);
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		break;
	case 1:
		offset = ((low & MASK_BLKPTR_LO) >> 21);
		if (offset)
			addr = MCG_XBLK_ADDR + offset;
		break;
	default:
		addr = ++current_addr;
	}
	return addr;
}

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static int
prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
			int offset, u32 misc_high)
{
	unsigned int cpu = smp_processor_id();
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	u32 smca_low, smca_high;
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	struct threshold_block b;
	int new;

	if (!block)
		per_cpu(bank_map, cpu) |= (1 << bank);

	memset(&b, 0, sizeof(b));
	b.cpu			= cpu;
	b.bank			= bank;
	b.block			= block;
	b.address		= addr;
	b.interrupt_capable	= lvt_interrupt_supported(bank, misc_high);

	if (!b.interrupt_capable)
		goto done;

	b.interrupt_enable = 1;

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	if (!mce_flags.smca) {
		new = (misc_high & MASK_LVTOFF_HI) >> 20;
		goto set_offset;
	}
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	/* Gather LVT offset for thresholding: */
	if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high))
		goto out;

	new = (smca_low & SMCA_THR_LVT_OFF) >> 12;

set_offset:
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	offset = setup_APIC_mce_threshold(offset, new);
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	if (offset == new)
		thresholding_irq_en = true;
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done:
	mce_threshold_block_init(&b, offset);

out:
	return offset;
}

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/* cpu init entry point, called from mce.c with preempt off */
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void mce_amd_feature_init(struct cpuinfo_x86 *c)
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{
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	u32 low = 0, high = 0, address = 0;
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	unsigned int bank, block, cpu = smp_processor_id();
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	int offset = -1;
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	for (bank = 0; bank < mca_cfg.banks; ++bank) {
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		if (mce_flags.smca)
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			smca_configure(bank, cpu);
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		for (block = 0; block < NR_BLOCKS; ++block) {
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			address = get_block_address(address, low, high, bank, block);
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			if (!address)
				break;
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			if (rdmsr_safe(address, &low, &high))
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				break;
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			if (!(high & MASK_VALID_HI))
				continue;
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			if (!(high & MASK_CNTP_HI)  ||
			     (high & MASK_LOCKED_HI))
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				continue;

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			offset = prepare_threshold_block(bank, block, address, offset, high);
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		}
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	}
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	if (mce_flags.succor)
		deferred_error_interrupt_enable(c);
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}

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int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr)
{
	u64 dram_base_addr, dram_limit_addr, dram_hole_base;
	/* We start from the normalized address */
	u64 ret_addr = norm_addr;

	u32 tmp;

	u8 die_id_shift, die_id_mask, socket_id_shift, socket_id_mask;
	u8 intlv_num_dies, intlv_num_chan, intlv_num_sockets;
	u8 intlv_addr_sel, intlv_addr_bit;
	u8 num_intlv_bits, hashed_bit;
	u8 lgcy_mmio_hole_en, base = 0;
	u8 cs_mask, cs_id = 0;
	bool hash_enabled = false;

	/* Read D18F0x1B4 (DramOffset), check if base 1 is used. */
	if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp))
		goto out_err;

	/* Remove HiAddrOffset from normalized address, if enabled: */
	if (tmp & BIT(0)) {
		u64 hi_addr_offset = (tmp & GENMASK_ULL(31, 20)) << 8;

		if (norm_addr >= hi_addr_offset) {
			ret_addr -= hi_addr_offset;
			base = 1;
		}
	}

	/* Read D18F0x110 (DramBaseAddress). */
	if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp))
		goto out_err;

	/* Check if address range is valid. */
	if (!(tmp & BIT(0))) {
		pr_err("%s: Invalid DramBaseAddress range: 0x%x.\n",
			__func__, tmp);
		goto out_err;
	}

	lgcy_mmio_hole_en = tmp & BIT(1);
	intlv_num_chan	  = (tmp >> 4) & 0xF;
	intlv_addr_sel	  = (tmp >> 8) & 0x7;
	dram_base_addr	  = (tmp & GENMASK_ULL(31, 12)) << 16;

	/* {0, 1, 2, 3} map to address bits {8, 9, 10, 11} respectively */
	if (intlv_addr_sel > 3) {
		pr_err("%s: Invalid interleave address select %d.\n",
			__func__, intlv_addr_sel);
		goto out_err;
	}

	/* Read D18F0x114 (DramLimitAddress). */
	if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp))
		goto out_err;

	intlv_num_sockets = (tmp >> 8) & 0x1;
	intlv_num_dies	  = (tmp >> 10) & 0x3;
	dram_limit_addr	  = ((tmp & GENMASK_ULL(31, 12)) << 16) | GENMASK_ULL(27, 0);

	intlv_addr_bit = intlv_addr_sel + 8;

	/* Re-use intlv_num_chan by setting it equal to log2(#channels) */
	switch (intlv_num_chan) {
	case 0:	intlv_num_chan = 0; break;
	case 1: intlv_num_chan = 1; break;
	case 3: intlv_num_chan = 2; break;
	case 5:	intlv_num_chan = 3; break;
	case 7:	intlv_num_chan = 4; break;

	case 8: intlv_num_chan = 1;
		hash_enabled = true;
		break;
	default:
		pr_err("%s: Invalid number of interleaved channels %d.\n",
			__func__, intlv_num_chan);
		goto out_err;
	}

	num_intlv_bits = intlv_num_chan;

	if (intlv_num_dies > 2) {
		pr_err("%s: Invalid number of interleaved nodes/dies %d.\n",
			__func__, intlv_num_dies);
		goto out_err;
	}

	num_intlv_bits += intlv_num_dies;

	/* Add a bit if sockets are interleaved. */
	num_intlv_bits += intlv_num_sockets;

	/* Assert num_intlv_bits <= 4 */
	if (num_intlv_bits > 4) {
		pr_err("%s: Invalid interleave bits %d.\n",
			__func__, num_intlv_bits);
		goto out_err;
	}

	if (num_intlv_bits > 0) {
		u64 temp_addr_x, temp_addr_i, temp_addr_y;
		u8 die_id_bit, sock_id_bit, cs_fabric_id;

		/*
		 * Read FabricBlockInstanceInformation3_CS[BlockFabricID].
		 * This is the fabric id for this coherent slave. Use
		 * umc/channel# as instance id of the coherent slave
		 * for FICAA.
		 */
		if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp))
			goto out_err;

		cs_fabric_id = (tmp >> 8) & 0xFF;
		die_id_bit   = 0;

		/* If interleaved over more than 1 channel: */
		if (intlv_num_chan) {
			die_id_bit = intlv_num_chan;
			cs_mask	   = (1 << die_id_bit) - 1;
			cs_id	   = cs_fabric_id & cs_mask;
		}

		sock_id_bit = die_id_bit;

		/* Read D18F1x208 (SystemFabricIdMask). */
		if (intlv_num_dies || intlv_num_sockets)
			if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp))
				goto out_err;

		/* If interleaved over more than 1 die. */
		if (intlv_num_dies) {
			sock_id_bit  = die_id_bit + intlv_num_dies;
			die_id_shift = (tmp >> 24) & 0xF;
			die_id_mask  = (tmp >> 8) & 0xFF;

			cs_id |= ((cs_fabric_id & die_id_mask) >> die_id_shift) << die_id_bit;
		}

		/* If interleaved over more than 1 socket. */
		if (intlv_num_sockets) {
			socket_id_shift	= (tmp >> 28) & 0xF;
			socket_id_mask	= (tmp >> 16) & 0xFF;

			cs_id |= ((cs_fabric_id & socket_id_mask) >> socket_id_shift) << sock_id_bit;
		}

		/*
		 * The pre-interleaved address consists of XXXXXXIIIYYYYY
		 * where III is the ID for this CS, and XXXXXXYYYYY are the
		 * address bits from the post-interleaved address.
		 * "num_intlv_bits" has been calculated to tell us how many "I"
		 * bits there are. "intlv_addr_bit" tells us how many "Y" bits
		 * there are (where "I" starts).
		 */
		temp_addr_y = ret_addr & GENMASK_ULL(intlv_addr_bit-1, 0);
		temp_addr_i = (cs_id << intlv_addr_bit);
		temp_addr_x = (ret_addr & GENMASK_ULL(63, intlv_addr_bit)) << num_intlv_bits;
		ret_addr    = temp_addr_x | temp_addr_i | temp_addr_y;
	}

	/* Add dram base address */
	ret_addr += dram_base_addr;

	/* If legacy MMIO hole enabled */
	if (lgcy_mmio_hole_en) {
		if (amd_df_indirect_read(nid, 0, 0x104, umc, &tmp))
			goto out_err;

		dram_hole_base = tmp & GENMASK(31, 24);
		if (ret_addr >= dram_hole_base)
			ret_addr += (BIT_ULL(32) - dram_hole_base);
	}

	if (hash_enabled) {
		/* Save some parentheses and grab ls-bit at the end. */
		hashed_bit =	(ret_addr >> 12) ^
				(ret_addr >> 18) ^
				(ret_addr >> 21) ^
				(ret_addr >> 30) ^
				cs_id;

		hashed_bit &= BIT(0);

		if (hashed_bit != ((ret_addr >> intlv_addr_bit) & BIT(0)))
			ret_addr ^= BIT(intlv_addr_bit);
	}

	/* Is calculated system address is above DRAM limit address? */
	if (ret_addr > dram_limit_addr)
		goto out_err;

	*sys_addr = ret_addr;
	return 0;

out_err:
	return -EINVAL;
}
EXPORT_SYMBOL_GPL(umc_normaddr_to_sysaddr);

781 782 783 784 785 786
bool amd_mce_is_memory_error(struct mce *m)
{
	/* ErrCodeExt[20:16] */
	u8 xec = (m->status >> 16) & 0x1f;

	if (mce_flags.smca)
787
		return smca_get_bank_type(m->bank) == SMCA_UMC && xec == 0x0;
788 789 790 791

	return m->bank == 4 && xec == 0x8;
}

792
static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc)
793 794 795 796 797 798
{
	struct mce m;

	mce_setup(&m);

	m.status = status;
799
	m.misc   = misc;
800 801
	m.bank   = bank;
	m.tsc	 = rdtsc();
802

803
	if (m.status & MCI_STATUS_ADDRV) {
804
		m.addr = addr;
805

806 807 808 809 810 811 812 813 814 815 816
		/*
		 * Extract [55:<lsb>] where lsb is the least significant
		 * *valid* bit of the address bits.
		 */
		if (mce_flags.smca) {
			u8 lsb = (m.addr >> 56) & 0x3f;

			m.addr &= GENMASK_ULL(55, lsb);
		}
	}

817 818 819 820 821 822
	if (mce_flags.smca) {
		rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid);

		if (m.status & MCI_STATUS_SYNDV)
			rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd);
	}
823

824
	mce_log(&m);
825 826
}

827
asmlinkage __visible void __irq_entry smp_deferred_error_interrupt(void)
828 829 830
{
	entering_irq();
	trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR);
831 832
	inc_irq_stat(irq_deferred_error_count);
	deferred_error_int_vector();
833 834 835 836
	trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR);
	exiting_ack_irq();
}

837 838 839 840 841
/*
 * Returns true if the logged error is deferred. False, otherwise.
 */
static inline bool
_log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc)
842
{
843
	u64 status, addr = 0;
844

845 846 847
	rdmsrl(msr_stat, status);
	if (!(status & MCI_STATUS_VAL))
		return false;
848

849 850
	if (status & MCI_STATUS_ADDRV)
		rdmsrl(msr_addr, addr);
851

852
	__log_error(bank, status, addr, misc);
853

854
	wrmsrl(msr_stat, 0);
855 856

	return status & MCI_STATUS_DEFERRED;
857 858
}

859
/*
860 861 862 863 864 865 866
 * We have three scenarios for checking for Deferred errors:
 *
 * 1) Non-SMCA systems check MCA_STATUS and log error if found.
 * 2) SMCA systems check MCA_STATUS. If error is found then log it and also
 *    clear MCA_DESTAT.
 * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and
 *    log it.
867
 */
868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904
static void log_error_deferred(unsigned int bank)
{
	bool defrd;

	defrd = _log_error_bank(bank, msr_ops.status(bank),
					msr_ops.addr(bank), 0);

	if (!mce_flags.smca)
		return;

	/* Clear MCA_DESTAT if we logged the deferred error from MCA_STATUS. */
	if (defrd) {
		wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0);
		return;
	}

	/*
	 * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check
	 * for a valid error.
	 */
	_log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank),
			      MSR_AMD64_SMCA_MCx_DEADDR(bank), 0);
}

/* APIC interrupt handler for deferred errors */
static void amd_deferred_error_interrupt(void)
{
	unsigned int bank;

	for (bank = 0; bank < mca_cfg.banks; ++bank)
		log_error_deferred(bank);
}

static void log_error_thresholding(unsigned int bank, u64 misc)
{
	_log_error_bank(bank, msr_ops.status(bank), msr_ops.addr(bank), misc);
}
905

906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928
static void log_and_reset_block(struct threshold_block *block)
{
	struct thresh_restart tr;
	u32 low = 0, high = 0;

	if (!block)
		return;

	if (rdmsr_safe(block->address, &low, &high))
		return;

	if (!(high & MASK_OVERFLOW_HI))
		return;

	/* Log the MCE which caused the threshold event. */
	log_error_thresholding(block->bank, ((u64)high << 32) | low);

	/* Reset threshold block after logging error. */
	memset(&tr, 0, sizeof(tr));
	tr.b = block;
	threshold_restart_bank(&tr);
}

929
/*
930 931
 * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt
 * goes off when error_count reaches threshold_limit.
932
 */
933
static void amd_threshold_interrupt(void)
934
{
935 936
	struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL;
	unsigned int bank, cpu = smp_processor_id();
937

938
	for (bank = 0; bank < mca_cfg.banks; ++bank) {
939
		if (!(per_cpu(bank_map, cpu) & (1 << bank)))
940
			continue;
941

942 943 944
		first_block = per_cpu(threshold_banks, cpu)[bank]->blocks;
		if (!first_block)
			continue;
945

946 947 948 949 950 951 952
		/*
		 * The first block is also the head of the list. Check it first
		 * before iterating over the rest.
		 */
		log_and_reset_block(first_block);
		list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj)
			log_and_reset_block(block);
953
	}
954 955 956 957 958 959 960
}

/*
 * Sysfs Interface
 */

struct threshold_attr {
J
Jacob Shin 已提交
961
	struct attribute attr;
I
Ingo Molnar 已提交
962 963
	ssize_t (*show) (struct threshold_block *, char *);
	ssize_t (*store) (struct threshold_block *, const char *, size_t count);
964 965
};

I
Ingo Molnar 已提交
966 967 968
#define SHOW_FIELDS(name)						\
static ssize_t show_ ## name(struct threshold_block *b, char *buf)	\
{									\
969
	return sprintf(buf, "%lu\n", (unsigned long) b->name);		\
J
Jacob Shin 已提交
970
}
971 972 973
SHOW_FIELDS(interrupt_enable)
SHOW_FIELDS(threshold_limit)

I
Ingo Molnar 已提交
974
static ssize_t
H
Hidetoshi Seto 已提交
975
store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)
976
{
977
	struct thresh_restart tr;
I
Ingo Molnar 已提交
978 979
	unsigned long new;

980 981 982
	if (!b->interrupt_capable)
		return -EINVAL;

983
	if (kstrtoul(buf, 0, &new) < 0)
984
		return -EINVAL;
I
Ingo Molnar 已提交
985

986 987
	b->interrupt_enable = !!new;

988
	memset(&tr, 0, sizeof(tr));
I
Ingo Molnar 已提交
989 990
	tr.b		= b;

991
	smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
992

H
Hidetoshi Seto 已提交
993
	return size;
994 995
}

I
Ingo Molnar 已提交
996
static ssize_t
H
Hidetoshi Seto 已提交
997
store_threshold_limit(struct threshold_block *b, const char *buf, size_t size)
998
{
999
	struct thresh_restart tr;
I
Ingo Molnar 已提交
1000 1001
	unsigned long new;

1002
	if (kstrtoul(buf, 0, &new) < 0)
1003
		return -EINVAL;
I
Ingo Molnar 已提交
1004

1005 1006 1007 1008
	if (new > THRESHOLD_MAX)
		new = THRESHOLD_MAX;
	if (new < 1)
		new = 1;
I
Ingo Molnar 已提交
1009

1010
	memset(&tr, 0, sizeof(tr));
1011
	tr.old_limit = b->threshold_limit;
1012
	b->threshold_limit = new;
1013
	tr.b = b;
1014

1015
	smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
1016

H
Hidetoshi Seto 已提交
1017
	return size;
1018 1019
}

1020 1021
static ssize_t show_error_count(struct threshold_block *b, char *buf)
{
1022 1023 1024
	u32 lo, hi;

	rdmsr_on_cpu(b->cpu, b->address, &lo, &hi);
1025

1026 1027
	return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) -
				     (THRESHOLD_MAX - b->threshold_limit)));
1028 1029
}

1030 1031 1032 1033
static struct threshold_attr error_count = {
	.attr = {.name = __stringify(error_count), .mode = 0444 },
	.show = show_error_count,
};
1034

1035 1036 1037 1038 1039
#define RW_ATTR(val)							\
static struct threshold_attr val = {					\
	.attr	= {.name = __stringify(val), .mode = 0644 },		\
	.show	= show_## val,						\
	.store	= store_## val,						\
1040 1041
};

J
Jacob Shin 已提交
1042 1043
RW_ATTR(interrupt_enable);
RW_ATTR(threshold_limit);
1044 1045 1046 1047

static struct attribute *default_attrs[] = {
	&threshold_limit.attr,
	&error_count.attr,
1048 1049
	NULL,	/* possibly interrupt_enable if supported, see below */
	NULL,
1050 1051
};

I
Ingo Molnar 已提交
1052 1053
#define to_block(k)	container_of(k, struct threshold_block, kobj)
#define to_attr(a)	container_of(a, struct threshold_attr, attr)
1054 1055 1056

static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
{
1057
	struct threshold_block *b = to_block(kobj);
1058 1059
	struct threshold_attr *a = to_attr(attr);
	ssize_t ret;
I
Ingo Molnar 已提交
1060

1061
	ret = a->show ? a->show(b, buf) : -EIO;
I
Ingo Molnar 已提交
1062

1063 1064 1065 1066 1067 1068
	return ret;
}

static ssize_t store(struct kobject *kobj, struct attribute *attr,
		     const char *buf, size_t count)
{
1069
	struct threshold_block *b = to_block(kobj);
1070 1071
	struct threshold_attr *a = to_attr(attr);
	ssize_t ret;
I
Ingo Molnar 已提交
1072

1073
	ret = a->store ? a->store(b, buf, count) : -EIO;
I
Ingo Molnar 已提交
1074

1075 1076 1077
	return ret;
}

1078
static const struct sysfs_ops threshold_ops = {
I
Ingo Molnar 已提交
1079 1080
	.show			= show,
	.store			= store,
1081 1082 1083
};

static struct kobj_type threshold_ktype = {
I
Ingo Molnar 已提交
1084 1085
	.sysfs_ops		= &threshold_ops,
	.default_attrs		= default_attrs,
1086 1087
};

1088 1089
static const char *get_name(unsigned int bank, struct threshold_block *b)
{
1090
	enum smca_bank_types bank_type;
1091 1092 1093 1094 1095 1096 1097 1098

	if (!mce_flags.smca) {
		if (b && bank == 4)
			return bank4_names(b);

		return th_names[bank];
	}

1099 1100
	bank_type = smca_get_bank_type(bank);
	if (bank_type >= N_SMCA_BANK_TYPES)
1101 1102 1103 1104 1105 1106 1107 1108
		return NULL;

	if (b && bank_type == SMCA_UMC) {
		if (b->block < ARRAY_SIZE(smca_umc_block_names))
			return smca_umc_block_names[b->block];
		return NULL;
	}

1109 1110 1111
	if (smca_banks[bank].hwid->count == 1)
		return smca_get_name(bank_type);

1112
	snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN,
B
Borislav Petkov 已提交
1113
		 "%s_%x", smca_get_name(bank_type),
1114
			  smca_banks[bank].sysfs_id);
1115 1116 1117
	return buf_mcatype;
}

1118 1119
static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank,
				     unsigned int block, u32 address)
1120 1121
{
	struct threshold_block *b = NULL;
I
Ingo Molnar 已提交
1122 1123
	u32 low, high;
	int err;
1124

1125
	if ((bank >= mca_cfg.banks) || (block >= NR_BLOCKS))
1126 1127
		return 0;

1128
	if (rdmsr_safe_on_cpu(cpu, address, &low, &high))
1129
		return 0;
1130 1131 1132 1133 1134 1135 1136 1137

	if (!(high & MASK_VALID_HI)) {
		if (block)
			goto recurse;
		else
			return 0;
	}

1138 1139
	if (!(high & MASK_CNTP_HI)  ||
	     (high & MASK_LOCKED_HI))
1140 1141 1142 1143 1144 1145
		goto recurse;

	b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
	if (!b)
		return -ENOMEM;

I
Ingo Molnar 已提交
1146 1147 1148 1149 1150
	b->block		= block;
	b->bank			= bank;
	b->cpu			= cpu;
	b->address		= address;
	b->interrupt_enable	= 0;
1151
	b->interrupt_capable	= lvt_interrupt_supported(bank, high);
I
Ingo Molnar 已提交
1152
	b->threshold_limit	= THRESHOLD_MAX;
1153

1154
	if (b->interrupt_capable) {
1155
		threshold_ktype.default_attrs[2] = &interrupt_enable.attr;
1156 1157
		b->interrupt_enable = 1;
	} else {
1158
		threshold_ktype.default_attrs[2] = NULL;
1159
	}
1160

1161 1162
	INIT_LIST_HEAD(&b->miscj);

I
Ingo Molnar 已提交
1163
	if (per_cpu(threshold_banks, cpu)[bank]->blocks) {
1164 1165
		list_add(&b->miscj,
			 &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);
I
Ingo Molnar 已提交
1166
	} else {
1167
		per_cpu(threshold_banks, cpu)[bank]->blocks = b;
I
Ingo Molnar 已提交
1168
	}
1169

1170 1171
	err = kobject_init_and_add(&b->kobj, &threshold_ktype,
				   per_cpu(threshold_banks, cpu)[bank]->kobj,
1172
				   get_name(bank, b));
1173 1174 1175
	if (err)
		goto out_free;
recurse:
1176
	address = get_block_address(address, low, high, bank, ++block);
1177 1178
	if (!address)
		return 0;
1179

1180
	err = allocate_threshold_blocks(cpu, bank, block, address);
1181 1182 1183
	if (err)
		goto out_free;

1184 1185
	if (b)
		kobject_uevent(&b->kobj, KOBJ_ADD);
1186

1187 1188 1189 1190
	return err;

out_free:
	if (b) {
1191
		kobject_put(&b->kobj);
1192
		list_del(&b->miscj);
1193 1194 1195 1196 1197
		kfree(b);
	}
	return err;
}

1198
static int __threshold_add_blocks(struct threshold_bank *b)
1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221
{
	struct list_head *head = &b->blocks->miscj;
	struct threshold_block *pos = NULL;
	struct threshold_block *tmp = NULL;
	int err = 0;

	err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name);
	if (err)
		return err;

	list_for_each_entry_safe(pos, tmp, head, miscj) {

		err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name);
		if (err) {
			list_for_each_entry_safe_reverse(pos, tmp, head, miscj)
				kobject_del(&pos->kobj);

			return err;
		}
	}
	return err;
}

1222
static int threshold_create_bank(unsigned int cpu, unsigned int bank)
1223
{
1224
	struct device *dev = per_cpu(mce_device, cpu);
1225
	struct amd_northbridge *nb = NULL;
1226
	struct threshold_bank *b = NULL;
1227
	const char *name = get_name(bank, NULL);
1228
	int err = 0;
1229

1230 1231 1232
	if (!dev)
		return -ENODEV;

1233
	if (is_shared_bank(bank)) {
1234 1235 1236
		nb = node_to_amd_nb(amd_get_nb_id(cpu));

		/* threshold descriptor already initialized on this node? */
1237
		if (nb && nb->bank4) {
1238 1239 1240 1241 1242 1243 1244
			/* yes, use it */
			b = nb->bank4;
			err = kobject_add(b->kobj, &dev->kobj, name);
			if (err)
				goto out;

			per_cpu(threshold_banks, cpu)[bank] = b;
1245
			refcount_inc(&b->cpus);
1246 1247 1248 1249 1250 1251 1252

			err = __threshold_add_blocks(b);

			goto out;
		}
	}

1253
	b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
1254 1255 1256 1257 1258
	if (!b) {
		err = -ENOMEM;
		goto out;
	}

1259
	b->kobj = kobject_create_and_add(name, &dev->kobj);
1260 1261
	if (!b->kobj) {
		err = -EINVAL;
1262
		goto out_free;
1263
	}
1264

1265
	per_cpu(threshold_banks, cpu)[bank] = b;
1266

1267
	if (is_shared_bank(bank)) {
1268
		refcount_set(&b->cpus, 1);
1269 1270

		/* nb is already initialized, see above */
1271 1272 1273 1274
		if (nb) {
			WARN_ON(nb->bank4);
			nb->bank4 = b;
		}
1275 1276
	}

1277
	err = allocate_threshold_blocks(cpu, bank, 0, msr_ops.misc(bank));
1278 1279
	if (!err)
		goto out;
1280

1281
 out_free:
1282
	kfree(b);
1283 1284

 out:
1285 1286 1287
	return err;
}

1288
static void deallocate_threshold_block(unsigned int cpu,
1289 1290 1291 1292 1293 1294 1295 1296 1297 1298
						 unsigned int bank)
{
	struct threshold_block *pos = NULL;
	struct threshold_block *tmp = NULL;
	struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];

	if (!head)
		return;

	list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
1299
		kobject_put(&pos->kobj);
1300 1301 1302 1303 1304 1305 1306 1307
		list_del(&pos->miscj);
		kfree(pos);
	}

	kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
	per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
}

1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318
static void __threshold_remove_blocks(struct threshold_bank *b)
{
	struct threshold_block *pos = NULL;
	struct threshold_block *tmp = NULL;

	kobject_del(b->kobj);

	list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj)
		kobject_del(&pos->kobj);
}

1319
static void threshold_remove_bank(unsigned int cpu, int bank)
1320
{
1321
	struct amd_northbridge *nb;
1322 1323 1324 1325 1326
	struct threshold_bank *b;

	b = per_cpu(threshold_banks, cpu)[bank];
	if (!b)
		return;
1327

1328 1329 1330
	if (!b->blocks)
		goto free_out;

1331
	if (is_shared_bank(bank)) {
1332
		if (!refcount_dec_and_test(&b->cpus)) {
1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345
			__threshold_remove_blocks(b);
			per_cpu(threshold_banks, cpu)[bank] = NULL;
			return;
		} else {
			/*
			 * the last CPU on this node using the shared bank is
			 * going away, remove that bank now.
			 */
			nb = node_to_amd_nb(amd_get_nb_id(cpu));
			nb->bank4 = NULL;
		}
	}

1346 1347 1348
	deallocate_threshold_block(cpu, bank);

free_out:
1349
	kobject_del(b->kobj);
1350
	kobject_put(b->kobj);
1351 1352
	kfree(b);
	per_cpu(threshold_banks, cpu)[bank] = NULL;
1353 1354
}

1355
int mce_threshold_remove_device(unsigned int cpu)
1356
{
J
Jacob Shin 已提交
1357
	unsigned int bank;
1358

1359
	for (bank = 0; bank < mca_cfg.banks; ++bank) {
1360
		if (!(per_cpu(bank_map, cpu) & (1 << bank)))
1361 1362 1363
			continue;
		threshold_remove_bank(cpu, bank);
	}
1364
	kfree(per_cpu(threshold_banks, cpu));
1365
	per_cpu(threshold_banks, cpu) = NULL;
1366
	return 0;
1367 1368
}

1369
/* create dir/files for all valid threshold banks */
1370
int mce_threshold_create_device(unsigned int cpu)
1371
{
1372 1373 1374 1375
	unsigned int bank;
	struct threshold_bank **bp;
	int err = 0;

1376 1377 1378 1379
	bp = per_cpu(threshold_banks, cpu);
	if (bp)
		return 0;

K
Kees Cook 已提交
1380
	bp = kcalloc(mca_cfg.banks, sizeof(struct threshold_bank *),
1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391
		     GFP_KERNEL);
	if (!bp)
		return -ENOMEM;

	per_cpu(threshold_banks, cpu) = bp;

	for (bank = 0; bank < mca_cfg.banks; ++bank) {
		if (!(per_cpu(bank_map, cpu) & (1 << bank)))
			continue;
		err = threshold_create_bank(cpu, bank);
		if (err)
1392
			goto err;
1393
	}
1394 1395
	return err;
err:
1396
	mce_threshold_remove_device(cpu);
1397
	return err;
1398 1399 1400 1401
}

static __init int threshold_init_device(void)
{
J
Jacob Shin 已提交
1402
	unsigned lcpu = 0;
1403 1404 1405

	/* to hit CPUs online before the notifier is up */
	for_each_online_cpu(lcpu) {
1406
		int err = mce_threshold_create_device(lcpu);
I
Ingo Molnar 已提交
1407

1408
		if (err)
1409
			return err;
1410
	}
I
Ingo Molnar 已提交
1411

1412 1413 1414
	if (thresholding_irq_en)
		mce_threshold_vector = amd_threshold_interrupt;

1415
	return 0;
1416
}
1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437
/*
 * there are 3 funcs which need to be _initcalled in a logic sequence:
 * 1. xen_late_init_mcelog
 * 2. mcheck_init_device
 * 3. threshold_init_device
 *
 * xen_late_init_mcelog must register xen_mce_chrdev_device before
 * native mce_chrdev_device registration if running under xen platform;
 *
 * mcheck_init_device should be inited before threshold_init_device to
 * initialize mce_device, otherwise a NULL ptr dereference will cause panic.
 *
 * so we use following _initcalls
 * 1. device_initcall(xen_late_init_mcelog);
 * 2. device_initcall_sync(mcheck_init_device);
 * 3. late_initcall(threshold_init_device);
 *
 * when running under xen, the initcall order is 1,2,3;
 * on baremetal, we skip 1 and we do only 2 and 3.
 */
late_initcall(threshold_init_device);