gpio.c 57.3 KB
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/*
 *  linux/arch/arm/plat-omap/gpio.c
 *
 * Support functions for OMAP GPIO
 *
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 * Copyright (C) 2003-2005 Nokia Corporation
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 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
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 *
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 * Copyright (C) 2009 Texas Instruments
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
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 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
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#include <linux/sysdev.h>
#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <mach/irqs.h>
#include <mach/gpio.h>
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#include <asm/mach/irq.h>

/*
 * OMAP1510 GPIO registers
 */
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#define OMAP1510_GPIO_BASE		IO_ADDRESS(0xfffce000)
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#define OMAP1510_GPIO_DATA_INPUT	0x00
#define OMAP1510_GPIO_DATA_OUTPUT	0x04
#define OMAP1510_GPIO_DIR_CONTROL	0x08
#define OMAP1510_GPIO_INT_CONTROL	0x0c
#define OMAP1510_GPIO_INT_MASK		0x10
#define OMAP1510_GPIO_INT_STATUS	0x14
#define OMAP1510_GPIO_PIN_CONTROL	0x18

#define OMAP1510_IH_GPIO_BASE		64

/*
 * OMAP1610 specific GPIO registers
 */
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#define OMAP1610_GPIO1_BASE		IO_ADDRESS(0xfffbe400)
#define OMAP1610_GPIO2_BASE		IO_ADDRESS(0xfffbec00)
#define OMAP1610_GPIO3_BASE		IO_ADDRESS(0xfffbb400)
#define OMAP1610_GPIO4_BASE		IO_ADDRESS(0xfffbbc00)
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#define OMAP1610_GPIO_REVISION		0x0000
#define OMAP1610_GPIO_SYSCONFIG		0x0010
#define OMAP1610_GPIO_SYSSTATUS		0x0014
#define OMAP1610_GPIO_IRQSTATUS1	0x0018
#define OMAP1610_GPIO_IRQENABLE1	0x001c
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#define OMAP1610_GPIO_WAKEUPENABLE	0x0028
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#define OMAP1610_GPIO_DATAIN		0x002c
#define OMAP1610_GPIO_DATAOUT		0x0030
#define OMAP1610_GPIO_DIRECTION		0x0034
#define OMAP1610_GPIO_EDGE_CTRL1	0x0038
#define OMAP1610_GPIO_EDGE_CTRL2	0x003c
#define OMAP1610_GPIO_CLEAR_IRQENABLE1	0x009c
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#define OMAP1610_GPIO_CLEAR_WAKEUPENA	0x00a8
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#define OMAP1610_GPIO_CLEAR_DATAOUT	0x00b0
#define OMAP1610_GPIO_SET_IRQENABLE1	0x00dc
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#define OMAP1610_GPIO_SET_WAKEUPENA	0x00e8
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#define OMAP1610_GPIO_SET_DATAOUT	0x00f0

/*
 * OMAP730 specific GPIO registers
 */
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#define OMAP730_GPIO1_BASE		IO_ADDRESS(0xfffbc000)
#define OMAP730_GPIO2_BASE		IO_ADDRESS(0xfffbc800)
#define OMAP730_GPIO3_BASE		IO_ADDRESS(0xfffbd000)
#define OMAP730_GPIO4_BASE		IO_ADDRESS(0xfffbd800)
#define OMAP730_GPIO5_BASE		IO_ADDRESS(0xfffbe000)
#define OMAP730_GPIO6_BASE		IO_ADDRESS(0xfffbe800)
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#define OMAP730_GPIO_DATA_INPUT		0x00
#define OMAP730_GPIO_DATA_OUTPUT	0x04
#define OMAP730_GPIO_DIR_CONTROL	0x08
#define OMAP730_GPIO_INT_CONTROL	0x0c
#define OMAP730_GPIO_INT_MASK		0x10
#define OMAP730_GPIO_INT_STATUS		0x14

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/*
 * OMAP850 specific GPIO registers
 */
#define OMAP850_GPIO1_BASE		IO_ADDRESS(0xfffbc000)
#define OMAP850_GPIO2_BASE		IO_ADDRESS(0xfffbc800)
#define OMAP850_GPIO3_BASE		IO_ADDRESS(0xfffbd000)
#define OMAP850_GPIO4_BASE		IO_ADDRESS(0xfffbd800)
#define OMAP850_GPIO5_BASE		IO_ADDRESS(0xfffbe000)
#define OMAP850_GPIO6_BASE		IO_ADDRESS(0xfffbe800)
#define OMAP850_GPIO_DATA_INPUT		0x00
#define OMAP850_GPIO_DATA_OUTPUT	0x04
#define OMAP850_GPIO_DIR_CONTROL	0x08
#define OMAP850_GPIO_INT_CONTROL	0x0c
#define OMAP850_GPIO_INT_MASK		0x10
#define OMAP850_GPIO_INT_STATUS		0x14

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/*
 * omap24xx specific GPIO registers
 */
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#define OMAP242X_GPIO1_BASE		IO_ADDRESS(0x48018000)
#define OMAP242X_GPIO2_BASE		IO_ADDRESS(0x4801a000)
#define OMAP242X_GPIO3_BASE		IO_ADDRESS(0x4801c000)
#define OMAP242X_GPIO4_BASE		IO_ADDRESS(0x4801e000)
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#define OMAP243X_GPIO1_BASE		IO_ADDRESS(0x4900C000)
#define OMAP243X_GPIO2_BASE		IO_ADDRESS(0x4900E000)
#define OMAP243X_GPIO3_BASE		IO_ADDRESS(0x49010000)
#define OMAP243X_GPIO4_BASE		IO_ADDRESS(0x49012000)
#define OMAP243X_GPIO5_BASE		IO_ADDRESS(0x480B6000)
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#define OMAP24XX_GPIO_REVISION		0x0000
#define OMAP24XX_GPIO_SYSCONFIG		0x0010
#define OMAP24XX_GPIO_SYSSTATUS		0x0014
#define OMAP24XX_GPIO_IRQSTATUS1	0x0018
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#define OMAP24XX_GPIO_IRQSTATUS2	0x0028
#define OMAP24XX_GPIO_IRQENABLE2	0x002c
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#define OMAP24XX_GPIO_IRQENABLE1	0x001c
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#define OMAP24XX_GPIO_WAKE_EN		0x0020
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#define OMAP24XX_GPIO_CTRL		0x0030
#define OMAP24XX_GPIO_OE		0x0034
#define OMAP24XX_GPIO_DATAIN		0x0038
#define OMAP24XX_GPIO_DATAOUT		0x003c
#define OMAP24XX_GPIO_LEVELDETECT0	0x0040
#define OMAP24XX_GPIO_LEVELDETECT1	0x0044
#define OMAP24XX_GPIO_RISINGDETECT	0x0048
#define OMAP24XX_GPIO_FALLINGDETECT	0x004c
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#define OMAP24XX_GPIO_DEBOUNCE_EN	0x0050
#define OMAP24XX_GPIO_DEBOUNCE_VAL	0x0054
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#define OMAP24XX_GPIO_CLEARIRQENABLE1	0x0060
#define OMAP24XX_GPIO_SETIRQENABLE1	0x0064
#define OMAP24XX_GPIO_CLEARWKUENA	0x0080
#define OMAP24XX_GPIO_SETWKUENA		0x0084
#define OMAP24XX_GPIO_CLEARDATAOUT	0x0090
#define OMAP24XX_GPIO_SETDATAOUT	0x0094

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#define OMAP4_GPIO_REVISION		0x0000
#define OMAP4_GPIO_SYSCONFIG		0x0010
#define OMAP4_GPIO_EOI			0x0020
#define OMAP4_GPIO_IRQSTATUSRAW0	0x0024
#define OMAP4_GPIO_IRQSTATUSRAW1	0x0028
#define OMAP4_GPIO_IRQSTATUS0		0x002c
#define OMAP4_GPIO_IRQSTATUS1		0x0030
#define OMAP4_GPIO_IRQSTATUSSET0	0x0034
#define OMAP4_GPIO_IRQSTATUSSET1	0x0038
#define OMAP4_GPIO_IRQSTATUSCLR0	0x003c
#define OMAP4_GPIO_IRQSTATUSCLR1	0x0040
#define OMAP4_GPIO_IRQWAKEN0		0x0044
#define OMAP4_GPIO_IRQWAKEN1		0x0048
#define OMAP4_GPIO_SYSSTATUS		0x0104
#define OMAP4_GPIO_CTRL			0x0130
#define OMAP4_GPIO_OE			0x0134
#define OMAP4_GPIO_DATAIN		0x0138
#define OMAP4_GPIO_DATAOUT		0x013c
#define OMAP4_GPIO_LEVELDETECT0		0x0140
#define OMAP4_GPIO_LEVELDETECT1		0x0144
#define OMAP4_GPIO_RISINGDETECT		0x0148
#define OMAP4_GPIO_FALLINGDETECT	0x014c
#define OMAP4_GPIO_DEBOUNCENABLE	0x0150
#define OMAP4_GPIO_DEBOUNCINGTIME	0x0154
#define OMAP4_GPIO_CLEARDATAOUT		0x0190
#define OMAP4_GPIO_SETDATAOUT		0x0194
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/*
 * omap34xx specific GPIO registers
 */

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#define OMAP34XX_GPIO1_BASE		IO_ADDRESS(0x48310000)
#define OMAP34XX_GPIO2_BASE		IO_ADDRESS(0x49050000)
#define OMAP34XX_GPIO3_BASE		IO_ADDRESS(0x49052000)
#define OMAP34XX_GPIO4_BASE		IO_ADDRESS(0x49054000)
#define OMAP34XX_GPIO5_BASE		IO_ADDRESS(0x49056000)
#define OMAP34XX_GPIO6_BASE		IO_ADDRESS(0x49058000)
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/*
 * OMAP44XX  specific GPIO registers
 */
#define OMAP44XX_GPIO1_BASE             IO_ADDRESS(0x4a310000)
#define OMAP44XX_GPIO2_BASE             IO_ADDRESS(0x48055000)
#define OMAP44XX_GPIO3_BASE             IO_ADDRESS(0x48057000)
#define OMAP44XX_GPIO4_BASE             IO_ADDRESS(0x48059000)
#define OMAP44XX_GPIO5_BASE             IO_ADDRESS(0x4805B000)
#define OMAP44XX_GPIO6_BASE             IO_ADDRESS(0x4805D000)

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#define OMAP_MPUIO_VBASE		IO_ADDRESS(OMAP_MPUIO_BASE)
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struct gpio_bank {
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	void __iomem *base;
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	u16 irq;
	u16 virtual_irq_start;
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	int method;
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#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) ||  \
		defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
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	u32 suspend_wakeup;
	u32 saved_wakeup;
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#endif
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#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
			defined(CONFIG_ARCH_OMAP4)
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	u32 non_wakeup_gpios;
	u32 enabled_non_wakeup_gpios;

	u32 saved_datain;
	u32 saved_fallingdetect;
	u32 saved_risingdetect;
#endif
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	u32 level_mask;
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	spinlock_t lock;
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	struct gpio_chip chip;
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	struct clk *dbck;
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};

#define METHOD_MPUIO		0
#define METHOD_GPIO_1510	1
#define METHOD_GPIO_1610	2
#define METHOD_GPIO_730		3
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#define METHOD_GPIO_850		4
#define METHOD_GPIO_24XX	5
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#ifdef CONFIG_ARCH_OMAP16XX
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static struct gpio_bank gpio_bank_1610[5] = {
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	{ OMAP_MPUIO_VBASE,    INT_MPUIO,	    IH_MPUIO_BASE,     METHOD_MPUIO},
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	{ OMAP1610_GPIO1_BASE, INT_GPIO_BANK1,	    IH_GPIO_BASE,      METHOD_GPIO_1610 },
	{ OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
	{ OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
	{ OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
};
#endif

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#ifdef CONFIG_ARCH_OMAP15XX
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static struct gpio_bank gpio_bank_1510[2] = {
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	{ OMAP_MPUIO_VBASE,   INT_MPUIO,      IH_MPUIO_BASE, METHOD_MPUIO },
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	{ OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE,  METHOD_GPIO_1510 }
};
#endif

#ifdef CONFIG_ARCH_OMAP730
static struct gpio_bank gpio_bank_730[7] = {
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	{ OMAP_MPUIO_VBASE,    INT_730_MPUIO,	    IH_MPUIO_BASE,	METHOD_MPUIO },
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	{ OMAP730_GPIO1_BASE,  INT_730_GPIO_BANK1,  IH_GPIO_BASE,	METHOD_GPIO_730 },
	{ OMAP730_GPIO2_BASE,  INT_730_GPIO_BANK2,  IH_GPIO_BASE + 32,	METHOD_GPIO_730 },
	{ OMAP730_GPIO3_BASE,  INT_730_GPIO_BANK3,  IH_GPIO_BASE + 64,	METHOD_GPIO_730 },
	{ OMAP730_GPIO4_BASE,  INT_730_GPIO_BANK4,  IH_GPIO_BASE + 96,	METHOD_GPIO_730 },
	{ OMAP730_GPIO5_BASE,  INT_730_GPIO_BANK5,  IH_GPIO_BASE + 128, METHOD_GPIO_730 },
	{ OMAP730_GPIO6_BASE,  INT_730_GPIO_BANK6,  IH_GPIO_BASE + 160, METHOD_GPIO_730 },
};
#endif

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#ifdef CONFIG_ARCH_OMAP850
static struct gpio_bank gpio_bank_850[7] = {
	{ OMAP_MPUIO_BASE,     INT_850_MPUIO,	    IH_MPUIO_BASE,	METHOD_MPUIO },
	{ OMAP850_GPIO1_BASE,  INT_850_GPIO_BANK1,  IH_GPIO_BASE,	METHOD_GPIO_850 },
	{ OMAP850_GPIO2_BASE,  INT_850_GPIO_BANK2,  IH_GPIO_BASE + 32,	METHOD_GPIO_850 },
	{ OMAP850_GPIO3_BASE,  INT_850_GPIO_BANK3,  IH_GPIO_BASE + 64,	METHOD_GPIO_850 },
	{ OMAP850_GPIO4_BASE,  INT_850_GPIO_BANK4,  IH_GPIO_BASE + 96,	METHOD_GPIO_850 },
	{ OMAP850_GPIO5_BASE,  INT_850_GPIO_BANK5,  IH_GPIO_BASE + 128, METHOD_GPIO_850 },
	{ OMAP850_GPIO6_BASE,  INT_850_GPIO_BANK6,  IH_GPIO_BASE + 160, METHOD_GPIO_850 },
};
#endif


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#ifdef CONFIG_ARCH_OMAP24XX
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static struct gpio_bank gpio_bank_242x[4] = {
	{ OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,	METHOD_GPIO_24XX },
	{ OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,	METHOD_GPIO_24XX },
	{ OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,	METHOD_GPIO_24XX },
	{ OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,	METHOD_GPIO_24XX },
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};
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static struct gpio_bank gpio_bank_243x[5] = {
	{ OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,	METHOD_GPIO_24XX },
	{ OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,	METHOD_GPIO_24XX },
	{ OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,	METHOD_GPIO_24XX },
	{ OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,	METHOD_GPIO_24XX },
	{ OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
};

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#endif

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#ifdef CONFIG_ARCH_OMAP34XX
static struct gpio_bank gpio_bank_34xx[6] = {
	{ OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,	METHOD_GPIO_24XX },
	{ OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,	METHOD_GPIO_24XX },
	{ OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,	METHOD_GPIO_24XX },
	{ OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,	METHOD_GPIO_24XX },
	{ OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
	{ OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
};

#endif

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#ifdef CONFIG_ARCH_OMAP4
static struct gpio_bank gpio_bank_44xx[6] = {
	{ OMAP44XX_GPIO1_BASE, INT_44XX_GPIO_BANK1, IH_GPIO_BASE,	\
		METHOD_GPIO_24XX },
	{ OMAP44XX_GPIO2_BASE, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32,	\
		METHOD_GPIO_24XX },
	{ OMAP44XX_GPIO3_BASE, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64,	\
		METHOD_GPIO_24XX },
	{ OMAP44XX_GPIO4_BASE, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96,	\
		METHOD_GPIO_24XX },
	{ OMAP44XX_GPIO5_BASE, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128, \
		METHOD_GPIO_24XX },
	{ OMAP44XX_GPIO6_BASE, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160, \
		METHOD_GPIO_24XX },
};

#endif

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static struct gpio_bank *gpio_bank;
static int gpio_bank_count;

static inline struct gpio_bank *get_gpio_bank(int gpio)
{
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	if (cpu_is_omap15xx()) {
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		if (OMAP_GPIO_IS_MPUIO(gpio))
			return &gpio_bank[0];
		return &gpio_bank[1];
	}
	if (cpu_is_omap16xx()) {
		if (OMAP_GPIO_IS_MPUIO(gpio))
			return &gpio_bank[0];
		return &gpio_bank[1 + (gpio >> 4)];
	}
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	if (cpu_is_omap7xx()) {
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		if (OMAP_GPIO_IS_MPUIO(gpio))
			return &gpio_bank[0];
		return &gpio_bank[1 + (gpio >> 5)];
	}
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	if (cpu_is_omap24xx())
		return &gpio_bank[gpio >> 5];
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	if (cpu_is_omap34xx() || cpu_is_omap44xx())
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		return &gpio_bank[gpio >> 5];
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	BUG();
	return NULL;
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}

static inline int get_gpio_index(int gpio)
{
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	if (cpu_is_omap7xx())
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		return gpio & 0x1f;
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	if (cpu_is_omap24xx())
		return gpio & 0x1f;
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	if (cpu_is_omap34xx() || cpu_is_omap44xx())
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		return gpio & 0x1f;
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	return gpio & 0x0f;
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}

static inline int gpio_valid(int gpio)
{
	if (gpio < 0)
		return -1;
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	if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
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		if (gpio >= OMAP_MAX_GPIO_LINES + 16)
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			return -1;
		return 0;
	}
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	if (cpu_is_omap15xx() && gpio < 16)
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		return 0;
	if ((cpu_is_omap16xx()) && gpio < 64)
		return 0;
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	if (cpu_is_omap7xx() && gpio < 192)
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		return 0;
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	if (cpu_is_omap24xx() && gpio < 128)
		return 0;
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	if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
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		return 0;
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	return -1;
}

static int check_gpio(int gpio)
{
	if (unlikely(gpio_valid(gpio)) < 0) {
		printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
		dump_stack();
		return -1;
	}
	return 0;
}

static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
{
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	void __iomem *reg = bank->base;
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	u32 l;

	switch (bank->method) {
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#ifdef CONFIG_ARCH_OMAP1
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	case METHOD_MPUIO:
		reg += OMAP_MPUIO_IO_CNTL;
		break;
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#endif
#ifdef CONFIG_ARCH_OMAP15XX
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	case METHOD_GPIO_1510:
		reg += OMAP1510_GPIO_DIR_CONTROL;
		break;
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#endif
#ifdef CONFIG_ARCH_OMAP16XX
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	case METHOD_GPIO_1610:
		reg += OMAP1610_GPIO_DIRECTION;
		break;
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#endif
#ifdef CONFIG_ARCH_OMAP730
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	case METHOD_GPIO_730:
		reg += OMAP730_GPIO_DIR_CONTROL;
		break;
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#endif
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#ifdef CONFIG_ARCH_OMAP850
	case METHOD_GPIO_850:
		reg += OMAP850_GPIO_DIR_CONTROL;
		break;
#endif
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#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
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	case METHOD_GPIO_24XX:
		reg += OMAP24XX_GPIO_OE;
		break;
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#endif
#if defined(CONFIG_ARCH_OMAP4)
	case METHOD_GPIO_24XX:
		reg += OMAP4_GPIO_OE;
		break;
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#endif
	default:
		WARN_ON(1);
		return;
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	}
	l = __raw_readl(reg);
	if (is_input)
		l |= 1 << gpio;
	else
		l &= ~(1 << gpio);
	__raw_writel(l, reg);
}

static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
{
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	void __iomem *reg = bank->base;
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	u32 l = 0;

	switch (bank->method) {
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#ifdef CONFIG_ARCH_OMAP1
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	case METHOD_MPUIO:
		reg += OMAP_MPUIO_OUTPUT;
		l = __raw_readl(reg);
		if (enable)
			l |= 1 << gpio;
		else
			l &= ~(1 << gpio);
		break;
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#endif
#ifdef CONFIG_ARCH_OMAP15XX
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	case METHOD_GPIO_1510:
		reg += OMAP1510_GPIO_DATA_OUTPUT;
		l = __raw_readl(reg);
		if (enable)
			l |= 1 << gpio;
		else
			l &= ~(1 << gpio);
		break;
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#endif
#ifdef CONFIG_ARCH_OMAP16XX
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	case METHOD_GPIO_1610:
		if (enable)
			reg += OMAP1610_GPIO_SET_DATAOUT;
		else
			reg += OMAP1610_GPIO_CLEAR_DATAOUT;
		l = 1 << gpio;
		break;
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#endif
#ifdef CONFIG_ARCH_OMAP730
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	case METHOD_GPIO_730:
		reg += OMAP730_GPIO_DATA_OUTPUT;
		l = __raw_readl(reg);
		if (enable)
			l |= 1 << gpio;
		else
			l &= ~(1 << gpio);
		break;
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#endif
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#ifdef CONFIG_ARCH_OMAP850
	case METHOD_GPIO_850:
		reg += OMAP850_GPIO_DATA_OUTPUT;
		l = __raw_readl(reg);
		if (enable)
			l |= 1 << gpio;
		else
			l &= ~(1 << gpio);
		break;
#endif
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#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
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	case METHOD_GPIO_24XX:
		if (enable)
			reg += OMAP24XX_GPIO_SETDATAOUT;
		else
			reg += OMAP24XX_GPIO_CLEARDATAOUT;
		l = 1 << gpio;
		break;
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#endif
#ifdef CONFIG_ARCH_OMAP4
	case METHOD_GPIO_24XX:
		if (enable)
			reg += OMAP4_GPIO_SETDATAOUT;
		else
			reg += OMAP4_GPIO_CLEARDATAOUT;
		l = 1 << gpio;
		break;
509
#endif
510
	default:
511
		WARN_ON(1);
512 513 514 515 516
		return;
	}
	__raw_writel(l, reg);
}

517
static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
518
{
519
	void __iomem *reg;
520 521

	if (check_gpio(gpio) < 0)
522
		return -EINVAL;
523 524
	reg = bank->base;
	switch (bank->method) {
525
#ifdef CONFIG_ARCH_OMAP1
526 527 528
	case METHOD_MPUIO:
		reg += OMAP_MPUIO_INPUT_LATCH;
		break;
529 530
#endif
#ifdef CONFIG_ARCH_OMAP15XX
531 532 533
	case METHOD_GPIO_1510:
		reg += OMAP1510_GPIO_DATA_INPUT;
		break;
534 535
#endif
#ifdef CONFIG_ARCH_OMAP16XX
536 537 538
	case METHOD_GPIO_1610:
		reg += OMAP1610_GPIO_DATAIN;
		break;
539 540
#endif
#ifdef CONFIG_ARCH_OMAP730
541 542 543
	case METHOD_GPIO_730:
		reg += OMAP730_GPIO_DATA_INPUT;
		break;
544
#endif
545 546 547 548 549
#ifdef CONFIG_ARCH_OMAP850
	case METHOD_GPIO_850:
		reg += OMAP850_GPIO_DATA_INPUT;
		break;
#endif
550
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
551 552 553
	case METHOD_GPIO_24XX:
		reg += OMAP24XX_GPIO_DATAIN;
		break;
554 555 556 557 558
#endif
#ifdef CONFIG_ARCH_OMAP4
	case METHOD_GPIO_24XX:
		reg += OMAP4_GPIO_DATAIN;
		break;
559
#endif
560
	default:
561
		return -EINVAL;
562
	}
563 564
	return (__raw_readl(reg)
			& (1 << get_gpio_index(gpio))) != 0;
565 566
}

567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613
static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
{
	void __iomem *reg;

	if (check_gpio(gpio) < 0)
		return -EINVAL;
	reg = bank->base;

	switch (bank->method) {
#ifdef CONFIG_ARCH_OMAP1
	case METHOD_MPUIO:
		reg += OMAP_MPUIO_OUTPUT;
		break;
#endif
#ifdef CONFIG_ARCH_OMAP15XX
	case METHOD_GPIO_1510:
		reg += OMAP1510_GPIO_DATA_OUTPUT;
		break;
#endif
#ifdef CONFIG_ARCH_OMAP16XX
	case METHOD_GPIO_1610:
		reg += OMAP1610_GPIO_DATAOUT;
		break;
#endif
#ifdef CONFIG_ARCH_OMAP730
	case METHOD_GPIO_730:
		reg += OMAP730_GPIO_DATA_OUTPUT;
		break;
#endif
#ifdef CONFIG_ARCH_OMAP850
	case METHOD_GPIO_850:
		reg += OMAP850_GPIO_DATA_OUTPUT;
		break;
#endif
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
		defined(CONFIG_ARCH_OMAP4)
	case METHOD_GPIO_24XX:
		reg += OMAP24XX_GPIO_DATAOUT;
		break;
#endif
	default:
		return -EINVAL;
	}

	return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
}

614 615 616 617 618 619 620 621
#define MOD_REG_BIT(reg, bit_mask, set)	\
do {	\
	int l = __raw_readl(base + reg); \
	if (set) l |= bit_mask; \
	else l &= ~bit_mask; \
	__raw_writel(l, base + reg); \
} while(0)

622 623 624 625
void omap_set_gpio_debounce(int gpio, int enable)
{
	struct gpio_bank *bank;
	void __iomem *reg;
D
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626
	unsigned long flags;
627 628 629 630 631 632 633
	u32 val, l = 1 << get_gpio_index(gpio);

	if (cpu_class_is_omap1())
		return;

	bank = get_gpio_bank(gpio);
	reg = bank->base;
634 635 636
#ifdef CONFIG_ARCH_OMAP4
	reg += OMAP4_GPIO_DEBOUNCENABLE;
#else
637
	reg += OMAP24XX_GPIO_DEBOUNCE_EN;
638
#endif
D
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639 640

	spin_lock_irqsave(&bank->lock, flags);
641 642
	val = __raw_readl(reg);

643
	if (enable && !(val & l))
644
		val |= l;
D
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645
	else if (!enable && (val & l))
646
		val &= ~l;
647
	else
D
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648
		goto done;
649

650
	if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
D
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651 652 653 654 655
		if (enable)
			clk_enable(bank->dbck);
		else
			clk_disable(bank->dbck);
	}
656 657

	__raw_writel(val, reg);
D
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658 659
done:
	spin_unlock_irqrestore(&bank->lock, flags);
660 661 662 663 664 665 666 667 668 669 670 671 672 673 674
}
EXPORT_SYMBOL(omap_set_gpio_debounce);

void omap_set_gpio_debounce_time(int gpio, int enc_time)
{
	struct gpio_bank *bank;
	void __iomem *reg;

	if (cpu_class_is_omap1())
		return;

	bank = get_gpio_bank(gpio);
	reg = bank->base;

	enc_time &= 0xff;
675 676 677
#ifdef CONFIG_ARCH_OMAP4
	reg += OMAP4_GPIO_DEBOUNCINGTIME;
#else
678
	reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
679
#endif
680 681 682 683
	__raw_writel(enc_time, reg);
}
EXPORT_SYMBOL(omap_set_gpio_debounce_time);

684 685
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
				defined(CONFIG_ARCH_OMAP4)
686 687
static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
						int trigger)
688
{
689
	void __iomem *base = bank->base;
690
	u32 gpio_bit = 1 << gpio;
691
	u32 val;
692

693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711
	if (cpu_is_omap44xx()) {
		MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
			trigger & IRQ_TYPE_LEVEL_LOW);
		MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
			trigger & IRQ_TYPE_LEVEL_HIGH);
		MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
			trigger & IRQ_TYPE_EDGE_RISING);
		MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
			trigger & IRQ_TYPE_EDGE_FALLING);
	} else {
		MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
			trigger & IRQ_TYPE_LEVEL_LOW);
		MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
			trigger & IRQ_TYPE_LEVEL_HIGH);
		MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
			trigger & IRQ_TYPE_EDGE_RISING);
		MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
			trigger & IRQ_TYPE_EDGE_FALLING);
	}
712
	if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
713 714 715 716 717 718 719 720 721 722 723 724 725
		if (cpu_is_omap44xx()) {
			if (trigger != 0)
				__raw_writel(1 << gpio, bank->base+
						OMAP4_GPIO_IRQWAKEN0);
			else {
				val = __raw_readl(bank->base +
							OMAP4_GPIO_IRQWAKEN0);
				__raw_writel(val & (~(1 << gpio)), bank->base +
							 OMAP4_GPIO_IRQWAKEN0);
			}
		} else {
			if (trigger != 0)
				__raw_writel(1 << gpio, bank->base
726
					+ OMAP24XX_GPIO_SETWKUENA);
727 728
			else
				__raw_writel(1 << gpio, bank->base
729
					+ OMAP24XX_GPIO_CLEARWKUENA);
730
		}
731 732 733 734 735 736
	} else {
		if (trigger != 0)
			bank->enabled_non_wakeup_gpios |= gpio_bit;
		else
			bank->enabled_non_wakeup_gpios &= ~gpio_bit;
	}
737

738 739 740 741 742 743 744 745 746
	if (cpu_is_omap44xx()) {
		bank->level_mask =
			__raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
			__raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
	} else {
		bank->level_mask =
			__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
			__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
	}
747
}
748
#endif
749 750 751 752 753

static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
{
	void __iomem *reg = bank->base;
	u32 l = 0;
754 755

	switch (bank->method) {
756
#ifdef CONFIG_ARCH_OMAP1
757 758 759
	case METHOD_MPUIO:
		reg += OMAP_MPUIO_GPIO_INT_EDGE;
		l = __raw_readl(reg);
760
		if (trigger & IRQ_TYPE_EDGE_RISING)
761
			l |= 1 << gpio;
762
		else if (trigger & IRQ_TYPE_EDGE_FALLING)
763
			l &= ~(1 << gpio);
764 765
		else
			goto bad;
766
		break;
767 768
#endif
#ifdef CONFIG_ARCH_OMAP15XX
769 770 771
	case METHOD_GPIO_1510:
		reg += OMAP1510_GPIO_INT_CONTROL;
		l = __raw_readl(reg);
772
		if (trigger & IRQ_TYPE_EDGE_RISING)
773
			l |= 1 << gpio;
774
		else if (trigger & IRQ_TYPE_EDGE_FALLING)
775
			l &= ~(1 << gpio);
776 777
		else
			goto bad;
778
		break;
779
#endif
780
#ifdef CONFIG_ARCH_OMAP16XX
781 782 783 784 785 786 787 788
	case METHOD_GPIO_1610:
		if (gpio & 0x08)
			reg += OMAP1610_GPIO_EDGE_CTRL2;
		else
			reg += OMAP1610_GPIO_EDGE_CTRL1;
		gpio &= 0x07;
		l = __raw_readl(reg);
		l &= ~(3 << (gpio << 1));
789
		if (trigger & IRQ_TYPE_EDGE_RISING)
790
			l |= 2 << (gpio << 1);
791
		if (trigger & IRQ_TYPE_EDGE_FALLING)
792
			l |= 1 << (gpio << 1);
793 794 795 796 797
		if (trigger)
			/* Enable wake-up during idle for dynamic tick */
			__raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
		else
			__raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
798
		break;
799 800
#endif
#ifdef CONFIG_ARCH_OMAP730
801 802 803
	case METHOD_GPIO_730:
		reg += OMAP730_GPIO_INT_CONTROL;
		l = __raw_readl(reg);
804
		if (trigger & IRQ_TYPE_EDGE_RISING)
805
			l |= 1 << gpio;
806
		else if (trigger & IRQ_TYPE_EDGE_FALLING)
807
			l &= ~(1 << gpio);
808 809 810
		else
			goto bad;
		break;
811
#endif
812 813 814 815 816 817 818 819 820 821 822 823
#ifdef CONFIG_ARCH_OMAP850
	case METHOD_GPIO_850:
		reg += OMAP850_GPIO_INT_CONTROL;
		l = __raw_readl(reg);
		if (trigger & IRQ_TYPE_EDGE_RISING)
			l |= 1 << gpio;
		else if (trigger & IRQ_TYPE_EDGE_FALLING)
			l &= ~(1 << gpio);
		else
			goto bad;
		break;
#endif
824 825
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
				defined(CONFIG_ARCH_OMAP4)
826
	case METHOD_GPIO_24XX:
827
		set_24xx_gpio_triggering(bank, gpio, trigger);
828
		break;
829
#endif
830
	default:
831
		goto bad;
832
	}
833 834 835 836
	__raw_writel(l, reg);
	return 0;
bad:
	return -EINVAL;
837 838
}

839
static int gpio_irq_type(unsigned irq, unsigned type)
840 841
{
	struct gpio_bank *bank;
842 843
	unsigned gpio;
	int retval;
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844
	unsigned long flags;
845

846
	if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
847 848 849
		gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
	else
		gpio = irq - IH_GPIO_BASE;
850 851

	if (check_gpio(gpio) < 0)
852 853
		return -EINVAL;

854
	if (type & ~IRQ_TYPE_SENSE_MASK)
855
		return -EINVAL;
856 857

	/* OMAP1 allows only only edge triggering */
858
	if (!cpu_class_is_omap2()
859
			&& (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
860 861
		return -EINVAL;

862
	bank = get_irq_chip_data(irq);
D
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863
	spin_lock_irqsave(&bank->lock, flags);
864
	retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
865 866 867 868
	if (retval == 0) {
		irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
		irq_desc[irq].status |= type;
	}
D
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869
	spin_unlock_irqrestore(&bank->lock, flags);
870 871 872 873 874 875

	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
		__set_irq_handler_unlocked(irq, handle_level_irq);
	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
		__set_irq_handler_unlocked(irq, handle_edge_irq);

876
	return retval;
877 878 879 880
}

static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
{
881
	void __iomem *reg = bank->base;
882 883

	switch (bank->method) {
884
#ifdef CONFIG_ARCH_OMAP1
885 886 887 888
	case METHOD_MPUIO:
		/* MPUIO irqstatus is reset by reading the status register,
		 * so do nothing here */
		return;
889 890
#endif
#ifdef CONFIG_ARCH_OMAP15XX
891 892 893
	case METHOD_GPIO_1510:
		reg += OMAP1510_GPIO_INT_STATUS;
		break;
894 895
#endif
#ifdef CONFIG_ARCH_OMAP16XX
896 897 898
	case METHOD_GPIO_1610:
		reg += OMAP1610_GPIO_IRQSTATUS1;
		break;
899 900
#endif
#ifdef CONFIG_ARCH_OMAP730
901 902 903
	case METHOD_GPIO_730:
		reg += OMAP730_GPIO_INT_STATUS;
		break;
904
#endif
905 906 907 908 909
#ifdef CONFIG_ARCH_OMAP850
	case METHOD_GPIO_850:
		reg += OMAP850_GPIO_INT_STATUS;
		break;
#endif
910
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
911 912 913
	case METHOD_GPIO_24XX:
		reg += OMAP24XX_GPIO_IRQSTATUS1;
		break;
914 915 916 917 918
#endif
#if defined(CONFIG_ARCH_OMAP4)
	case METHOD_GPIO_24XX:
		reg += OMAP4_GPIO_IRQSTATUS0;
		break;
919
#endif
920
	default:
921
		WARN_ON(1);
922 923 924
		return;
	}
	__raw_writel(gpio_mask, reg);
925 926

	/* Workaround for clearing DSP GPIO interrupts to allow retention */
927
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
928
	reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
929 930 931 932 933
#endif
#if defined(CONFIG_ARCH_OMAP4)
	reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
#endif
	if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
934 935 936 937
		__raw_writel(gpio_mask, reg);

	/* Flush posted write for the irq status to avoid spurious interrupts */
	__raw_readl(reg);
938
	}
939 940 941 942 943 944 945
}

static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
{
	_clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
}

946 947 948
static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
{
	void __iomem *reg = bank->base;
949 950 951
	int inv = 0;
	u32 l;
	u32 mask;
952 953

	switch (bank->method) {
954
#ifdef CONFIG_ARCH_OMAP1
955 956
	case METHOD_MPUIO:
		reg += OMAP_MPUIO_GPIO_MASKIT;
957 958
		mask = 0xffff;
		inv = 1;
959
		break;
960 961
#endif
#ifdef CONFIG_ARCH_OMAP15XX
962 963
	case METHOD_GPIO_1510:
		reg += OMAP1510_GPIO_INT_MASK;
964 965
		mask = 0xffff;
		inv = 1;
966
		break;
967 968
#endif
#ifdef CONFIG_ARCH_OMAP16XX
969 970
	case METHOD_GPIO_1610:
		reg += OMAP1610_GPIO_IRQENABLE1;
971
		mask = 0xffff;
972
		break;
973 974
#endif
#ifdef CONFIG_ARCH_OMAP730
975 976
	case METHOD_GPIO_730:
		reg += OMAP730_GPIO_INT_MASK;
977 978
		mask = 0xffffffff;
		inv = 1;
979
		break;
980
#endif
981 982 983 984 985 986 987
#ifdef CONFIG_ARCH_OMAP850
	case METHOD_GPIO_850:
		reg += OMAP850_GPIO_INT_MASK;
		mask = 0xffffffff;
		inv = 1;
		break;
#endif
988
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
989 990
	case METHOD_GPIO_24XX:
		reg += OMAP24XX_GPIO_IRQENABLE1;
991
		mask = 0xffffffff;
992
		break;
993 994 995 996 997 998
#endif
#if defined(CONFIG_ARCH_OMAP4)
	case METHOD_GPIO_24XX:
		reg += OMAP4_GPIO_IRQSTATUSSET0;
		mask = 0xffffffff;
		break;
999
#endif
1000
	default:
1001
		WARN_ON(1);
1002 1003 1004
		return 0;
	}

1005 1006 1007 1008 1009
	l = __raw_readl(reg);
	if (inv)
		l = ~l;
	l &= mask;
	return l;
1010 1011
}

1012 1013
static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
{
1014
	void __iomem *reg = bank->base;
1015 1016 1017
	u32 l;

	switch (bank->method) {
1018
#ifdef CONFIG_ARCH_OMAP1
1019 1020 1021 1022 1023 1024 1025 1026
	case METHOD_MPUIO:
		reg += OMAP_MPUIO_GPIO_MASKIT;
		l = __raw_readl(reg);
		if (enable)
			l &= ~(gpio_mask);
		else
			l |= gpio_mask;
		break;
1027 1028
#endif
#ifdef CONFIG_ARCH_OMAP15XX
1029 1030 1031 1032 1033 1034 1035 1036
	case METHOD_GPIO_1510:
		reg += OMAP1510_GPIO_INT_MASK;
		l = __raw_readl(reg);
		if (enable)
			l &= ~(gpio_mask);
		else
			l |= gpio_mask;
		break;
1037 1038
#endif
#ifdef CONFIG_ARCH_OMAP16XX
1039 1040 1041 1042 1043 1044 1045
	case METHOD_GPIO_1610:
		if (enable)
			reg += OMAP1610_GPIO_SET_IRQENABLE1;
		else
			reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
		l = gpio_mask;
		break;
1046 1047
#endif
#ifdef CONFIG_ARCH_OMAP730
1048 1049 1050 1051 1052 1053 1054 1055
	case METHOD_GPIO_730:
		reg += OMAP730_GPIO_INT_MASK;
		l = __raw_readl(reg);
		if (enable)
			l &= ~(gpio_mask);
		else
			l |= gpio_mask;
		break;
1056
#endif
1057 1058 1059 1060 1061 1062 1063 1064 1065 1066
#ifdef CONFIG_ARCH_OMAP850
	case METHOD_GPIO_850:
		reg += OMAP850_GPIO_INT_MASK;
		l = __raw_readl(reg);
		if (enable)
			l &= ~(gpio_mask);
		else
			l |= gpio_mask;
		break;
#endif
1067
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1068 1069 1070 1071 1072 1073 1074
	case METHOD_GPIO_24XX:
		if (enable)
			reg += OMAP24XX_GPIO_SETIRQENABLE1;
		else
			reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
		l = gpio_mask;
		break;
1075 1076 1077 1078 1079 1080 1081 1082 1083
#endif
#ifdef CONFIG_ARCH_OMAP4
	case METHOD_GPIO_24XX:
		if (enable)
			reg += OMAP4_GPIO_IRQSTATUSSET0;
		else
			reg += OMAP4_GPIO_IRQSTATUSCLR0;
		l = gpio_mask;
		break;
1084
#endif
1085
	default:
1086
		WARN_ON(1);
1087 1088 1089 1090 1091 1092 1093 1094 1095 1096
		return;
	}
	__raw_writel(l, reg);
}

static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
{
	_enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
}

1097 1098 1099 1100 1101 1102 1103 1104 1105 1106
/*
 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
 * 1510 does not seem to have a wake-up register. If JTAG is connected
 * to the target, system will wake up always on GPIO events. While
 * system is running all registered GPIO interrupts need to have wake-up
 * enabled. When system is suspended, only selected GPIO interrupts need
 * to have wake-up enabled.
 */
static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
{
D
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1107 1108
	unsigned long flags;

1109
	switch (bank->method) {
1110
#ifdef CONFIG_ARCH_OMAP16XX
D
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1111
	case METHOD_MPUIO:
1112
	case METHOD_GPIO_1610:
D
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1113
		spin_lock_irqsave(&bank->lock, flags);
1114
		if (enable)
1115
			bank->suspend_wakeup |= (1 << gpio);
1116
		else
1117
			bank->suspend_wakeup &= ~(1 << gpio);
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		spin_unlock_irqrestore(&bank->lock, flags);
1119
		return 0;
1120
#endif
1121 1122
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
				defined(CONFIG_ARCH_OMAP4)
1123
	case METHOD_GPIO_24XX:
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1124 1125 1126 1127 1128 1129
		if (bank->non_wakeup_gpios & (1 << gpio)) {
			printk(KERN_ERR "Unable to modify wakeup on "
					"non-wakeup GPIO%d\n",
					(bank - gpio_bank) * 32 + gpio);
			return -EINVAL;
		}
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1130
		spin_lock_irqsave(&bank->lock, flags);
1131
		if (enable)
1132
			bank->suspend_wakeup |= (1 << gpio);
1133
		else
1134
			bank->suspend_wakeup &= ~(1 << gpio);
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		spin_unlock_irqrestore(&bank->lock, flags);
1136 1137
		return 0;
#endif
1138 1139 1140 1141 1142 1143 1144
	default:
		printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
		       bank->method);
		return -EINVAL;
	}
}

1145 1146 1147 1148 1149
static void _reset_gpio(struct gpio_bank *bank, int gpio)
{
	_set_gpio_direction(bank, get_gpio_index(gpio), 1);
	_set_gpio_irqenable(bank, gpio, 0);
	_clear_gpio_irqstatus(bank, gpio);
1150
	_set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1151 1152
}

1153 1154 1155 1156 1157 1158 1159 1160 1161
/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
static int gpio_wake_enable(unsigned int irq, unsigned int enable)
{
	unsigned int gpio = irq - IH_GPIO_BASE;
	struct gpio_bank *bank;
	int retval;

	if (check_gpio(gpio) < 0)
		return -ENODEV;
1162
	bank = get_irq_chip_data(irq);
1163 1164 1165 1166 1167
	retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);

	return retval;
}

1168
static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
1169
{
1170
	struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
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	unsigned long flags;
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1172

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	spin_lock_irqsave(&bank->lock, flags);
1174

1175 1176 1177
	/* Set trigger to none. You need to enable the desired trigger with
	 * request_irq() or set_irq_type().
	 */
1178
	_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
1179

1180
#ifdef CONFIG_ARCH_OMAP15XX
1181
	if (bank->method == METHOD_GPIO_1510) {
1182
		void __iomem *reg;
1183

1184
		/* Claim the pin for MPU */
1185
		reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
1186
		__raw_writel(__raw_readl(reg) | (1 << offset), reg);
1187 1188
	}
#endif
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	spin_unlock_irqrestore(&bank->lock, flags);
1190 1191 1192 1193

	return 0;
}

1194
static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1195
{
1196
	struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
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1197
	unsigned long flags;
1198

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1199
	spin_lock_irqsave(&bank->lock, flags);
1200 1201 1202 1203
#ifdef CONFIG_ARCH_OMAP16XX
	if (bank->method == METHOD_GPIO_1610) {
		/* Disable wake-up during idle for dynamic tick */
		void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1204
		__raw_writel(1 << offset, reg);
1205 1206
	}
#endif
1207 1208
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
				defined(CONFIG_ARCH_OMAP4)
1209 1210 1211
	if (bank->method == METHOD_GPIO_24XX) {
		/* Disable wake-up during idle for dynamic tick */
		void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1212
		__raw_writel(1 << offset, reg);
1213 1214
	}
#endif
1215
	_reset_gpio(bank, bank->chip.base + offset);
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	spin_unlock_irqrestore(&bank->lock, flags);
1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227
}

/*
 * We need to unmask the GPIO bank interrupt as soon as possible to
 * avoid missing GPIO interrupts for other lines in the bank.
 * Then we need to mask-read-clear-unmask the triggered GPIO lines
 * in the bank to avoid missing nested interrupts for a GPIO line.
 * If we wait to unmask individual GPIO lines in the bank after the
 * line's interrupt handler has been run, we may miss some nested
 * interrupts.
 */
1228
static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1229
{
1230
	void __iomem *isr_reg = NULL;
1231 1232 1233
	u32 isr;
	unsigned int gpio_irq;
	struct gpio_bank *bank;
1234 1235
	u32 retrigger = 0;
	int unmasked = 0;
1236 1237 1238

	desc->chip->ack(irq);

1239
	bank = get_irq_data(irq);
1240
#ifdef CONFIG_ARCH_OMAP1
1241 1242
	if (bank->method == METHOD_MPUIO)
		isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
1243
#endif
1244
#ifdef CONFIG_ARCH_OMAP15XX
1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255
	if (bank->method == METHOD_GPIO_1510)
		isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
#endif
#if defined(CONFIG_ARCH_OMAP16XX)
	if (bank->method == METHOD_GPIO_1610)
		isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
#endif
#ifdef CONFIG_ARCH_OMAP730
	if (bank->method == METHOD_GPIO_730)
		isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
#endif
1256 1257 1258 1259
#ifdef CONFIG_ARCH_OMAP850
	if (bank->method == METHOD_GPIO_850)
		isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
#endif
1260
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1261 1262
	if (bank->method == METHOD_GPIO_24XX)
		isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1263 1264 1265 1266
#endif
#if defined(CONFIG_ARCH_OMAP4)
	if (bank->method == METHOD_GPIO_24XX)
		isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1267 1268
#endif
	while(1) {
1269
		u32 isr_saved, level_mask = 0;
1270
		u32 enabled;
1271

1272 1273
		enabled = _get_gpio_irqbank_mask(bank);
		isr_saved = isr = __raw_readl(isr_reg) & enabled;
1274 1275 1276 1277

		if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
			isr &= 0x0000ffff;

1278
		if (cpu_class_is_omap2()) {
1279
			level_mask = bank->level_mask & enabled;
1280
		}
1281 1282 1283 1284 1285 1286 1287 1288 1289 1290

		/* clear edge sensitive interrupts before handler(s) are
		called so that we don't miss any interrupt occurred while
		executing them */
		_enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
		_clear_gpio_irqbank(bank, isr_saved & ~level_mask);
		_enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);

		/* if there is only edge sensitive GPIO pin interrupts
		configured, we could unmask GPIO bank interrupt immediately */
1291 1292
		if (!level_mask && !unmasked) {
			unmasked = 1;
1293
			desc->chip->unmask(irq);
1294
		}
1295

1296 1297
		isr |= retrigger;
		retrigger = 0;
1298 1299 1300 1301 1302 1303 1304
		if (!isr)
			break;

		gpio_irq = bank->virtual_irq_start;
		for (; isr != 0; isr >>= 1, gpio_irq++) {
			if (!(isr & 1))
				continue;
1305

1306
			generic_handle_irq(gpio_irq);
1307
		}
1308
	}
1309 1310 1311 1312 1313 1314 1315
	/* if bank has any level sensitive GPIO pin interrupt
	configured, we must unmask the bank interrupt only after
	handler(s) are executed in order to avoid spurious bank
	interrupt */
	if (!unmasked)
		desc->chip->unmask(irq);

1316 1317
}

1318 1319 1320
static void gpio_irq_shutdown(unsigned int irq)
{
	unsigned int gpio = irq - IH_GPIO_BASE;
1321
	struct gpio_bank *bank = get_irq_chip_data(irq);
1322 1323 1324 1325

	_reset_gpio(bank, gpio);
}

1326 1327 1328
static void gpio_ack_irq(unsigned int irq)
{
	unsigned int gpio = irq - IH_GPIO_BASE;
1329
	struct gpio_bank *bank = get_irq_chip_data(irq);
1330 1331 1332 1333 1334 1335 1336

	_clear_gpio_irqstatus(bank, gpio);
}

static void gpio_mask_irq(unsigned int irq)
{
	unsigned int gpio = irq - IH_GPIO_BASE;
1337
	struct gpio_bank *bank = get_irq_chip_data(irq);
1338 1339

	_set_gpio_irqenable(bank, gpio, 0);
1340
	_set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1341 1342 1343 1344 1345
}

static void gpio_unmask_irq(unsigned int irq)
{
	unsigned int gpio = irq - IH_GPIO_BASE;
1346
	struct gpio_bank *bank = get_irq_chip_data(irq);
1347
	unsigned int irq_mask = 1 << get_gpio_index(gpio);
1348 1349 1350 1351 1352
	struct irq_desc *desc = irq_to_desc(irq);
	u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;

	if (trigger)
		_set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1353 1354 1355 1356 1357 1358 1359

	/* For level-triggered GPIOs, the clearing must be done after
	 * the HW source is cleared, thus after the handler has run */
	if (bank->level_mask & irq_mask) {
		_set_gpio_irqenable(bank, gpio, 0);
		_clear_gpio_irqstatus(bank, gpio);
	}
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	_set_gpio_irqenable(bank, gpio, 1);
1362 1363
}

1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379
static struct irq_chip gpio_irq_chip = {
	.name		= "GPIO",
	.shutdown	= gpio_irq_shutdown,
	.ack		= gpio_ack_irq,
	.mask		= gpio_mask_irq,
	.unmask		= gpio_unmask_irq,
	.set_type	= gpio_irq_type,
	.set_wake	= gpio_wake_enable,
};

/*---------------------------------------------------------------------*/

#ifdef CONFIG_ARCH_OMAP1

/* MPUIO uses the always-on 32k clock */

1380 1381 1382 1383 1384 1385 1386 1387
static void mpuio_ack_irq(unsigned int irq)
{
	/* The ISR is reset automatically, so do nothing here. */
}

static void mpuio_mask_irq(unsigned int irq)
{
	unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1388
	struct gpio_bank *bank = get_irq_chip_data(irq);
1389 1390 1391 1392 1393 1394 1395

	_set_gpio_irqenable(bank, gpio, 0);
}

static void mpuio_unmask_irq(unsigned int irq)
{
	unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1396
	struct gpio_bank *bank = get_irq_chip_data(irq);
1397 1398 1399 1400

	_set_gpio_irqenable(bank, gpio, 1);
}

1401 1402 1403 1404 1405
static struct irq_chip mpuio_irq_chip = {
	.name		= "MPUIO",
	.ack		= mpuio_ack_irq,
	.mask		= mpuio_mask_irq,
	.unmask		= mpuio_unmask_irq,
1406
	.set_type	= gpio_irq_type,
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#ifdef CONFIG_ARCH_OMAP16XX
	/* REVISIT: assuming only 16xx supports MPUIO wake events */
	.set_wake	= gpio_wake_enable,
#endif
1411 1412
};

1413 1414 1415

#define bank_is_mpuio(bank)	((bank)->method == METHOD_MPUIO)

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#ifdef CONFIG_ARCH_OMAP16XX

#include <linux/platform_device.h>

static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
{
	struct gpio_bank	*bank = platform_get_drvdata(pdev);
	void __iomem		*mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
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	unsigned long		flags;
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1426

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1427
	spin_lock_irqsave(&bank->lock, flags);
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1428 1429
	bank->saved_wakeup = __raw_readl(mask_reg);
	__raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
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1430
	spin_unlock_irqrestore(&bank->lock, flags);
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1431 1432 1433 1434 1435 1436 1437 1438

	return 0;
}

static int omap_mpuio_resume_early(struct platform_device *pdev)
{
	struct gpio_bank	*bank = platform_get_drvdata(pdev);
	void __iomem		*mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
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1439
	unsigned long		flags;
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1440

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1441
	spin_lock_irqsave(&bank->lock, flags);
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1442
	__raw_writel(bank->saved_wakeup, mask_reg);
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1443
	spin_unlock_irqrestore(&bank->lock, flags);
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1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469

	return 0;
}

/* use platform_driver for this, now that there's no longer any
 * point to sys_device (other than not disturbing old code).
 */
static struct platform_driver omap_mpuio_driver = {
	.suspend_late	= omap_mpuio_suspend_late,
	.resume_early	= omap_mpuio_resume_early,
	.driver		= {
		.name	= "mpuio",
	},
};

static struct platform_device omap_mpuio_device = {
	.name		= "mpuio",
	.id		= -1,
	.dev = {
		.driver = &omap_mpuio_driver.driver,
	}
	/* could list the /proc/iomem resources */
};

static inline void mpuio_init(void)
{
1470 1471
	platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);

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1472 1473 1474 1475 1476 1477 1478 1479
	if (platform_driver_register(&omap_mpuio_driver) == 0)
		(void) platform_device_register(&omap_mpuio_device);
}

#else
static inline void mpuio_init(void) {}
#endif	/* 16xx */

1480 1481 1482 1483 1484
#else

extern struct irq_chip mpuio_irq_chip;

#define bank_is_mpuio(bank)	0
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static inline void mpuio_init(void) {}
1486 1487 1488 1489

#endif

/*---------------------------------------------------------------------*/
1490

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1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506
/* REVISIT these are stupid implementations!  replace by ones that
 * don't switch on METHOD_* and which mostly avoid spinlocks
 */

static int gpio_input(struct gpio_chip *chip, unsigned offset)
{
	struct gpio_bank *bank;
	unsigned long flags;

	bank = container_of(chip, struct gpio_bank, chip);
	spin_lock_irqsave(&bank->lock, flags);
	_set_gpio_direction(bank, offset, 1);
	spin_unlock_irqrestore(&bank->lock, flags);
	return 0;
}

1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533
static int gpio_is_input(struct gpio_bank *bank, int mask)
{
	void __iomem *reg = bank->base;

	switch (bank->method) {
	case METHOD_MPUIO:
		reg += OMAP_MPUIO_IO_CNTL;
		break;
	case METHOD_GPIO_1510:
		reg += OMAP1510_GPIO_DIR_CONTROL;
		break;
	case METHOD_GPIO_1610:
		reg += OMAP1610_GPIO_DIRECTION;
		break;
	case METHOD_GPIO_730:
		reg += OMAP730_GPIO_DIR_CONTROL;
		break;
	case METHOD_GPIO_850:
		reg += OMAP850_GPIO_DIR_CONTROL;
		break;
	case METHOD_GPIO_24XX:
		reg += OMAP24XX_GPIO_OE;
		break;
	}
	return __raw_readl(reg) & mask;
}

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1534 1535
static int gpio_get(struct gpio_chip *chip, unsigned offset)
{
1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549
	struct gpio_bank *bank;
	void __iomem *reg;
	int gpio;
	u32 mask;

	gpio = chip->base + offset;
	bank = get_gpio_bank(gpio);
	reg = bank->base;
	mask = 1 << get_gpio_index(gpio);

	if (gpio_is_input(bank, mask))
		return _get_gpio_datain(bank, gpio);
	else
		return _get_gpio_dataout(bank, gpio);
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1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575
}

static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
{
	struct gpio_bank *bank;
	unsigned long flags;

	bank = container_of(chip, struct gpio_bank, chip);
	spin_lock_irqsave(&bank->lock, flags);
	_set_gpio_dataout(bank, offset, value);
	_set_gpio_direction(bank, offset, 0);
	spin_unlock_irqrestore(&bank->lock, flags);
	return 0;
}

static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct gpio_bank *bank;
	unsigned long flags;

	bank = container_of(chip, struct gpio_bank, chip);
	spin_lock_irqsave(&bank->lock, flags);
	_set_gpio_dataout(bank, offset, value);
	spin_unlock_irqrestore(&bank->lock, flags);
}

1576 1577 1578 1579 1580 1581 1582 1583
static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
{
	struct gpio_bank *bank;

	bank = container_of(chip, struct gpio_bank, chip);
	return bank->virtual_irq_start + offset;
}

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1584 1585
/*---------------------------------------------------------------------*/

1586
static int initialized;
1587
#if !(defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4))
1588
static struct clk * gpio_ick;
1589 1590 1591
#endif

#if defined(CONFIG_ARCH_OMAP2)
1592
static struct clk * gpio_fck;
1593
#endif
1594

1595
#if defined(CONFIG_ARCH_OMAP2430)
1596 1597 1598 1599
static struct clk * gpio5_ick;
static struct clk * gpio5_fck;
#endif

1600
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1601 1602 1603
static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
#endif

1604 1605 1606 1607 1608
/* This lock class tells lockdep that GPIO irqs are in a different
 * category than their parents, so it won't report false recursion.
 */
static struct lock_class_key gpio_lock_class;

1609 1610 1611
static int __init _omap_gpio_init(void)
{
	int i;
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1612
	int gpio = 0;
1613
	struct gpio_bank *bank;
1614
	char clk_name[11];
1615 1616 1617

	initialized = 1;

1618
#if defined(CONFIG_ARCH_OMAP1)
1619
	if (cpu_is_omap15xx()) {
1620 1621
		gpio_ick = clk_get(NULL, "arm_gpio_ck");
		if (IS_ERR(gpio_ick))
1622 1623
			printk("Could not get arm_gpio_ck\n");
		else
1624
			clk_enable(gpio_ick);
1625
	}
1626 1627 1628
#endif
#if defined(CONFIG_ARCH_OMAP2)
	if (cpu_class_is_omap2()) {
1629 1630 1631 1632
		gpio_ick = clk_get(NULL, "gpios_ick");
		if (IS_ERR(gpio_ick))
			printk("Could not get gpios_ick\n");
		else
1633
			clk_enable(gpio_ick);
1634
		gpio_fck = clk_get(NULL, "gpios_fck");
1635
		if (IS_ERR(gpio_fck))
1636 1637
			printk("Could not get gpios_fck\n");
		else
1638
			clk_enable(gpio_fck);
1639 1640

		/*
1641
		 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1642
		 */
1643
#if defined(CONFIG_ARCH_OMAP2430)
1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656
		if (cpu_is_omap2430()) {
			gpio5_ick = clk_get(NULL, "gpio5_ick");
			if (IS_ERR(gpio5_ick))
				printk("Could not get gpio5_ick\n");
			else
				clk_enable(gpio5_ick);
			gpio5_fck = clk_get(NULL, "gpio5_fck");
			if (IS_ERR(gpio5_fck))
				printk("Could not get gpio5_fck\n");
			else
				clk_enable(gpio5_fck);
		}
#endif
1657 1658 1659
	}
#endif

1660 1661
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
	if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672
		for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
			sprintf(clk_name, "gpio%d_ick", i + 1);
			gpio_iclks[i] = clk_get(NULL, clk_name);
			if (IS_ERR(gpio_iclks[i]))
				printk(KERN_ERR "Could not get %s\n", clk_name);
			else
				clk_enable(gpio_iclks[i]);
		}
	}
#endif

1673

1674
#ifdef CONFIG_ARCH_OMAP15XX
1675
	if (cpu_is_omap15xx()) {
1676 1677 1678 1679 1680 1681 1682
		printk(KERN_INFO "OMAP1510 GPIO hardware\n");
		gpio_bank_count = 2;
		gpio_bank = gpio_bank_1510;
	}
#endif
#if defined(CONFIG_ARCH_OMAP16XX)
	if (cpu_is_omap16xx()) {
1683
		u32 rev;
1684 1685 1686

		gpio_bank_count = 5;
		gpio_bank = gpio_bank_1610;
1687
		rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1688 1689 1690 1691 1692 1693 1694 1695 1696 1697
		printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
		       (rev >> 4) & 0x0f, rev & 0x0f);
	}
#endif
#ifdef CONFIG_ARCH_OMAP730
	if (cpu_is_omap730()) {
		printk(KERN_INFO "OMAP730 GPIO hardware\n");
		gpio_bank_count = 7;
		gpio_bank = gpio_bank_730;
	}
1698
#endif
1699 1700 1701 1702 1703 1704 1705
#ifdef CONFIG_ARCH_OMAP850
	if (cpu_is_omap850()) {
		printk(KERN_INFO "OMAP850 GPIO hardware\n");
		gpio_bank_count = 7;
		gpio_bank = gpio_bank_850;
	}
#endif
1706

1707
#ifdef CONFIG_ARCH_OMAP24XX
1708
	if (cpu_is_omap242x()) {
1709 1710 1711
		int rev;

		gpio_bank_count = 4;
1712
		gpio_bank = gpio_bank_242x;
1713
		rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1714 1715 1716 1717 1718 1719 1720 1721
		printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
			(rev >> 4) & 0x0f, rev & 0x0f);
	}
	if (cpu_is_omap243x()) {
		int rev;

		gpio_bank_count = 5;
		gpio_bank = gpio_bank_243x;
1722
		rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1723
		printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1724 1725
			(rev >> 4) & 0x0f, rev & 0x0f);
	}
1726 1727 1728 1729 1730 1731 1732
#endif
#ifdef CONFIG_ARCH_OMAP34XX
	if (cpu_is_omap34xx()) {
		int rev;

		gpio_bank_count = OMAP34XX_NR_GPIOS;
		gpio_bank = gpio_bank_34xx;
1733
		rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1734 1735 1736
		printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
			(rev >> 4) & 0x0f, rev & 0x0f);
	}
1737 1738 1739 1740 1741 1742 1743
#endif
#ifdef CONFIG_ARCH_OMAP4
	if (cpu_is_omap44xx()) {
		int rev;

		gpio_bank_count = OMAP34XX_NR_GPIOS;
		gpio_bank = gpio_bank_44xx;
1744
		rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
1745 1746 1747
		printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n",
			(rev >> 4) & 0x0f, rev & 0x0f);
	}
1748 1749 1750 1751 1752 1753
#endif
	for (i = 0; i < gpio_bank_count; i++) {
		int j, gpio_count = 16;

		bank = &gpio_bank[i];
		spin_lock_init(&bank->lock);
1754
		if (bank_is_mpuio(bank))
1755
			__raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1756
		if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1757 1758 1759
			__raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
			__raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
		}
1760
		if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1761 1762
			__raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
			__raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1763
			__raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1764
		}
1765
		if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_730) {
1766 1767 1768 1769 1770
			__raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
			__raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);

			gpio_count = 32; /* 730 has 32-bit GPIOs */
		}
1771

1772 1773
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
				defined(CONFIG_ARCH_OMAP4)
1774
		if (bank->method == METHOD_GPIO_24XX) {
1775 1776 1777
			static const u32 non_wakeup_gpios[] = {
				0xe203ffc0, 0x08700040
			};
1778 1779 1780 1781 1782 1783 1784 1785 1786 1787
		if (cpu_is_omap44xx()) {
			__raw_writel(0xffffffff, bank->base +
						OMAP4_GPIO_IRQSTATUSCLR0);
			__raw_writew(0x0015, bank->base +
						OMAP4_GPIO_SYSCONFIG);
			__raw_writel(0x00000000, bank->base +
						 OMAP4_GPIO_DEBOUNCENABLE);
			/* Initialize interface clock ungated, module enabled */
			__raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
		} else {
1788 1789
			__raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
			__raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1790
			__raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1791
			__raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN);
1792 1793 1794

			/* Initialize interface clock ungated, module enabled */
			__raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1795
		}
1796 1797
			if (i < ARRAY_SIZE(non_wakeup_gpios))
				bank->non_wakeup_gpios = non_wakeup_gpios[i];
1798 1799
			gpio_count = 32;
		}
1800
#endif
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1801 1802 1803
		/* REVISIT eventually switch from OMAP-specific gpio structs
		 * over to the generic ones
		 */
1804 1805
		bank->chip.request = omap_gpio_request;
		bank->chip.free = omap_gpio_free;
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1806 1807 1808 1809
		bank->chip.direction_input = gpio_input;
		bank->chip.get = gpio_get;
		bank->chip.direction_output = gpio_output;
		bank->chip.set = gpio_set;
1810
		bank->chip.to_irq = gpio_2irq;
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1811 1812
		if (bank_is_mpuio(bank)) {
			bank->chip.label = "mpuio";
1813
#ifdef CONFIG_ARCH_OMAP16XX
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1814 1815
			bank->chip.dev = &omap_mpuio_device.dev;
#endif
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1816 1817 1818 1819 1820 1821 1822 1823 1824 1825
			bank->chip.base = OMAP_MPUIO(0);
		} else {
			bank->chip.label = "gpio";
			bank->chip.base = gpio;
			gpio += gpio_count;
		}
		bank->chip.ngpio = gpio_count;

		gpiochip_add(&bank->chip);

1826 1827
		for (j = bank->virtual_irq_start;
		     j < bank->virtual_irq_start + gpio_count; j++) {
1828
			lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1829
			set_irq_chip_data(j, bank);
1830
			if (bank_is_mpuio(bank))
1831 1832 1833
				set_irq_chip(j, &mpuio_irq_chip);
			else
				set_irq_chip(j, &gpio_irq_chip);
1834
			set_irq_handler(j, handle_simple_irq);
1835 1836 1837 1838
			set_irq_flags(j, IRQF_VALID);
		}
		set_irq_chained_handler(bank->irq, gpio_irq_handler);
		set_irq_data(bank->irq, bank);
1839

1840
		if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1841 1842 1843 1844 1845
			sprintf(clk_name, "gpio%d_dbck", i + 1);
			bank->dbck = clk_get(NULL, clk_name);
			if (IS_ERR(bank->dbck))
				printk(KERN_ERR "Could not get %s\n", clk_name);
		}
1846 1847 1848 1849
	}

	/* Enable system clock for GPIO module.
	 * The CAM_CLK_CTRL *is* really the right place. */
1850
	if (cpu_is_omap16xx())
1851 1852
		omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);

1853 1854 1855
	/* Enable autoidle for the OCP interface */
	if (cpu_is_omap24xx())
		omap_writel(1 << 0, 0x48019010);
1856 1857
	if (cpu_is_omap34xx())
		omap_writel(1 << 0, 0x48306814);
1858

1859 1860 1861
	return 0;
}

1862 1863
#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
		defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
1864 1865 1866 1867
static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
{
	int i;

1868
	if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1869 1870 1871 1872 1873 1874 1875
		return 0;

	for (i = 0; i < gpio_bank_count; i++) {
		struct gpio_bank *bank = &gpio_bank[i];
		void __iomem *wake_status;
		void __iomem *wake_clear;
		void __iomem *wake_set;
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1876
		unsigned long flags;
1877 1878

		switch (bank->method) {
1879
#ifdef CONFIG_ARCH_OMAP16XX
1880 1881 1882 1883 1884
		case METHOD_GPIO_1610:
			wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
			wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
			wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
			break;
1885
#endif
1886
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1887
		case METHOD_GPIO_24XX:
1888
			wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1889 1890 1891
			wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
			wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
			break;
1892 1893 1894 1895 1896 1897 1898
#endif
#ifdef CONFIG_ARCH_OMAP4
		case METHOD_GPIO_24XX:
			wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
			wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
			wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
			break;
1899
#endif
1900 1901 1902 1903
		default:
			continue;
		}

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1904
		spin_lock_irqsave(&bank->lock, flags);
1905 1906 1907
		bank->saved_wakeup = __raw_readl(wake_status);
		__raw_writel(0xffffffff, wake_clear);
		__raw_writel(bank->suspend_wakeup, wake_set);
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1908
		spin_unlock_irqrestore(&bank->lock, flags);
1909 1910 1911 1912 1913 1914 1915 1916 1917
	}

	return 0;
}

static int omap_gpio_resume(struct sys_device *dev)
{
	int i;

1918
	if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1919 1920 1921 1922 1923 1924
		return 0;

	for (i = 0; i < gpio_bank_count; i++) {
		struct gpio_bank *bank = &gpio_bank[i];
		void __iomem *wake_clear;
		void __iomem *wake_set;
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1925
		unsigned long flags;
1926 1927

		switch (bank->method) {
1928
#ifdef CONFIG_ARCH_OMAP16XX
1929 1930 1931 1932
		case METHOD_GPIO_1610:
			wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
			wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
			break;
1933
#endif
1934
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1935
		case METHOD_GPIO_24XX:
1936 1937
			wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
			wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1938
			break;
1939 1940 1941 1942 1943 1944
#endif
#ifdef CONFIG_ARCH_OMAP4
		case METHOD_GPIO_24XX:
			wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
			wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
			break;
1945
#endif
1946 1947 1948 1949
		default:
			continue;
		}

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1950
		spin_lock_irqsave(&bank->lock, flags);
1951 1952
		__raw_writel(0xffffffff, wake_clear);
		__raw_writel(bank->saved_wakeup, wake_set);
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1953
		spin_unlock_irqrestore(&bank->lock, flags);
1954 1955 1956 1957 1958 1959
	}

	return 0;
}

static struct sysdev_class omap_gpio_sysclass = {
1960
	.name		= "gpio",
1961 1962 1963 1964 1965 1966 1967 1968
	.suspend	= omap_gpio_suspend,
	.resume		= omap_gpio_resume,
};

static struct sys_device omap_gpio_device = {
	.id		= 0,
	.cls		= &omap_gpio_sysclass,
};
1969 1970 1971

#endif

1972 1973
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
				defined(CONFIG_ARCH_OMAP4)
1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988

static int workaround_enabled;

void omap2_gpio_prepare_for_retention(void)
{
	int i, c = 0;

	/* Remove triggering for all non-wakeup GPIOs.  Otherwise spurious
	 * IRQs will be generated.  See OMAP2420 Errata item 1.101. */
	for (i = 0; i < gpio_bank_count; i++) {
		struct gpio_bank *bank = &gpio_bank[i];
		u32 l1, l2;

		if (!(bank->enabled_non_wakeup_gpios))
			continue;
1989
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1990 1991 1992
		bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
		l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
		l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1993 1994 1995 1996 1997 1998
#endif
#ifdef CONFIG_ARCH_OMAP4
		bank->saved_datain = __raw_readl(bank->base +
							OMAP4_GPIO_DATAIN);
		l1 = __raw_readl(bank->base + OMAP4_GPIO_FALLINGDETECT);
		l2 = __raw_readl(bank->base + OMAP4_GPIO_RISINGDETECT);
1999
#endif
2000 2001 2002 2003
		bank->saved_fallingdetect = l1;
		bank->saved_risingdetect = l2;
		l1 &= ~bank->enabled_non_wakeup_gpios;
		l2 &= ~bank->enabled_non_wakeup_gpios;
2004
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
2005 2006
		__raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
		__raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
2007 2008 2009 2010
#endif
#ifdef CONFIG_ARCH_OMAP4
		__raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
		__raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
2011
#endif
2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032
		c++;
	}
	if (!c) {
		workaround_enabled = 0;
		return;
	}
	workaround_enabled = 1;
}

void omap2_gpio_resume_after_retention(void)
{
	int i;

	if (!workaround_enabled)
		return;
	for (i = 0; i < gpio_bank_count; i++) {
		struct gpio_bank *bank = &gpio_bank[i];
		u32 l;

		if (!(bank->enabled_non_wakeup_gpios))
			continue;
2033
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
2034 2035 2036 2037
		__raw_writel(bank->saved_fallingdetect,
				 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
		__raw_writel(bank->saved_risingdetect,
				 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2038 2039 2040 2041 2042 2043 2044 2045
		l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
#endif
#ifdef CONFIG_ARCH_OMAP4
		__raw_writel(bank->saved_fallingdetect,
				 bank->base + OMAP4_GPIO_FALLINGDETECT);
		__raw_writel(bank->saved_risingdetect,
				 bank->base + OMAP4_GPIO_RISINGDETECT);
		l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
2046
#endif
2047 2048 2049 2050 2051 2052 2053 2054
		/* Check if any of the non-wakeup interrupt GPIOs have changed
		 * state.  If so, generate an IRQ by software.  This is
		 * horribly racy, but it's the best we can do to work around
		 * this silicon bug. */
		l ^= bank->saved_datain;
		l &= bank->non_wakeup_gpios;
		if (l) {
			u32 old0, old1;
2055
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
2056 2057 2058 2059 2060 2061
			old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
			old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
			__raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
			__raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
			__raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
			__raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075
#endif
#ifdef CONFIG_ARCH_OMAP4
			old0 = __raw_readl(bank->base +
						OMAP4_GPIO_LEVELDETECT0);
			old1 = __raw_readl(bank->base +
						OMAP4_GPIO_LEVELDETECT1);
			__raw_writel(old0 | l, bank->base +
						OMAP4_GPIO_LEVELDETECT0);
			__raw_writel(old1 | l, bank->base +
						OMAP4_GPIO_LEVELDETECT1);
			__raw_writel(old0, bank->base +
						OMAP4_GPIO_LEVELDETECT0);
			__raw_writel(old1, bank->base +
						OMAP4_GPIO_LEVELDETECT1);
2076
#endif
2077 2078 2079 2080 2081
		}
	}

}

2082 2083
#endif

2084 2085
/*
 * This may get called early from board specific init
2086
 * for boards that have interrupts routed via FPGA.
2087
 */
2088
int __init omap_gpio_init(void)
2089 2090 2091 2092 2093 2094 2095
{
	if (!initialized)
		return _omap_gpio_init();
	else
		return 0;
}

2096 2097 2098 2099 2100 2101 2102
static int __init omap_gpio_sysinit(void)
{
	int ret = 0;

	if (!initialized)
		ret = _omap_gpio_init();

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2103 2104
	mpuio_init();

2105 2106
#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
		defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
2107
	if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119
		if (ret == 0) {
			ret = sysdev_class_register(&omap_gpio_sysclass);
			if (ret == 0)
				ret = sysdev_register(&omap_gpio_device);
		}
	}
#endif

	return ret;
}

arch_initcall(omap_gpio_sysinit);
2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135


#ifdef	CONFIG_DEBUG_FS

#include <linux/debugfs.h>
#include <linux/seq_file.h>

static int dbg_gpio_show(struct seq_file *s, void *unused)
{
	unsigned	i, j, gpio;

	for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
		struct gpio_bank	*bank = gpio_bank + i;
		unsigned		bankwidth = 16;
		u32			mask = 1;

2136
		if (bank_is_mpuio(bank))
2137
			gpio = OMAP_MPUIO(0);
2138 2139
		else if (cpu_class_is_omap2() || cpu_is_omap730() ||
				cpu_is_omap850())
2140 2141 2142 2143
			bankwidth = 32;

		for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
			unsigned	irq, value, is_in, irqstat;
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2144
			const char	*label;
2145

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2146 2147
			label = gpiochip_is_requested(&bank->chip, j);
			if (!label)
2148 2149 2150
				continue;

			irq = bank->virtual_irq_start + j;
2151
			value = gpio_get_value(gpio);
2152 2153
			is_in = gpio_is_input(bank, mask);

2154
			if (bank_is_mpuio(bank))
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2155
				seq_printf(s, "MPUIO %2d ", j);
2156
			else
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2157
				seq_printf(s, "GPIO %3d ", gpio);
2158
			seq_printf(s, "(%-20.20s): %s %s",
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2159
					label,
2160 2161 2162
					is_in ? "in " : "out",
					value ? "hi"  : "lo");

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2163 2164
/* FIXME for at least omap2, show pullup/pulldown state */

2165
			irqstat = irq_desc[irq].status;
2166
#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) ||	\
2167
		defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188
			if (is_in && ((bank->suspend_wakeup & mask)
					|| irqstat & IRQ_TYPE_SENSE_MASK)) {
				char	*trigger = NULL;

				switch (irqstat & IRQ_TYPE_SENSE_MASK) {
				case IRQ_TYPE_EDGE_FALLING:
					trigger = "falling";
					break;
				case IRQ_TYPE_EDGE_RISING:
					trigger = "rising";
					break;
				case IRQ_TYPE_EDGE_BOTH:
					trigger = "bothedge";
					break;
				case IRQ_TYPE_LEVEL_LOW:
					trigger = "low";
					break;
				case IRQ_TYPE_LEVEL_HIGH:
					trigger = "high";
					break;
				case IRQ_TYPE_NONE:
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2189
					trigger = "(?)";
2190 2191
					break;
				}
D
David Brownell 已提交
2192
				seq_printf(s, ", irq-%d %-8s%s",
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						irq, trigger,
						(bank->suspend_wakeup & mask)
							? " wakeup" : "");
			}
2197
#endif
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			seq_printf(s, "\n");
		}

2201
		if (bank_is_mpuio(bank)) {
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			seq_printf(s, "\n");
			gpio = 0;
		}
	}
	return 0;
}

static int dbg_gpio_open(struct inode *inode, struct file *file)
{
2211
	return single_open(file, dbg_gpio_show, &inode->i_private);
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}

static const struct file_operations debug_fops = {
	.open		= dbg_gpio_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= single_release,
};

static int __init omap_gpio_debuginit(void)
{
2223 2224
	(void) debugfs_create_file("omap_gpio", S_IRUGO,
					NULL, NULL, &debug_fops);
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	return 0;
}
late_initcall(omap_gpio_debuginit);
#endif