imx-dma.c 34.5 KB
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/*
 * drivers/dma/imx-dma.c
 *
 * This file contains a driver for the Freescale i.MX DMA engine
 * found on i.MX1/21/27
 *
 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
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 * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
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 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */
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#include <linux/err.h>
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#include <linux/init.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/dmaengine.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
#include <linux/of_dma.h>
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#include <asm/irq.h>
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#include <linux/platform_data/dma-imx.h>
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#include "dmaengine.h"
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#define IMXDMA_MAX_CHAN_DESCRIPTORS	16
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#define IMX_DMA_CHANNELS  16

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#define IMX_DMA_2D_SLOTS	2
#define IMX_DMA_2D_SLOT_A	0
#define IMX_DMA_2D_SLOT_B	1

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#define IMX_DMA_LENGTH_LOOP	((unsigned int)-1)
#define IMX_DMA_MEMSIZE_32	(0 << 4)
#define IMX_DMA_MEMSIZE_8	(1 << 4)
#define IMX_DMA_MEMSIZE_16	(2 << 4)
#define IMX_DMA_TYPE_LINEAR	(0 << 10)
#define IMX_DMA_TYPE_2D		(1 << 10)
#define IMX_DMA_TYPE_FIFO	(2 << 10)

#define IMX_DMA_ERR_BURST     (1 << 0)
#define IMX_DMA_ERR_REQUEST   (1 << 1)
#define IMX_DMA_ERR_TRANSFER  (1 << 2)
#define IMX_DMA_ERR_BUFFER    (1 << 3)
#define IMX_DMA_ERR_TIMEOUT   (1 << 4)

#define DMA_DCR     0x00		/* Control Register */
#define DMA_DISR    0x04		/* Interrupt status Register */
#define DMA_DIMR    0x08		/* Interrupt mask Register */
#define DMA_DBTOSR  0x0c		/* Burst timeout status Register */
#define DMA_DRTOSR  0x10		/* Request timeout Register */
#define DMA_DSESR   0x14		/* Transfer Error Status Register */
#define DMA_DBOSR   0x18		/* Buffer overflow status Register */
#define DMA_DBTOCR  0x1c		/* Burst timeout control Register */
#define DMA_WSRA    0x40		/* W-Size Register A */
#define DMA_XSRA    0x44		/* X-Size Register A */
#define DMA_YSRA    0x48		/* Y-Size Register A */
#define DMA_WSRB    0x4c		/* W-Size Register B */
#define DMA_XSRB    0x50		/* X-Size Register B */
#define DMA_YSRB    0x54		/* Y-Size Register B */
#define DMA_SAR(x)  (0x80 + ((x) << 6))	/* Source Address Registers */
#define DMA_DAR(x)  (0x84 + ((x) << 6))	/* Destination Address Registers */
#define DMA_CNTR(x) (0x88 + ((x) << 6))	/* Count Registers */
#define DMA_CCR(x)  (0x8c + ((x) << 6))	/* Control Registers */
#define DMA_RSSR(x) (0x90 + ((x) << 6))	/* Request source select Registers */
#define DMA_BLR(x)  (0x94 + ((x) << 6))	/* Burst length Registers */
#define DMA_RTOR(x) (0x98 + ((x) << 6))	/* Request timeout Registers */
#define DMA_BUCR(x) (0x98 + ((x) << 6))	/* Bus Utilization Registers */
#define DMA_CCNR(x) (0x9C + ((x) << 6))	/* Channel counter Registers */

#define DCR_DRST           (1<<1)
#define DCR_DEN            (1<<0)
#define DBTOCR_EN          (1<<15)
#define DBTOCR_CNT(x)      ((x) & 0x7fff)
#define CNTR_CNT(x)        ((x) & 0xffffff)
#define CCR_ACRPT          (1<<14)
#define CCR_DMOD_LINEAR    (0x0 << 12)
#define CCR_DMOD_2D        (0x1 << 12)
#define CCR_DMOD_FIFO      (0x2 << 12)
#define CCR_DMOD_EOBFIFO   (0x3 << 12)
#define CCR_SMOD_LINEAR    (0x0 << 10)
#define CCR_SMOD_2D        (0x1 << 10)
#define CCR_SMOD_FIFO      (0x2 << 10)
#define CCR_SMOD_EOBFIFO   (0x3 << 10)
#define CCR_MDIR_DEC       (1<<9)
#define CCR_MSEL_B         (1<<8)
#define CCR_DSIZ_32        (0x0 << 6)
#define CCR_DSIZ_8         (0x1 << 6)
#define CCR_DSIZ_16        (0x2 << 6)
#define CCR_SSIZ_32        (0x0 << 4)
#define CCR_SSIZ_8         (0x1 << 4)
#define CCR_SSIZ_16        (0x2 << 4)
#define CCR_REN            (1<<3)
#define CCR_RPT            (1<<2)
#define CCR_FRC            (1<<1)
#define CCR_CEN            (1<<0)
#define RTOR_EN            (1<<15)
#define RTOR_CLK           (1<<14)
#define RTOR_PSC           (1<<13)
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enum  imxdma_prep_type {
	IMXDMA_DESC_MEMCPY,
	IMXDMA_DESC_INTERLEAVED,
	IMXDMA_DESC_SLAVE_SG,
	IMXDMA_DESC_CYCLIC,
};

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struct imx_dma_2d_config {
	u16		xsr;
	u16		ysr;
	u16		wsr;
	int		count;
};

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struct imxdma_desc {
	struct list_head		node;
	struct dma_async_tx_descriptor	desc;
	enum dma_status			status;
	dma_addr_t			src;
	dma_addr_t			dest;
	size_t				len;
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	enum dma_transfer_direction	direction;
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	enum imxdma_prep_type		type;
	/* For memcpy and interleaved */
	unsigned int			config_port;
	unsigned int			config_mem;
	/* For interleaved transfers */
	unsigned int			x;
	unsigned int			y;
	unsigned int			w;
	/* For slave sg and cyclic */
	struct scatterlist		*sg;
	unsigned int			sgcount;
};

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struct imxdma_channel {
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	int				hw_chaining;
	struct timer_list		watchdog;
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	struct imxdma_engine		*imxdma;
	unsigned int			channel;

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	struct tasklet_struct		dma_tasklet;
	struct list_head		ld_free;
	struct list_head		ld_queue;
	struct list_head		ld_active;
	int				descs_allocated;
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	enum dma_slave_buswidth		word_size;
	dma_addr_t			per_address;
	u32				watermark_level;
	struct dma_chan			chan;
	struct dma_async_tx_descriptor	desc;
	enum dma_status			status;
	int				dma_request;
	struct scatterlist		*sg_list;
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	u32				ccr_from_device;
	u32				ccr_to_device;
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	bool				enabled_2d;
	int				slot_2d;
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	unsigned int			irq;
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};

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enum imx_dma_type {
	IMX1_DMA,
	IMX21_DMA,
	IMX27_DMA,
};

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struct imxdma_engine {
	struct device			*dev;
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	struct device_dma_parameters	dma_parms;
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	struct dma_device		dma_device;
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	void __iomem			*base;
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	struct clk			*dma_ahb;
	struct clk			*dma_ipg;
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	spinlock_t			lock;
	struct imx_dma_2d_config	slots_2d[IMX_DMA_2D_SLOTS];
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	struct imxdma_channel		channel[IMX_DMA_CHANNELS];
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	enum imx_dma_type		devtype;
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	unsigned int			irq;
	unsigned int			irq_err;

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};

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struct imxdma_filter_data {
	struct imxdma_engine	*imxdma;
	int			 request;
};

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static const struct platform_device_id imx_dma_devtype[] = {
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	{
		.name = "imx1-dma",
		.driver_data = IMX1_DMA,
	}, {
		.name = "imx21-dma",
		.driver_data = IMX21_DMA,
	}, {
		.name = "imx27-dma",
		.driver_data = IMX27_DMA,
	}, {
		/* sentinel */
	}
};
MODULE_DEVICE_TABLE(platform, imx_dma_devtype);

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static const struct of_device_id imx_dma_of_dev_id[] = {
	{
		.compatible = "fsl,imx1-dma",
		.data = &imx_dma_devtype[IMX1_DMA],
	}, {
		.compatible = "fsl,imx21-dma",
		.data = &imx_dma_devtype[IMX21_DMA],
	}, {
		.compatible = "fsl,imx27-dma",
		.data = &imx_dma_devtype[IMX27_DMA],
	}, {
		/* sentinel */
	}
};
MODULE_DEVICE_TABLE(of, imx_dma_of_dev_id);

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static inline int is_imx1_dma(struct imxdma_engine *imxdma)
{
	return imxdma->devtype == IMX1_DMA;
}

static inline int is_imx27_dma(struct imxdma_engine *imxdma)
{
	return imxdma->devtype == IMX27_DMA;
}

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static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
{
	return container_of(chan, struct imxdma_channel, chan);
}

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static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
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{
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	struct imxdma_desc *desc;

	if (!list_empty(&imxdmac->ld_active)) {
		desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc,
					node);
		if (desc->type == IMXDMA_DESC_CYCLIC)
			return true;
	}
	return false;
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}

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static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val,
			     unsigned offset)
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{
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	__raw_writel(val, imxdma->base + offset);
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}

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static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset)
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{
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	return __raw_readl(imxdma->base + offset);
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}
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static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
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{
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	struct imxdma_engine *imxdma = imxdmac->imxdma;

	if (is_imx27_dma(imxdma))
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		return imxdmac->hw_chaining;
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	else
		return 0;
}

/*
 * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
 */
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static inline int imxdma_sg_next(struct imxdma_desc *d)
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{
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	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
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	struct imxdma_engine *imxdma = imxdmac->imxdma;
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	struct scatterlist *sg = d->sg;
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	unsigned long now;

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	now = min(d->len, sg_dma_len(sg));
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	if (d->len != IMX_DMA_LENGTH_LOOP)
		d->len -= now;
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	if (d->direction == DMA_DEV_TO_MEM)
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		imx_dmav1_writel(imxdma, sg->dma_address,
				 DMA_DAR(imxdmac->channel));
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	else
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		imx_dmav1_writel(imxdma, sg->dma_address,
				 DMA_SAR(imxdmac->channel));
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	imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
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	dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, "
		"size 0x%08x\n", __func__, imxdmac->channel,
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		 imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
		 imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
		 imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
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	return now;
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}

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static void imxdma_enable_hw(struct imxdma_desc *d)
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{
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	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
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	struct imxdma_engine *imxdma = imxdmac->imxdma;
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	int channel = imxdmac->channel;
	unsigned long flags;

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	dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
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	local_irq_save(flags);

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	imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) &
			 ~(1 << channel), DMA_DIMR);
	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) |
			 CCR_CEN | CCR_ACRPT, DMA_CCR(channel));
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	if (!is_imx1_dma(imxdma) &&
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			d->sg && imxdma_hw_chain(imxdmac)) {
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		d->sg = sg_next(d->sg);
		if (d->sg) {
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			u32 tmp;
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			imxdma_sg_next(d);
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			tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel));
			imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT,
					 DMA_CCR(channel));
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		}
	}

	local_irq_restore(flags);
}

static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
{
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	struct imxdma_engine *imxdma = imxdmac->imxdma;
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	int channel = imxdmac->channel;
	unsigned long flags;

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	dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
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	if (imxdma_hw_chain(imxdmac))
		del_timer(&imxdmac->watchdog);
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	local_irq_save(flags);
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	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) |
			 (1 << channel), DMA_DIMR);
	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) &
			 ~CCR_CEN, DMA_CCR(channel));
	imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
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	local_irq_restore(flags);
}

static void imxdma_watchdog(unsigned long data)
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{
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	struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
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	struct imxdma_engine *imxdma = imxdmac->imxdma;
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	int channel = imxdmac->channel;
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	imx_dmav1_writel(imxdma, 0, DMA_CCR(channel));
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	/* Tasklet watchdog error handler */
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	tasklet_schedule(&imxdmac->dma_tasklet);
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	dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n",
		imxdmac->channel);
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}

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static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
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{
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	struct imxdma_engine *imxdma = dev_id;
	unsigned int err_mask;
	int i, disr;
	int errcode;

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	disr = imx_dmav1_readl(imxdma, DMA_DISR);
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	err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) |
		   imx_dmav1_readl(imxdma, DMA_DRTOSR) |
		   imx_dmav1_readl(imxdma, DMA_DSESR)  |
		   imx_dmav1_readl(imxdma, DMA_DBOSR);
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	if (!err_mask)
		return IRQ_HANDLED;

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	imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR);
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	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
		if (!(err_mask & (1 << i)))
			continue;
		errcode = 0;

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		if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) {
			imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR);
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			errcode |= IMX_DMA_ERR_BURST;
		}
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		if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) {
			imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR);
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			errcode |= IMX_DMA_ERR_REQUEST;
		}
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		if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) {
			imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR);
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			errcode |= IMX_DMA_ERR_TRANSFER;
		}
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		if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) {
			imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR);
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			errcode |= IMX_DMA_ERR_BUFFER;
		}
		/* Tasklet error handler */
		tasklet_schedule(&imxdma->channel[i].dma_tasklet);

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		dev_warn(imxdma->dev,
			 "DMA timeout on channel %d -%s%s%s%s\n", i,
			 errcode & IMX_DMA_ERR_BURST ?    " burst" : "",
			 errcode & IMX_DMA_ERR_REQUEST ?  " request" : "",
			 errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
			 errcode & IMX_DMA_ERR_BUFFER ?   " buffer" : "");
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	}
	return IRQ_HANDLED;
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}

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static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
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{
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	struct imxdma_engine *imxdma = imxdmac->imxdma;
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	int chno = imxdmac->channel;
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	struct imxdma_desc *desc;
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	unsigned long flags;
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	spin_lock_irqsave(&imxdma->lock, flags);
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	if (list_empty(&imxdmac->ld_active)) {
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		spin_unlock_irqrestore(&imxdma->lock, flags);
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		goto out;
	}
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	desc = list_first_entry(&imxdmac->ld_active,
				struct imxdma_desc,
				node);
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	spin_unlock_irqrestore(&imxdma->lock, flags);
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	if (desc->sg) {
		u32 tmp;
		desc->sg = sg_next(desc->sg);
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		if (desc->sg) {
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			imxdma_sg_next(desc);
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			tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno));
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			if (imxdma_hw_chain(imxdmac)) {
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				/* FIXME: The timeout should probably be
				 * configurable
				 */
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				mod_timer(&imxdmac->watchdog,
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					jiffies + msecs_to_jiffies(500));

				tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
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				imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
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			} else {
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				imx_dmav1_writel(imxdma, tmp & ~CCR_CEN,
						 DMA_CCR(chno));
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				tmp |= CCR_CEN;
			}

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			imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
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			if (imxdma_chan_is_doing_cyclic(imxdmac))
				/* Tasklet progression */
				tasklet_schedule(&imxdmac->dma_tasklet);
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			return;
		}

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		if (imxdma_hw_chain(imxdmac)) {
			del_timer(&imxdmac->watchdog);
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			return;
		}
	}

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out:
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	imx_dmav1_writel(imxdma, 0, DMA_CCR(chno));
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	/* Tasklet irq */
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	tasklet_schedule(&imxdmac->dma_tasklet);
}

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static irqreturn_t dma_irq_handler(int irq, void *dev_id)
{
	struct imxdma_engine *imxdma = dev_id;
	int i, disr;

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	if (!is_imx1_dma(imxdma))
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		imxdma_err_handler(irq, dev_id);

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	disr = imx_dmav1_readl(imxdma, DMA_DISR);
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	dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr);
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	imx_dmav1_writel(imxdma, disr, DMA_DISR);
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	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
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		if (disr & (1 << i))
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			dma_irq_handle_channel(&imxdma->channel[i]);
	}

	return IRQ_HANDLED;
}

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static int imxdma_xfer_desc(struct imxdma_desc *d)
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
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	struct imxdma_engine *imxdma = imxdmac->imxdma;
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	int slot = -1;
	int i;
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	/* Configure and enable */
	switch (d->type) {
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	case IMXDMA_DESC_INTERLEAVED:
		/* Try to get a free 2D slot */
		for (i = 0; i < IMX_DMA_2D_SLOTS; i++) {
			if ((imxdma->slots_2d[i].count > 0) &&
			((imxdma->slots_2d[i].xsr != d->x) ||
			(imxdma->slots_2d[i].ysr != d->y) ||
			(imxdma->slots_2d[i].wsr != d->w)))
				continue;
			slot = i;
			break;
		}
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		if (slot < 0)
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			return -EBUSY;

		imxdma->slots_2d[slot].xsr = d->x;
		imxdma->slots_2d[slot].ysr = d->y;
		imxdma->slots_2d[slot].wsr = d->w;
		imxdma->slots_2d[slot].count++;

		imxdmac->slot_2d = slot;
		imxdmac->enabled_2d = true;

		if (slot == IMX_DMA_2D_SLOT_A) {
			d->config_mem &= ~CCR_MSEL_B;
			d->config_port &= ~CCR_MSEL_B;
			imx_dmav1_writel(imxdma, d->x, DMA_XSRA);
			imx_dmav1_writel(imxdma, d->y, DMA_YSRA);
			imx_dmav1_writel(imxdma, d->w, DMA_WSRA);
		} else {
			d->config_mem |= CCR_MSEL_B;
			d->config_port |= CCR_MSEL_B;
			imx_dmav1_writel(imxdma, d->x, DMA_XSRB);
			imx_dmav1_writel(imxdma, d->y, DMA_YSRB);
			imx_dmav1_writel(imxdma, d->w, DMA_WSRB);
		}
		/*
		 * We fall-through here intentionally, since a 2D transfer is
		 * similar to MEMCPY just adding the 2D slot configuration.
		 */
566
	case IMXDMA_DESC_MEMCPY:
567 568 569
		imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
		imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
		imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2),
570
			 DMA_CCR(imxdmac->channel));
571

572
		imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel));
573

574 575 576 577 578
		dev_dbg(imxdma->dev,
			"%s channel: %d dest=0x%08llx src=0x%08llx dma_length=%zu\n",
			__func__, imxdmac->channel,
			(unsigned long long)d->dest,
			(unsigned long long)d->src, d->len);
579 580

		break;
581
	/* Cyclic transfer is the same as slave_sg with special sg configuration. */
582 583
	case IMXDMA_DESC_CYCLIC:
	case IMXDMA_DESC_SLAVE_SG:
584
		if (d->direction == DMA_DEV_TO_MEM) {
585
			imx_dmav1_writel(imxdma, imxdmac->per_address,
586
					 DMA_SAR(imxdmac->channel));
587
			imx_dmav1_writel(imxdma, imxdmac->ccr_from_device,
588 589
					 DMA_CCR(imxdmac->channel));

590 591 592 593 594
			dev_dbg(imxdma->dev,
				"%s channel: %d sg=%p sgcount=%d total length=%zu dev_addr=0x%08llx (dev2mem)\n",
				__func__, imxdmac->channel,
				d->sg, d->sgcount, d->len,
				(unsigned long long)imxdmac->per_address);
595
		} else if (d->direction == DMA_MEM_TO_DEV) {
596
			imx_dmav1_writel(imxdma, imxdmac->per_address,
597
					 DMA_DAR(imxdmac->channel));
598
			imx_dmav1_writel(imxdma, imxdmac->ccr_to_device,
599 600
					 DMA_CCR(imxdmac->channel));

601 602 603 604 605
			dev_dbg(imxdma->dev,
				"%s channel: %d sg=%p sgcount=%d total length=%zu dev_addr=0x%08llx (mem2dev)\n",
				__func__, imxdmac->channel,
				d->sg, d->sgcount, d->len,
				(unsigned long long)imxdmac->per_address);
606 607 608 609 610 611
		} else {
			dev_err(imxdma->dev, "%s channel: %d bad dma mode\n",
				__func__, imxdmac->channel);
			return -EINVAL;
		}

612
		imxdma_sg_next(d);
613

614 615 616 617
		break;
	default:
		return -EINVAL;
	}
618
	imxdma_enable_hw(d);
619
	return 0;
620 621
}

622
static void imxdma_tasklet(unsigned long data)
623
{
624 625 626
	struct imxdma_channel *imxdmac = (void *)data;
	struct imxdma_engine *imxdma = imxdmac->imxdma;
	struct imxdma_desc *desc;
627
	unsigned long flags;
628

629
	spin_lock_irqsave(&imxdma->lock, flags);
630 631 632

	if (list_empty(&imxdmac->ld_active)) {
		/* Someone might have called terminate all */
633 634
		spin_unlock_irqrestore(&imxdma->lock, flags);
		return;
635 636 637
	}
	desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node);

M
Masanari Iida 已提交
638 639
	/* If we are dealing with a cyclic descriptor, keep it on ld_active
	 * and dont mark the descriptor as complete.
640 641
	 * Only in non-cyclic cases it would be marked as complete
	 */
642 643
	if (imxdma_chan_is_doing_cyclic(imxdmac))
		goto out;
644 645
	else
		dma_cookie_complete(&desc->desc);
646

647 648 649 650 651 652
	/* Free 2D slot if it was an interleaved transfer */
	if (imxdmac->enabled_2d) {
		imxdma->slots_2d[imxdmac->slot_2d].count--;
		imxdmac->enabled_2d = false;
	}

653 654 655 656 657 658 659 660 661 662 663
	list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);

	if (!list_empty(&imxdmac->ld_queue)) {
		desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc,
					node);
		list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active);
		if (imxdma_xfer_desc(desc) < 0)
			dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n",
				 __func__, imxdmac->channel);
	}
out:
664
	spin_unlock_irqrestore(&imxdma->lock, flags);
665

666
	dmaengine_desc_get_callback_invoke(&desc->desc, NULL);
667 668
}

669
static int imxdma_terminate_all(struct dma_chan *chan)
670 671
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
672
	struct imxdma_engine *imxdma = imxdmac->imxdma;
673 674
	unsigned long flags;

675
	imxdma_disable_hw(imxdmac);
676

677 678 679 680 681 682
	spin_lock_irqsave(&imxdma->lock, flags);
	list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
	list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
	spin_unlock_irqrestore(&imxdma->lock, flags);
	return 0;
}
683

684 685 686 687 688 689
static int imxdma_config(struct dma_chan *chan,
			 struct dma_slave_config *dmaengine_cfg)
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	struct imxdma_engine *imxdma = imxdmac->imxdma;
	unsigned int mode = 0;
690

691 692 693 694 695 696 697 698 699
	if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
		imxdmac->per_address = dmaengine_cfg->src_addr;
		imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
		imxdmac->word_size = dmaengine_cfg->src_addr_width;
	} else {
		imxdmac->per_address = dmaengine_cfg->dst_addr;
		imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
		imxdmac->word_size = dmaengine_cfg->dst_addr_width;
	}
700

701 702 703 704 705 706 707
	switch (imxdmac->word_size) {
	case DMA_SLAVE_BUSWIDTH_1_BYTE:
		mode = IMX_DMA_MEMSIZE_8;
		break;
	case DMA_SLAVE_BUSWIDTH_2_BYTES:
		mode = IMX_DMA_MEMSIZE_16;
		break;
708
	default:
709 710 711
	case DMA_SLAVE_BUSWIDTH_4_BYTES:
		mode = IMX_DMA_MEMSIZE_32;
		break;
712 713
	}

714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729
	imxdmac->hw_chaining = 0;

	imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
		((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
		CCR_REN;
	imxdmac->ccr_to_device =
		(IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
		((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
	imx_dmav1_writel(imxdma, imxdmac->dma_request,
			 DMA_RSSR(imxdmac->channel));

	/* Set burst length */
	imx_dmav1_writel(imxdma, imxdmac->watermark_level *
			 imxdmac->word_size, DMA_BLR(imxdmac->channel));

	return 0;
730 731 732 733 734 735
}

static enum dma_status imxdma_tx_status(struct dma_chan *chan,
					    dma_cookie_t cookie,
					    struct dma_tx_state *txstate)
{
736
	return dma_cookie_status(chan, cookie, txstate);
737 738 739 740 741
}

static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
742
	struct imxdma_engine *imxdma = imxdmac->imxdma;
743
	dma_cookie_t cookie;
744
	unsigned long flags;
745

746
	spin_lock_irqsave(&imxdma->lock, flags);
747
	list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue);
748
	cookie = dma_cookie_assign(tx);
749
	spin_unlock_irqrestore(&imxdma->lock, flags);
750 751 752 753 754 755 756 757 758

	return cookie;
}

static int imxdma_alloc_chan_resources(struct dma_chan *chan)
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	struct imx_dma_data *data = chan->private;

759 760
	if (data != NULL)
		imxdmac->dma_request = data->dma_request;
761

762 763
	while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) {
		struct imxdma_desc *desc;
764

765 766 767 768 769 770 771 772
		desc = kzalloc(sizeof(*desc), GFP_KERNEL);
		if (!desc)
			break;
		__memzero(&desc->desc, sizeof(struct dma_async_tx_descriptor));
		dma_async_tx_descriptor_init(&desc->desc, chan);
		desc->desc.tx_submit = imxdma_tx_submit;
		/* txd.flags will be overwritten in prep funcs */
		desc->desc.flags = DMA_CTRL_ACK;
773
		desc->status = DMA_COMPLETE;
774 775 776 777

		list_add_tail(&desc->node, &imxdmac->ld_free);
		imxdmac->descs_allocated++;
	}
778

779 780 781 782
	if (!imxdmac->descs_allocated)
		return -ENOMEM;

	return imxdmac->descs_allocated;
783 784 785 786 787
}

static void imxdma_free_chan_resources(struct dma_chan *chan)
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
788
	struct imxdma_engine *imxdma = imxdmac->imxdma;
789 790 791
	struct imxdma_desc *desc, *_desc;
	unsigned long flags;

792
	spin_lock_irqsave(&imxdma->lock, flags);
793

794
	imxdma_disable_hw(imxdmac);
795 796
	list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
	list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
797

798
	spin_unlock_irqrestore(&imxdma->lock, flags);
799 800 801 802 803 804

	list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) {
		kfree(desc);
		imxdmac->descs_allocated--;
	}
	INIT_LIST_HEAD(&imxdmac->ld_free);
805

806 807
	kfree(imxdmac->sg_list);
	imxdmac->sg_list = NULL;
808 809 810 811
}

static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
		struct dma_chan *chan, struct scatterlist *sgl,
812
		unsigned int sg_len, enum dma_transfer_direction direction,
813
		unsigned long flags, void *context)
814 815 816
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	struct scatterlist *sg;
817 818
	int i, dma_length = 0;
	struct imxdma_desc *desc;
819

820 821
	if (list_empty(&imxdmac->ld_free) ||
	    imxdma_chan_is_doing_cyclic(imxdmac))
822 823
		return NULL;

824
	desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
825 826

	for_each_sg(sgl, sg, sg_len, i) {
827
		dma_length += sg_dma_len(sg);
828 829
	}

830 831
	switch (imxdmac->word_size) {
	case DMA_SLAVE_BUSWIDTH_4_BYTES:
832
		if (sg_dma_len(sgl) & 3 || sgl->dma_address & 3)
833 834 835
			return NULL;
		break;
	case DMA_SLAVE_BUSWIDTH_2_BYTES:
836
		if (sg_dma_len(sgl) & 1 || sgl->dma_address & 1)
837 838 839 840 841 842 843 844
			return NULL;
		break;
	case DMA_SLAVE_BUSWIDTH_1_BYTE:
		break;
	default:
		return NULL;
	}

845 846 847 848
	desc->type = IMXDMA_DESC_SLAVE_SG;
	desc->sg = sgl;
	desc->sgcount = sg_len;
	desc->len = dma_length;
849
	desc->direction = direction;
850 851 852 853 854 855 856
	if (direction == DMA_DEV_TO_MEM) {
		desc->src = imxdmac->per_address;
	} else {
		desc->dest = imxdmac->per_address;
	}
	desc->desc.callback = NULL;
	desc->desc.callback_param = NULL;
857

858
	return &desc->desc;
859 860 861 862
}

static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
		struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
863
		size_t period_len, enum dma_transfer_direction direction,
864
		unsigned long flags)
865 866 867
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	struct imxdma_engine *imxdma = imxdmac->imxdma;
868 869
	struct imxdma_desc *desc;
	int i;
870 871
	unsigned int periods = buf_len / period_len;

872
	dev_dbg(imxdma->dev, "%s channel: %d buf_len=%zu period_len=%zu\n",
873 874
			__func__, imxdmac->channel, buf_len, period_len);

875 876
	if (list_empty(&imxdmac->ld_free) ||
	    imxdma_chan_is_doing_cyclic(imxdmac))
877 878
		return NULL;

879
	desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
880

881
	kfree(imxdmac->sg_list);
882 883

	imxdmac->sg_list = kcalloc(periods + 1,
884
			sizeof(struct scatterlist), GFP_ATOMIC);
885 886 887 888 889 890
	if (!imxdmac->sg_list)
		return NULL;

	sg_init_table(imxdmac->sg_list, periods);

	for (i = 0; i < periods; i++) {
891
		sg_assign_page(&imxdmac->sg_list[i], NULL);
892 893
		imxdmac->sg_list[i].offset = 0;
		imxdmac->sg_list[i].dma_address = dma_addr;
894
		sg_dma_len(&imxdmac->sg_list[i]) = period_len;
895 896 897 898
		dma_addr += period_len;
	}

	/* close the loop */
899
	sg_chain(imxdmac->sg_list, periods + 1, imxdmac->sg_list);
900

901 902 903 904
	desc->type = IMXDMA_DESC_CYCLIC;
	desc->sg = imxdmac->sg_list;
	desc->sgcount = periods;
	desc->len = IMX_DMA_LENGTH_LOOP;
905
	desc->direction = direction;
906 907 908 909 910 911 912
	if (direction == DMA_DEV_TO_MEM) {
		desc->src = imxdmac->per_address;
	} else {
		desc->dest = imxdmac->per_address;
	}
	desc->desc.callback = NULL;
	desc->desc.callback_param = NULL;
913

914
	return &desc->desc;
915 916
}

917 918 919 920 921 922
static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
	struct dma_chan *chan, dma_addr_t dest,
	dma_addr_t src, size_t len, unsigned long flags)
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	struct imxdma_engine *imxdma = imxdmac->imxdma;
923
	struct imxdma_desc *desc;
924

925 926 927
	dev_dbg(imxdma->dev, "%s channel: %d src=0x%llx dst=0x%llx len=%zu\n",
		__func__, imxdmac->channel, (unsigned long long)src,
		(unsigned long long)dest, len);
928

929 930
	if (list_empty(&imxdmac->ld_free) ||
	    imxdma_chan_is_doing_cyclic(imxdmac))
931 932
		return NULL;

933
	desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
934

935 936 937 938
	desc->type = IMXDMA_DESC_MEMCPY;
	desc->src = src;
	desc->dest = dest;
	desc->len = len;
939
	desc->direction = DMA_MEM_TO_MEM;
940 941 942 943
	desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
	desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
	desc->desc.callback = NULL;
	desc->desc.callback_param = NULL;
944

945
	return &desc->desc;
946 947
}

948 949 950 951 952 953 954 955
static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved(
	struct dma_chan *chan, struct dma_interleaved_template *xt,
	unsigned long flags)
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	struct imxdma_engine *imxdma = imxdmac->imxdma;
	struct imxdma_desc *desc;

956 957 958 959
	dev_dbg(imxdma->dev, "%s channel: %d src_start=0x%llx dst_start=0x%llx\n"
		"   src_sgl=%s dst_sgl=%s numf=%zu frame_size=%zu\n", __func__,
		imxdmac->channel, (unsigned long long)xt->src_start,
		(unsigned long long) xt->dst_start,
960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989
		xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false",
		xt->numf, xt->frame_size);

	if (list_empty(&imxdmac->ld_free) ||
	    imxdma_chan_is_doing_cyclic(imxdmac))
		return NULL;

	if (xt->frame_size != 1 || xt->numf <= 0 || xt->dir != DMA_MEM_TO_MEM)
		return NULL;

	desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);

	desc->type = IMXDMA_DESC_INTERLEAVED;
	desc->src = xt->src_start;
	desc->dest = xt->dst_start;
	desc->x = xt->sgl[0].size;
	desc->y = xt->numf;
	desc->w = xt->sgl[0].icg + desc->x;
	desc->len = desc->x * desc->y;
	desc->direction = DMA_MEM_TO_MEM;
	desc->config_port = IMX_DMA_MEMSIZE_32;
	desc->config_mem = IMX_DMA_MEMSIZE_32;
	if (xt->src_sgl)
		desc->config_mem |= IMX_DMA_TYPE_2D;
	if (xt->dst_sgl)
		desc->config_port |= IMX_DMA_TYPE_2D;
	desc->desc.callback = NULL;
	desc->desc.callback_param = NULL;

	return &desc->desc;
990 991 992 993
}

static void imxdma_issue_pending(struct dma_chan *chan)
{
994
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
995 996 997 998
	struct imxdma_engine *imxdma = imxdmac->imxdma;
	struct imxdma_desc *desc;
	unsigned long flags;

999
	spin_lock_irqsave(&imxdma->lock, flags);
1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013
	if (list_empty(&imxdmac->ld_active) &&
	    !list_empty(&imxdmac->ld_queue)) {
		desc = list_first_entry(&imxdmac->ld_queue,
					struct imxdma_desc, node);

		if (imxdma_xfer_desc(desc) < 0) {
			dev_warn(imxdma->dev,
				 "%s: channel: %d couldn't issue DMA xfer\n",
				 __func__, imxdmac->channel);
		} else {
			list_move_tail(imxdmac->ld_queue.next,
				       &imxdmac->ld_active);
		}
	}
1014
	spin_unlock_irqrestore(&imxdma->lock, flags);
1015 1016
}

1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048
static bool imxdma_filter_fn(struct dma_chan *chan, void *param)
{
	struct imxdma_filter_data *fdata = param;
	struct imxdma_channel *imxdma_chan = to_imxdma_chan(chan);

	if (chan->device->dev != fdata->imxdma->dev)
		return false;

	imxdma_chan->dma_request = fdata->request;
	chan->private = NULL;

	return true;
}

static struct dma_chan *imxdma_xlate(struct of_phandle_args *dma_spec,
						struct of_dma *ofdma)
{
	int count = dma_spec->args_count;
	struct imxdma_engine *imxdma = ofdma->of_dma_data;
	struct imxdma_filter_data fdata = {
		.imxdma = imxdma,
	};

	if (count != 1)
		return NULL;

	fdata.request = dma_spec->args[0];

	return dma_request_channel(imxdma->dma_device.cap_mask,
					imxdma_filter_fn, &fdata);
}

1049
static int __init imxdma_probe(struct platform_device *pdev)
1050
{
1051
	struct imxdma_engine *imxdma;
1052
	struct resource *res;
1053
	const struct of_device_id *of_id;
1054
	int ret, i;
1055
	int irq, irq_err;
1056

1057 1058 1059 1060
	of_id = of_match_device(imx_dma_of_dev_id, &pdev->dev);
	if (of_id)
		pdev->id_entry = of_id->data;

1061
	imxdma = devm_kzalloc(&pdev->dev, sizeof(*imxdma), GFP_KERNEL);
1062 1063 1064
	if (!imxdma)
		return -ENOMEM;

1065
	imxdma->dev = &pdev->dev;
1066 1067
	imxdma->devtype = pdev->id_entry->driver_data;

1068
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1069 1070 1071
	imxdma->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(imxdma->base))
		return PTR_ERR(imxdma->base);
1072 1073 1074 1075

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;
1076

1077
	imxdma->dma_ipg = devm_clk_get(&pdev->dev, "ipg");
1078 1079
	if (IS_ERR(imxdma->dma_ipg))
		return PTR_ERR(imxdma->dma_ipg);
1080 1081

	imxdma->dma_ahb = devm_clk_get(&pdev->dev, "ahb");
1082 1083
	if (IS_ERR(imxdma->dma_ahb))
		return PTR_ERR(imxdma->dma_ahb);
1084

1085 1086 1087 1088 1089 1090
	ret = clk_prepare_enable(imxdma->dma_ipg);
	if (ret)
		return ret;
	ret = clk_prepare_enable(imxdma->dma_ahb);
	if (ret)
		goto disable_dma_ipg_clk;
1091 1092

	/* reset DMA module */
1093
	imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR);
1094

1095
	if (is_imx1_dma(imxdma)) {
1096
		ret = devm_request_irq(&pdev->dev, irq,
1097
				       dma_irq_handler, 0, "DMA", imxdma);
1098
		if (ret) {
1099
			dev_warn(imxdma->dev, "Can't register IRQ for DMA\n");
1100
			goto disable_dma_ahb_clk;
1101
		}
1102
		imxdma->irq = irq;
1103

1104 1105 1106
		irq_err = platform_get_irq(pdev, 1);
		if (irq_err < 0) {
			ret = irq_err;
1107
			goto disable_dma_ahb_clk;
1108 1109 1110
		}

		ret = devm_request_irq(&pdev->dev, irq_err,
1111
				       imxdma_err_handler, 0, "DMA", imxdma);
1112
		if (ret) {
1113
			dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n");
1114
			goto disable_dma_ahb_clk;
1115
		}
1116
		imxdma->irq_err = irq_err;
1117 1118 1119
	}

	/* enable DMA module */
1120
	imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR);
1121 1122

	/* clear all interrupts */
1123
	imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
1124 1125

	/* disable interrupts */
1126
	imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
1127 1128 1129

	INIT_LIST_HEAD(&imxdma->dma_device.channels);

1130 1131
	dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
	dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
1132
	dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
1133 1134 1135 1136 1137 1138 1139
	dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask);

	/* Initialize 2D global parameters */
	for (i = 0; i < IMX_DMA_2D_SLOTS; i++)
		imxdma->slots_2d[i].count = 0;

	spin_lock_init(&imxdma->lock);
1140

1141
	/* Initialize channel parameters */
1142
	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
1143 1144
		struct imxdma_channel *imxdmac = &imxdma->channel[i];

1145
		if (!is_imx1_dma(imxdma)) {
1146
			ret = devm_request_irq(&pdev->dev, irq + i,
1147 1148
					dma_irq_handler, 0, "DMA", imxdma);
			if (ret) {
1149 1150
				dev_warn(imxdma->dev, "Can't register IRQ %d "
					 "for DMA channel %d\n",
1151
					 irq + i, i);
1152
				goto disable_dma_ahb_clk;
1153
			}
1154 1155

			imxdmac->irq = irq + i;
1156 1157 1158
			init_timer(&imxdmac->watchdog);
			imxdmac->watchdog.function = &imxdma_watchdog;
			imxdmac->watchdog.data = (unsigned long)imxdmac;
S
Sascha Hauer 已提交
1159
		}
1160 1161 1162

		imxdmac->imxdma = imxdma;

1163 1164 1165 1166 1167 1168
		INIT_LIST_HEAD(&imxdmac->ld_queue);
		INIT_LIST_HEAD(&imxdmac->ld_free);
		INIT_LIST_HEAD(&imxdmac->ld_active);

		tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet,
			     (unsigned long)imxdmac);
1169
		imxdmac->chan.device = &imxdma->dma_device;
1170
		dma_cookie_init(&imxdmac->chan);
1171 1172 1173
		imxdmac->channel = i;

		/* Add the channel to the DMAC list */
1174 1175
		list_add_tail(&imxdmac->chan.device_node,
			      &imxdma->dma_device.channels);
1176 1177 1178 1179 1180 1181 1182 1183 1184
	}

	imxdma->dma_device.dev = &pdev->dev;

	imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
	imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
	imxdma->dma_device.device_tx_status = imxdma_tx_status;
	imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
	imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
1185
	imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy;
1186
	imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved;
1187 1188
	imxdma->dma_device.device_config = imxdma_config;
	imxdma->dma_device.device_terminate_all = imxdma_terminate_all;
1189 1190 1191 1192
	imxdma->dma_device.device_issue_pending = imxdma_issue_pending;

	platform_set_drvdata(pdev, imxdma);

1193
	imxdma->dma_device.copy_align = DMAENGINE_ALIGN_4_BYTES;
1194 1195 1196
	imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms;
	dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);

1197 1198 1199
	ret = dma_async_device_register(&imxdma->dma_device);
	if (ret) {
		dev_err(&pdev->dev, "unable to register\n");
1200
		goto disable_dma_ahb_clk;
1201 1202
	}

1203 1204 1205 1206 1207 1208 1209 1210 1211
	if (pdev->dev.of_node) {
		ret = of_dma_controller_register(pdev->dev.of_node,
				imxdma_xlate, imxdma);
		if (ret) {
			dev_err(&pdev->dev, "unable to register of_dma_controller\n");
			goto err_of_dma_controller;
		}
	}

1212 1213
	return 0;

1214 1215
err_of_dma_controller:
	dma_async_device_unregister(&imxdma->dma_device);
1216
disable_dma_ahb_clk:
1217
	clk_disable_unprepare(imxdma->dma_ahb);
1218 1219
disable_dma_ipg_clk:
	clk_disable_unprepare(imxdma->dma_ipg);
1220 1221 1222
	return ret;
}

1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241
static void imxdma_free_irq(struct platform_device *pdev, struct imxdma_engine *imxdma)
{
	int i;

	if (is_imx1_dma(imxdma)) {
		disable_irq(imxdma->irq);
		disable_irq(imxdma->irq_err);
	}

	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
		struct imxdma_channel *imxdmac = &imxdma->channel[i];

		if (!is_imx1_dma(imxdma))
			disable_irq(imxdmac->irq);

		tasklet_kill(&imxdmac->dma_tasklet);
	}
}

1242
static int imxdma_remove(struct platform_device *pdev)
1243 1244 1245
{
	struct imxdma_engine *imxdma = platform_get_drvdata(pdev);

1246 1247
	imxdma_free_irq(pdev, imxdma);

1248 1249
        dma_async_device_unregister(&imxdma->dma_device);

1250 1251 1252
	if (pdev->dev.of_node)
		of_dma_controller_free(pdev->dev.of_node);

1253 1254
	clk_disable_unprepare(imxdma->dma_ipg);
	clk_disable_unprepare(imxdma->dma_ahb);
1255 1256 1257 1258 1259 1260 1261

        return 0;
}

static struct platform_driver imxdma_driver = {
	.driver		= {
		.name	= "imx-dma",
1262
		.of_match_table = imx_dma_of_dev_id,
1263
	},
1264
	.id_table	= imx_dma_devtype,
1265
	.remove		= imxdma_remove,
1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276
};

static int __init imxdma_module_init(void)
{
	return platform_driver_probe(&imxdma_driver, imxdma_probe);
}
subsys_initcall(imxdma_module_init);

MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
MODULE_DESCRIPTION("i.MX dma driver");
MODULE_LICENSE("GPL");