imx-dma.c 31.4 KB
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/*
 * drivers/dma/imx-dma.c
 *
 * This file contains a driver for the Freescale i.MX DMA engine
 * found on i.MX1/21/27
 *
 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
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 * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
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 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */
#include <linux/init.h>
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/dmaengine.h>
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#include <linux/module.h>
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#include <asm/irq.h>
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#include <mach/dma.h>
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#include <mach/hardware.h>

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#include "dmaengine.h"
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#define IMXDMA_MAX_CHAN_DESCRIPTORS	16
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#define IMX_DMA_CHANNELS  16

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#define IMX_DMA_2D_SLOTS	2
#define IMX_DMA_2D_SLOT_A	0
#define IMX_DMA_2D_SLOT_B	1

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#define IMX_DMA_LENGTH_LOOP	((unsigned int)-1)
#define IMX_DMA_MEMSIZE_32	(0 << 4)
#define IMX_DMA_MEMSIZE_8	(1 << 4)
#define IMX_DMA_MEMSIZE_16	(2 << 4)
#define IMX_DMA_TYPE_LINEAR	(0 << 10)
#define IMX_DMA_TYPE_2D		(1 << 10)
#define IMX_DMA_TYPE_FIFO	(2 << 10)

#define IMX_DMA_ERR_BURST     (1 << 0)
#define IMX_DMA_ERR_REQUEST   (1 << 1)
#define IMX_DMA_ERR_TRANSFER  (1 << 2)
#define IMX_DMA_ERR_BUFFER    (1 << 3)
#define IMX_DMA_ERR_TIMEOUT   (1 << 4)

#define DMA_DCR     0x00		/* Control Register */
#define DMA_DISR    0x04		/* Interrupt status Register */
#define DMA_DIMR    0x08		/* Interrupt mask Register */
#define DMA_DBTOSR  0x0c		/* Burst timeout status Register */
#define DMA_DRTOSR  0x10		/* Request timeout Register */
#define DMA_DSESR   0x14		/* Transfer Error Status Register */
#define DMA_DBOSR   0x18		/* Buffer overflow status Register */
#define DMA_DBTOCR  0x1c		/* Burst timeout control Register */
#define DMA_WSRA    0x40		/* W-Size Register A */
#define DMA_XSRA    0x44		/* X-Size Register A */
#define DMA_YSRA    0x48		/* Y-Size Register A */
#define DMA_WSRB    0x4c		/* W-Size Register B */
#define DMA_XSRB    0x50		/* X-Size Register B */
#define DMA_YSRB    0x54		/* Y-Size Register B */
#define DMA_SAR(x)  (0x80 + ((x) << 6))	/* Source Address Registers */
#define DMA_DAR(x)  (0x84 + ((x) << 6))	/* Destination Address Registers */
#define DMA_CNTR(x) (0x88 + ((x) << 6))	/* Count Registers */
#define DMA_CCR(x)  (0x8c + ((x) << 6))	/* Control Registers */
#define DMA_RSSR(x) (0x90 + ((x) << 6))	/* Request source select Registers */
#define DMA_BLR(x)  (0x94 + ((x) << 6))	/* Burst length Registers */
#define DMA_RTOR(x) (0x98 + ((x) << 6))	/* Request timeout Registers */
#define DMA_BUCR(x) (0x98 + ((x) << 6))	/* Bus Utilization Registers */
#define DMA_CCNR(x) (0x9C + ((x) << 6))	/* Channel counter Registers */

#define DCR_DRST           (1<<1)
#define DCR_DEN            (1<<0)
#define DBTOCR_EN          (1<<15)
#define DBTOCR_CNT(x)      ((x) & 0x7fff)
#define CNTR_CNT(x)        ((x) & 0xffffff)
#define CCR_ACRPT          (1<<14)
#define CCR_DMOD_LINEAR    (0x0 << 12)
#define CCR_DMOD_2D        (0x1 << 12)
#define CCR_DMOD_FIFO      (0x2 << 12)
#define CCR_DMOD_EOBFIFO   (0x3 << 12)
#define CCR_SMOD_LINEAR    (0x0 << 10)
#define CCR_SMOD_2D        (0x1 << 10)
#define CCR_SMOD_FIFO      (0x2 << 10)
#define CCR_SMOD_EOBFIFO   (0x3 << 10)
#define CCR_MDIR_DEC       (1<<9)
#define CCR_MSEL_B         (1<<8)
#define CCR_DSIZ_32        (0x0 << 6)
#define CCR_DSIZ_8         (0x1 << 6)
#define CCR_DSIZ_16        (0x2 << 6)
#define CCR_SSIZ_32        (0x0 << 4)
#define CCR_SSIZ_8         (0x1 << 4)
#define CCR_SSIZ_16        (0x2 << 4)
#define CCR_REN            (1<<3)
#define CCR_RPT            (1<<2)
#define CCR_FRC            (1<<1)
#define CCR_CEN            (1<<0)
#define RTOR_EN            (1<<15)
#define RTOR_CLK           (1<<14)
#define RTOR_PSC           (1<<13)
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enum  imxdma_prep_type {
	IMXDMA_DESC_MEMCPY,
	IMXDMA_DESC_INTERLEAVED,
	IMXDMA_DESC_SLAVE_SG,
	IMXDMA_DESC_CYCLIC,
};

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struct imx_dma_2d_config {
	u16		xsr;
	u16		ysr;
	u16		wsr;
	int		count;
};

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struct imxdma_desc {
	struct list_head		node;
	struct dma_async_tx_descriptor	desc;
	enum dma_status			status;
	dma_addr_t			src;
	dma_addr_t			dest;
	size_t				len;
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	enum dma_transfer_direction	direction;
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	enum imxdma_prep_type		type;
	/* For memcpy and interleaved */
	unsigned int			config_port;
	unsigned int			config_mem;
	/* For interleaved transfers */
	unsigned int			x;
	unsigned int			y;
	unsigned int			w;
	/* For slave sg and cyclic */
	struct scatterlist		*sg;
	unsigned int			sgcount;
};

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struct imxdma_channel {
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	int				hw_chaining;
	struct timer_list		watchdog;
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	struct imxdma_engine		*imxdma;
	unsigned int			channel;

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	struct tasklet_struct		dma_tasklet;
	struct list_head		ld_free;
	struct list_head		ld_queue;
	struct list_head		ld_active;
	int				descs_allocated;
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	enum dma_slave_buswidth		word_size;
	dma_addr_t			per_address;
	u32				watermark_level;
	struct dma_chan			chan;
	struct dma_async_tx_descriptor	desc;
	enum dma_status			status;
	int				dma_request;
	struct scatterlist		*sg_list;
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	u32				ccr_from_device;
	u32				ccr_to_device;
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	bool				enabled_2d;
	int				slot_2d;
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};

struct imxdma_engine {
	struct device			*dev;
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	struct device_dma_parameters	dma_parms;
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	struct dma_device		dma_device;
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	void __iomem			*base;
	struct clk			*dma_clk;
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	spinlock_t			lock;
	struct imx_dma_2d_config	slots_2d[IMX_DMA_2D_SLOTS];
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	struct imxdma_channel		channel[IMX_DMA_CHANNELS];
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};

static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
{
	return container_of(chan, struct imxdma_channel, chan);
}

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static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
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{
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	struct imxdma_desc *desc;

	if (!list_empty(&imxdmac->ld_active)) {
		desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc,
					node);
		if (desc->type == IMXDMA_DESC_CYCLIC)
			return true;
	}
	return false;
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}

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static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val,
			     unsigned offset)
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{
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	__raw_writel(val, imxdma->base + offset);
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}

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static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset)
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{
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	return __raw_readl(imxdma->base + offset);
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}
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static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
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{
	if (cpu_is_mx27())
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		return imxdmac->hw_chaining;
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	else
		return 0;
}

/*
 * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
 */
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static inline int imxdma_sg_next(struct imxdma_desc *d)
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{
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	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
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	struct imxdma_engine *imxdma = imxdmac->imxdma;
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	struct scatterlist *sg = d->sg;
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	unsigned long now;

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	now = min(d->len, sg_dma_len(sg));
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	if (d->len != IMX_DMA_LENGTH_LOOP)
		d->len -= now;
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	if (d->direction == DMA_DEV_TO_MEM)
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		imx_dmav1_writel(imxdma, sg->dma_address,
				 DMA_DAR(imxdmac->channel));
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	else
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		imx_dmav1_writel(imxdma, sg->dma_address,
				 DMA_SAR(imxdmac->channel));
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	imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
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	dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, "
		"size 0x%08x\n", __func__, imxdmac->channel,
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		 imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
		 imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
		 imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
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	return now;
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}

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static void imxdma_enable_hw(struct imxdma_desc *d)
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{
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	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
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	struct imxdma_engine *imxdma = imxdmac->imxdma;
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	int channel = imxdmac->channel;
	unsigned long flags;

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	dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
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	local_irq_save(flags);

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	imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) &
			 ~(1 << channel), DMA_DIMR);
	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) |
			 CCR_CEN | CCR_ACRPT, DMA_CCR(channel));
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	if ((cpu_is_mx21() || cpu_is_mx27()) &&
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			d->sg && imxdma_hw_chain(imxdmac)) {
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		d->sg = sg_next(d->sg);
		if (d->sg) {
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			u32 tmp;
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			imxdma_sg_next(d);
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			tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel));
			imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT,
					 DMA_CCR(channel));
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		}
	}

	local_irq_restore(flags);
}

static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
{
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	struct imxdma_engine *imxdma = imxdmac->imxdma;
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	int channel = imxdmac->channel;
	unsigned long flags;

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	dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
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	if (imxdma_hw_chain(imxdmac))
		del_timer(&imxdmac->watchdog);
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	local_irq_save(flags);
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	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) |
			 (1 << channel), DMA_DIMR);
	imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) &
			 ~CCR_CEN, DMA_CCR(channel));
	imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
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	local_irq_restore(flags);
}

static void imxdma_watchdog(unsigned long data)
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{
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	struct imxdma_channel *imxdmac = (struct imxdma_channel *)data;
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	struct imxdma_engine *imxdma = imxdmac->imxdma;
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	int channel = imxdmac->channel;
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	imx_dmav1_writel(imxdma, 0, DMA_CCR(channel));
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	/* Tasklet watchdog error handler */
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	tasklet_schedule(&imxdmac->dma_tasklet);
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	dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n",
		imxdmac->channel);
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}

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static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
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{
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	struct imxdma_engine *imxdma = dev_id;
	unsigned int err_mask;
	int i, disr;
	int errcode;

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	disr = imx_dmav1_readl(imxdma, DMA_DISR);
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	err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) |
		   imx_dmav1_readl(imxdma, DMA_DRTOSR) |
		   imx_dmav1_readl(imxdma, DMA_DSESR)  |
		   imx_dmav1_readl(imxdma, DMA_DBOSR);
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	if (!err_mask)
		return IRQ_HANDLED;

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	imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR);
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	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
		if (!(err_mask & (1 << i)))
			continue;
		errcode = 0;

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		if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) {
			imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR);
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			errcode |= IMX_DMA_ERR_BURST;
		}
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		if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) {
			imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR);
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			errcode |= IMX_DMA_ERR_REQUEST;
		}
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		if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) {
			imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR);
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			errcode |= IMX_DMA_ERR_TRANSFER;
		}
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		if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) {
			imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR);
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			errcode |= IMX_DMA_ERR_BUFFER;
		}
		/* Tasklet error handler */
		tasklet_schedule(&imxdma->channel[i].dma_tasklet);

		printk(KERN_WARNING
		       "DMA timeout on channel %d -%s%s%s%s\n", i,
		       errcode & IMX_DMA_ERR_BURST ?    " burst" : "",
		       errcode & IMX_DMA_ERR_REQUEST ?  " request" : "",
		       errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
		       errcode & IMX_DMA_ERR_BUFFER ?   " buffer" : "");
	}
	return IRQ_HANDLED;
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}

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static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
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{
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	struct imxdma_engine *imxdma = imxdmac->imxdma;
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	int chno = imxdmac->channel;
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	struct imxdma_desc *desc;
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	spin_lock(&imxdma->lock);
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	if (list_empty(&imxdmac->ld_active)) {
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		spin_unlock(&imxdma->lock);
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		goto out;
	}
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	desc = list_first_entry(&imxdmac->ld_active,
				struct imxdma_desc,
				node);
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	spin_unlock(&imxdma->lock);
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	if (desc->sg) {
		u32 tmp;
		desc->sg = sg_next(desc->sg);
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		if (desc->sg) {
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			imxdma_sg_next(desc);
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			tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno));
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			if (imxdma_hw_chain(imxdmac)) {
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				/* FIXME: The timeout should probably be
				 * configurable
				 */
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				mod_timer(&imxdmac->watchdog,
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					jiffies + msecs_to_jiffies(500));

				tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
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				imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
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			} else {
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				imx_dmav1_writel(imxdma, tmp & ~CCR_CEN,
						 DMA_CCR(chno));
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				tmp |= CCR_CEN;
			}

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			imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
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			if (imxdma_chan_is_doing_cyclic(imxdmac))
				/* Tasklet progression */
				tasklet_schedule(&imxdmac->dma_tasklet);
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			return;
		}

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		if (imxdma_hw_chain(imxdmac)) {
			del_timer(&imxdmac->watchdog);
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			return;
		}
	}

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out:
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	imx_dmav1_writel(imxdma, 0, DMA_CCR(chno));
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	/* Tasklet irq */
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	tasklet_schedule(&imxdmac->dma_tasklet);
}

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static irqreturn_t dma_irq_handler(int irq, void *dev_id)
{
	struct imxdma_engine *imxdma = dev_id;
	int i, disr;

	if (cpu_is_mx21() || cpu_is_mx27())
		imxdma_err_handler(irq, dev_id);

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	disr = imx_dmav1_readl(imxdma, DMA_DISR);
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	dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr);
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	imx_dmav1_writel(imxdma, disr, DMA_DISR);
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	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
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		if (disr & (1 << i))
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			dma_irq_handle_channel(&imxdma->channel[i]);
	}

	return IRQ_HANDLED;
}

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static int imxdma_xfer_desc(struct imxdma_desc *d)
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
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	struct imxdma_engine *imxdma = imxdmac->imxdma;
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	unsigned long flags;
	int slot = -1;
	int i;
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	/* Configure and enable */
	switch (d->type) {
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	case IMXDMA_DESC_INTERLEAVED:
		/* Try to get a free 2D slot */
		spin_lock_irqsave(&imxdma->lock, flags);
		for (i = 0; i < IMX_DMA_2D_SLOTS; i++) {
			if ((imxdma->slots_2d[i].count > 0) &&
			((imxdma->slots_2d[i].xsr != d->x) ||
			(imxdma->slots_2d[i].ysr != d->y) ||
			(imxdma->slots_2d[i].wsr != d->w)))
				continue;
			slot = i;
			break;
		}
		if (slot < 0)
			return -EBUSY;

		imxdma->slots_2d[slot].xsr = d->x;
		imxdma->slots_2d[slot].ysr = d->y;
		imxdma->slots_2d[slot].wsr = d->w;
		imxdma->slots_2d[slot].count++;

		imxdmac->slot_2d = slot;
		imxdmac->enabled_2d = true;
		spin_unlock_irqrestore(&imxdma->lock, flags);

		if (slot == IMX_DMA_2D_SLOT_A) {
			d->config_mem &= ~CCR_MSEL_B;
			d->config_port &= ~CCR_MSEL_B;
			imx_dmav1_writel(imxdma, d->x, DMA_XSRA);
			imx_dmav1_writel(imxdma, d->y, DMA_YSRA);
			imx_dmav1_writel(imxdma, d->w, DMA_WSRA);
		} else {
			d->config_mem |= CCR_MSEL_B;
			d->config_port |= CCR_MSEL_B;
			imx_dmav1_writel(imxdma, d->x, DMA_XSRB);
			imx_dmav1_writel(imxdma, d->y, DMA_YSRB);
			imx_dmav1_writel(imxdma, d->w, DMA_WSRB);
		}
		/*
		 * We fall-through here intentionally, since a 2D transfer is
		 * similar to MEMCPY just adding the 2D slot configuration.
		 */
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	case IMXDMA_DESC_MEMCPY:
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		imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
		imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
		imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2),
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			 DMA_CCR(imxdmac->channel));
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		imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel));
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		dev_dbg(imxdma->dev, "%s channel: %d dest=0x%08x src=0x%08x "
			"dma_length=%d\n", __func__, imxdmac->channel,
			d->dest, d->src, d->len);

		break;
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	/* Cyclic transfer is the same as slave_sg with special sg configuration. */
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	case IMXDMA_DESC_CYCLIC:
	case IMXDMA_DESC_SLAVE_SG:
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		if (d->direction == DMA_DEV_TO_MEM) {
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			imx_dmav1_writel(imxdma, imxdmac->per_address,
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					 DMA_SAR(imxdmac->channel));
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			imx_dmav1_writel(imxdma, imxdmac->ccr_from_device,
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					 DMA_CCR(imxdmac->channel));

			dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
				"total length=%d dev_addr=0x%08x (dev2mem)\n",
				__func__, imxdmac->channel, d->sg, d->sgcount,
				d->len, imxdmac->per_address);
		} else if (d->direction == DMA_MEM_TO_DEV) {
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			imx_dmav1_writel(imxdma, imxdmac->per_address,
533
					 DMA_DAR(imxdmac->channel));
534
			imx_dmav1_writel(imxdma, imxdmac->ccr_to_device,
535 536 537 538 539 540 541 542 543 544 545 546
					 DMA_CCR(imxdmac->channel));

			dev_dbg(imxdma->dev, "%s channel: %d sg=%p sgcount=%d "
				"total length=%d dev_addr=0x%08x (mem2dev)\n",
				__func__, imxdmac->channel, d->sg, d->sgcount,
				d->len, imxdmac->per_address);
		} else {
			dev_err(imxdma->dev, "%s channel: %d bad dma mode\n",
				__func__, imxdmac->channel);
			return -EINVAL;
		}

547
		imxdma_sg_next(d);
548

549 550 551 552
		break;
	default:
		return -EINVAL;
	}
553
	imxdma_enable_hw(d);
554
	return 0;
555 556
}

557
static void imxdma_tasklet(unsigned long data)
558
{
559 560 561
	struct imxdma_channel *imxdmac = (void *)data;
	struct imxdma_engine *imxdma = imxdmac->imxdma;
	struct imxdma_desc *desc;
562

563
	spin_lock(&imxdma->lock);
564 565 566 567 568 569 570 571 572 573

	if (list_empty(&imxdmac->ld_active)) {
		/* Someone might have called terminate all */
		goto out;
	}
	desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node);

	if (desc->desc.callback)
		desc->desc.callback(desc->desc.callback_param);

574 575 576 577
	/* If we are dealing with a cyclic descriptor keep it on ld_active
	 * and dont mark the descripor as complete.
	 * Only in non-cyclic cases it would be marked as complete
	 */
578 579
	if (imxdma_chan_is_doing_cyclic(imxdmac))
		goto out;
580 581
	else
		dma_cookie_complete(&desc->desc);
582

583 584 585 586 587 588
	/* Free 2D slot if it was an interleaved transfer */
	if (imxdmac->enabled_2d) {
		imxdma->slots_2d[imxdmac->slot_2d].count--;
		imxdmac->enabled_2d = false;
	}

589 590 591 592 593 594 595 596 597 598 599
	list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);

	if (!list_empty(&imxdmac->ld_queue)) {
		desc = list_first_entry(&imxdmac->ld_queue, struct imxdma_desc,
					node);
		list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active);
		if (imxdma_xfer_desc(desc) < 0)
			dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n",
				 __func__, imxdmac->channel);
	}
out:
600
	spin_unlock(&imxdma->lock);
601 602 603 604 605 606 607
}

static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
		unsigned long arg)
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	struct dma_slave_config *dmaengine_cfg = (void *)arg;
608
	struct imxdma_engine *imxdma = imxdmac->imxdma;
609
	unsigned long flags;
610 611 612 613
	unsigned int mode = 0;

	switch (cmd) {
	case DMA_TERMINATE_ALL:
614
		imxdma_disable_hw(imxdmac);
615

616
		spin_lock_irqsave(&imxdma->lock, flags);
617 618
		list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
		list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
619
		spin_unlock_irqrestore(&imxdma->lock, flags);
620 621
		return 0;
	case DMA_SLAVE_CONFIG:
622
		if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644
			imxdmac->per_address = dmaengine_cfg->src_addr;
			imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
			imxdmac->word_size = dmaengine_cfg->src_addr_width;
		} else {
			imxdmac->per_address = dmaengine_cfg->dst_addr;
			imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
			imxdmac->word_size = dmaengine_cfg->dst_addr_width;
		}

		switch (imxdmac->word_size) {
		case DMA_SLAVE_BUSWIDTH_1_BYTE:
			mode = IMX_DMA_MEMSIZE_8;
			break;
		case DMA_SLAVE_BUSWIDTH_2_BYTES:
			mode = IMX_DMA_MEMSIZE_16;
			break;
		default:
		case DMA_SLAVE_BUSWIDTH_4_BYTES:
			mode = IMX_DMA_MEMSIZE_32;
			break;
		}

645 646
		imxdmac->hw_chaining = 1;
		if (!imxdma_hw_chain(imxdmac))
647
			return -EINVAL;
648
		imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
649 650
			((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
			CCR_REN;
651
		imxdmac->ccr_to_device =
652 653
			(IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
			((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
654
		imx_dmav1_writel(imxdma, imxdmac->dma_request,
655 656
				 DMA_RSSR(imxdmac->channel));

657
		/* Set burst length */
658 659
		imx_dmav1_writel(imxdma, imxdmac->watermark_level *
				imxdmac->word_size, DMA_BLR(imxdmac->channel));
660 661 662 663 664 665 666 667 668 669 670 671 672

		return 0;
	default:
		return -ENOSYS;
	}

	return -EINVAL;
}

static enum dma_status imxdma_tx_status(struct dma_chan *chan,
					    dma_cookie_t cookie,
					    struct dma_tx_state *txstate)
{
673
	return dma_cookie_status(chan, cookie, txstate);
674 675 676 677 678
}

static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
679
	struct imxdma_engine *imxdma = imxdmac->imxdma;
680
	dma_cookie_t cookie;
681
	unsigned long flags;
682

683
	spin_lock_irqsave(&imxdma->lock, flags);
684
	list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue);
685
	cookie = dma_cookie_assign(tx);
686
	spin_unlock_irqrestore(&imxdma->lock, flags);
687 688 689 690 691 692 693 694 695

	return cookie;
}

static int imxdma_alloc_chan_resources(struct dma_chan *chan)
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	struct imx_dma_data *data = chan->private;

696 697
	if (data != NULL)
		imxdmac->dma_request = data->dma_request;
698

699 700
	while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) {
		struct imxdma_desc *desc;
701

702 703 704 705 706 707 708 709 710 711 712 713 714
		desc = kzalloc(sizeof(*desc), GFP_KERNEL);
		if (!desc)
			break;
		__memzero(&desc->desc, sizeof(struct dma_async_tx_descriptor));
		dma_async_tx_descriptor_init(&desc->desc, chan);
		desc->desc.tx_submit = imxdma_tx_submit;
		/* txd.flags will be overwritten in prep funcs */
		desc->desc.flags = DMA_CTRL_ACK;
		desc->status = DMA_SUCCESS;

		list_add_tail(&desc->node, &imxdmac->ld_free);
		imxdmac->descs_allocated++;
	}
715

716 717 718 719
	if (!imxdmac->descs_allocated)
		return -ENOMEM;

	return imxdmac->descs_allocated;
720 721 722 723 724
}

static void imxdma_free_chan_resources(struct dma_chan *chan)
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
725
	struct imxdma_engine *imxdma = imxdmac->imxdma;
726 727 728
	struct imxdma_desc *desc, *_desc;
	unsigned long flags;

729
	spin_lock_irqsave(&imxdma->lock, flags);
730

731
	imxdma_disable_hw(imxdmac);
732 733
	list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
	list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
734

735
	spin_unlock_irqrestore(&imxdma->lock, flags);
736 737 738 739 740 741

	list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) {
		kfree(desc);
		imxdmac->descs_allocated--;
	}
	INIT_LIST_HEAD(&imxdmac->ld_free);
742 743 744 745 746 747 748 749 750

	if (imxdmac->sg_list) {
		kfree(imxdmac->sg_list);
		imxdmac->sg_list = NULL;
	}
}

static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
		struct dma_chan *chan, struct scatterlist *sgl,
751
		unsigned int sg_len, enum dma_transfer_direction direction,
752
		unsigned long flags, void *context)
753 754 755
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	struct scatterlist *sg;
756 757
	int i, dma_length = 0;
	struct imxdma_desc *desc;
758

759 760
	if (list_empty(&imxdmac->ld_free) ||
	    imxdma_chan_is_doing_cyclic(imxdmac))
761 762
		return NULL;

763
	desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
764 765

	for_each_sg(sgl, sg, sg_len, i) {
766
		dma_length += sg_dma_len(sg);
767 768
	}

769 770
	switch (imxdmac->word_size) {
	case DMA_SLAVE_BUSWIDTH_4_BYTES:
771
		if (sg_dma_len(sgl) & 3 || sgl->dma_address & 3)
772 773 774
			return NULL;
		break;
	case DMA_SLAVE_BUSWIDTH_2_BYTES:
775
		if (sg_dma_len(sgl) & 1 || sgl->dma_address & 1)
776 777 778 779 780 781 782 783
			return NULL;
		break;
	case DMA_SLAVE_BUSWIDTH_1_BYTE:
		break;
	default:
		return NULL;
	}

784 785 786 787
	desc->type = IMXDMA_DESC_SLAVE_SG;
	desc->sg = sgl;
	desc->sgcount = sg_len;
	desc->len = dma_length;
788
	desc->direction = direction;
789 790 791 792 793 794 795
	if (direction == DMA_DEV_TO_MEM) {
		desc->src = imxdmac->per_address;
	} else {
		desc->dest = imxdmac->per_address;
	}
	desc->desc.callback = NULL;
	desc->desc.callback_param = NULL;
796

797
	return &desc->desc;
798 799 800 801
}

static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
		struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
802 803
		size_t period_len, enum dma_transfer_direction direction,
		void *context)
804 805 806
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	struct imxdma_engine *imxdma = imxdmac->imxdma;
807 808
	struct imxdma_desc *desc;
	int i;
809 810 811 812 813
	unsigned int periods = buf_len / period_len;

	dev_dbg(imxdma->dev, "%s channel: %d buf_len=%d period_len=%d\n",
			__func__, imxdmac->channel, buf_len, period_len);

814 815
	if (list_empty(&imxdmac->ld_free) ||
	    imxdma_chan_is_doing_cyclic(imxdmac))
816 817
		return NULL;

818
	desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
819 820 821 822 823 824 825 826 827 828 829 830 831 832 833

	if (imxdmac->sg_list)
		kfree(imxdmac->sg_list);

	imxdmac->sg_list = kcalloc(periods + 1,
			sizeof(struct scatterlist), GFP_KERNEL);
	if (!imxdmac->sg_list)
		return NULL;

	sg_init_table(imxdmac->sg_list, periods);

	for (i = 0; i < periods; i++) {
		imxdmac->sg_list[i].page_link = 0;
		imxdmac->sg_list[i].offset = 0;
		imxdmac->sg_list[i].dma_address = dma_addr;
834
		sg_dma_len(&imxdmac->sg_list[i]) = period_len;
835 836 837 838 839
		dma_addr += period_len;
	}

	/* close the loop */
	imxdmac->sg_list[periods].offset = 0;
840
	sg_dma_len(&imxdmac->sg_list[periods]) = 0;
841 842 843
	imxdmac->sg_list[periods].page_link =
		((unsigned long)imxdmac->sg_list | 0x01) & ~0x02;

844 845 846 847
	desc->type = IMXDMA_DESC_CYCLIC;
	desc->sg = imxdmac->sg_list;
	desc->sgcount = periods;
	desc->len = IMX_DMA_LENGTH_LOOP;
848
	desc->direction = direction;
849 850 851 852 853 854 855
	if (direction == DMA_DEV_TO_MEM) {
		desc->src = imxdmac->per_address;
	} else {
		desc->dest = imxdmac->per_address;
	}
	desc->desc.callback = NULL;
	desc->desc.callback_param = NULL;
856

857
	return &desc->desc;
858 859
}

860 861 862 863 864 865
static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
	struct dma_chan *chan, dma_addr_t dest,
	dma_addr_t src, size_t len, unsigned long flags)
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	struct imxdma_engine *imxdma = imxdmac->imxdma;
866
	struct imxdma_desc *desc;
867

868 869 870
	dev_dbg(imxdma->dev, "%s channel: %d src=0x%x dst=0x%x len=%d\n",
			__func__, imxdmac->channel, src, dest, len);

871 872
	if (list_empty(&imxdmac->ld_free) ||
	    imxdma_chan_is_doing_cyclic(imxdmac))
873 874
		return NULL;

875
	desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
876

877 878 879 880
	desc->type = IMXDMA_DESC_MEMCPY;
	desc->src = src;
	desc->dest = dest;
	desc->len = len;
881
	desc->direction = DMA_MEM_TO_MEM;
882 883 884 885
	desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
	desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
	desc->desc.callback = NULL;
	desc->desc.callback_param = NULL;
886

887
	return &desc->desc;
888 889
}

890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930
static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved(
	struct dma_chan *chan, struct dma_interleaved_template *xt,
	unsigned long flags)
{
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
	struct imxdma_engine *imxdma = imxdmac->imxdma;
	struct imxdma_desc *desc;

	dev_dbg(imxdma->dev, "%s channel: %d src_start=0x%x dst_start=0x%x\n"
		"   src_sgl=%s dst_sgl=%s numf=%d frame_size=%d\n", __func__,
		imxdmac->channel, xt->src_start, xt->dst_start,
		xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false",
		xt->numf, xt->frame_size);

	if (list_empty(&imxdmac->ld_free) ||
	    imxdma_chan_is_doing_cyclic(imxdmac))
		return NULL;

	if (xt->frame_size != 1 || xt->numf <= 0 || xt->dir != DMA_MEM_TO_MEM)
		return NULL;

	desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);

	desc->type = IMXDMA_DESC_INTERLEAVED;
	desc->src = xt->src_start;
	desc->dest = xt->dst_start;
	desc->x = xt->sgl[0].size;
	desc->y = xt->numf;
	desc->w = xt->sgl[0].icg + desc->x;
	desc->len = desc->x * desc->y;
	desc->direction = DMA_MEM_TO_MEM;
	desc->config_port = IMX_DMA_MEMSIZE_32;
	desc->config_mem = IMX_DMA_MEMSIZE_32;
	if (xt->src_sgl)
		desc->config_mem |= IMX_DMA_TYPE_2D;
	if (xt->dst_sgl)
		desc->config_port |= IMX_DMA_TYPE_2D;
	desc->desc.callback = NULL;
	desc->desc.callback_param = NULL;

	return &desc->desc;
931 932 933 934
}

static void imxdma_issue_pending(struct dma_chan *chan)
{
935
	struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
936 937 938 939
	struct imxdma_engine *imxdma = imxdmac->imxdma;
	struct imxdma_desc *desc;
	unsigned long flags;

940
	spin_lock_irqsave(&imxdma->lock, flags);
941 942 943 944 945 946 947 948 949 950 951 952 953 954
	if (list_empty(&imxdmac->ld_active) &&
	    !list_empty(&imxdmac->ld_queue)) {
		desc = list_first_entry(&imxdmac->ld_queue,
					struct imxdma_desc, node);

		if (imxdma_xfer_desc(desc) < 0) {
			dev_warn(imxdma->dev,
				 "%s: channel: %d couldn't issue DMA xfer\n",
				 __func__, imxdmac->channel);
		} else {
			list_move_tail(imxdmac->ld_queue.next,
				       &imxdmac->ld_active);
		}
	}
955
	spin_unlock_irqrestore(&imxdma->lock, flags);
956 957 958
}

static int __init imxdma_probe(struct platform_device *pdev)
959
	{
960 961 962
	struct imxdma_engine *imxdma;
	int ret, i;

963

964 965 966 967
	imxdma = kzalloc(sizeof(*imxdma), GFP_KERNEL);
	if (!imxdma)
		return -ENOMEM;

968 969 970 971 972 973 974 975
	if (cpu_is_mx1()) {
		imxdma->base = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
	} else if (cpu_is_mx21()) {
		imxdma->base = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
	} else if (cpu_is_mx27()) {
		imxdma->base = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
	} else {
		kfree(imxdma);
976
		return 0;
977
	}
978

979 980 981 982
	imxdma->dma_clk = clk_get(NULL, "dma");
	if (IS_ERR(imxdma->dma_clk))
		return PTR_ERR(imxdma->dma_clk);
	clk_enable(imxdma->dma_clk);
983 984

	/* reset DMA module */
985
	imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR);
986 987 988 989

	if (cpu_is_mx1()) {
		ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", imxdma);
		if (ret) {
990
			dev_warn(imxdma->dev, "Can't register IRQ for DMA\n");
991
			kfree(imxdma);
992 993 994 995 996
			return ret;
		}

		ret = request_irq(MX1_DMA_ERR, imxdma_err_handler, 0, "DMA", imxdma);
		if (ret) {
997
			dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n");
998
			free_irq(MX1_DMA_INT, NULL);
999
			kfree(imxdma);
1000 1001 1002 1003 1004
			return ret;
		}
	}

	/* enable DMA module */
1005
	imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR);
1006 1007

	/* clear all interrupts */
1008
	imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
1009 1010

	/* disable interrupts */
1011
	imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
1012 1013 1014

	INIT_LIST_HEAD(&imxdma->dma_device.channels);

1015 1016
	dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
	dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
1017
	dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
1018 1019 1020 1021 1022 1023 1024
	dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask);

	/* Initialize 2D global parameters */
	for (i = 0; i < IMX_DMA_2D_SLOTS; i++)
		imxdma->slots_2d[i].count = 0;

	spin_lock_init(&imxdma->lock);
1025

1026
	/* Initialize channel parameters */
1027
	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
1028 1029
		struct imxdma_channel *imxdmac = &imxdma->channel[i];

1030 1031 1032 1033
		if (cpu_is_mx21() || cpu_is_mx27()) {
			ret = request_irq(MX2x_INT_DMACH0 + i,
					dma_irq_handler, 0, "DMA", imxdma);
			if (ret) {
1034 1035 1036
				dev_warn(imxdma->dev, "Can't register IRQ %d "
					 "for DMA channel %d\n",
					 MX2x_INT_DMACH0 + i, i);
1037 1038
				goto err_init;
			}
1039 1040 1041
			init_timer(&imxdmac->watchdog);
			imxdmac->watchdog.function = &imxdma_watchdog;
			imxdmac->watchdog.data = (unsigned long)imxdmac;
S
Sascha Hauer 已提交
1042
		}
1043 1044 1045

		imxdmac->imxdma = imxdma;

1046 1047 1048 1049 1050 1051
		INIT_LIST_HEAD(&imxdmac->ld_queue);
		INIT_LIST_HEAD(&imxdmac->ld_free);
		INIT_LIST_HEAD(&imxdmac->ld_active);

		tasklet_init(&imxdmac->dma_tasklet, imxdma_tasklet,
			     (unsigned long)imxdmac);
1052
		imxdmac->chan.device = &imxdma->dma_device;
1053
		dma_cookie_init(&imxdmac->chan);
1054 1055 1056
		imxdmac->channel = i;

		/* Add the channel to the DMAC list */
1057 1058
		list_add_tail(&imxdmac->chan.device_node,
			      &imxdma->dma_device.channels);
1059 1060 1061 1062 1063 1064 1065 1066 1067 1068
	}

	imxdma->dev = &pdev->dev;
	imxdma->dma_device.dev = &pdev->dev;

	imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
	imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
	imxdma->dma_device.device_tx_status = imxdma_tx_status;
	imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
	imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
1069
	imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy;
1070
	imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved;
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	imxdma->dma_device.device_control = imxdma_control;
	imxdma->dma_device.device_issue_pending = imxdma_issue_pending;

	platform_set_drvdata(pdev, imxdma);

1076
	imxdma->dma_device.copy_align = 2; /* 2^2 = 4 bytes alignment */
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	imxdma->dma_device.dev->dma_parms = &imxdma->dma_parms;
	dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);

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	ret = dma_async_device_register(&imxdma->dma_device);
	if (ret) {
		dev_err(&pdev->dev, "unable to register\n");
		goto err_init;
	}

	return 0;

err_init:
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	if (cpu_is_mx21() || cpu_is_mx27()) {
		while (--i >= 0)
			free_irq(MX2x_INT_DMACH0 + i, NULL);
	} else if cpu_is_mx1() {
		free_irq(MX1_DMA_INT, NULL);
		free_irq(MX1_DMA_ERR, NULL);
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	}

	kfree(imxdma);
	return ret;
}

static int __exit imxdma_remove(struct platform_device *pdev)
{
	struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
	int i;

        dma_async_device_unregister(&imxdma->dma_device);

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	if (cpu_is_mx21() || cpu_is_mx27()) {
		for (i = 0; i < IMX_DMA_CHANNELS; i++)
			free_irq(MX2x_INT_DMACH0 + i, NULL);
	} else if cpu_is_mx1() {
		free_irq(MX1_DMA_INT, NULL);
		free_irq(MX1_DMA_ERR, NULL);
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	}

        kfree(imxdma);

        return 0;
}

static struct platform_driver imxdma_driver = {
	.driver		= {
		.name	= "imx-dma",
	},
	.remove		= __exit_p(imxdma_remove),
};

static int __init imxdma_module_init(void)
{
	return platform_driver_probe(&imxdma_driver, imxdma_probe);
}
subsys_initcall(imxdma_module_init);

MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
MODULE_DESCRIPTION("i.MX dma driver");
MODULE_LICENSE("GPL");