edma.c 62.1 KB
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/*
 * TI EDMA DMA engine driver
 *
 * Copyright 2012 Texas Instruments
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
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#include <linux/edma.h>
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#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
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#include <linux/of.h>
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#include <linux/of_dma.h>
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#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
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#include <linux/platform_data/edma.h>
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#include "dmaengine.h"
#include "virt-dma.h"

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/* Offsets matching "struct edmacc_param" */
#define PARM_OPT		0x00
#define PARM_SRC		0x04
#define PARM_A_B_CNT		0x08
#define PARM_DST		0x0c
#define PARM_SRC_DST_BIDX	0x10
#define PARM_LINK_BCNTRLD	0x14
#define PARM_SRC_DST_CIDX	0x18
#define PARM_CCNT		0x1c

#define PARM_SIZE		0x20

/* Offsets for EDMA CC global channel registers and their shadows */
#define SH_ER			0x00	/* 64 bits */
#define SH_ECR			0x08	/* 64 bits */
#define SH_ESR			0x10	/* 64 bits */
#define SH_CER			0x18	/* 64 bits */
#define SH_EER			0x20	/* 64 bits */
#define SH_EECR			0x28	/* 64 bits */
#define SH_EESR			0x30	/* 64 bits */
#define SH_SER			0x38	/* 64 bits */
#define SH_SECR			0x40	/* 64 bits */
#define SH_IER			0x50	/* 64 bits */
#define SH_IECR			0x58	/* 64 bits */
#define SH_IESR			0x60	/* 64 bits */
#define SH_IPR			0x68	/* 64 bits */
#define SH_ICR			0x70	/* 64 bits */
#define SH_IEVAL		0x78
#define SH_QER			0x80
#define SH_QEER			0x84
#define SH_QEECR		0x88
#define SH_QEESR		0x8c
#define SH_QSER			0x90
#define SH_QSECR		0x94
#define SH_SIZE			0x200

/* Offsets for EDMA CC global registers */
#define EDMA_REV		0x0000
#define EDMA_CCCFG		0x0004
#define EDMA_QCHMAP		0x0200	/* 8 registers */
#define EDMA_DMAQNUM		0x0240	/* 8 registers (4 on OMAP-L1xx) */
#define EDMA_QDMAQNUM		0x0260
#define EDMA_QUETCMAP		0x0280
#define EDMA_QUEPRI		0x0284
#define EDMA_EMR		0x0300	/* 64 bits */
#define EDMA_EMCR		0x0308	/* 64 bits */
#define EDMA_QEMR		0x0310
#define EDMA_QEMCR		0x0314
#define EDMA_CCERR		0x0318
#define EDMA_CCERRCLR		0x031c
#define EDMA_EEVAL		0x0320
#define EDMA_DRAE		0x0340	/* 4 x 64 bits*/
#define EDMA_QRAE		0x0380	/* 4 registers */
#define EDMA_QUEEVTENTRY	0x0400	/* 2 x 16 registers */
#define EDMA_QSTAT		0x0600	/* 2 registers */
#define EDMA_QWMTHRA		0x0620
#define EDMA_QWMTHRB		0x0624
#define EDMA_CCSTAT		0x0640

#define EDMA_M			0x1000	/* global channel registers */
#define EDMA_ECR		0x1008
#define EDMA_ECRH		0x100C
#define EDMA_SHADOW0		0x2000	/* 4 shadow regions */
#define EDMA_PARM		0x4000	/* PaRAM entries */

#define PARM_OFFSET(param_no)	(EDMA_PARM + ((param_no) << 5))

#define EDMA_DCHMAP		0x0100  /* 64 registers */

/* CCCFG register */
#define GET_NUM_DMACH(x)	(x & 0x7) /* bits 0-2 */
#define GET_NUM_PAENTRY(x)	((x & 0x7000) >> 12) /* bits 12-14 */
#define GET_NUM_EVQUE(x)	((x & 0x70000) >> 16) /* bits 16-18 */
#define GET_NUM_REGN(x)		((x & 0x300000) >> 20) /* bits 20-21 */
#define CHMAP_EXIST		BIT(24)

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/*
 * Max of 20 segments per channel to conserve PaRAM slots
 * Also note that MAX_NR_SG should be atleast the no.of periods
 * that are required for ASoC, otherwise DMA prep calls will
 * fail. Today davinci-pcm is the only user of this driver and
 * requires atleast 17 slots, so we setup the default to 20.
 */
#define MAX_NR_SG		20
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#define EDMA_MAX_SLOTS		MAX_NR_SG
#define EDMA_DESCRIPTORS	16

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#define EDMA_CHANNEL_ANY		-1	/* for edma_alloc_channel() */
#define EDMA_SLOT_ANY			-1	/* for edma_alloc_slot() */
#define EDMA_CONT_PARAMS_ANY		 1001
#define EDMA_CONT_PARAMS_FIXED_EXACT	 1002
#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003

/* PaRAM slots are laid out like this */
struct edmacc_param {
	u32 opt;
	u32 src;
	u32 a_b_cnt;
	u32 dst;
	u32 src_dst_bidx;
	u32 link_bcntrld;
	u32 src_dst_cidx;
	u32 ccnt;
} __packed;

/* fields in edmacc_param.opt */
#define SAM		BIT(0)
#define DAM		BIT(1)
#define SYNCDIM		BIT(2)
#define STATIC		BIT(3)
#define EDMA_FWID	(0x07 << 8)
#define TCCMODE		BIT(11)
#define EDMA_TCC(t)	((t) << 12)
#define TCINTEN		BIT(20)
#define ITCINTEN	BIT(21)
#define TCCHEN		BIT(22)
#define ITCCHEN		BIT(23)

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struct edma_pset {
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	u32				len;
	dma_addr_t			addr;
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	struct edmacc_param		param;
};

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struct edma_desc {
	struct virt_dma_desc		vdesc;
	struct list_head		node;
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	enum dma_transfer_direction	direction;
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	int				cyclic;
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	int				absync;
	int				pset_nr;
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	struct edma_chan		*echan;
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	int				processed;
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	/*
	 * The following 4 elements are used for residue accounting.
	 *
	 * - processed_stat: the number of SG elements we have traversed
	 * so far to cover accounting. This is updated directly to processed
	 * during edma_callback and is always <= processed, because processed
	 * refers to the number of pending transfer (programmed to EDMA
	 * controller), where as processed_stat tracks number of transfers
	 * accounted for so far.
	 *
	 * - residue: The amount of bytes we have left to transfer for this desc
	 *
	 * - residue_stat: The residue in bytes of data we have covered
	 * so far for accounting. This is updated directly to residue
	 * during callbacks to keep it current.
	 *
	 * - sg_len: Tracks the length of the current intermediate transfer,
	 * this is required to update the residue during intermediate transfer
	 * completion callback.
	 */
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	int				processed_stat;
	u32				sg_len;
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	u32				residue;
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	u32				residue_stat;
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	struct edma_pset		pset[0];
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};

struct edma_cc;

struct edma_chan {
	struct virt_dma_chan		vchan;
	struct list_head		node;
	struct edma_desc		*edesc;
	struct edma_cc			*ecc;
	int				ch_num;
	bool				alloced;
	int				slot[EDMA_MAX_SLOTS];
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	int				missed;
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	struct dma_slave_config		cfg;
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};

struct edma_cc {
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	struct device			*dev;
	struct edma_soc_info		*info;
	void __iomem			*base;
	int				id;

	/* eDMA3 resource information */
	unsigned			num_channels;
	unsigned			num_region;
	unsigned			num_slots;
	unsigned			num_tc;
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	bool				chmap_exist;
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	enum dma_event_q		default_queue;

	bool				unused_chan_list_done;
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	/* The slot_inuse bit for each PaRAM slot is clear unless the
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	 * channel is in use ... by ARM or DSP, for QDMA, or whatever.
	 */
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	unsigned long *slot_inuse;
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	/* The channel_unused bit for each channel is clear unless
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	 * it is not being used on this platform. It uses a bit
	 * of SOC-specific initialization code.
	 */
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	unsigned long *channel_unused;
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	struct dma_device		dma_slave;
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	struct edma_chan		*slave_chans;
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	int				dummy_slot;
};

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/* dummy param set used to (re)initialize parameter RAM slots */
static const struct edmacc_param dummy_paramset = {
	.link_bcntrld = 0xffff,
	.ccnt = 1,
};

static const struct of_device_id edma_of_ids[] = {
	{ .compatible = "ti,edma3", },
	{}
};

static inline unsigned int edma_read(struct edma_cc *ecc, int offset)
{
	return (unsigned int)__raw_readl(ecc->base + offset);
}

static inline void edma_write(struct edma_cc *ecc, int offset, int val)
{
	__raw_writel(val, ecc->base + offset);
}

static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and,
			       unsigned or)
{
	unsigned val = edma_read(ecc, offset);

	val &= and;
	val |= or;
	edma_write(ecc, offset, val);
}

static inline void edma_and(struct edma_cc *ecc, int offset, unsigned and)
{
	unsigned val = edma_read(ecc, offset);

	val &= and;
	edma_write(ecc, offset, val);
}

static inline void edma_or(struct edma_cc *ecc, int offset, unsigned or)
{
	unsigned val = edma_read(ecc, offset);

	val |= or;
	edma_write(ecc, offset, val);
}

static inline unsigned int edma_read_array(struct edma_cc *ecc, int offset,
					   int i)
{
	return edma_read(ecc, offset + (i << 2));
}

static inline void edma_write_array(struct edma_cc *ecc, int offset, int i,
				    unsigned val)
{
	edma_write(ecc, offset + (i << 2), val);
}

static inline void edma_modify_array(struct edma_cc *ecc, int offset, int i,
				     unsigned and, unsigned or)
{
	edma_modify(ecc, offset + (i << 2), and, or);
}

static inline void edma_or_array(struct edma_cc *ecc, int offset, int i,
				 unsigned or)
{
	edma_or(ecc, offset + (i << 2), or);
}

static inline void edma_or_array2(struct edma_cc *ecc, int offset, int i, int j,
				  unsigned or)
{
	edma_or(ecc, offset + ((i * 2 + j) << 2), or);
}

static inline void edma_write_array2(struct edma_cc *ecc, int offset, int i,
				     int j, unsigned val)
{
	edma_write(ecc, offset + ((i * 2 + j) << 2), val);
}

static inline unsigned int edma_shadow0_read(struct edma_cc *ecc, int offset)
{
	return edma_read(ecc, EDMA_SHADOW0 + offset);
}

static inline unsigned int edma_shadow0_read_array(struct edma_cc *ecc,
						   int offset, int i)
{
	return edma_read(ecc, EDMA_SHADOW0 + offset + (i << 2));
}

static inline void edma_shadow0_write(struct edma_cc *ecc, int offset,
				      unsigned val)
{
	edma_write(ecc, EDMA_SHADOW0 + offset, val);
}

static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset,
					    int i, unsigned val)
{
	edma_write(ecc, EDMA_SHADOW0 + offset + (i << 2), val);
}

static inline unsigned int edma_parm_read(struct edma_cc *ecc, int offset,
					  int param_no)
{
	return edma_read(ecc, EDMA_PARM + offset + (param_no << 5));
}

static inline void edma_parm_write(struct edma_cc *ecc, int offset,
				   int param_no, unsigned val)
{
	edma_write(ecc, EDMA_PARM + offset + (param_no << 5), val);
}

static inline void edma_parm_modify(struct edma_cc *ecc, int offset,
				    int param_no, unsigned and, unsigned or)
{
	edma_modify(ecc, EDMA_PARM + offset + (param_no << 5), and, or);
}

static inline void edma_parm_and(struct edma_cc *ecc, int offset, int param_no,
				 unsigned and)
{
	edma_and(ecc, EDMA_PARM + offset + (param_no << 5), and);
}

static inline void edma_parm_or(struct edma_cc *ecc, int offset, int param_no,
				unsigned or)
{
	edma_or(ecc, EDMA_PARM + offset + (param_no << 5), or);
}

static inline void set_bits(int offset, int len, unsigned long *p)
{
	for (; len > 0; len--)
		set_bit(offset + (len - 1), p);
}

static inline void clear_bits(int offset, int len, unsigned long *p)
{
	for (; len > 0; len--)
		clear_bit(offset + (len - 1), p);
}

static void edma_map_dmach_to_queue(struct edma_cc *ecc, unsigned ch_no,
				    enum dma_event_q queue_no)
{
	int bit = (ch_no & 0x7) * 4;

	/* default to low priority queue */
	if (queue_no == EVENTQ_DEFAULT)
		queue_no = ecc->default_queue;

	queue_no &= 7;
	edma_modify_array(ecc, EDMA_DMAQNUM, (ch_no >> 3), ~(0x7 << bit),
			  queue_no << bit);
}

static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no,
					  int priority)
{
	int bit = queue_no * 4;

	edma_modify(ecc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit));
}

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static void edma_set_chmap(struct edma_cc *ecc, int channel, int slot)
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{
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	if (ecc->chmap_exist) {
		channel = EDMA_CHAN_SLOT(channel);
		slot = EDMA_CHAN_SLOT(slot);
		edma_write_array(ecc, EDMA_DCHMAP, channel, (slot << 5));
	}
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}

static int prepare_unused_channel_list(struct device *dev, void *data)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct edma_cc *ecc = data;
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	int dma_req_min = EDMA_CTLR_CHAN(ecc->id, 0);
	int dma_req_max = dma_req_min + ecc->num_channels;
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	int i, count;
	struct of_phandle_args  dma_spec;

	if (dev->of_node) {
		struct platform_device *dma_pdev;

		count = of_property_count_strings(dev->of_node, "dma-names");
		if (count < 0)
			return 0;
		for (i = 0; i < count; i++) {
			if (of_parse_phandle_with_args(dev->of_node, "dmas",
						       "#dma-cells", i,
						       &dma_spec))
				continue;

			if (!of_match_node(edma_of_ids, dma_spec.np)) {
				of_node_put(dma_spec.np);
				continue;
			}

			dma_pdev = of_find_device_by_node(dma_spec.np);
			if (&dma_pdev->dev != ecc->dev)
				continue;

			clear_bit(EDMA_CHAN_SLOT(dma_spec.args[0]),
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				  ecc->channel_unused);
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			of_node_put(dma_spec.np);
		}
		return 0;
	}

	/* For non-OF case */
	for (i = 0; i < pdev->num_resources; i++) {
		struct resource	*res = &pdev->resource[i];
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		int dma_req;
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		if (!(res->flags & IORESOURCE_DMA))
			continue;

		dma_req = (int)res->start;
		if (dma_req >= dma_req_min && dma_req < dma_req_max)
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			clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
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				  ecc->channel_unused);
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	}

	return 0;
}

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static void edma_setup_interrupt(struct edma_cc *ecc, unsigned lch, bool enable)
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{
	lch = EDMA_CHAN_SLOT(lch);

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	if (enable) {
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		edma_shadow0_write_array(ecc, SH_ICR, lch >> 5,
					 BIT(lch & 0x1f));
		edma_shadow0_write_array(ecc, SH_IESR, lch >> 5,
					 BIT(lch & 0x1f));
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	} else {
		edma_shadow0_write_array(ecc, SH_IECR, lch >> 5,
					 BIT(lch & 0x1f));
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	}
}

/*
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 * paRAM slot management functions
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 */
static void edma_write_slot(struct edma_cc *ecc, unsigned slot,
			    const struct edmacc_param *param)
{
	slot = EDMA_CHAN_SLOT(slot);
	if (slot >= ecc->num_slots)
		return;
	memcpy_toio(ecc->base + PARM_OFFSET(slot), param, PARM_SIZE);
}

static void edma_read_slot(struct edma_cc *ecc, unsigned slot,
			   struct edmacc_param *param)
{
	slot = EDMA_CHAN_SLOT(slot);
	if (slot >= ecc->num_slots)
		return;
	memcpy_fromio(param, ecc->base + PARM_OFFSET(slot), PARM_SIZE);
}

/**
 * edma_alloc_slot - allocate DMA parameter RAM
 * @ecc: pointer to edma_cc struct
 * @slot: specific slot to allocate; negative for "any unused slot"
 *
 * This allocates a parameter RAM slot, initializing it to hold a
 * dummy transfer.  Slots allocated using this routine have not been
 * mapped to a hardware DMA channel, and will normally be used by
 * linking to them from a slot associated with a DMA channel.
 *
 * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
 * slots may be allocated on behalf of DSP firmware.
 *
 * Returns the number of the slot, else negative errno.
 */
static int edma_alloc_slot(struct edma_cc *ecc, int slot)
{
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	if (slot > 0) {
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		slot = EDMA_CHAN_SLOT(slot);
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		/* Requesting entry paRAM slot for a HW triggered channel. */
		if (ecc->chmap_exist && slot < ecc->num_channels)
			slot = EDMA_SLOT_ANY;
	}

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	if (slot < 0) {
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		if (ecc->chmap_exist)
			slot = 0;
		else
			slot = ecc->num_channels;
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		for (;;) {
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			slot = find_next_zero_bit(ecc->slot_inuse,
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						  ecc->num_slots,
						  slot);
			if (slot == ecc->num_slots)
				return -ENOMEM;
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			if (!test_and_set_bit(slot, ecc->slot_inuse))
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				break;
		}
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	} else if (slot >= ecc->num_slots) {
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		return -EINVAL;
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	} else if (test_and_set_bit(slot, ecc->slot_inuse)) {
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		return -EBUSY;
	}

	edma_write_slot(ecc, slot, &dummy_paramset);

	return EDMA_CTLR_CHAN(ecc->id, slot);
}

static void edma_free_slot(struct edma_cc *ecc, unsigned slot)
{
	slot = EDMA_CHAN_SLOT(slot);
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	if (slot >= ecc->num_slots)
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		return;

	edma_write_slot(ecc, slot, &dummy_paramset);
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	clear_bit(slot, ecc->slot_inuse);
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}

/**
 * edma_link - link one parameter RAM slot to another
 * @ecc: pointer to edma_cc struct
 * @from: parameter RAM slot originating the link
 * @to: parameter RAM slot which is the link target
 *
 * The originating slot should not be part of any active DMA transfer.
 */
static void edma_link(struct edma_cc *ecc, unsigned from, unsigned to)
{
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	if (unlikely(EDMA_CTLR(from) != EDMA_CTLR(to)))
		dev_warn(ecc->dev, "Ignoring eDMA instance for linking\n");

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	from = EDMA_CHAN_SLOT(from);
	to = EDMA_CHAN_SLOT(to);
	if (from >= ecc->num_slots || to >= ecc->num_slots)
		return;

	edma_parm_modify(ecc, PARM_LINK_BCNTRLD, from, 0xffff0000,
			 PARM_OFFSET(to));
}

/**
 * edma_get_position - returns the current transfer point
 * @ecc: pointer to edma_cc struct
 * @slot: parameter RAM slot being examined
 * @dst:  true selects the dest position, false the source
 *
 * Returns the position of the current active slot
 */
static dma_addr_t edma_get_position(struct edma_cc *ecc, unsigned slot,
				    bool dst)
{
	u32 offs;

	slot = EDMA_CHAN_SLOT(slot);
	offs = PARM_OFFSET(slot);
	offs += dst ? PARM_DST : PARM_SRC;

	return edma_read(ecc, offs);
}

/*-----------------------------------------------------------------------*/
/**
 * edma_start - start dma on a channel
 * @ecc: pointer to edma_cc struct
 * @channel: channel being activated
 *
 * Channels with event associations will be triggered by their hardware
 * events, and channels without such associations will be triggered by
 * software.  (At this writing there is no interface for using software
 * triggers except with channels that don't support hardware triggers.)
 *
 * Returns zero on success, else negative errno.
 */
static int edma_start(struct edma_cc *ecc, unsigned channel)
{
	if (ecc->id != EDMA_CTLR(channel)) {
		dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
			ecc->id, EDMA_CTLR(channel));
		return -EINVAL;
	}
	channel = EDMA_CHAN_SLOT(channel);

	if (channel < ecc->num_channels) {
		int j = channel >> 5;
		unsigned int mask = BIT(channel & 0x1f);

		/* EDMA channels without event association */
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		if (test_bit(channel, ecc->channel_unused)) {
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			dev_dbg(ecc->dev, "ESR%d %08x\n", j,
				edma_shadow0_read_array(ecc, SH_ESR, j));
646 647 648 649 650
			edma_shadow0_write_array(ecc, SH_ESR, j, mask);
			return 0;
		}

		/* EDMA channel with event association */
651 652
		dev_dbg(ecc->dev, "ER%d %08x\n", j,
			edma_shadow0_read_array(ecc, SH_ER, j));
653 654 655 656 657 658
		/* Clear any pending event or error */
		edma_write_array(ecc, EDMA_ECR, j, mask);
		edma_write_array(ecc, EDMA_EMCR, j, mask);
		/* Clear any SER */
		edma_shadow0_write_array(ecc, SH_SECR, j, mask);
		edma_shadow0_write_array(ecc, SH_EESR, j, mask);
659 660
		dev_dbg(ecc->dev, "EER%d %08x\n", j,
			edma_shadow0_read_array(ecc, SH_EER, j));
661 662 663 664 665 666 667 668 669 670 671
		return 0;
	}

	return -EINVAL;
}

/**
 * edma_stop - stops dma on the channel passed
 * @ecc: pointer to edma_cc struct
 * @channel: channel being deactivated
 *
672 673 674
 * Any active transfer is paused and all pending hardware events are cleared.
 * The current transfer may not be resumed, and the channel's Parameter RAM
 * should be reinitialized before being reused.
675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696
 */
static void edma_stop(struct edma_cc *ecc, unsigned channel)
{
	if (ecc->id != EDMA_CTLR(channel)) {
		dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
			ecc->id, EDMA_CTLR(channel));
		return;
	}
	channel = EDMA_CHAN_SLOT(channel);

	if (channel < ecc->num_channels) {
		int j = channel >> 5;
		unsigned int mask = BIT(channel & 0x1f);

		edma_shadow0_write_array(ecc, SH_EECR, j, mask);
		edma_shadow0_write_array(ecc, SH_ECR, j, mask);
		edma_shadow0_write_array(ecc, SH_SECR, j, mask);
		edma_write_array(ecc, EDMA_EMCR, j, mask);

		/* clear possibly pending completion interrupt */
		edma_shadow0_write_array(ecc, SH_ICR, j, mask);

697 698
		dev_dbg(ecc->dev, "EER%d %08x\n", j,
			edma_shadow0_read_array(ecc, SH_EER, j));
699 700 701 702 703 704 705

		/* REVISIT:  consider guarding against inappropriate event
		 * chaining by overwriting with dummy_paramset.
		 */
	}
}

706 707 708
/*
 * Temporarily disable EDMA hardware events on the specified channel,
 * preventing them from triggering new transfers
709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725
 */
static void edma_pause(struct edma_cc *ecc, unsigned channel)
{
	if (ecc->id != EDMA_CTLR(channel)) {
		dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
			ecc->id, EDMA_CTLR(channel));
		return;
	}
	channel = EDMA_CHAN_SLOT(channel);

	if (channel < ecc->num_channels) {
		unsigned int mask = BIT(channel & 0x1f);

		edma_shadow0_write_array(ecc, SH_EECR, channel >> 5, mask);
	}
}

726
/* Re-enable EDMA hardware events on the specified channel.  */
727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756
static void edma_resume(struct edma_cc *ecc, unsigned channel)
{
	if (ecc->id != EDMA_CTLR(channel)) {
		dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
			ecc->id, EDMA_CTLR(channel));
		return;
	}
	channel = EDMA_CHAN_SLOT(channel);

	if (channel < ecc->num_channels) {
		unsigned int mask = BIT(channel & 0x1f);

		edma_shadow0_write_array(ecc, SH_EESR, channel >> 5, mask);
	}
}

static int edma_trigger_channel(struct edma_cc *ecc, unsigned channel)
{
	unsigned int mask;

	if (ecc->id != EDMA_CTLR(channel)) {
		dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
			ecc->id, EDMA_CTLR(channel));
		return -EINVAL;
	}
	channel = EDMA_CHAN_SLOT(channel);
	mask = BIT(channel & 0x1f);

	edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask);

757 758
	dev_dbg(ecc->dev, "ESR%d %08x\n", (channel >> 5),
		edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5)));
759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774
	return 0;
}

static void edma_clean_channel(struct edma_cc *ecc, unsigned channel)
{
	if (ecc->id != EDMA_CTLR(channel)) {
		dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
			ecc->id, EDMA_CTLR(channel));
		return;
	}
	channel = EDMA_CHAN_SLOT(channel);

	if (channel < ecc->num_channels) {
		int j = (channel >> 5);
		unsigned int mask = BIT(channel & 0x1f);

775 776
		dev_dbg(ecc->dev, "EMR%d %08x\n", j,
			edma_read_array(ecc, EDMA_EMR, j));
777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815
		edma_shadow0_write_array(ecc, SH_ECR, j, mask);
		/* Clear the corresponding EMR bits */
		edma_write_array(ecc, EDMA_EMCR, j, mask);
		/* Clear any SER */
		edma_shadow0_write_array(ecc, SH_SECR, j, mask);
		edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
	}
}

/**
 * edma_alloc_channel - allocate DMA channel and paired parameter RAM
 * @ecc: pointer to edma_cc struct
 * @channel: specific channel to allocate; negative for "any unmapped channel"
 * @eventq_no: an EVENTQ_* constant, used to choose which Transfer
 *	Controller (TC) executes requests using this channel.  Use
 *	EVENTQ_DEFAULT unless you really need a high priority queue.
 *
 * This allocates a DMA channel and its associated parameter RAM slot.
 * The parameter RAM is initialized to hold a dummy transfer.
 *
 * Normal use is to pass a specific channel number as @channel, to make
 * use of hardware events mapped to that channel.  When the channel will
 * be used only for software triggering or event chaining, channels not
 * mapped to hardware events (or mapped to unused events) are preferable.
 *
 * DMA transfers start from a channel using edma_start(), or by
 * chaining.  When the transfer described in that channel's parameter RAM
 * slot completes, that slot's data may be reloaded through a link.
 *
 * DMA errors are only reported to the @callback associated with the
 * channel driving that transfer, but transfer completion callbacks can
 * be sent to another channel under control of the TCC field in
 * the option word of the transfer's parameter RAM set.  Drivers must not
 * use DMA transfer completion callbacks for channels they did not allocate.
 * (The same applies to TCC codes used in transfer chaining.)
 *
 * Returns the number of the channel, else negative errno.
 */
static int edma_alloc_channel(struct edma_cc *ecc, int channel,
816
			      enum dma_event_q eventq_no)
817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843
{
	int ret = 0;

	if (!ecc->unused_chan_list_done) {
		/*
		 * Scan all the platform devices to find out the EDMA channels
		 * used and clear them in the unused list, making the rest
		 * available for ARM usage.
		 */
		ret = bus_for_each_dev(&platform_bus_type, NULL, ecc,
				       prepare_unused_channel_list);
		if (ret < 0)
			return ret;

		ecc->unused_chan_list_done = true;
	}

	if (channel >= 0) {
		if (ecc->id != EDMA_CTLR(channel)) {
			dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n",
				__func__, ecc->id, EDMA_CTLR(channel));
			return -EINVAL;
		}
		channel = EDMA_CHAN_SLOT(channel);
	}

	if (channel < 0) {
844 845 846 847
		channel = find_next_bit(ecc->channel_unused, ecc->num_channels,
					0);
		if (channel == ecc->num_channels)
			return -EBUSY;
848 849 850 851 852 853 854 855 856 857
	} else if (channel >= ecc->num_channels) {
		return -EINVAL;
	}

	/* ensure access through shadow region 0 */
	edma_or_array2(ecc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));

	/* ensure no events are pending */
	edma_stop(ecc, EDMA_CTLR_CHAN(ecc->id, channel));

858
	edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, channel), true);
859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889

	edma_map_dmach_to_queue(ecc, channel, eventq_no);

	return EDMA_CTLR_CHAN(ecc->id, channel);
}

/**
 * edma_free_channel - deallocate DMA channel
 * @ecc: pointer to edma_cc struct
 * @channel: dma channel returned from edma_alloc_channel()
 *
 * This deallocates the DMA channel and associated parameter RAM slot
 * allocated by edma_alloc_channel().
 *
 * Callers are responsible for ensuring the channel is inactive, and
 * will not be reactivated by linking, chaining, or software calls to
 * edma_start().
 */
static void edma_free_channel(struct edma_cc *ecc, unsigned channel)
{
	if (ecc->id != EDMA_CTLR(channel)) {
		dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
			ecc->id, EDMA_CTLR(channel));
		return;
	}
	channel = EDMA_CHAN_SLOT(channel);

	if (channel >= ecc->num_channels)
		return;

	/* REVISIT should probably take out of shadow region 0 */
890
	edma_setup_interrupt(ecc, channel, false);
891 892
}

893
/* Move channel to a specific event queue */
894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915
static void edma_assign_channel_eventq(struct edma_cc *ecc, unsigned channel,
				       enum dma_event_q eventq_no)
{
	if (ecc->id != EDMA_CTLR(channel)) {
		dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
			ecc->id, EDMA_CTLR(channel));
		return;
	}
	channel = EDMA_CHAN_SLOT(channel);

	if (channel >= ecc->num_channels)
		return;

	/* default to low priority queue */
	if (eventq_no == EVENTQ_DEFAULT)
		eventq_no = ecc->default_queue;
	if (eventq_no >= ecc->num_tc)
		return;

	edma_map_dmach_to_queue(ecc, channel, eventq_no);
}

916 917 918 919 920 921 922 923 924 925
static inline struct edma_cc *to_edma_cc(struct dma_device *d)
{
	return container_of(d, struct edma_cc, dma_slave);
}

static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
{
	return container_of(c, struct edma_chan, vchan.chan);
}

926
static inline struct edma_desc *to_edma_desc(struct dma_async_tx_descriptor *tx)
927 928 929 930 931 932 933 934 935 936 937 938
{
	return container_of(tx, struct edma_desc, vdesc.tx);
}

static void edma_desc_free(struct virt_dma_desc *vdesc)
{
	kfree(container_of(vdesc, struct edma_desc, vdesc));
}

/* Dispatch a queued descriptor to the controller (caller holds lock) */
static void edma_execute(struct edma_chan *echan)
{
939
	struct edma_cc *ecc = echan->ecc;
940
	struct virt_dma_desc *vdesc;
941
	struct edma_desc *edesc;
942 943 944
	struct device *dev = echan->vchan.chan.device->dev;
	int i, j, left, nslots;

945 946
	if (!echan->edesc) {
		/* Setup is needed for the first transfer */
947
		vdesc = vchan_next_desc(&echan->vchan);
948
		if (!vdesc)
949 950 951
			return;
		list_del(&vdesc->node);
		echan->edesc = to_edma_desc(&vdesc->tx);
952 953
	}

954
	edesc = echan->edesc;
955

956 957 958
	/* Find out how many left */
	left = edesc->pset_nr - edesc->processed;
	nslots = min(MAX_NR_SG, left);
959
	edesc->sg_len = 0;
960 961

	/* Write descriptor PaRAM set(s) */
962 963
	for (i = 0; i < nslots; i++) {
		j = i + edesc->processed;
964
		edma_write_slot(ecc, echan->slot[i], &edesc->pset[j].param);
965
		edesc->sg_len += edesc->pset[j].len;
966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986
		dev_vdbg(dev,
			 "\n pset[%d]:\n"
			 "  chnum\t%d\n"
			 "  slot\t%d\n"
			 "  opt\t%08x\n"
			 "  src\t%08x\n"
			 "  dst\t%08x\n"
			 "  abcnt\t%08x\n"
			 "  ccnt\t%08x\n"
			 "  bidx\t%08x\n"
			 "  cidx\t%08x\n"
			 "  lkrld\t%08x\n",
			 j, echan->ch_num, echan->slot[i],
			 edesc->pset[j].param.opt,
			 edesc->pset[j].param.src,
			 edesc->pset[j].param.dst,
			 edesc->pset[j].param.a_b_cnt,
			 edesc->pset[j].param.ccnt,
			 edesc->pset[j].param.src_dst_bidx,
			 edesc->pset[j].param.src_dst_cidx,
			 edesc->pset[j].param.link_bcntrld);
987
		/* Link to the previous slot if not the last set */
988
		if (i != (nslots - 1))
989
			edma_link(ecc, echan->slot[i], echan->slot[i + 1]);
990 991
	}

992 993
	edesc->processed += nslots;

994 995 996 997 998
	/*
	 * If this is either the last set in a set of SG-list transactions
	 * then setup a link to the dummy slot, this results in all future
	 * events being absorbed and that's OK because we're done
	 */
999 1000
	if (edesc->processed == edesc->pset_nr) {
		if (edesc->cyclic)
1001
			edma_link(ecc, echan->slot[nslots - 1], echan->slot[1]);
1002
		else
1003
			edma_link(ecc, echan->slot[nslots - 1],
1004 1005
				  echan->ecc->dummy_slot);
	}
1006

1007
	if (echan->missed) {
1008 1009 1010 1011 1012
		/*
		 * This happens due to setup times between intermediate
		 * transfers in long SG lists which have to be broken up into
		 * transfers of MAX_NR_SG
		 */
1013
		dev_dbg(dev, "missed event on channel %d\n", echan->ch_num);
1014 1015 1016 1017
		edma_clean_channel(ecc, echan->ch_num);
		edma_stop(ecc, echan->ch_num);
		edma_start(ecc, echan->ch_num);
		edma_trigger_channel(ecc, echan->ch_num);
1018
		echan->missed = 0;
1019 1020 1021
	} else if (edesc->processed <= MAX_NR_SG) {
		dev_dbg(dev, "first transfer starting on channel %d\n",
			echan->ch_num);
1022
		edma_start(ecc, echan->ch_num);
1023 1024 1025
	} else {
		dev_dbg(dev, "chan: %d: completed %d elements, resuming\n",
			echan->ch_num, edesc->processed);
1026
		edma_resume(ecc, echan->ch_num);
1027
	}
1028 1029
}

1030
static int edma_terminate_all(struct dma_chan *chan)
1031
{
1032
	struct edma_chan *echan = to_edma_chan(chan);
1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043
	unsigned long flags;
	LIST_HEAD(head);

	spin_lock_irqsave(&echan->vchan.lock, flags);

	/*
	 * Stop DMA activity: we assume the callback will not be called
	 * after edma_dma() returns (even if it does, it will see
	 * echan->edesc is NULL and exit.)
	 */
	if (echan->edesc) {
1044
		edma_stop(echan->ecc, echan->ch_num);
1045 1046
		/* Move the cyclic channel back to default queue */
		if (echan->edesc->cyclic)
1047
			edma_assign_channel_eventq(echan->ecc, echan->ch_num,
1048
						   EVENTQ_DEFAULT);
1049 1050 1051 1052 1053
		/*
		 * free the running request descriptor
		 * since it is not in any of the vdesc lists
		 */
		edma_desc_free(&echan->edesc->vdesc);
1054 1055 1056 1057 1058 1059 1060 1061 1062 1063
		echan->edesc = NULL;
	}

	vchan_get_all_descriptors(&echan->vchan, &head);
	spin_unlock_irqrestore(&echan->vchan.lock, flags);
	vchan_dma_desc_free_list(&echan->vchan, &head);

	return 0;
}

1064
static int edma_slave_config(struct dma_chan *chan,
1065
	struct dma_slave_config *cfg)
1066
{
1067 1068
	struct edma_chan *echan = to_edma_chan(chan);

1069 1070
	if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
	    cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
1071 1072
		return -EINVAL;

1073
	memcpy(&echan->cfg, cfg, sizeof(echan->cfg));
1074 1075 1076 1077

	return 0;
}

1078
static int edma_dma_pause(struct dma_chan *chan)
1079
{
1080 1081
	struct edma_chan *echan = to_edma_chan(chan);

1082
	if (!echan->edesc)
1083 1084
		return -EINVAL;

1085
	edma_pause(echan->ecc, echan->ch_num);
1086 1087 1088
	return 0;
}

1089
static int edma_dma_resume(struct dma_chan *chan)
1090
{
1091 1092
	struct edma_chan *echan = to_edma_chan(chan);

1093
	edma_resume(echan->ecc, echan->ch_num);
1094 1095 1096
	return 0;
}

1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107
/*
 * A PaRAM set configuration abstraction used by other modes
 * @chan: Channel who's PaRAM set we're configuring
 * @pset: PaRAM set to initialize and setup.
 * @src_addr: Source address of the DMA
 * @dst_addr: Destination address of the DMA
 * @burst: In units of dev_width, how much to send
 * @dev_width: How much is the dev_width
 * @dma_length: Total length of the DMA transfer
 * @direction: Direction of the transfer
 */
1108
static int edma_config_pset(struct dma_chan *chan, struct edma_pset *epset,
1109 1110 1111 1112
			    dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst,
			    enum dma_slave_buswidth dev_width,
			    unsigned int dma_length,
			    enum dma_transfer_direction direction)
1113 1114 1115
{
	struct edma_chan *echan = to_edma_chan(chan);
	struct device *dev = chan->device->dev;
1116
	struct edmacc_param *param = &epset->param;
1117 1118 1119 1120 1121
	int acnt, bcnt, ccnt, cidx;
	int src_bidx, dst_bidx, src_cidx, dst_cidx;
	int absync;

	acnt = dev_width;
1122 1123 1124 1125

	/* src/dst_maxburst == 0 is the same case as src/dst_maxburst == 1 */
	if (!burst)
		burst = 1;
1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175
	/*
	 * If the maxburst is equal to the fifo width, use
	 * A-synced transfers. This allows for large contiguous
	 * buffer transfers using only one PaRAM set.
	 */
	if (burst == 1) {
		/*
		 * For the A-sync case, bcnt and ccnt are the remainder
		 * and quotient respectively of the division of:
		 * (dma_length / acnt) by (SZ_64K -1). This is so
		 * that in case bcnt over flows, we have ccnt to use.
		 * Note: In A-sync tranfer only, bcntrld is used, but it
		 * only applies for sg_dma_len(sg) >= SZ_64K.
		 * In this case, the best way adopted is- bccnt for the
		 * first frame will be the remainder below. Then for
		 * every successive frame, bcnt will be SZ_64K-1. This
		 * is assured as bcntrld = 0xffff in end of function.
		 */
		absync = false;
		ccnt = dma_length / acnt / (SZ_64K - 1);
		bcnt = dma_length / acnt - ccnt * (SZ_64K - 1);
		/*
		 * If bcnt is non-zero, we have a remainder and hence an
		 * extra frame to transfer, so increment ccnt.
		 */
		if (bcnt)
			ccnt++;
		else
			bcnt = SZ_64K - 1;
		cidx = acnt;
	} else {
		/*
		 * If maxburst is greater than the fifo address_width,
		 * use AB-synced transfers where A count is the fifo
		 * address_width and B count is the maxburst. In this
		 * case, we are limited to transfers of C count frames
		 * of (address_width * maxburst) where C count is limited
		 * to SZ_64K-1. This places an upper bound on the length
		 * of an SG segment that can be handled.
		 */
		absync = true;
		bcnt = burst;
		ccnt = dma_length / (acnt * bcnt);
		if (ccnt > (SZ_64K - 1)) {
			dev_err(dev, "Exceeded max SG segment size\n");
			return -EINVAL;
		}
		cidx = acnt * bcnt;
	}

1176 1177
	epset->len = dma_length;

1178 1179 1180 1181 1182
	if (direction == DMA_MEM_TO_DEV) {
		src_bidx = acnt;
		src_cidx = cidx;
		dst_bidx = 0;
		dst_cidx = 0;
1183
		epset->addr = src_addr;
1184 1185 1186 1187 1188
	} else if (direction == DMA_DEV_TO_MEM)  {
		src_bidx = 0;
		src_cidx = 0;
		dst_bidx = acnt;
		dst_cidx = cidx;
1189
		epset->addr = dst_addr;
1190 1191 1192 1193 1194
	} else if (direction == DMA_MEM_TO_MEM)  {
		src_bidx = acnt;
		src_cidx = cidx;
		dst_bidx = acnt;
		dst_cidx = cidx;
1195 1196 1197 1198 1199
	} else {
		dev_err(dev, "%s: direction not implemented yet\n", __func__);
		return -EINVAL;
	}

1200
	param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
1201 1202
	/* Configure A or AB synchronized transfers */
	if (absync)
1203
		param->opt |= SYNCDIM;
1204

1205 1206
	param->src = src_addr;
	param->dst = dst_addr;
1207

1208 1209
	param->src_dst_bidx = (dst_bidx << 16) | src_bidx;
	param->src_dst_cidx = (dst_cidx << 16) | src_cidx;
1210

1211 1212
	param->a_b_cnt = bcnt << 16 | acnt;
	param->ccnt = ccnt;
1213 1214 1215 1216 1217 1218
	/*
	 * Only time when (bcntrld) auto reload is required is for
	 * A-sync case, and in this case, a requirement of reload value
	 * of SZ_64K-1 only is assured. 'link' is initially set to NULL
	 * and then later will be populated by edma_execute.
	 */
1219
	param->link_bcntrld = 0xffffffff;
1220 1221 1222
	return absync;
}

1223 1224 1225 1226 1227 1228 1229 1230
static struct dma_async_tx_descriptor *edma_prep_slave_sg(
	struct dma_chan *chan, struct scatterlist *sgl,
	unsigned int sg_len, enum dma_transfer_direction direction,
	unsigned long tx_flags, void *context)
{
	struct edma_chan *echan = to_edma_chan(chan);
	struct device *dev = chan->device->dev;
	struct edma_desc *edesc;
1231
	dma_addr_t src_addr = 0, dst_addr = 0;
1232 1233
	enum dma_slave_buswidth dev_width;
	u32 burst;
1234
	struct scatterlist *sg;
1235
	int i, nslots, ret;
1236 1237 1238 1239

	if (unlikely(!echan || !sgl || !sg_len))
		return NULL;

1240
	if (direction == DMA_DEV_TO_MEM) {
1241
		src_addr = echan->cfg.src_addr;
1242 1243 1244
		dev_width = echan->cfg.src_addr_width;
		burst = echan->cfg.src_maxburst;
	} else if (direction == DMA_MEM_TO_DEV) {
1245
		dst_addr = echan->cfg.dst_addr;
1246 1247 1248
		dev_width = echan->cfg.dst_addr_width;
		burst = echan->cfg.dst_maxburst;
	} else {
1249
		dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
1250 1251 1252 1253
		return NULL;
	}

	if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
1254
		dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
1255 1256 1257
		return NULL;
	}

1258 1259
	edesc = kzalloc(sizeof(*edesc) + sg_len * sizeof(edesc->pset[0]),
			GFP_ATOMIC);
1260
	if (!edesc) {
1261
		dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__);
1262 1263 1264 1265
		return NULL;
	}

	edesc->pset_nr = sg_len;
1266
	edesc->residue = 0;
1267
	edesc->direction = direction;
1268
	edesc->echan = echan;
1269

1270 1271 1272 1273
	/* Allocate a PaRAM slot, if needed */
	nslots = min_t(unsigned, MAX_NR_SG, sg_len);

	for (i = 0; i < nslots; i++) {
1274 1275
		if (echan->slot[i] < 0) {
			echan->slot[i] =
1276
				edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY);
1277
			if (echan->slot[i] < 0) {
V
Valentin Ilie 已提交
1278
				kfree(edesc);
1279 1280
				dev_err(dev, "%s: Failed to allocate slot\n",
					__func__);
1281 1282 1283
				return NULL;
			}
		}
1284 1285 1286 1287
	}

	/* Configure PaRAM sets for each SG */
	for_each_sg(sgl, sg, sg_len, i) {
1288 1289 1290 1291 1292
		/* Get address for each SG */
		if (direction == DMA_DEV_TO_MEM)
			dst_addr = sg_dma_address(sg);
		else
			src_addr = sg_dma_address(sg);
1293

1294 1295 1296
		ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
				       dst_addr, burst, dev_width,
				       sg_dma_len(sg), direction);
V
Vinod Koul 已提交
1297 1298
		if (ret < 0) {
			kfree(edesc);
1299
			return NULL;
1300 1301
		}

1302
		edesc->absync = ret;
1303
		edesc->residue += sg_dma_len(sg);
1304 1305 1306 1307

		/* If this is the last in a current SG set of transactions,
		   enable interrupts so that next set is processed */
		if (!((i+1) % MAX_NR_SG))
1308
			edesc->pset[i].param.opt |= TCINTEN;
1309

1310 1311
		/* If this is the last set, enable completion interrupt flag */
		if (i == sg_len - 1)
1312
			edesc->pset[i].param.opt |= TCINTEN;
1313
	}
1314
	edesc->residue_stat = edesc->residue;
1315 1316 1317 1318

	return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
}

1319
static struct dma_async_tx_descriptor *edma_prep_dma_memcpy(
1320 1321 1322 1323 1324 1325 1326
	struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
	size_t len, unsigned long tx_flags)
{
	int ret;
	struct edma_desc *edesc;
	struct device *dev = chan->device->dev;
	struct edma_chan *echan = to_edma_chan(chan);
1327
	unsigned int width;
1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339

	if (unlikely(!echan || !len))
		return NULL;

	edesc = kzalloc(sizeof(*edesc) + sizeof(edesc->pset[0]), GFP_ATOMIC);
	if (!edesc) {
		dev_dbg(dev, "Failed to allocate a descriptor\n");
		return NULL;
	}

	edesc->pset_nr = 1;

1340 1341 1342 1343
	width = 1 << __ffs((src | dest | len));
	if (width > DMA_SLAVE_BUSWIDTH_64_BYTES)
		width = DMA_SLAVE_BUSWIDTH_64_BYTES;

1344
	ret = edma_config_pset(chan, &edesc->pset[0], src, dest, 1,
1345
			       width, len, DMA_MEM_TO_MEM);
1346 1347 1348 1349 1350 1351 1352 1353 1354 1355
	if (ret < 0)
		return NULL;

	edesc->absync = ret;

	/*
	 * Enable intermediate transfer chaining to re-trigger channel
	 * on completion of every TR, and enable transfer-completion
	 * interrupt on completion of the whole transfer.
	 */
1356 1357
	edesc->pset[0].param.opt |= ITCCHEN;
	edesc->pset[0].param.opt |= TCINTEN;
1358 1359 1360 1361

	return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
}

1362 1363 1364
static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
	struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
	size_t period_len, enum dma_transfer_direction direction,
1365
	unsigned long tx_flags)
1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388
{
	struct edma_chan *echan = to_edma_chan(chan);
	struct device *dev = chan->device->dev;
	struct edma_desc *edesc;
	dma_addr_t src_addr, dst_addr;
	enum dma_slave_buswidth dev_width;
	u32 burst;
	int i, ret, nslots;

	if (unlikely(!echan || !buf_len || !period_len))
		return NULL;

	if (direction == DMA_DEV_TO_MEM) {
		src_addr = echan->cfg.src_addr;
		dst_addr = buf_addr;
		dev_width = echan->cfg.src_addr_width;
		burst = echan->cfg.src_maxburst;
	} else if (direction == DMA_MEM_TO_DEV) {
		src_addr = buf_addr;
		dst_addr = echan->cfg.dst_addr;
		dev_width = echan->cfg.dst_addr_width;
		burst = echan->cfg.dst_maxburst;
	} else {
1389
		dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
1390 1391 1392 1393
		return NULL;
	}

	if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
1394
		dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415
		return NULL;
	}

	if (unlikely(buf_len % period_len)) {
		dev_err(dev, "Period should be multiple of Buffer length\n");
		return NULL;
	}

	nslots = (buf_len / period_len) + 1;

	/*
	 * Cyclic DMA users such as audio cannot tolerate delays introduced
	 * by cases where the number of periods is more than the maximum
	 * number of SGs the EDMA driver can handle at a time. For DMA types
	 * such as Slave SGs, such delays are tolerable and synchronized,
	 * but the synchronization is difficult to achieve with Cyclic and
	 * cannot be guaranteed, so we error out early.
	 */
	if (nslots > MAX_NR_SG)
		return NULL;

1416 1417
	edesc = kzalloc(sizeof(*edesc) + nslots * sizeof(edesc->pset[0]),
			GFP_ATOMIC);
1418
	if (!edesc) {
1419
		dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__);
1420 1421 1422 1423 1424
		return NULL;
	}

	edesc->cyclic = 1;
	edesc->pset_nr = nslots;
1425
	edesc->residue = edesc->residue_stat = buf_len;
1426
	edesc->direction = direction;
1427
	edesc->echan = echan;
1428

1429 1430
	dev_dbg(dev, "%s: channel=%d nslots=%d period_len=%zu buf_len=%zu\n",
		__func__, echan->ch_num, nslots, period_len, buf_len);
1431 1432 1433 1434 1435

	for (i = 0; i < nslots; i++) {
		/* Allocate a PaRAM slot, if needed */
		if (echan->slot[i] < 0) {
			echan->slot[i] =
1436
				edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY);
1437
			if (echan->slot[i] < 0) {
1438
				kfree(edesc);
1439 1440
				dev_err(dev, "%s: Failed to allocate slot\n",
					__func__);
1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453
				return NULL;
			}
		}

		if (i == nslots - 1) {
			memcpy(&edesc->pset[i], &edesc->pset[0],
			       sizeof(edesc->pset[0]));
			break;
		}

		ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
				       dst_addr, burst, dev_width, period_len,
				       direction);
1454 1455
		if (ret < 0) {
			kfree(edesc);
1456
			return NULL;
1457
		}
1458

1459 1460 1461 1462
		if (direction == DMA_DEV_TO_MEM)
			dst_addr += period_len;
		else
			src_addr += period_len;
1463

1464 1465
		dev_vdbg(dev, "%s: Configure period %d of buf:\n", __func__, i);
		dev_vdbg(dev,
1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477
			"\n pset[%d]:\n"
			"  chnum\t%d\n"
			"  slot\t%d\n"
			"  opt\t%08x\n"
			"  src\t%08x\n"
			"  dst\t%08x\n"
			"  abcnt\t%08x\n"
			"  ccnt\t%08x\n"
			"  bidx\t%08x\n"
			"  cidx\t%08x\n"
			"  lkrld\t%08x\n",
			i, echan->ch_num, echan->slot[i],
1478 1479 1480 1481 1482 1483 1484 1485
			edesc->pset[i].param.opt,
			edesc->pset[i].param.src,
			edesc->pset[i].param.dst,
			edesc->pset[i].param.a_b_cnt,
			edesc->pset[i].param.ccnt,
			edesc->pset[i].param.src_dst_bidx,
			edesc->pset[i].param.src_dst_cidx,
			edesc->pset[i].param.link_bcntrld);
1486 1487 1488 1489

		edesc->absync = ret;

		/*
1490
		 * Enable period interrupt only if it is requested
1491
		 */
1492 1493
		if (tx_flags & DMA_PREP_INTERRUPT)
			edesc->pset[i].param.opt |= TCINTEN;
1494 1495
	}

1496
	/* Place the cyclic channel to highest priority queue */
1497
	edma_assign_channel_eventq(echan->ecc, echan->ch_num, EVENTQ_0);
1498

1499 1500 1501
	return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
}

1502
static void edma_completion_handler(struct edma_chan *echan)
1503
{
1504
	struct edma_cc *ecc = echan->ecc;
1505
	struct device *dev = echan->vchan.chan.device->dev;
1506
	struct edma_desc *edesc = echan->edesc;
1507

1508 1509
	if (!edesc)
		return;
1510

1511
	spin_lock(&echan->vchan.lock);
1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578
	if (edesc->cyclic) {
		vchan_cyclic_callback(&edesc->vdesc);
		spin_unlock(&echan->vchan.lock);
		return;
	} else if (edesc->processed == edesc->pset_nr) {
		edesc->residue = 0;
		edma_stop(ecc, echan->ch_num);
		vchan_cookie_complete(&edesc->vdesc);
		echan->edesc = NULL;

		dev_dbg(dev, "Transfer completed on channel %d\n",
			echan->ch_num);
	} else {
		dev_dbg(dev, "Sub transfer completed on channel %d\n",
			echan->ch_num);

		edma_pause(ecc, echan->ch_num);

		/* Update statistics for tx_status */
		edesc->residue -= edesc->sg_len;
		edesc->residue_stat = edesc->residue;
		edesc->processed_stat = edesc->processed;
	}
	edma_execute(echan);

	spin_unlock(&echan->vchan.lock);
}

/* eDMA interrupt handler */
static irqreturn_t dma_irq_handler(int irq, void *data)
{
	struct edma_cc *ecc = data;
	int ctlr;
	u32 sh_ier;
	u32 sh_ipr;
	u32 bank;

	ctlr = ecc->id;
	if (ctlr < 0)
		return IRQ_NONE;

	dev_vdbg(ecc->dev, "dma_irq_handler\n");

	sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0);
	if (!sh_ipr) {
		sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1);
		if (!sh_ipr)
			return IRQ_NONE;
		sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1);
		bank = 1;
	} else {
		sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0);
		bank = 0;
	}

	do {
		u32 slot;
		u32 channel;

		slot = __ffs(sh_ipr);
		sh_ipr &= ~(BIT(slot));

		if (sh_ier & BIT(slot)) {
			channel = (bank << 5) | slot;
			/* Clear the corresponding IPR bits */
			edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot));
			edma_completion_handler(&ecc->slave_chans[channel]);
1579
		}
1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595
	} while (sh_ipr);

	edma_shadow0_write(ecc, SH_IEVAL, 1);
	return IRQ_HANDLED;
}

static void edma_error_handler(struct edma_chan *echan)
{
	struct edma_cc *ecc = echan->ecc;
	struct device *dev = echan->vchan.chan.device->dev;
	struct edmacc_param p;

	if (!echan->edesc)
		return;

	spin_lock(&echan->vchan.lock);
1596

1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613
	edma_read_slot(ecc, echan->slot[0], &p);
	/*
	 * Issue later based on missed flag which will be sure
	 * to happen as:
	 * (1) we finished transmitting an intermediate slot and
	 *     edma_execute is coming up.
	 * (2) or we finished current transfer and issue will
	 *     call edma_execute.
	 *
	 * Important note: issuing can be dangerous here and
	 * lead to some nasty recursion when we are in a NULL
	 * slot. So we avoid doing so and set the missed flag.
	 */
	if (p.a_b_cnt == 0 && p.ccnt == 0) {
		dev_dbg(dev, "Error on null slot, setting miss\n");
		echan->missed = 1;
	} else {
1614
		/*
1615 1616
		 * The slot is already programmed but the event got
		 * missed, so its safe to issue it here.
1617
		 */
1618 1619 1620 1621 1622 1623 1624 1625 1626
		dev_dbg(dev, "Missed event, TRIGGERING\n");
		edma_clean_channel(ecc, echan->ch_num);
		edma_stop(ecc, echan->ch_num);
		edma_start(ecc, echan->ch_num);
		edma_trigger_channel(ecc, echan->ch_num);
	}
	spin_unlock(&echan->vchan.lock);
}

1627 1628 1629 1630 1631 1632 1633 1634 1635 1636
static inline bool edma_error_pending(struct edma_cc *ecc)
{
	if (edma_read_array(ecc, EDMA_EMR, 0) ||
	    edma_read_array(ecc, EDMA_EMR, 1) ||
	    edma_read(ecc, EDMA_QEMR) || edma_read(ecc, EDMA_CCERR))
		return true;

	return false;
}

1637 1638 1639 1640
/* eDMA error interrupt handler */
static irqreturn_t dma_ccerr_handler(int irq, void *data)
{
	struct edma_cc *ecc = data;
1641
	int i, j;
1642 1643
	int ctlr;
	unsigned int cnt = 0;
1644
	unsigned int val;
1645 1646 1647 1648 1649 1650 1651

	ctlr = ecc->id;
	if (ctlr < 0)
		return IRQ_NONE;

	dev_vdbg(ecc->dev, "dma_ccerr_handler\n");

1652
	if (!edma_error_pending(ecc))
1653 1654 1655
		return IRQ_NONE;

	while (1) {
1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667
		/* Event missed register(s) */
		for (j = 0; j < 2; j++) {
			unsigned long emr;

			val = edma_read_array(ecc, EDMA_EMR, j);
			if (!val)
				continue;

			dev_dbg(ecc->dev, "EMR%d 0x%08x\n", j, val);
			emr = val;
			for (i = find_next_bit(&emr, 32, 0); i < 32;
			     i = find_next_bit(&emr, 32, i + 1)) {
1668 1669
				int k = (j << 5) + i;

1670 1671 1672 1673
				/* Clear the corresponding EMR bits */
				edma_write_array(ecc, EDMA_EMCR, j, BIT(i));
				/* Clear any SER */
				edma_shadow0_write_array(ecc, SH_SECR, j,
1674
							 BIT(i));
1675
				edma_error_handler(&ecc->slave_chans[k]);
1676
			}
1677
		}
1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693

		val = edma_read(ecc, EDMA_QEMR);
		if (val) {
			dev_dbg(ecc->dev, "QEMR 0x%02x\n", val);
			/* Not reported, just clear the interrupt reason. */
			edma_write(ecc, EDMA_QEMCR, val);
			edma_shadow0_write(ecc, SH_QSECR, val);
		}

		val = edma_read(ecc, EDMA_CCERR);
		if (val) {
			dev_warn(ecc->dev, "CCERR 0x%08x\n", val);
			/* Not reported, just clear the interrupt reason. */
			edma_write(ecc, EDMA_CCERRCLR, val);
		}

1694
		if (!edma_error_pending(ecc))
1695 1696 1697 1698
			break;
		cnt++;
		if (cnt > 10)
			break;
1699
	}
1700 1701
	edma_write(ecc, EDMA_EEVAL, 1);
	return IRQ_HANDLED;
1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712
}

/* Alloc channel resources */
static int edma_alloc_chan_resources(struct dma_chan *chan)
{
	struct edma_chan *echan = to_edma_chan(chan);
	struct device *dev = chan->device->dev;
	int ret;
	int a_ch_num;
	LIST_HEAD(descs);

1713
	a_ch_num = edma_alloc_channel(echan->ecc, echan->ch_num, EVENTQ_DEFAULT);
1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728

	if (a_ch_num < 0) {
		ret = -ENODEV;
		goto err_no_chan;
	}

	if (a_ch_num != echan->ch_num) {
		dev_err(dev, "failed to allocate requested channel %u:%u\n",
			EDMA_CTLR(echan->ch_num),
			EDMA_CHAN_SLOT(echan->ch_num));
		ret = -ENODEV;
		goto err_wrong_chan;
	}

	echan->alloced = true;
1729 1730 1731 1732 1733 1734 1735 1736 1737
	echan->slot[0] = edma_alloc_slot(echan->ecc, echan->ch_num);
	if (echan->slot[0] < 0) {
		dev_err(dev, "Entry slot allocation failed for channel %u\n",
			EDMA_CHAN_SLOT(echan->ch_num));
		goto err_wrong_chan;
	}

	/* Set up channel -> slot mapping for the entry slot */
	edma_set_chmap(echan->ecc, echan->ch_num, echan->slot[0]);
1738

1739
	dev_dbg(dev, "allocated channel %d for %u:%u\n", echan->ch_num,
1740
		EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num));
1741 1742 1743 1744

	return 0;

err_wrong_chan:
1745
	edma_free_channel(echan->ecc, a_ch_num);
1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756
err_no_chan:
	return ret;
}

/* Free channel resources */
static void edma_free_chan_resources(struct dma_chan *chan)
{
	struct edma_chan *echan = to_edma_chan(chan);
	int i;

	/* Terminate transfers */
1757
	edma_stop(echan->ecc, echan->ch_num);
1758 1759 1760 1761

	vchan_free_chan_resources(&echan->vchan);

	/* Free EDMA PaRAM slots */
1762
	for (i = 0; i < EDMA_MAX_SLOTS; i++) {
1763
		if (echan->slot[i] >= 0) {
1764
			edma_free_slot(echan->ecc, echan->slot[i]);
1765 1766 1767 1768
			echan->slot[i] = -1;
		}
	}

1769 1770 1771
	/* Set entry slot to the dummy slot */
	edma_set_chmap(echan->ecc, echan->ch_num, echan->ecc->dummy_slot);

1772 1773
	/* Free EDMA channel */
	if (echan->alloced) {
1774
		edma_free_channel(echan->ecc, echan->ch_num);
1775 1776 1777
		echan->alloced = false;
	}

1778
	dev_dbg(chan->device->dev, "freeing channel for %u\n", echan->ch_num);
1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792
}

/* Send pending descriptor to hardware */
static void edma_issue_pending(struct dma_chan *chan)
{
	struct edma_chan *echan = to_edma_chan(chan);
	unsigned long flags;

	spin_lock_irqsave(&echan->vchan.lock, flags);
	if (vchan_issue_pending(&echan->vchan) && !echan->edesc)
		edma_execute(echan);
	spin_unlock_irqrestore(&echan->vchan.lock, flags);
}

1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803
static u32 edma_residue(struct edma_desc *edesc)
{
	bool dst = edesc->direction == DMA_DEV_TO_MEM;
	struct edma_pset *pset = edesc->pset;
	dma_addr_t done, pos;
	int i;

	/*
	 * We always read the dst/src position from the first RamPar
	 * pset. That's the one which is active now.
	 */
1804
	pos = edma_get_position(edesc->echan->ecc, edesc->echan->slot[0], dst);
1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840

	/*
	 * Cyclic is simple. Just subtract pset[0].addr from pos.
	 *
	 * We never update edesc->residue in the cyclic case, so we
	 * can tell the remaining room to the end of the circular
	 * buffer.
	 */
	if (edesc->cyclic) {
		done = pos - pset->addr;
		edesc->residue_stat = edesc->residue - done;
		return edesc->residue_stat;
	}

	/*
	 * For SG operation we catch up with the last processed
	 * status.
	 */
	pset += edesc->processed_stat;

	for (i = edesc->processed_stat; i < edesc->processed; i++, pset++) {
		/*
		 * If we are inside this pset address range, we know
		 * this is the active one. Get the current delta and
		 * stop walking the psets.
		 */
		if (pos >= pset->addr && pos < pset->addr + pset->len)
			return edesc->residue_stat - (pos - pset->addr);

		/* Otherwise mark it done and update residue_stat. */
		edesc->processed_stat++;
		edesc->residue_stat -= pset->len;
	}
	return edesc->residue_stat;
}

1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851
/* Check request completion status */
static enum dma_status edma_tx_status(struct dma_chan *chan,
				      dma_cookie_t cookie,
				      struct dma_tx_state *txstate)
{
	struct edma_chan *echan = to_edma_chan(chan);
	struct virt_dma_desc *vdesc;
	enum dma_status ret;
	unsigned long flags;

	ret = dma_cookie_status(chan, cookie, txstate);
1852
	if (ret == DMA_COMPLETE || !txstate)
1853 1854 1855
		return ret;

	spin_lock_irqsave(&echan->vchan.lock, flags);
1856
	if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie)
1857
		txstate->residue = edma_residue(echan->edesc);
1858 1859
	else if ((vdesc = vchan_find_desc(&echan->vchan, cookie)))
		txstate->residue = to_edma_desc(&vdesc->tx)->residue;
1860 1861 1862 1863 1864
	spin_unlock_irqrestore(&echan->vchan.lock, flags);

	return ret;
}

1865
static void __init edma_chan_init(struct edma_cc *ecc, struct dma_device *dma,
1866 1867 1868 1869
				  struct edma_chan *echans)
{
	int i, j;

1870
	for (i = 0; i < ecc->num_channels; i++) {
1871
		struct edma_chan *echan = &echans[i];
1872
		echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i);
1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883
		echan->ecc = ecc;
		echan->vchan.desc_free = edma_desc_free;

		vchan_init(&echan->vchan, dma);

		INIT_LIST_HEAD(&echan->node);
		for (j = 0; j < EDMA_MAX_SLOTS; j++)
			echan->slot[j] = -1;
	}
}

1884 1885
#define EDMA_DMA_BUSWIDTHS	(BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
				 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
1886
				 BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \
1887 1888
				 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))

1889 1890 1891 1892
static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma,
			  struct device *dev)
{
	dma->device_prep_slave_sg = edma_prep_slave_sg;
1893
	dma->device_prep_dma_cyclic = edma_prep_dma_cyclic;
1894
	dma->device_prep_dma_memcpy = edma_prep_dma_memcpy;
1895 1896 1897 1898
	dma->device_alloc_chan_resources = edma_alloc_chan_resources;
	dma->device_free_chan_resources = edma_free_chan_resources;
	dma->device_issue_pending = edma_issue_pending;
	dma->device_tx_status = edma_tx_status;
1899 1900 1901 1902
	dma->device_config = edma_slave_config;
	dma->device_pause = edma_dma_pause;
	dma->device_resume = edma_dma_resume;
	dma->device_terminate_all = edma_terminate_all;
1903 1904 1905 1906 1907 1908

	dma->src_addr_widths = EDMA_DMA_BUSWIDTHS;
	dma->dst_addr_widths = EDMA_DMA_BUSWIDTHS;
	dma->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
	dma->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;

1909 1910 1911 1912 1913
	dma->dev = dev;

	INIT_LIST_HEAD(&dma->channels);
}

1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935
static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
			      struct edma_cc *ecc)
{
	int i;
	u32 value, cccfg;
	s8 (*queue_priority_map)[2];

	/* Decode the eDMA3 configuration from CCCFG register */
	cccfg = edma_read(ecc, EDMA_CCCFG);

	value = GET_NUM_REGN(cccfg);
	ecc->num_region = BIT(value);

	value = GET_NUM_DMACH(cccfg);
	ecc->num_channels = BIT(value + 1);

	value = GET_NUM_PAENTRY(cccfg);
	ecc->num_slots = BIT(value + 4);

	value = GET_NUM_EVQUE(cccfg);
	ecc->num_tc = value + 1;

1936 1937
	ecc->chmap_exist = (cccfg & CHMAP_EXIST) ? true : false;

1938 1939 1940 1941 1942
	dev_dbg(dev, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg);
	dev_dbg(dev, "num_region: %u\n", ecc->num_region);
	dev_dbg(dev, "num_channels: %u\n", ecc->num_channels);
	dev_dbg(dev, "num_slots: %u\n", ecc->num_slots);
	dev_dbg(dev, "num_tc: %u\n", ecc->num_tc);
1943
	dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no");
1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958

	/* Nothing need to be done if queue priority is provided */
	if (pdata->queue_priority_mapping)
		return 0;

	/*
	 * Configure TC/queue priority as follows:
	 * Q0 - priority 0
	 * Q1 - priority 1
	 * Q2 - priority 2
	 * ...
	 * The meaning of priority numbers: 0 highest priority, 7 lowest
	 * priority. So Q0 is the highest priority queue and the last queue has
	 * the lowest priority.
	 */
1959
	queue_priority_map = devm_kcalloc(dev, ecc->num_tc + 1, sizeof(s8),
1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989
					  GFP_KERNEL);
	if (!queue_priority_map)
		return -ENOMEM;

	for (i = 0; i < ecc->num_tc; i++) {
		queue_priority_map[i][0] = i;
		queue_priority_map[i][1] = i;
	}
	queue_priority_map[i][0] = -1;
	queue_priority_map[i][1] = -1;

	pdata->queue_priority_mapping = queue_priority_map;
	/* Default queue has the lowest priority */
	pdata->default_queue = i - 1;

	return 0;
}

#if IS_ENABLED(CONFIG_OF)
static int edma_xbar_event_map(struct device *dev, struct edma_soc_info *pdata,
			       size_t sz)
{
	const char pname[] = "ti,edma-xbar-event-map";
	struct resource res;
	void __iomem *xbar;
	s16 (*xbar_chans)[2];
	size_t nelm = sz / sizeof(s16);
	u32 shift, offset, mux;
	int ret, i;

1990
	xbar_chans = devm_kcalloc(dev, nelm + 2, sizeof(s16), GFP_KERNEL);
1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065
	if (!xbar_chans)
		return -ENOMEM;

	ret = of_address_to_resource(dev->of_node, 1, &res);
	if (ret)
		return -ENOMEM;

	xbar = devm_ioremap(dev, res.start, resource_size(&res));
	if (!xbar)
		return -ENOMEM;

	ret = of_property_read_u16_array(dev->of_node, pname, (u16 *)xbar_chans,
					 nelm);
	if (ret)
		return -EIO;

	/* Invalidate last entry for the other user of this mess */
	nelm >>= 1;
	xbar_chans[nelm][0] = -1;
	xbar_chans[nelm][1] = -1;

	for (i = 0; i < nelm; i++) {
		shift = (xbar_chans[i][1] & 0x03) << 3;
		offset = xbar_chans[i][1] & 0xfffffffc;
		mux = readl(xbar + offset);
		mux &= ~(0xff << shift);
		mux |= xbar_chans[i][0] << shift;
		writel(mux, (xbar + offset));
	}

	pdata->xbar_chans = (const s16 (*)[2]) xbar_chans;
	return 0;
}

static int edma_of_parse_dt(struct device *dev, struct edma_soc_info *pdata)
{
	int ret = 0;
	struct property *prop;
	size_t sz;
	struct edma_rsv_info *rsv_info;

	rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL);
	if (!rsv_info)
		return -ENOMEM;
	pdata->rsv = rsv_info;

	prop = of_find_property(dev->of_node, "ti,edma-xbar-event-map", &sz);
	if (prop)
		ret = edma_xbar_event_map(dev, pdata, sz);

	return ret;
}

static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev)
{
	struct edma_soc_info *info;
	int ret;

	info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL);
	if (!info)
		return ERR_PTR(-ENOMEM);

	ret = edma_of_parse_dt(dev, info);
	if (ret)
		return ERR_PTR(ret);

	return info;
}
#else
static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev)
{
	return ERR_PTR(-EINVAL);
}
#endif

B
Bill Pemberton 已提交
2066
static int edma_probe(struct platform_device *pdev)
2067
{
2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079
	struct edma_soc_info	*info = pdev->dev.platform_data;
	s8			(*queue_priority_mapping)[2];
	int			i, off, ln;
	const s16		(*rsv_chans)[2];
	const s16		(*rsv_slots)[2];
	const s16		(*xbar_chans)[2];
	int			irq;
	char			*irq_name;
	struct resource		*mem;
	struct device_node	*node = pdev->dev.of_node;
	struct device		*dev = &pdev->dev;
	struct edma_cc		*ecc;
2080 2081
	int ret;

2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099
	if (node) {
		info = edma_setup_info_from_dt(dev);
		if (IS_ERR(info)) {
			dev_err(dev, "failed to get DT data\n");
			return PTR_ERR(info);
		}
	}

	if (!info)
		return -ENODEV;

	pm_runtime_enable(dev);
	ret = pm_runtime_get_sync(dev);
	if (ret < 0) {
		dev_err(dev, "pm_runtime_get_sync() failed\n");
		return ret;
	}

2100
	ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
2101 2102 2103
	if (ret)
		return ret;

2104
	ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
2105
	if (!ecc) {
2106
		dev_err(dev, "Can't allocate controller\n");
2107 2108 2109
		return -ENOMEM;
	}

2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135
	ecc->dev = dev;
	ecc->id = pdev->id;
	/* When booting with DT the pdev->id is -1 */
	if (ecc->id < 0)
		ecc->id = 0;

	mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma3_cc");
	if (!mem) {
		dev_dbg(dev, "mem resource not found, using index 0\n");
		mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		if (!mem) {
			dev_err(dev, "no mem resource?\n");
			return -ENODEV;
		}
	}
	ecc->base = devm_ioremap_resource(dev, mem);
	if (IS_ERR(ecc->base))
		return PTR_ERR(ecc->base);

	platform_set_drvdata(pdev, ecc);

	/* Get eDMA3 configuration from IP */
	ret = edma_setup_from_hw(dev, info, ecc);
	if (ret)
		return ret;

2136 2137 2138 2139 2140 2141
	/* Allocate memory based on the information we got from the IP */
	ecc->slave_chans = devm_kcalloc(dev, ecc->num_channels,
					sizeof(*ecc->slave_chans), GFP_KERNEL);
	if (!ecc->slave_chans)
		return -ENOMEM;

2142 2143 2144 2145
	ecc->channel_unused = devm_kcalloc(dev,
					   BITS_TO_LONGS(ecc->num_channels),
					   sizeof(unsigned long), GFP_KERNEL);
	if (!ecc->channel_unused)
2146 2147
		return -ENOMEM;

2148
	ecc->slot_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots),
2149
				       sizeof(unsigned long), GFP_KERNEL);
2150
	if (!ecc->slot_inuse)
2151 2152
		return -ENOMEM;

2153 2154 2155 2156 2157 2158
	ecc->default_queue = info->default_queue;

	for (i = 0; i < ecc->num_slots; i++)
		edma_write_slot(ecc, i, &dummy_paramset);

	/* Mark all channels as unused */
2159
	memset(ecc->channel_unused, 0xff, sizeof(ecc->channel_unused));
2160 2161 2162 2163 2164 2165 2166 2167

	if (info->rsv) {
		/* Clear the reserved channels in unused list */
		rsv_chans = info->rsv->rsv_chans;
		if (rsv_chans) {
			for (i = 0; rsv_chans[i][0] != -1; i++) {
				off = rsv_chans[i][0];
				ln = rsv_chans[i][1];
2168
				clear_bits(off, ln, ecc->channel_unused);
2169 2170 2171 2172 2173 2174 2175 2176 2177
			}
		}

		/* Set the reserved slots in inuse list */
		rsv_slots = info->rsv->rsv_slots;
		if (rsv_slots) {
			for (i = 0; rsv_slots[i][0] != -1; i++) {
				off = rsv_slots[i][0];
				ln = rsv_slots[i][1];
2178
				set_bits(off, ln, ecc->slot_inuse);
2179 2180 2181 2182 2183 2184 2185 2186 2187
			}
		}
	}

	/* Clear the xbar mapped channels in unused list */
	xbar_chans = info->xbar_chans;
	if (xbar_chans) {
		for (i = 0; xbar_chans[i][1] != -1; i++) {
			off = xbar_chans[i][1];
2188
			clear_bits(off, 1, ecc->channel_unused);
2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221
		}
	}

	irq = platform_get_irq_byname(pdev, "edma3_ccint");
	if (irq < 0 && node)
		irq = irq_of_parse_and_map(node, 0);

	if (irq >= 0) {
		irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint",
					  dev_name(dev));
		ret = devm_request_irq(dev, irq, dma_irq_handler, 0, irq_name,
				       ecc);
		if (ret) {
			dev_err(dev, "CCINT (%d) failed --> %d\n", irq, ret);
			return ret;
		}
	}

	irq = platform_get_irq_byname(pdev, "edma3_ccerrint");
	if (irq < 0 && node)
		irq = irq_of_parse_and_map(node, 2);

	if (irq >= 0) {
		irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccerrint",
					  dev_name(dev));
		ret = devm_request_irq(dev, irq, dma_ccerr_handler, 0, irq_name,
				       ecc);
		if (ret) {
			dev_err(dev, "CCERRINT (%d) failed --> %d\n", irq, ret);
			return ret;
		}
	}

2222 2223 2224 2225 2226 2227 2228 2229
	ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY);
	if (ecc->dummy_slot < 0) {
		dev_err(dev, "Can't allocate PaRAM dummy slot\n");
		return ecc->dummy_slot;
	}

	for (i = 0; i < ecc->num_channels; i++) {
		/* Assign all channels to the default queue */
2230
		edma_map_dmach_to_queue(ecc, i, info->default_queue);
2231 2232 2233
		/* Set entry slot to the dummy slot */
		edma_set_chmap(ecc, i, ecc->dummy_slot);
	}
2234 2235 2236 2237 2238 2239 2240

	queue_priority_mapping = info->queue_priority_mapping;

	/* Event queue priority mapping */
	for (i = 0; queue_priority_mapping[i][0] != -1; i++)
		edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0],
					      queue_priority_mapping[i][1]);
2241

2242 2243 2244 2245 2246 2247 2248
	for (i = 0; i < ecc->num_region; i++) {
		edma_write_array2(ecc, EDMA_DRAE, i, 0, 0x0);
		edma_write_array2(ecc, EDMA_DRAE, i, 1, 0x0);
		edma_write_array(ecc, EDMA_QRAE, i, 0x0);
	}
	ecc->info = info;

2249 2250
	dma_cap_zero(ecc->dma_slave.cap_mask);
	dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask);
2251
	dma_cap_set(DMA_CYCLIC, ecc->dma_slave.cap_mask);
2252
	dma_cap_set(DMA_MEMCPY, ecc->dma_slave.cap_mask);
2253

2254
	edma_dma_init(ecc, &ecc->dma_slave, dev);
2255 2256 2257 2258 2259 2260 2261

	edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans);

	ret = dma_async_device_register(&ecc->dma_slave);
	if (ret)
		goto err_reg1;

2262 2263
	if (node)
		of_dma_controller_register(node, of_dma_xlate_by_chan_id,
2264
					   &ecc->dma_slave);
2265

2266
	dev_info(dev, "TI EDMA DMA engine driver\n");
2267 2268 2269 2270

	return 0;

err_reg1:
2271
	edma_free_slot(ecc, ecc->dummy_slot);
2272 2273 2274
	return ret;
}

2275
static int edma_remove(struct platform_device *pdev)
2276 2277 2278 2279
{
	struct device *dev = &pdev->dev;
	struct edma_cc *ecc = dev_get_drvdata(dev);

2280 2281
	if (dev->of_node)
		of_dma_controller_free(dev->of_node);
2282
	dma_async_device_unregister(&ecc->dma_slave);
2283
	edma_free_slot(ecc, ecc->dummy_slot);
2284 2285 2286 2287

	return 0;
}

2288 2289 2290 2291
#ifdef CONFIG_PM_SLEEP
static int edma_pm_resume(struct device *dev)
{
	struct edma_cc *ecc = dev_get_drvdata(dev);
2292
	struct edma_chan *echan = ecc->slave_chans;
2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303
	int i;
	s8 (*queue_priority_mapping)[2];

	queue_priority_mapping = ecc->info->queue_priority_mapping;

	/* Event queue priority mapping */
	for (i = 0; queue_priority_mapping[i][0] != -1; i++)
		edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0],
					      queue_priority_mapping[i][1]);

	for (i = 0; i < ecc->num_channels; i++) {
2304
		if (echan[i].alloced) {
2305 2306 2307 2308 2309
			/* ensure access through shadow region 0 */
			edma_or_array2(ecc, EDMA_DRAE, 0, i >> 5,
				       BIT(i & 0x1f));

			edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, i),
2310
					     true);
2311 2312 2313

			/* Set up channel -> slot mapping for the entry slot */
			edma_set_chmap(ecc, echan[i].ch_num, echan[i].slot[0]);
2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324
		}
	}

	return 0;
}
#endif

static const struct dev_pm_ops edma_pm_ops = {
	SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, edma_pm_resume)
};

2325 2326
static struct platform_driver edma_driver = {
	.probe		= edma_probe,
B
Bill Pemberton 已提交
2327
	.remove		= edma_remove,
2328
	.driver = {
2329 2330 2331
		.name	= "edma",
		.pm	= &edma_pm_ops,
		.of_match_table = edma_of_ids,
2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347
	},
};

bool edma_filter_fn(struct dma_chan *chan, void *param)
{
	if (chan->device->dev->driver == &edma_driver.driver) {
		struct edma_chan *echan = to_edma_chan(chan);
		unsigned ch_req = *(unsigned *)param;
		return ch_req == echan->ch_num;
	}
	return false;
}
EXPORT_SYMBOL(edma_filter_fn);

static int edma_init(void)
{
2348
	return platform_driver_register(&edma_driver);
2349 2350 2351 2352 2353 2354 2355 2356 2357
}
subsys_initcall(edma_init);

static void __exit edma_exit(void)
{
	platform_driver_unregister(&edma_driver);
}
module_exit(edma_exit);

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Josh Boyer 已提交
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MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>");
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MODULE_DESCRIPTION("TI EDMA DMA engine driver");
MODULE_LICENSE("GPL v2");