Kconfig 29.2 KB
Newer Older
L
Linus Torvalds 已提交
1 2 3 4 5 6
comment "Processor Type"

# Select CPU types depending on the architecture selected.  This selects
# which CPUs we support in the kernel image, and the compiler instruction
# optimiser behaviour.

7 8
# ARM7TDMI
config CPU_ARM7TDMI
9
	bool
10
	depends on !MMU
11 12 13
	select CPU_32v4T
	select CPU_ABRT_LV4T
	select CPU_CACHE_V4
14
	select CPU_PABRT_LEGACY
15 16 17 18 19 20 21
	help
	  A 32-bit RISC microprocessor based on the ARM7 processor core
	  which has no memory control unit and cache.

	  Say Y if you want support for the ARM7TDMI processor.
	  Otherwise, say N.

L
Linus Torvalds 已提交
22 23
# ARM720T
config CPU_ARM720T
24
	bool "Support ARM720T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
25
	select CPU_32v4T
L
Linus Torvalds 已提交
26 27 28
	select CPU_ABRT_LV4T
	select CPU_CACHE_V4
	select CPU_CACHE_VIVT
29
	select CPU_COPY_V4WT if MMU
30 31
	select CPU_CP15_MMU
	select CPU_PABRT_LEGACY
32
	select CPU_TLB_V4WT if MMU
L
Linus Torvalds 已提交
33 34 35 36 37 38 39
	help
	  A 32-bit RISC processor with 8kByte Cache, Write Buffer and
	  MMU built around an ARM7TDMI core.

	  Say Y if you want support for the ARM720T processor.
	  Otherwise, say N.

40 41
# ARM740T
config CPU_ARM740T
42
	bool "Support ARM740T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
43
	depends on !MMU
44 45
	select CPU_32v4T
	select CPU_ABRT_LV4T
46
	select CPU_CACHE_V4
47
	select CPU_CP15_MPU
48
	select CPU_PABRT_LEGACY
49 50 51 52 53 54 55 56
	help
	  A 32-bit RISC processor with 8KB cache or 4KB variants,
	  write buffer and MPU(Protection Unit) built around
	  an ARM7TDMI core.

	  Say Y if you want support for the ARM740T processor.
	  Otherwise, say N.

57 58
# ARM9TDMI
config CPU_ARM9TDMI
59
	bool
60
	depends on !MMU
61
	select CPU_32v4T
62
	select CPU_ABRT_NOMMU
63
	select CPU_CACHE_V4
64
	select CPU_PABRT_LEGACY
65 66 67 68 69 70 71
	help
	  A 32-bit RISC microprocessor based on the ARM9 processor core
	  which has no memory control unit and cache.

	  Say Y if you want support for the ARM9TDMI processor.
	  Otherwise, say N.

L
Linus Torvalds 已提交
72 73
# ARM920T
config CPU_ARM920T
74
	bool "Support ARM920T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
75
	select CPU_32v4T
L
Linus Torvalds 已提交
76 77 78
	select CPU_ABRT_EV4T
	select CPU_CACHE_V4WT
	select CPU_CACHE_VIVT
79
	select CPU_COPY_V4WB if MMU
80 81
	select CPU_CP15_MMU
	select CPU_PABRT_LEGACY
82
	select CPU_TLB_V4WBI if MMU
L
Linus Torvalds 已提交
83 84
	help
	  The ARM920T is licensed to be produced by numerous vendors,
85
	  and is used in the Cirrus EP93xx and the Samsung S3C2410.
L
Linus Torvalds 已提交
86 87 88 89 90 91

	  Say Y if you want support for the ARM920T processor.
	  Otherwise, say N.

# ARM922T
config CPU_ARM922T
92
	bool "Support ARM922T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
93
	select CPU_32v4T
L
Linus Torvalds 已提交
94 95 96
	select CPU_ABRT_EV4T
	select CPU_CACHE_V4WT
	select CPU_CACHE_VIVT
97
	select CPU_COPY_V4WB if MMU
98 99
	select CPU_CP15_MMU
	select CPU_PABRT_LEGACY
100
	select CPU_TLB_V4WBI if MMU
L
Linus Torvalds 已提交
101 102 103
	help
	  The ARM922T is a version of the ARM920T, but with smaller
	  instruction and data caches. It is used in Altera's
104
	  Excalibur XA device family and Micrel's KS8695 Centaur.
L
Linus Torvalds 已提交
105 106 107 108 109 110

	  Say Y if you want support for the ARM922T processor.
	  Otherwise, say N.

# ARM925T
config CPU_ARM925T
111
 	bool "Support ARM925T processor" if ARCH_OMAP1
112
	select CPU_32v4T
L
Linus Torvalds 已提交
113 114 115
	select CPU_ABRT_EV4T
	select CPU_CACHE_V4WT
	select CPU_CACHE_VIVT
116
	select CPU_COPY_V4WB if MMU
117 118
	select CPU_CP15_MMU
	select CPU_PABRT_LEGACY
119
	select CPU_TLB_V4WBI if MMU
L
Linus Torvalds 已提交
120 121 122 123 124 125 126 127 128 129
 	help
 	  The ARM925T is a mix between the ARM920T and ARM926T, but with
	  different instruction and data caches. It is used in TI's OMAP
 	  device family.

 	  Say Y if you want support for the ARM925T processor.
 	  Otherwise, say N.

# ARM926T
config CPU_ARM926T
130
	bool "Support ARM926T processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V5) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB)
L
Linus Torvalds 已提交
131 132 133
	select CPU_32v5
	select CPU_ABRT_EV5TJ
	select CPU_CACHE_VIVT
134
	select CPU_COPY_V4WB if MMU
135 136
	select CPU_CP15_MMU
	select CPU_PABRT_LEGACY
137
	select CPU_TLB_V4WBI if MMU
L
Linus Torvalds 已提交
138 139 140 141 142 143 144 145
	help
	  This is a variant of the ARM920.  It has slightly different
	  instruction sequences for cache and TLB operations.  Curiously,
	  there is no documentation on it at the ARM corporate website.

	  Say Y if you want support for the ARM926T processor.
	  Otherwise, say N.

P
Paulius Zaleckas 已提交
146 147 148 149 150 151
# FA526
config CPU_FA526
	bool
	select CPU_32v4
	select CPU_ABRT_EV4
	select CPU_CACHE_FA
152
	select CPU_CACHE_VIVT
P
Paulius Zaleckas 已提交
153
	select CPU_COPY_FA if MMU
154 155
	select CPU_CP15_MMU
	select CPU_PABRT_LEGACY
P
Paulius Zaleckas 已提交
156 157 158 159 160 161 162 163
	select CPU_TLB_FA if MMU
	help
	  The FA526 is a version of the ARMv4 compatible processor with
	  Branch Target Buffer, Unified TLB and cache line size 16.

	  Say Y if you want support for the FA526 processor.
	  Otherwise, say N.

164 165
# ARM940T
config CPU_ARM940T
166
	bool "Support ARM940T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
167
	depends on !MMU
168
	select CPU_32v4T
169
	select CPU_ABRT_NOMMU
170 171
	select CPU_CACHE_VIVT
	select CPU_CP15_MPU
172
	select CPU_PABRT_LEGACY
173 174
	help
	  ARM940T is a member of the ARM9TDMI family of general-
M
Matt LaPlante 已提交
175
	  purpose microprocessors with MPU and separate 4KB
176 177 178 179 180 181
	  instruction and 4KB data cases, each with a 4-word line
	  length.

	  Say Y if you want support for the ARM940T processor.
	  Otherwise, say N.

182 183
# ARM946E-S
config CPU_ARM946E
184
	bool "Support ARM946E-S processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
185
	depends on !MMU
186
	select CPU_32v5
187
	select CPU_ABRT_NOMMU
188 189
	select CPU_CACHE_VIVT
	select CPU_CP15_MPU
190
	select CPU_PABRT_LEGACY
191 192 193 194 195 196 197 198
	help
	  ARM946E-S is a member of the ARM9E-S family of high-
	  performance, 32-bit system-on-chip processor solutions.
	  The TCM and ARMv5TE 32-bit instruction set is supported.

	  Say Y if you want support for the ARM946E-S processor.
	  Otherwise, say N.

L
Linus Torvalds 已提交
199 200
# ARM1020 - needs validating
config CPU_ARM1020
201
	bool "Support ARM1020T (rev 0) processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
L
Linus Torvalds 已提交
202 203 204 205
	select CPU_32v5
	select CPU_ABRT_EV4T
	select CPU_CACHE_V4WT
	select CPU_CACHE_VIVT
206
	select CPU_COPY_V4WB if MMU
207 208
	select CPU_CP15_MMU
	select CPU_PABRT_LEGACY
209
	select CPU_TLB_V4WBI if MMU
L
Linus Torvalds 已提交
210 211 212 213 214 215 216 217 218
	help
	  The ARM1020 is the 32K cached version of the ARM10 processor,
	  with an addition of a floating-point unit.

	  Say Y if you want support for the ARM1020 processor.
	  Otherwise, say N.

# ARM1020E - needs validating
config CPU_ARM1020E
219
	bool "Support ARM1020E processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
220
	depends on n
L
Linus Torvalds 已提交
221 222 223 224
	select CPU_32v5
	select CPU_ABRT_EV4T
	select CPU_CACHE_V4WT
	select CPU_CACHE_VIVT
225
	select CPU_COPY_V4WB if MMU
226 227
	select CPU_CP15_MMU
	select CPU_PABRT_LEGACY
228
	select CPU_TLB_V4WBI if MMU
L
Linus Torvalds 已提交
229 230 231

# ARM1022E
config CPU_ARM1022
232
	bool "Support ARM1022E processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
L
Linus Torvalds 已提交
233 234 235
	select CPU_32v5
	select CPU_ABRT_EV4T
	select CPU_CACHE_VIVT
236
	select CPU_COPY_V4WB if MMU # can probably do better
237 238
	select CPU_CP15_MMU
	select CPU_PABRT_LEGACY
239
	select CPU_TLB_V4WBI if MMU
L
Linus Torvalds 已提交
240 241 242 243 244 245 246 247 248 249
	help
	  The ARM1022E is an implementation of the ARMv5TE architecture
	  based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
	  embedded trace macrocell, and a floating-point unit.

	  Say Y if you want support for the ARM1022E processor.
	  Otherwise, say N.

# ARM1026EJ-S
config CPU_ARM1026
250
	bool "Support ARM1026EJ-S processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
L
Linus Torvalds 已提交
251 252 253
	select CPU_32v5
	select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
	select CPU_CACHE_VIVT
254
	select CPU_COPY_V4WB if MMU # can probably do better
255 256
	select CPU_CP15_MMU
	select CPU_PABRT_LEGACY
257
	select CPU_TLB_V4WBI if MMU
L
Linus Torvalds 已提交
258 259 260 261 262 263 264 265 266
	help
	  The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
	  based upon the ARM10 integer core.

	  Say Y if you want support for the ARM1026EJ-S processor.
	  Otherwise, say N.

# SA110
config CPU_SA110
A
Arnd Bergmann 已提交
267
	bool
L
Linus Torvalds 已提交
268 269 270 271 272
	select CPU_32v3 if ARCH_RPC
	select CPU_32v4 if !ARCH_RPC
	select CPU_ABRT_EV4
	select CPU_CACHE_V4WB
	select CPU_CACHE_VIVT
273
	select CPU_COPY_V4WB if MMU
274 275
	select CPU_CP15_MMU
	select CPU_PABRT_LEGACY
276
	select CPU_TLB_V4WB if MMU
L
Linus Torvalds 已提交
277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292
	help
	  The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
	  is available at five speeds ranging from 100 MHz to 233 MHz.
	  More information is available at
	  <http://developer.intel.com/design/strong/sa110.htm>.

	  Say Y if you want support for the SA-110 processor.
	  Otherwise, say N.

# SA1100
config CPU_SA1100
	bool
	select CPU_32v4
	select CPU_ABRT_EV4
	select CPU_CACHE_V4WB
	select CPU_CACHE_VIVT
293
	select CPU_CP15_MMU
294
	select CPU_PABRT_LEGACY
295
	select CPU_TLB_V4WB if MMU
L
Linus Torvalds 已提交
296 297 298 299 300 301 302

# XScale
config CPU_XSCALE
	bool
	select CPU_32v5
	select CPU_ABRT_EV5T
	select CPU_CACHE_VIVT
303
	select CPU_CP15_MMU
304
	select CPU_PABRT_LEGACY
305
	select CPU_TLB_V4WBI if MMU
L
Linus Torvalds 已提交
306

307 308 309 310 311 312
# XScale Core Version 3
config CPU_XSC3
	bool
	select CPU_32v5
	select CPU_ABRT_EV5T
	select CPU_CACHE_VIVT
313
	select CPU_CP15_MMU
314
	select CPU_PABRT_LEGACY
315
	select CPU_TLB_V4WBI if MMU
316 317
	select IO_36

318 319 320 321 322 323
# Marvell PJ1 (Mohawk)
config CPU_MOHAWK
	bool
	select CPU_32v5
	select CPU_ABRT_EV5T
	select CPU_CACHE_VIVT
324
	select CPU_COPY_V4WB if MMU
325
	select CPU_CP15_MMU
326
	select CPU_PABRT_LEGACY
327 328
	select CPU_TLB_V4WBI if MMU

329 330 331 332 333 334
# Feroceon
config CPU_FEROCEON
	bool
	select CPU_32v5
	select CPU_ABRT_EV5T
	select CPU_CACHE_VIVT
335
	select CPU_COPY_FEROCEON if MMU
336 337
	select CPU_CP15_MMU
	select CPU_PABRT_LEGACY
338
	select CPU_TLB_FEROCEON if MMU
339

340 341 342 343 344 345 346 347 348
config CPU_FEROCEON_OLD_ID
	bool "Accept early Feroceon cores with an ARM926 ID"
	depends on CPU_FEROCEON && !CPU_ARM926T
	default y
	help
	  This enables the usage of some old Feroceon cores
	  for which the CPU ID is equal to the ARM926 ID.
	  Relevant for Feroceon-1850 and early Feroceon-2850.

H
Haojian Zhuang 已提交
349 350 351 352
# Marvell PJ4
config CPU_PJ4
	bool
	select ARM_THUMBEE
353
	select CPU_V7
H
Haojian Zhuang 已提交
354

355 356 357 358
config CPU_PJ4B
	bool
	select CPU_V7

L
Linus Torvalds 已提交
359 360
# ARMv6
config CPU_V6
361
	bool "Support ARM V6 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX)
L
Linus Torvalds 已提交
362 363 364 365
	select CPU_32v6
	select CPU_ABRT_EV6
	select CPU_CACHE_V6
	select CPU_CACHE_VIPT
366
	select CPU_COPY_V6 if MMU
367
	select CPU_CP15_MMU
368
	select CPU_HAS_ASID if MMU
369
	select CPU_PABRT_V6
370
	select CPU_TLB_V6 if MMU
L
Linus Torvalds 已提交
371

372
# ARMv6k
373
config CPU_V6K
374
	bool "Support ARM V6K processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX)
375
	select CPU_32v6
376
	select CPU_32v6K
377 378 379
	select CPU_ABRT_EV6
	select CPU_CACHE_V6
	select CPU_CACHE_VIPT
380
	select CPU_COPY_V6 if MMU
381 382
	select CPU_CP15_MMU
	select CPU_HAS_ASID if MMU
383
	select CPU_PABRT_V6
384
	select CPU_TLB_V6 if MMU
385

386 387
# ARMv7
config CPU_V7
388
	bool "Support ARM V7 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V7) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX)
389
	select CPU_32v6K
390 391 392 393
	select CPU_32v7
	select CPU_ABRT_EV7
	select CPU_CACHE_V7
	select CPU_CACHE_VIPT
394
	select CPU_COPY_V6 if MMU
395 396
	select CPU_CP15_MMU if MMU
	select CPU_CP15_MPU if !MMU
397
	select CPU_HAS_ASID if MMU
398
	select CPU_PABRT_V7
399
	select CPU_TLB_V7 if MMU
400

401 402 403 404 405 406 407 408 409
# ARMv7M
config CPU_V7M
	bool
	select CPU_32v7M
	select CPU_ABRT_NOMMU
	select CPU_CACHE_NOP
	select CPU_PABRT_LEGACY
	select CPU_THUMBONLY

410 411 412 413 414 415 416
config CPU_THUMBONLY
	bool
	# There are no CPUs available with MMU that don't implement an ARM ISA:
	depends on !MMU
	help
	  Select this if your CPU doesn't support the 32 bit ARM instructions.

L
Linus Torvalds 已提交
417 418 419 420
# Figure out what processor architecture version we should be using.
# This defines the compiler instruction set which depends on the machine type.
config CPU_32v3
	bool
421
	select CPU_USE_DOMAINS if MMU
422
	select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
423
	select NEED_KUSER_HELPERS
424
	select TLS_REG_EMUL if SMP || !MMU
L
Linus Torvalds 已提交
425 426 427

config CPU_32v4
	bool
428
	select CPU_USE_DOMAINS if MMU
429
	select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
430
	select NEED_KUSER_HELPERS
431
	select TLS_REG_EMUL if SMP || !MMU
L
Linus Torvalds 已提交
432

433 434
config CPU_32v4T
	bool
435
	select CPU_USE_DOMAINS if MMU
436
	select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
437
	select NEED_KUSER_HELPERS
438
	select TLS_REG_EMUL if SMP || !MMU
439

L
Linus Torvalds 已提交
440 441
config CPU_32v5
	bool
442
	select CPU_USE_DOMAINS if MMU
443
	select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
444
	select NEED_KUSER_HELPERS
445
	select TLS_REG_EMUL if SMP || !MMU
L
Linus Torvalds 已提交
446 447 448

config CPU_32v6
	bool
449
	select TLS_REG_EMUL if !CPU_32v6K && !MMU
L
Linus Torvalds 已提交
450

451
config CPU_32v6K
452
	bool
L
Linus Torvalds 已提交
453

454 455 456
config CPU_32v7
	bool

457 458 459
config CPU_32v7M
	bool

L
Linus Torvalds 已提交
460
# The abort model
461 462 463
config CPU_ABRT_NOMMU
	bool

L
Linus Torvalds 已提交
464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481
config CPU_ABRT_EV4
	bool

config CPU_ABRT_EV4T
	bool

config CPU_ABRT_LV4T
	bool

config CPU_ABRT_EV5T
	bool

config CPU_ABRT_EV5TJ
	bool

config CPU_ABRT_EV6
	bool

482 483 484
config CPU_ABRT_EV7
	bool

485
config CPU_PABRT_LEGACY
P
Paul Brook 已提交
486 487
	bool

488 489 490 491
config CPU_PABRT_V6
	bool

config CPU_PABRT_V7
P
Paul Brook 已提交
492 493
	bool

L
Linus Torvalds 已提交
494 495 496 497 498 499 500 501 502 503 504 505 506
# The cache model
config CPU_CACHE_V4
	bool

config CPU_CACHE_V4WT
	bool

config CPU_CACHE_V4WB
	bool

config CPU_CACHE_V6
	bool

507 508 509
config CPU_CACHE_V7
	bool

510 511 512
config CPU_CACHE_NOP
	bool

L
Linus Torvalds 已提交
513 514 515 516 517 518
config CPU_CACHE_VIVT
	bool

config CPU_CACHE_VIPT
	bool

P
Paulius Zaleckas 已提交
519 520 521
config CPU_CACHE_FA
	bool

522
if MMU
L
Linus Torvalds 已提交
523 524 525 526 527 528 529
# The copy-page model
config CPU_COPY_V4WT
	bool

config CPU_COPY_V4WB
	bool

530 531 532
config CPU_COPY_FEROCEON
	bool

P
Paulius Zaleckas 已提交
533 534 535
config CPU_COPY_FA
	bool

L
Linus Torvalds 已提交
536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555
config CPU_COPY_V6
	bool

# This selects the TLB model
config CPU_TLB_V4WT
	bool
	help
	  ARM Architecture Version 4 TLB with writethrough cache.

config CPU_TLB_V4WB
	bool
	help
	  ARM Architecture Version 4 TLB with writeback cache.

config CPU_TLB_V4WBI
	bool
	help
	  ARM Architecture Version 4 TLB with writeback cache and invalidate
	  instruction cache entry.

556 557 558 559 560
config CPU_TLB_FEROCEON
	bool
	help
	  Feroceon TLB (v4wbi with non-outer-cachable page table walks).

P
Paulius Zaleckas 已提交
561 562 563 564 565 566 567
config CPU_TLB_FA
	bool
	help
	  Faraday ARM FA526 architecture, unified TLB with writeback cache
	  and invalidate instruction cache entry. Branch target buffer is
	  also supported.

L
Linus Torvalds 已提交
568 569 570
config CPU_TLB_V6
	bool

571 572 573
config CPU_TLB_V7
	bool

574 575
config VERIFY_PERMISSION_FAULT
	bool
576 577
endif

578 579 580 581 582 583
config CPU_HAS_ASID
	bool
	help
	  This indicates whether the CPU has the ASID register; used to
	  tag TLB and possibly cache entries.

584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600
config CPU_CP15
	bool
	help
	  Processor has the CP15 register.

config CPU_CP15_MMU
	bool
	select CPU_CP15
	help
	  Processor has the CP15 register, which has MMU related registers.

config CPU_CP15_MPU
	bool
	select CPU_CP15
	help
	  Processor has the CP15 register, which has MPU related registers.

601 602 603 604 605 606
config CPU_USE_DOMAINS
	bool
	help
	  This option enables or disables the use of domain switching
	  via the set_fs() function.

607 608 609 610 611
config CPU_V7M_NUM_IRQ
	int "Number of external interrupts connected to the NVIC"
	depends on CPU_V7M
	default 90 if ARCH_STM32
	default 38 if ARCH_EFM32
612
	default 112 if SOC_VF610
613 614 615 616 617 618 619 620 621 622
	default 240
	help
	  This option indicates the number of interrupts connected to the NVIC.
	  The value can be larger than the real number of interrupts supported
	  by the system, but must not be lower.
	  The default value is 240, corresponding to the maximum number of
	  interrupts supported by the NVIC on Cortex-M family.

	  If unsure, keep default value.

623 624 625 626 627 628
#
# CPU supports 36-bit I/O
#
config IO_36
	bool

L
Linus Torvalds 已提交
629 630
comment "Processor Features"

631 632
config ARM_LPAE
	bool "Support for the Large Physical Address Extension"
633 634
	depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
		!CPU_32v4 && !CPU_32v3
635 636 637 638 639 640 641 642
	help
	  Say Y if you have an ARMv7 processor supporting the LPAE page
	  table format and you would like to access memory beyond the
	  4GB limit. The resulting kernel image will not run on
	  processors without the LPA extension.

	  If unsure, say N.

643 644 645 646
config ARM_PV_FIXUP
	def_bool y
	depends on ARM_LPAE && ARM_PATCH_PHYS_VIRT && ARCH_KEYSTONE

647 648 649 650 651 652
config ARCH_PHYS_ADDR_T_64BIT
	def_bool ARM_LPAE

config ARCH_DMA_ADDR_T_64BIT
	bool

L
Linus Torvalds 已提交
653
config ARM_THUMB
654
	bool "Support Thumb user binaries" if !CPU_THUMBONLY
655 656 657 658 659
	depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || \
		CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || \
		CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
		CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || \
		CPU_V7 || CPU_FEROCEON || CPU_V7M
L
Linus Torvalds 已提交
660 661 662 663 664 665 666 667 668 669 670
	default y
	help
	  Say Y if you want to include kernel support for running user space
	  Thumb binaries.

	  The Thumb instruction set is a compressed form of the standard ARM
	  instruction set resulting in smaller binaries at the expense of
	  slightly less efficient code.

	  If you don't know what this all is, saying Y is a safe choice.

671 672 673 674 675 676 677
config ARM_THUMBEE
	bool "Enable ThumbEE CPU extension"
	depends on CPU_V7
	help
	  Say Y here if you have a CPU with the ThumbEE extension and code to
	  make use of it. Say N for code that can run on CPUs without ThumbEE.

678
config ARM_VIRT_EXT
679 680 681
	bool
	depends on MMU
	default y if CPU_V7
682 683 684 685 686 687 688 689 690
	help
	  Enable the kernel to make use of the ARM Virtualization
	  Extensions to install hypervisors without run-time firmware
	  assistance.

	  A compliant bootloader is required in order to make maximum
	  use of this feature.  Refer to Documentation/arm/Booting for
	  details.

691
config SWP_EMULATE
692
	bool "Emulate SWP/SWPB instructions" if !SMP
693
	depends on CPU_V7
694
	default y if SMP
695
	select HAVE_PROC_CPU if PROC_FS
696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717
	help
	  ARMv6 architecture deprecates use of the SWP/SWPB instructions.
	  ARMv7 multiprocessing extensions introduce the ability to disable
	  these instructions, triggering an undefined instruction exception
	  when executed. Say Y here to enable software emulation of these
	  instructions for userspace (not kernel) using LDREX/STREX.
	  Also creates /proc/cpu/swp_emulation for statistics.

	  In some older versions of glibc [<=2.8] SWP is used during futex
	  trylock() operations with the assumption that the code will not
	  be preempted. This invalid assumption may be more likely to fail
	  with SWP emulation enabled, leading to deadlock of the user
	  application.

	  NOTE: when accessing uncached shared regions, LDREX/STREX rely
	  on an external transaction monitoring block called a global
	  monitor to maintain update atomicity. If your system does not
	  implement a global monitor, this option can cause programs that
	  perform SWP operations to uncached memory to deadlock.

	  If unsure, say Y.

L
Linus Torvalds 已提交
718 719 720 721 722 723 724 725 726
config CPU_BIG_ENDIAN
	bool "Build big-endian kernel"
	depends on ARCH_SUPPORTS_BIG_ENDIAN
	help
	  Say Y if you plan on running a kernel in big-endian mode.
	  Note that your board must be properly built and your board
	  port must properly enable any big-endian related features
	  of your chipset/board/processor.

727 728 729
config CPU_ENDIAN_BE8
	bool
	depends on CPU_BIG_ENDIAN
730
	default CPU_V6 || CPU_V6K || CPU_V7
731 732 733 734 735 736 737 738 739 740
	help
	  Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.

config CPU_ENDIAN_BE32
	bool
	depends on CPU_BIG_ENDIAN
	default !CPU_ENDIAN_BE8
	help
	  Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.

741
config CPU_HIGH_VECTOR
742
	depends on !MMU && CPU_CP15 && !CPU_ARM740T
743 744 745
	bool "Select the High exception vector"
	help
	  Say Y here to select high exception vector(0xFFFF0000~).
746
	  The exception vector can vary depending on the platform
747 748 749 750 751
	  design in nommu mode. If your platform needs to select
	  high exception vector, say Y.
	  Otherwise or if you are unsure, say N, and the low exception
	  vector (0x00000000~) will be used.

L
Linus Torvalds 已提交
752
config CPU_ICACHE_DISABLE
753
	bool "Disable I-Cache (I-bit)"
754
	depends on CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
L
Linus Torvalds 已提交
755 756 757 758 759
	help
	  Say Y here to disable the processor instruction cache. Unless
	  you have a reason not to or are unsure, say N.

config CPU_DCACHE_DISABLE
760
	bool "Disable D-Cache (C-bit)"
761
	depends on CPU_CP15 && !SMP
L
Linus Torvalds 已提交
762 763 764 765
	help
	  Say Y here to disable the processor data cache. Unless
	  you have a reason not to or are unsure, say N.

766 767 768 769 770 771 772 773 774 775 776 777 778
config CPU_DCACHE_SIZE
	hex
	depends on CPU_ARM740T || CPU_ARM946E
	default 0x00001000 if CPU_ARM740T
	default 0x00002000 # default size for ARM946E-S
	help
	  Some cores are synthesizable to have various sized cache. For
	  ARM946E-S case, it can vary from 0KB to 1MB.
	  To support such cache operations, it is efficient to know the size
	  before compile time.
	  If your SoC is configured to have a different size, define the value
	  here with proper conditions.

L
Linus Torvalds 已提交
779 780
config CPU_DCACHE_WRITETHROUGH
	bool "Force write through D-cache"
P
Paulius Zaleckas 已提交
781
	depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
L
Linus Torvalds 已提交
782 783 784 785 786 787 788
	default y if CPU_ARM925T
	help
	  Say Y here to use the data cache in writethrough mode. Unless you
	  specifically require this or are unsure, say N.

config CPU_CACHE_ROUND_ROBIN
	bool "Round robin I and D cache replacement algorithm"
789
	depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
L
Linus Torvalds 已提交
790 791 792 793 794 795
	help
	  Say Y here to use the predictable round-robin cache replacement
	  policy.  Unless you specifically require this or are unsure, say N.

config CPU_BPREDICT_DISABLE
	bool "Disable branch prediction"
796
	depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526
L
Linus Torvalds 已提交
797 798
	help
	  Say Y here to disable branch prediction.  If unsure, say N.
799

800 801
config TLS_REG_EMUL
	bool
802
	select NEED_KUSER_HELPERS
803
	help
804 805 806
	  An SMP system using a pre-ARMv6 processor (there are apparently
	  a few prototypes like that in existence) and therefore access to
	  that required register must be emulated.
807

808 809
config NEEDS_SYSCALL_FOR_CMPXCHG
	bool
810
	select NEED_KUSER_HELPERS
811 812 813 814 815
	help
	  SMP on a pre-ARMv6 processor?  Well OK then.
	  Forget about fast user space cmpxchg support.
	  It is just not possible.

816 817 818 819 820
config NEED_KUSER_HELPERS
	bool

config KUSER_HELPERS
	bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS
821
	depends on MMU
822 823 824 825 826 827 828 829 830 831
	default y
	help
	  Warning: disabling this option may break user programs.

	  Provide kuser helpers in the vector page.  The kernel provides
	  helper code to userspace in read only form at a fixed location
	  in the high vector page to allow userspace to be independent of
	  the CPU type fitted to the system.  This permits binaries to be
	  run on ARMv4 through to ARMv7 without modification.

832 833
	  See Documentation/arm/kernel_user_helpers.txt for details.

834 835 836 837 838 839
	  However, the fixed address nature of these helpers can be used
	  by ROP (return orientated programming) authors when creating
	  exploits.

	  If all of the binaries and libraries which run on your platform
	  are built specifically for your platform, and make no use of
840 841 842 843
	  these helpers, then you can turn this option off to hinder
	  such exploits. However, in that case, if a binary or library
	  relying on those helpers is run, it will receive a SIGILL signal,
	  which will terminate the program.
844 845 846 847

	  Say N here only if you are absolutely certain that you do not
	  need these helpers; otherwise, the safe option is to say Y.

848 849
config VDSO
	bool "Enable VDSO for acceleration of some system calls"
850
	depends on AEABI && MMU && CPU_V7
851 852 853 854 855 856 857 858 859 860 861
	default y if ARM_ARCH_TIMER
	select GENERIC_TIME_VSYSCALL
	help
	  Place in the process address space an ELF shared object
	  providing fast implementations of gettimeofday and
	  clock_gettime.  Systems that implement the ARM architected
	  timer will receive maximum benefit.

	  You must have glibc 2.22 or later for programs to seamlessly
	  take advantage of this.

862 863
config DMA_CACHE_RWFO
	bool "Enable read/write for ownership DMA cache maintenance"
864
	depends on CPU_V6K && SMP
865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880
	default y
	help
	  The Snoop Control Unit on ARM11MPCore does not detect the
	  cache maintenance operations and the dma_{map,unmap}_area()
	  functions may leave stale cache entries on other CPUs. By
	  enabling this option, Read or Write For Ownership in the ARMv6
	  DMA cache maintenance functions is performed. These LDR/STR
	  instructions change the cache line state to shared or modified
	  so that the cache operation has the desired effect.

	  Note that the workaround is only valid on processors that do
	  not perform speculative loads into the D-cache. For such
	  processors, if cache maintenance operations are not broadcast
	  in hardware, other workarounds are needed (e.g. cache
	  maintenance broadcasting in software via FIQ).

881 882
config OUTER_CACHE
	bool
883

884 885
config OUTER_CACHE_SYNC
	bool
886
	select ARM_HEAVY_MB
887 888 889 890
	help
	  The outer cache has a outer_cache_fns.sync function pointer
	  that can be used to drain the write buffer of the outer cache.

891 892
config CACHE_FEROCEON_L2
	bool "Enable the Feroceon L2 cache controller"
893
	depends on ARCH_MV78XX0 || ARCH_MVEBU
894 895 896 897 898
	default y
	select OUTER_CACHE
	help
	  This option enables the Feroceon L2 cache controller.

899 900 901 902 903 904 905
config CACHE_FEROCEON_L2_WRITETHROUGH
	bool "Force Feroceon L2 cache write through"
	depends on CACHE_FEROCEON_L2
	help
	  Say Y here to use the Feroceon L2 cache in writethrough mode.
	  Unless you specifically require this, say N for writeback mode.

906 907 908 909 910 911 912 913 914 915 916 917 918 919
config MIGHT_HAVE_CACHE_L2X0
	bool
	help
	  This option should be selected by machines which have a L2x0
	  or PL310 cache controller, but where its use is optional.

	  The only effect of this option is to make CACHE_L2X0 and
	  related options available to the user for configuration.

	  Boards or SoCs which always require the cache controller
	  support to be present should select CACHE_L2X0 directly
	  instead of this option, thus preventing the user from
	  inadvertently configuring a broken kernel.

920
config CACHE_L2X0
921 922
	bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
	default MIGHT_HAVE_CACHE_L2X0
923
	select OUTER_CACHE
924
	select OUTER_CACHE_SYNC
925 926
	help
	  This option enables the L2x0 PrimeCell.
927

928 929
if CACHE_L2X0

930 931 932 933 934 935 936 937 938
config PL310_ERRATA_588369
	bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
	help
	   The PL310 L2 cache controller implements three types of Clean &
	   Invalidate maintenance operations: by Physical Address
	   (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
	   They are architecturally defined to behave as the execution of a
	   clean operation followed immediately by an invalidate operation,
	   both performing to the same memory location. This functionality
939 940
	   is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0)
	   as clean lines are not invalidated as a result of these operations.
941 942 943 944 945 946 947 948 949

config PL310_ERRATA_727915
	bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
	help
	  PL310 implements the Clean & Invalidate by Way L2 cache maintenance
	  operation (offset 0x7FC). This operation runs in background so that
	  PL310 can handle normal accesses while it is in progress. Under very
	  rare circumstances, due to this erratum, write data can be lost when
	  PL310 treats a cacheable write transaction during a Clean &
950 951
	  Invalidate by Way operation.  Revisions prior to r3p1 are affected by
	  this errata (fixed in r3p1).
952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977

config PL310_ERRATA_753970
	bool "PL310 errata: cache sync operation may be faulty"
	help
	  This option enables the workaround for the 753970 PL310 (r3p0) erratum.

	  Under some condition the effect of cache sync operation on
	  the store buffer still remains when the operation completes.
	  This means that the store buffer is always asked to drain and
	  this prevents it from merging any further writes. The workaround
	  is to replace the normal offset of cache sync operation (0x730)
	  by another offset targeting an unmapped PL310 register 0x740.
	  This has the same effect as the cache sync operation: store buffer
	  drain and waiting for all buffers empty.

config PL310_ERRATA_769419
	bool "PL310 errata: no automatic Store Buffer drain"
	help
	  On revisions of the PL310 prior to r3p2, the Store Buffer does
	  not automatically drain. This can cause normal, non-cacheable
	  writes to be retained when the memory system is idle, leading
	  to suboptimal I/O performance for drivers using coherent DMA.
	  This option adds a write barrier to the cpu_idle loop so that,
	  on systems with an outer cache, the store buffer is drained
	  explicitly.

978 979
endif

980 981
config CACHE_TAUROS2
	bool "Enable the Tauros2 L2 cache controller"
H
Haojian Zhuang 已提交
982
	depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
983 984 985 986 987 988
	default y
	select OUTER_CACHE
	help
	  This option enables the Tauros2 L2 cache controller (as
	  found on PJ1/PJ4).

989 990 991 992 993 994 995
config CACHE_XSC3L2
	bool "Enable the L2 cache on XScale3"
	depends on CPU_XSC3
	default y
	select OUTER_CACHE
	help
	  This option enables the L2 cache on XScale3.
996

997 998
config ARM_L1_CACHE_SHIFT_6
	bool
999
	default y if CPU_V7
1000 1001 1002
	help
	  Setting ARM L1 cache line size to 64 Bytes.

1003 1004
config ARM_L1_CACHE_SHIFT
	int
1005
	default 6 if ARM_L1_CACHE_SHIFT_6
1006
	default 5
1007 1008

config ARM_DMA_MEM_BUFFERABLE
1009
	bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7
1010 1011
	depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
		     MACH_REALVIEW_PB11MP)
1012
	default y if CPU_V6 || CPU_V6K || CPU_V7
1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027
	help
	  Historically, the kernel has used strongly ordered mappings to
	  provide DMA coherent memory.  With the advent of ARMv7, mapping
	  memory with differing types results in unpredictable behaviour,
	  so on these CPUs, this option is forced on.

	  Multiple mappings with differing attributes is also unpredictable
	  on ARMv6 CPUs, but since they do not have aggressive speculative
	  prefetch, no harm appears to occur.

	  However, drivers may be missing the necessary barriers for ARMv6,
	  and therefore turning this on may result in unpredictable driver
	  behaviour.  Therefore, we offer this as an option.

	  You are recommended say 'Y' here and debug any affected drivers.
1028

1029 1030 1031 1032 1033
config ARCH_HAS_BARRIERS
	bool
	help
	  This option allows the use of custom mandatory barriers
	  included via the mach/barriers.h file.
1034

1035 1036 1037
config ARM_HEAVY_MB
	bool

1038 1039 1040 1041 1042
config ARCH_SUPPORTS_BIG_ENDIAN
	bool
	help
	  This option specifies the architecture can support big endian
	  operation.
1043 1044 1045

config ARM_KERNMEM_PERMS
	bool "Restrict kernel memory permissions"
1046
	depends on MMU
1047 1048 1049 1050 1051 1052
	help
	  If this is set, kernel memory other than kernel text (and rodata)
	  will be made non-executable. The tradeoff is that each region is
	  padded to section-size (1MiB) boundaries (because their permissions
	  are different and splitting the 1M pages into 4K ones causes TLB
	  performance problems), wasting memory.
1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064

config DEBUG_RODATA
	bool "Make kernel text and rodata read-only"
	depends on ARM_KERNMEM_PERMS
	default y
	help
	  If this is set, kernel text and rodata will be made read-only. This
	  is to help catch accidental or malicious attempts to change the
	  kernel's executable code. Additionally splits rodata from kernel
	  text so it can be made explicitly non-executable. This creates
	  another section-size padded region, so it can waste more memory
	  space while gaining the read-only protections.