io_apic.c 76.9 KB
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/*
 *	Intel IO-APIC support for multi-Pentium hosts.
 *
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 *	Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
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 *
 *	Many thanks to Stig Venaas for trying out countless experimental
 *	patches and reporting/debugging problems patiently!
 *
 *	(c) 1999, Multiple IO-APIC support, developed by
 *	Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
 *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
 *	further tested and cleaned up by Zach Brown <zab@redhat.com>
 *	and Ingo Molnar <mingo@redhat.com>
 *
 *	Fixes
 *	Maciej W. Rozycki	:	Bits for genuine 82489DX APICs;
 *					thanks to Eric Gilmore
 *					and Rolf G. Tews
 *					for testing these extensively
 *	Paul Diefenbaugh	:	Added full ACPI support
 */

#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/mc146818rtc.h>
#include <linux/compiler.h>
#include <linux/acpi.h>
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#include <linux/module.h>
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#include <linux/syscore_ops.h>
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#include <linux/irqdomain.h>
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#include <linux/freezer.h>
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#include <linux/kthread.h>
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#include <linux/jiffies.h>	/* time_after() */
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#include <linux/slab.h>
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#include <linux/bootmem.h>
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#include <asm/idle.h>
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#include <asm/io.h>
#include <asm/smp.h>
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#include <asm/cpu.h>
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#include <asm/desc.h>
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#include <asm/proto.h>
#include <asm/acpi.h>
#include <asm/dma.h>
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#include <asm/timer.h>
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#include <asm/i8259.h>
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#include <asm/setup.h>
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#include <asm/irq_remapping.h>
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#include <asm/hw_irq.h>
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#include <asm/apic.h>
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#define	for_each_ioapic(idx)		\
	for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
#define	for_each_ioapic_reverse(idx)	\
	for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
#define	for_each_pin(idx, pin)		\
	for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
#define	for_each_ioapic_pin(idx, pin)	\
	for_each_ioapic((idx))		\
		for_each_pin((idx), (pin))
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#define for_each_irq_pin(entry, head) \
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	list_for_each_entry(entry, &head, list)
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/*
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 * Is the SiS APIC rmw bug present ?
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 *      -1 = don't know, 0 = no, 1 = yes
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 * When doing a read-modify-write operation on IOAPIC registers, older SiS APIC
 * requires we rewrite the index register again where the read already set up
 * the index register.
 * The code to make use of sis_apic_bug has been removed, but we don't want to
 * lose this knowledge.
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 */
int sis_apic_bug = -1;

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static DEFINE_RAW_SPINLOCK(ioapic_lock);
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static DEFINE_MUTEX(ioapic_mutex);
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static unsigned int ioapic_dynirq_base;
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static int ioapic_initialized;
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struct irq_pin_list {
	struct list_head list;
	int apic, pin;
};

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struct mp_chip_data {
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	struct list_head irq_2_pin;
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	struct IO_APIC_route_entry entry;
	int trigger;
	int polarity;
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	u32 count;
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	bool isa_irq;
};

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struct mp_ioapic_gsi {
	u32 gsi_base;
	u32 gsi_end;
};

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static struct ioapic {
	/*
	 * # of IRQ routing registers
	 */
	int nr_registers;
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	/*
	 * Saved state during suspend/resume, or while enabling intr-remap.
	 */
	struct IO_APIC_route_entry *saved_registers;
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	/* I/O APIC config */
	struct mpc_ioapic mp_config;
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	/* IO APIC gsi routing info */
	struct mp_ioapic_gsi  gsi_config;
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	struct ioapic_domain_cfg irqdomain_cfg;
	struct irq_domain *irqdomain;
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	struct resource *iomem_res;
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} ioapics[MAX_IO_APICS];
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#define mpc_ioapic_ver(ioapic_idx)	ioapics[ioapic_idx].mp_config.apicver
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int mpc_ioapic_id(int ioapic_idx)
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{
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	return ioapics[ioapic_idx].mp_config.apicid;
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}

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unsigned int mpc_ioapic_addr(int ioapic_idx)
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{
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	return ioapics[ioapic_idx].mp_config.apicaddr;
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}

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static inline struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
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{
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	return &ioapics[ioapic_idx].gsi_config;
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}
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static inline int mp_ioapic_pin_count(int ioapic)
{
	struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);

	return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
}

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static inline u32 mp_pin_to_gsi(int ioapic, int pin)
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{
	return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
}

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static inline bool mp_is_legacy_irq(int irq)
{
	return irq >= 0 && irq < nr_legacy_irqs();
}

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/*
 * Initialize all legacy IRQs and all pins on the first IOAPIC
 * if we have legacy interrupt controller. Kernel boot option "pirq="
 * may rely on non-legacy pins on the first IOAPIC.
 */
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static inline int mp_init_irq_at_boot(int ioapic, int irq)
{
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	if (!nr_legacy_irqs())
		return 0;

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	return ioapic == 0 || mp_is_legacy_irq(irq);
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}

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static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
{
	return ioapics[ioapic].irqdomain;
}

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int nr_ioapics;
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/* The one past the highest gsi number used */
u32 gsi_top;
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/* MP IRQ source entries */
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struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
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/* # of MP IRQ source entries */
int mp_irq_entries;

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#ifdef CONFIG_EISA
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int mp_bus_id_to_type[MAX_MP_BUSSES];
#endif

DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);

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int skip_ioapic_setup;

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/**
 * disable_ioapic_support() - disables ioapic support at runtime
 */
void disable_ioapic_support(void)
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{
#ifdef CONFIG_PCI
	noioapicquirk = 1;
	noioapicreroute = -1;
#endif
	skip_ioapic_setup = 1;
}

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static int __init parse_noapic(char *str)
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{
	/* disable IO-APIC */
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	disable_ioapic_support();
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	return 0;
}
early_param("noapic", parse_noapic);
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/* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
void mp_save_irq(struct mpc_intsrc *m)
{
	int i;

	apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
		" IRQ %02x, APIC ID %x, APIC INT %02x\n",
		m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
		m->srcbusirq, m->dstapic, m->dstirq);

	for (i = 0; i < mp_irq_entries; i++) {
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		if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
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			return;
	}

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	memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
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	if (++mp_irq_entries == MAX_IRQ_SOURCES)
		panic("Max # of irq sources exceeded!!\n");
}

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static void alloc_ioapic_saved_registers(int idx)
{
	size_t size;

	if (ioapics[idx].saved_registers)
		return;

	size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers;
	ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL);
	if (!ioapics[idx].saved_registers)
		pr_err("IOAPIC %d: suspend/resume impossible!\n", idx);
}

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static void free_ioapic_saved_registers(int idx)
{
	kfree(ioapics[idx].saved_registers);
	ioapics[idx].saved_registers = NULL;
}

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int __init arch_early_ioapic_init(void)
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{
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	int i;
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	if (!nr_legacy_irqs())
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		io_apic_irqs = ~0UL;

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	for_each_ioapic(i)
		alloc_ioapic_saved_registers(i);
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	return 0;
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}
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struct io_apic {
	unsigned int index;
	unsigned int unused[3];
	unsigned int data;
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	unsigned int unused2[11];
	unsigned int eoi;
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};

static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
{
	return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
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		+ (mpc_ioapic_addr(idx) & ~PAGE_MASK);
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}

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static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
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{
	struct io_apic __iomem *io_apic = io_apic_base(apic);
	writel(vector, &io_apic->eoi);
}

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unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
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{
	struct io_apic __iomem *io_apic = io_apic_base(apic);
	writel(reg, &io_apic->index);
	return readl(&io_apic->data);
}

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static void io_apic_write(unsigned int apic, unsigned int reg,
			  unsigned int value)
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{
	struct io_apic __iomem *io_apic = io_apic_base(apic);
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	writel(reg, &io_apic->index);
	writel(value, &io_apic->data);
}

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union entry_union {
	struct { u32 w1, w2; };
	struct IO_APIC_route_entry entry;
};

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static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
{
	union entry_union eu;

	eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
	eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
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	return eu.entry;
}

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static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
{
	union entry_union eu;
	unsigned long flags;
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	raw_spin_lock_irqsave(&ioapic_lock, flags);
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	eu.entry = __ioapic_read_entry(apic, pin);
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	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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	return eu.entry;
}

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/*
 * When we write a new IO APIC routing entry, we need to write the high
 * word first! If the mask bit in the low word is clear, we will enable
 * the interrupt, and we need to make sure the entry is fully populated
 * before that happens.
 */
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static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
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{
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	union entry_union eu = {{0, 0}};

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	eu.entry = e;
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	io_apic_write(apic, 0x11 + 2*pin, eu.w2);
	io_apic_write(apic, 0x10 + 2*pin, eu.w1);
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}

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static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
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{
	unsigned long flags;
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	raw_spin_lock_irqsave(&ioapic_lock, flags);
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	__ioapic_write_entry(apic, pin, e);
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	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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}

/*
 * When we mask an IO APIC routing entry, we need to write the low
 * word first, in order to set the mask bit before we change the
 * high bits!
 */
static void ioapic_mask_entry(int apic, int pin)
{
	unsigned long flags;
	union entry_union eu = { .entry.mask = 1 };

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	raw_spin_lock_irqsave(&ioapic_lock, flags);
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	io_apic_write(apic, 0x10 + 2*pin, eu.w1);
	io_apic_write(apic, 0x11 + 2*pin, eu.w2);
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	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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}

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/*
 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 * shared ISA-space IRQs, so we have to support them. We are super
 * fast in the common case, and fast for shared ISA-space IRQs.
 */
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static int __add_pin_to_irq_node(struct mp_chip_data *data,
				 int node, int apic, int pin)
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{
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	struct irq_pin_list *entry;
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	/* don't allow duplicates */
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	for_each_irq_pin(entry, data->irq_2_pin)
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		if (entry->apic == apic && entry->pin == pin)
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			return 0;
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	entry = kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node);
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	if (!entry) {
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		pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
		       node, apic, pin);
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		return -ENOMEM;
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	}
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	entry->apic = apic;
	entry->pin = pin;
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	list_add_tail(&entry->list, &data->irq_2_pin);
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	return 0;
}

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static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin)
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{
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	struct irq_pin_list *tmp, *entry;
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	list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list)
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		if (entry->apic == apic && entry->pin == pin) {
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			list_del(&entry->list);
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			kfree(entry);
			return;
		}
}

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static void add_pin_to_irq_node(struct mp_chip_data *data,
				int node, int apic, int pin)
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{
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	if (__add_pin_to_irq_node(data, node, apic, pin))
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		panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
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}

/*
 * Reroute an IRQ to a different pin.
 */
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static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node,
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					   int oldapic, int oldpin,
					   int newapic, int newpin)
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{
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	struct irq_pin_list *entry;
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	for_each_irq_pin(entry, data->irq_2_pin) {
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		if (entry->apic == oldapic && entry->pin == oldpin) {
			entry->apic = newapic;
			entry->pin = newpin;
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			/* every one is different, right? */
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			return;
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		}
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	}
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	/* old apic/pin didn't exist, so just add new ones */
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	add_pin_to_irq_node(data, node, newapic, newpin);
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}

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static void io_apic_modify_irq(struct mp_chip_data *data,
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			       int mask_and, int mask_or,
			       void (*final)(struct irq_pin_list *entry))
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{
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	union entry_union eu;
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	struct irq_pin_list *entry;
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	eu.entry = data->entry;
	eu.w1 &= mask_and;
	eu.w1 |= mask_or;
	data->entry = eu.entry;

	for_each_irq_pin(entry, data->irq_2_pin) {
		io_apic_write(entry->apic, 0x10 + 2 * entry->pin, eu.w1);
		if (final)
			final(entry);
	}
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}

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static void io_apic_sync(struct irq_pin_list *entry)
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{
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	/*
	 * Synchronize the IO-APIC and the CPU by doing
	 * a dummy read from the IO-APIC
	 */
	struct io_apic __iomem *io_apic;
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	io_apic = io_apic_base(entry->apic);
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	readl(&io_apic->data);
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}

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static void mask_ioapic_irq(struct irq_data *irq_data)
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{
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	struct mp_chip_data *data = irq_data->chip_data;
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	unsigned long flags;

	raw_spin_lock_irqsave(&ioapic_lock, flags);
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	io_apic_modify_irq(data, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
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	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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}
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static void __unmask_ioapic(struct mp_chip_data *data)
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{
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	io_apic_modify_irq(data, ~IO_APIC_REDIR_MASKED, 0, NULL);
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}

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static void unmask_ioapic_irq(struct irq_data *irq_data)
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{
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	struct mp_chip_data *data = irq_data->chip_data;
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	unsigned long flags;

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	raw_spin_lock_irqsave(&ioapic_lock, flags);
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	__unmask_ioapic(data);
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	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
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}

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/*
 * IO-APIC versions below 0x20 don't support EOI register.
 * For the record, here is the information about various versions:
 *     0Xh     82489DX
 *     1Xh     I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
 *     2Xh     I/O(x)APIC which is PCI 2.2 Compliant
 *     30h-FFh Reserved
 *
 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
 * version as 0x2. This is an error with documentation and these ICH chips
 * use io-apic's of version 0x20.
 *
 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
 * Otherwise, we simulate the EOI message manually by changing the trigger
 * mode to edge and then back to level, with RTE being masked during this.
 */
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static void __eoi_ioapic_pin(int apic, int pin, int vector)
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{
	if (mpc_ioapic_ver(apic) >= 0x20) {
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		io_apic_eoi(apic, vector);
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	} else {
		struct IO_APIC_route_entry entry, entry1;

		entry = entry1 = __ioapic_read_entry(apic, pin);

		/*
		 * Mask the entry and change the trigger mode to edge.
		 */
		entry1.mask = 1;
		entry1.trigger = IOAPIC_EDGE;

		__ioapic_write_entry(apic, pin, entry1);

		/*
		 * Restore the previous level triggered entry.
		 */
		__ioapic_write_entry(apic, pin, entry);
	}
}

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void eoi_ioapic_pin(int vector, struct mp_chip_data *data)
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{
	unsigned long flags;
	struct irq_pin_list *entry;

	raw_spin_lock_irqsave(&ioapic_lock, flags);
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	for_each_irq_pin(entry, data->irq_2_pin)
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		__eoi_ioapic_pin(entry->apic, entry->pin, vector);
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	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
}

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static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
{
	struct IO_APIC_route_entry entry;
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	/* Check delivery_mode to be sure we're not clearing an SMI pin */
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	entry = ioapic_read_entry(apic, pin);
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	if (entry.delivery_mode == dest_SMI)
		return;
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	/*
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	 * Make sure the entry is masked and re-read the contents to check
	 * if it is a level triggered pin and if the remote-IRR is set.
	 */
	if (!entry.mask) {
		entry.mask = 1;
		ioapic_write_entry(apic, pin, entry);
		entry = ioapic_read_entry(apic, pin);
	}

	if (entry.irr) {
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		unsigned long flags;

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		/*
		 * Make sure the trigger mode is set to level. Explicit EOI
		 * doesn't clear the remote-IRR if the trigger mode is not
		 * set to level.
		 */
		if (!entry.trigger) {
			entry.trigger = IOAPIC_LEVEL;
			ioapic_write_entry(apic, pin, entry);
		}
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		raw_spin_lock_irqsave(&ioapic_lock, flags);
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		__eoi_ioapic_pin(apic, pin, entry.vector);
577
		raw_spin_unlock_irqrestore(&ioapic_lock, flags);
578 579 580 581 582
	}

	/*
	 * Clear the rest of the bits in the IO-APIC RTE except for the mask
	 * bit.
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	 */
584
	ioapic_mask_entry(apic, pin);
585 586
	entry = ioapic_read_entry(apic, pin);
	if (entry.irr)
587
		pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
588
		       mpc_ioapic_id(apic), pin);
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}

591
static void clear_IO_APIC (void)
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{
	int apic, pin;

595 596
	for_each_ioapic_pin(apic, pin)
		clear_IO_APIC_pin(apic, pin);
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}

599
#ifdef CONFIG_X86_32
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/*
 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 * specific CPU-side IRQs.
 */

#define MAX_PIRQS 8
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static int pirq_entries[MAX_PIRQS] = {
	[0 ... MAX_PIRQS - 1] = -1
};
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static int __init ioapic_pirq_setup(char *str)
{
	int i, max;
	int ints[MAX_PIRQS+1];

	get_options(str, ARRAY_SIZE(ints), ints);

	apic_printk(APIC_VERBOSE, KERN_INFO
			"PIRQ redirection, working around broken MP-BIOS.\n");
	max = MAX_PIRQS;
	if (ints[0] < MAX_PIRQS)
		max = ints[0];

	for (i = 0; i < max; i++) {
		apic_printk(APIC_VERBOSE, KERN_DEBUG
				"... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
		/*
		 * PIRQs are mapped upside down, usually.
		 */
		pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
	}
	return 1;
}

__setup("pirq=", ioapic_pirq_setup);
635 636 637
#endif /* CONFIG_X86_32 */

/*
638
 * Saves all the IO-APIC RTE's
639
 */
640
int save_ioapic_entries(void)
641 642
{
	int apic, pin;
643
	int err = 0;
644

645
	for_each_ioapic(apic) {
646
		if (!ioapics[apic].saved_registers) {
647 648 649
			err = -ENOMEM;
			continue;
		}
650

651
		for_each_pin(apic, pin)
652
			ioapics[apic].saved_registers[pin] =
653
				ioapic_read_entry(apic, pin);
654
	}
655

656
	return err;
657 658
}

659 660 661
/*
 * Mask all IO APIC entries.
 */
662
void mask_ioapic_entries(void)
663 664 665
{
	int apic, pin;

666
	for_each_ioapic(apic) {
667
		if (!ioapics[apic].saved_registers)
668
			continue;
669

670
		for_each_pin(apic, pin) {
671 672
			struct IO_APIC_route_entry entry;

673
			entry = ioapics[apic].saved_registers[pin];
674 675 676 677 678 679 680 681
			if (!entry.mask) {
				entry.mask = 1;
				ioapic_write_entry(apic, pin, entry);
			}
		}
	}
}

682
/*
683
 * Restore IO APIC entries which was saved in the ioapic structure.
684
 */
685
int restore_ioapic_entries(void)
686 687 688
{
	int apic, pin;

689
	for_each_ioapic(apic) {
690
		if (!ioapics[apic].saved_registers)
691
			continue;
692

693
		for_each_pin(apic, pin)
694
			ioapic_write_entry(apic, pin,
695
					   ioapics[apic].saved_registers[pin]);
696
	}
697
	return 0;
698 699
}

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/*
 * Find the IRQ entry number of a certain pin.
 */
703
static int find_irq_entry(int ioapic_idx, int pin, int type)
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{
	int i;

	for (i = 0; i < mp_irq_entries; i++)
708
		if (mp_irqs[i].irqtype == type &&
709
		    (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
710 711
		     mp_irqs[i].dstapic == MP_APIC_ALL) &&
		    mp_irqs[i].dstirq == pin)
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			return i;

	return -1;
}

/*
 * Find the pin to which IRQ[irq] (ISA) is connected
 */
720
static int __init find_isa_irq_pin(int irq, int type)
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{
	int i;

	for (i = 0; i < mp_irq_entries; i++) {
725
		int lbus = mp_irqs[i].srcbus;
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		if (test_bit(lbus, mp_bus_not_pci) &&
728 729
		    (mp_irqs[i].irqtype == type) &&
		    (mp_irqs[i].srcbusirq == irq))
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731
			return mp_irqs[i].dstirq;
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	}
	return -1;
}

736 737 738 739 740
static int __init find_isa_irq_apic(int irq, int type)
{
	int i;

	for (i = 0; i < mp_irq_entries; i++) {
741
		int lbus = mp_irqs[i].srcbus;
742

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		if (test_bit(lbus, mp_bus_not_pci) &&
744 745
		    (mp_irqs[i].irqtype == type) &&
		    (mp_irqs[i].srcbusirq == irq))
746 747
			break;
	}
748

749
	if (i < mp_irq_entries) {
750 751
		int ioapic_idx;

752
		for_each_ioapic(ioapic_idx)
753 754
			if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
				return ioapic_idx;
755 756 757 758 759
	}

	return -1;
}

760
#ifdef CONFIG_EISA
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/*
 * EISA Edge/Level control register, ELCR
 */
static int EISA_ELCR(unsigned int irq)
{
766
	if (irq < nr_legacy_irqs()) {
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		unsigned int port = 0x4d0 + (irq >> 3);
		return (inb(port) >> (irq & 7)) & 1;
	}
	apic_printk(APIC_VERBOSE, KERN_INFO
			"Broken MPtable reports ISA irq %d\n", irq);
	return 0;
}
774

775
#endif
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/* ISA interrupts are always polarity zero edge triggered,
 * when listed as conforming in the MP table. */

#define default_ISA_trigger(idx)	(0)
#define default_ISA_polarity(idx)	(0)

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/* EISA interrupts are always polarity zero and can be edge or level
 * trigger depending on the ELCR value.  If an interrupt is listed as
 * EISA conforming in the MP table, that means its trigger type must
 * be read in from the ELCR */

788
#define default_EISA_trigger(idx)	(EISA_ELCR(mp_irqs[idx].srcbusirq))
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#define default_EISA_polarity(idx)	default_ISA_polarity(idx)
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/* PCI interrupts are always polarity one level triggered,
 * when listed as conforming in the MP table. */

#define default_PCI_trigger(idx)	(1)
#define default_PCI_polarity(idx)	(1)

797
static int irq_polarity(int idx)
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{
799
	int bus = mp_irqs[idx].srcbus;
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	int polarity;

	/*
	 * Determine IRQ line polarity (high active or low active):
	 */
805
	switch (mp_irqs[idx].irqflag & 3)
806
	{
807 808 809 810 811 812 813 814 815 816 817 818 819
		case 0: /* conforms, ie. bus-type dependent polarity */
			if (test_bit(bus, mp_bus_not_pci))
				polarity = default_ISA_polarity(idx);
			else
				polarity = default_PCI_polarity(idx);
			break;
		case 1: /* high active */
		{
			polarity = 0;
			break;
		}
		case 2: /* reserved */
		{
820
			pr_warn("broken BIOS!!\n");
821 822 823 824 825 826 827 828 829 830
			polarity = 1;
			break;
		}
		case 3: /* low active */
		{
			polarity = 1;
			break;
		}
		default: /* invalid */
		{
831
			pr_warn("broken BIOS!!\n");
832 833 834
			polarity = 1;
			break;
		}
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	}
	return polarity;
}

839
static int irq_trigger(int idx)
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{
841
	int bus = mp_irqs[idx].srcbus;
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	int trigger;

	/*
	 * Determine IRQ trigger mode (edge or level sensitive):
	 */
847
	switch ((mp_irqs[idx].irqflag>>2) & 3)
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	{
849 850 851 852 853
		case 0: /* conforms, ie. bus-type dependent */
			if (test_bit(bus, mp_bus_not_pci))
				trigger = default_ISA_trigger(idx);
			else
				trigger = default_PCI_trigger(idx);
854
#ifdef CONFIG_EISA
855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872
			switch (mp_bus_id_to_type[bus]) {
				case MP_BUS_ISA: /* ISA pin */
				{
					/* set before the switch */
					break;
				}
				case MP_BUS_EISA: /* EISA pin */
				{
					trigger = default_EISA_trigger(idx);
					break;
				}
				case MP_BUS_PCI: /* PCI pin */
				{
					/* set before the switch */
					break;
				}
				default:
				{
873
					pr_warn("broken BIOS!!\n");
874 875 876 877 878
					trigger = 1;
					break;
				}
			}
#endif
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			break;
880
		case 1: /* edge */
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		{
882
			trigger = 0;
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			break;
		}
885
		case 2: /* reserved */
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		{
887
			pr_warn("broken BIOS!!\n");
888
			trigger = 1;
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			break;
		}
891
		case 3: /* level */
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		{
893
			trigger = 1;
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			break;
		}
896
		default: /* invalid */
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		{
898
			pr_warn("broken BIOS!!\n");
899
			trigger = 0;
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			break;
		}
	}
	return trigger;
}

906 907 908 909 910 911 912 913 914 915 916
void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node,
			   int trigger, int polarity)
{
	init_irq_alloc_info(info, NULL);
	info->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
	info->ioapic_node = node;
	info->ioapic_trigger = trigger;
	info->ioapic_polarity = polarity;
	info->ioapic_valid = 1;
}

917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956
#ifndef CONFIG_ACPI
int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity);
#endif

static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst,
				   struct irq_alloc_info *src,
				   u32 gsi, int ioapic_idx, int pin)
{
	int trigger, polarity;

	copy_irq_alloc_info(dst, src);
	dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
	dst->ioapic_id = mpc_ioapic_id(ioapic_idx);
	dst->ioapic_pin = pin;
	dst->ioapic_valid = 1;
	if (src && src->ioapic_valid) {
		dst->ioapic_node = src->ioapic_node;
		dst->ioapic_trigger = src->ioapic_trigger;
		dst->ioapic_polarity = src->ioapic_polarity;
	} else {
		dst->ioapic_node = NUMA_NO_NODE;
		if (acpi_get_override_irq(gsi, &trigger, &polarity) >= 0) {
			dst->ioapic_trigger = trigger;
			dst->ioapic_polarity = polarity;
		} else {
			/*
			 * PCI interrupts are always polarity one level
			 * triggered.
			 */
			dst->ioapic_trigger = 1;
			dst->ioapic_polarity = 1;
		}
	}
}

static int ioapic_alloc_attr_node(struct irq_alloc_info *info)
{
	return (info && info->ioapic_valid) ? info->ioapic_node : NUMA_NO_NODE;
}

957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973
static void mp_register_handler(unsigned int irq, unsigned long trigger)
{
	irq_flow_handler_t hdl;
	bool fasteoi;

	if (trigger) {
		irq_set_status_flags(irq, IRQ_LEVEL);
		fasteoi = true;
	} else {
		irq_clear_status_flags(irq, IRQ_LEVEL);
		fasteoi = false;
	}

	hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
	__irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge");
}

974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993
static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info)
{
	struct mp_chip_data *data = irq_get_chip_data(irq);

	/*
	 * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger
	 * and polarity attirbutes. So allow the first user to reprogram the
	 * pin with real trigger and polarity attributes.
	 */
	if (irq < nr_legacy_irqs() && data->count == 1) {
		if (info->ioapic_trigger != data->trigger)
			mp_register_handler(irq, data->trigger);
		data->entry.trigger = data->trigger = info->ioapic_trigger;
		data->entry.polarity = data->polarity = info->ioapic_polarity;
	}

	return data->trigger == info->ioapic_trigger &&
	       data->polarity == info->ioapic_polarity;
}

994
static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi,
995
				 struct irq_alloc_info *info)
996
{
997
	bool legacy = false;
998 999 1000 1001 1002 1003
	int irq = -1;
	int type = ioapics[ioapic].irqdomain_cfg.type;

	switch (type) {
	case IOAPIC_DOMAIN_LEGACY:
		/*
1004 1005
		 * Dynamically allocate IRQ number for non-ISA IRQs in the first
		 * 16 GSIs on some weird platforms.
1006
		 */
1007
		if (!ioapic_initialized || gsi >= nr_legacy_irqs())
1008
			irq = gsi;
1009
		legacy = mp_is_legacy_irq(irq);
1010 1011
		break;
	case IOAPIC_DOMAIN_STRICT:
1012
		irq = gsi;
1013 1014 1015 1016 1017
		break;
	case IOAPIC_DOMAIN_DYNAMIC:
		break;
	default:
		WARN(1, "ioapic: unknown irqdomain type %d\n", type);
1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051
		return -1;
	}

	return __irq_domain_alloc_irqs(domain, irq, 1,
				       ioapic_alloc_attr_node(info),
				       info, legacy);
}

/*
 * Need special handling for ISA IRQs because there may be multiple IOAPIC pins
 * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping
 * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are
 * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
 * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and
 * some BIOSes may use MP Interrupt Source records to override IRQ numbers for
 * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be
 * multiple pins sharing the same legacy IRQ number when ACPI is disabled.
 */
static int alloc_isa_irq_from_domain(struct irq_domain *domain,
				     int irq, int ioapic, int pin,
				     struct irq_alloc_info *info)
{
	struct mp_chip_data *data;
	struct irq_data *irq_data = irq_get_irq_data(irq);
	int node = ioapic_alloc_attr_node(info);

	/*
	 * Legacy ISA IRQ has already been allocated, just add pin to
	 * the pin list assoicated with this IRQ and program the IOAPIC
	 * entry. The IOAPIC entry
	 */
	if (irq_data && irq_data->parent_data) {
		if (!mp_check_pin_attr(irq, info))
			return -EBUSY;
1052 1053
		if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic,
					  info->ioapic_pin))
1054 1055 1056 1057 1058 1059 1060 1061
			return -ENOMEM;
	} else {
		irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true);
		if (irq >= 0) {
			irq_data = irq_domain_get_irq_data(domain, irq);
			data = irq_data->chip_data;
			data->isa_irq = true;
		}
1062 1063
	}

1064
	return irq;
1065 1066 1067
}

static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
1068
			     unsigned int flags, struct irq_alloc_info *info)
1069 1070
{
	int irq;
1071 1072 1073
	bool legacy = false;
	struct irq_alloc_info tmp;
	struct mp_chip_data *data;
1074 1075
	struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);

1076
	if (!domain)
1077
		return -ENOSYS;
1078 1079 1080

	if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) {
		irq = mp_irqs[idx].srcbusirq;
1081 1082
		legacy = mp_is_legacy_irq(irq);
	}
1083

1084 1085 1086 1087
	mutex_lock(&ioapic_mutex);
	if (!(flags & IOAPIC_MAP_ALLOC)) {
		if (!legacy) {
			irq = irq_find_mapping(domain, pin);
1088
			if (irq == 0)
1089
				irq = -ENOENT;
1090 1091
		}
	} else {
1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103
		ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin);
		if (legacy)
			irq = alloc_isa_irq_from_domain(domain, irq,
							ioapic, pin, &tmp);
		else if ((irq = irq_find_mapping(domain, pin)) == 0)
			irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp);
		else if (!mp_check_pin_attr(irq, &tmp))
			irq = -EBUSY;
		if (irq >= 0) {
			data = irq_get_chip_data(irq);
			data->count++;
		}
1104
	}
1105 1106
	mutex_unlock(&ioapic_mutex);

1107
	return irq;
1108 1109
}

1110
static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
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{
1112
	u32 gsi = mp_pin_to_gsi(ioapic, pin);
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1113 1114 1115 1116

	/*
	 * Debugging check, we are in big trouble if this message pops up!
	 */
1117
	if (mp_irqs[idx].dstirq != pin)
1118
		pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
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1119

1120
#ifdef CONFIG_X86_32
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1121 1122 1123 1124 1125 1126 1127 1128 1129
	/*
	 * PCI IRQ command line redirection. Yes, limits are hardcoded.
	 */
	if ((pin >= 16) && (pin <= 23)) {
		if (pirq_entries[pin-16] != -1) {
			if (!pirq_entries[pin-16]) {
				apic_printk(APIC_VERBOSE, KERN_DEBUG
						"disabling PIRQ%d\n", pin-16);
			} else {
1130
				int irq = pirq_entries[pin-16];
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				apic_printk(APIC_VERBOSE, KERN_DEBUG
						"using PIRQ%d -> IRQ %d\n",
						pin-16, irq);
1134
				return irq;
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1135 1136 1137
			}
		}
	}
1138 1139
#endif

1140
	return  mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL);
1141
}
1142

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int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, struct irq_alloc_info *info)
1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155
{
	int ioapic, pin, idx;

	ioapic = mp_find_ioapic(gsi);
	if (ioapic < 0)
		return -1;

	pin = mp_find_ioapic_pin(ioapic, gsi);
	idx = find_irq_entry(ioapic, pin, mp_INT);
	if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
		return -1;

1156
	return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info);
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}

1159 1160
void mp_unmap_irq(int irq)
{
1161 1162
	struct irq_data *irq_data = irq_get_irq_data(irq);
	struct mp_chip_data *data;
1163

1164
	if (!irq_data || !irq_data->domain)
1165 1166
		return;

1167 1168 1169
	data = irq_data->chip_data;
	if (!data || data->isa_irq)
		return;
1170 1171

	mutex_lock(&ioapic_mutex);
1172 1173
	if (--data->count == 0)
		irq_domain_free_irqs(irq, 1);
1174 1175 1176
	mutex_unlock(&ioapic_mutex);
}

1177 1178 1179 1180
/*
 * Find a specific PCI IRQ entry.
 * Not an __init, possibly needed by modules
 */
1181
int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1182
{
1183
	int irq, i, best_ioapic = -1, best_idx = -1;
1184 1185 1186 1187 1188 1189 1190 1191 1192

	apic_printk(APIC_DEBUG,
		    "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
		    bus, slot, pin);
	if (test_bit(bus, mp_bus_not_pci)) {
		apic_printk(APIC_VERBOSE,
			    "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
		return -1;
	}
1193

1194 1195
	for (i = 0; i < mp_irq_entries; i++) {
		int lbus = mp_irqs[i].srcbus;
1196 1197 1198 1199 1200
		int ioapic_idx, found = 0;

		if (bus != lbus || mp_irqs[i].irqtype != mp_INT ||
		    slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f))
			continue;
1201

1202
		for_each_ioapic(ioapic_idx)
1203
			if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1204 1205
			    mp_irqs[i].dstapic == MP_APIC_ALL) {
				found = 1;
1206 1207
				break;
			}
1208 1209 1210 1211
		if (!found)
			continue;

		/* Skip ISA IRQs */
1212 1213
		irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0);
		if (irq > 0 && !IO_APIC_IRQ(irq))
1214 1215 1216
			continue;

		if (pin == (mp_irqs[i].srcbusirq & 3)) {
1217 1218 1219
			best_idx = i;
			best_ioapic = ioapic_idx;
			goto out;
1220
		}
1221

1222 1223 1224 1225
		/*
		 * Use the first all-but-pin matching entry as a
		 * best-guess fuzzy result for broken mptables.
		 */
1226 1227 1228
		if (best_idx < 0) {
			best_idx = i;
			best_ioapic = ioapic_idx;
1229 1230
		}
	}
1231 1232 1233 1234
	if (best_idx < 0)
		return -1;

out:
1235 1236
	return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq,
			 IOAPIC_MAP_ALLOC);
1237 1238 1239
}
EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);

1240
static struct irq_chip ioapic_chip, ioapic_ir_chip;
L
Linus Torvalds 已提交
1241

1242
#ifdef CONFIG_X86_32
1243 1244
static inline int IO_APIC_irq_trigger(int irq)
{
T
Thomas Gleixner 已提交
1245
	int apic, idx, pin;
1246

1247 1248
	for_each_ioapic_pin(apic, pin) {
		idx = find_irq_entry(apic, pin, mp_INT);
1249
		if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin, 0)))
1250
			return irq_trigger(idx);
T
Thomas Gleixner 已提交
1251 1252
	}
	/*
1253 1254
         * nonexistent IRQs are edge default
         */
T
Thomas Gleixner 已提交
1255
	return 0;
1256
}
1257 1258 1259
#else
static inline int IO_APIC_irq_trigger(int irq)
{
1260
	return 1;
1261 1262
}
#endif
1263

1264 1265
static void __init setup_IO_APIC_irqs(void)
{
1266 1267
	unsigned int ioapic, pin;
	int idx;
1268 1269 1270

	apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");

1271 1272 1273 1274 1275 1276 1277 1278 1279 1280
	for_each_ioapic_pin(ioapic, pin) {
		idx = find_irq_entry(ioapic, pin, mp_INT);
		if (idx < 0)
			apic_printk(APIC_VERBOSE,
				    KERN_DEBUG " apic %d pin %d not connected\n",
				    mpc_ioapic_id(ioapic), pin);
		else
			pin_2_irq(idx, ioapic, pin,
				  ioapic ? 0 : IOAPIC_MAP_ALLOC);
	}
1281 1282
}

1283 1284 1285 1286 1287
void ioapic_zap_locks(void)
{
	raw_spin_lock_init(&ioapic_lock);
}

1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314
static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
{
	int i;
	char buf[256];
	struct IO_APIC_route_entry entry;
	struct IR_IO_APIC_route_entry *ir_entry = (void *)&entry;

	printk(KERN_DEBUG "IOAPIC %d:\n", apic);
	for (i = 0; i <= nr_entries; i++) {
		entry = ioapic_read_entry(apic, i);
		snprintf(buf, sizeof(buf),
			 " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)",
			 i, entry.mask ? "disabled" : "enabled ",
			 entry.trigger ? "level" : "edge ",
			 entry.polarity ? "low " : "high",
			 entry.vector, entry.irr, entry.delivery_status);
		if (ir_entry->format)
			printk(KERN_DEBUG "%s, remapped, I(%04X),  Z(%X)\n",
			       buf, (ir_entry->index << 15) | ir_entry->index,
			       ir_entry->zero);
		else
			printk(KERN_DEBUG "%s, %s, D(%02X), M(%1d)\n",
			       buf, entry.dest_mode ? "logical " : "physical",
			       entry.dest, entry.delivery_mode);
	}
}

1315
static void __init print_IO_APIC(int ioapic_idx)
1316
{
L
Linus Torvalds 已提交
1317 1318 1319 1320 1321 1322
	union IO_APIC_reg_00 reg_00;
	union IO_APIC_reg_01 reg_01;
	union IO_APIC_reg_02 reg_02;
	union IO_APIC_reg_03 reg_03;
	unsigned long flags;

1323
	raw_spin_lock_irqsave(&ioapic_lock, flags);
1324 1325
	reg_00.raw = io_apic_read(ioapic_idx, 0);
	reg_01.raw = io_apic_read(ioapic_idx, 1);
L
Linus Torvalds 已提交
1326
	if (reg_01.bits.version >= 0x10)
1327
		reg_02.raw = io_apic_read(ioapic_idx, 2);
T
Thomas Gleixner 已提交
1328
	if (reg_01.bits.version >= 0x20)
1329
		reg_03.raw = io_apic_read(ioapic_idx, 3);
1330
	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
L
Linus Torvalds 已提交
1331

1332
	printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
L
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1333 1334 1335 1336 1337
	printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
	printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
	printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
	printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);

1338
	printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1339 1340
	printk(KERN_DEBUG ".......     : max redirection entries: %02X\n",
		reg_01.bits.entries);
L
Linus Torvalds 已提交
1341 1342

	printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1343 1344
	printk(KERN_DEBUG ".......     : IO APIC version: %02X\n",
		reg_01.bits.version);
L
Linus Torvalds 已提交
1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367

	/*
	 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
	 * but the value of reg_02 is read as the previous read register
	 * value, so ignore it if reg_02 == reg_01.
	 */
	if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
		printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
		printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
	}

	/*
	 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
	 * or reg_03, but the value of reg_0[23] is read as the previous read
	 * register value, so ignore it if reg_03 == reg_0[12].
	 */
	if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
	    reg_03.raw != reg_01.raw) {
		printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
		printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
	}

	printk(KERN_DEBUG ".... IRQ redirection table:\n");
1368
	io_apic_print_entries(ioapic_idx, reg_01.bits.entries);
1369 1370
}

1371
void __init print_IO_APICs(void)
1372
{
1373
	int ioapic_idx;
1374 1375 1376
	unsigned int irq;

	printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1377
	for_each_ioapic(ioapic_idx)
1378
		printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1379 1380
		       mpc_ioapic_id(ioapic_idx),
		       ioapics[ioapic_idx].nr_registers);
1381 1382 1383 1384 1385 1386 1387

	/*
	 * We are a bit conservative about what we expect.  We have to
	 * know about every hardware change ASAP.
	 */
	printk(KERN_INFO "testing the IO APIC.......................\n");

1388
	for_each_ioapic(ioapic_idx)
1389
		print_IO_APIC(ioapic_idx);
1390

L
Linus Torvalds 已提交
1391
	printk(KERN_DEBUG "IRQ to pin mappings:\n");
T
Thomas Gleixner 已提交
1392
	for_each_active_irq(irq) {
1393
		struct irq_pin_list *entry;
1394 1395
		struct irq_chip *chip;
		struct mp_chip_data *data;
1396

1397
		chip = irq_get_chip(irq);
1398
		if (chip != &ioapic_chip && chip != &ioapic_ir_chip)
1399
			continue;
1400 1401
		data = irq_get_chip_data(irq);
		if (!data)
1402
			continue;
1403
		if (list_empty(&data->irq_2_pin))
L
Linus Torvalds 已提交
1404
			continue;
1405

1406
		printk(KERN_DEBUG "IRQ%d ", irq);
1407
		for_each_irq_pin(entry, data->irq_2_pin)
1408 1409
			pr_cont("-> %d:%d", entry->apic, entry->pin);
		pr_cont("\n");
L
Linus Torvalds 已提交
1410 1411 1412 1413 1414
	}

	printk(KERN_INFO ".................................... done.\n");
}

Y
Yinghai Lu 已提交
1415 1416 1417
/* Where if anywhere is the i8259 connect in external int mode */
static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };

1418
void __init enable_IO_APIC(void)
L
Linus Torvalds 已提交
1419
{
1420
	int i8259_apic, i8259_pin;
1421
	int apic, pin;
1422

1423 1424 1425 1426
	if (skip_ioapic_setup)
		nr_ioapics = 0;

	if (!nr_legacy_irqs() || !nr_ioapics)
1427 1428
		return;

1429
	for_each_ioapic_pin(apic, pin) {
1430
		/* See if any of the pins is in ExtINT mode */
1431
		struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin);
1432

1433 1434 1435 1436 1437 1438 1439
		/* If the interrupt line is enabled and in ExtInt mode
		 * I have found the pin where the i8259 is connected.
		 */
		if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
			ioapic_i8259.apic = apic;
			ioapic_i8259.pin  = pin;
			goto found_i8259;
1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460
		}
	}
 found_i8259:
	/* Look to see what if the MP table has reported the ExtINT */
	/* If we could not find the appropriate pin by looking at the ioapic
	 * the i8259 probably is not connected the ioapic but give the
	 * mptable a chance anyway.
	 */
	i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
	i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
	/* Trust the MP table if nothing is setup in the hardware */
	if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
		printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
		ioapic_i8259.pin  = i8259_pin;
		ioapic_i8259.apic = i8259_apic;
	}
	/* Complain if the MP table and the hardware disagree */
	if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
		(i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
	{
		printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
L
Linus Torvalds 已提交
1461 1462 1463 1464 1465 1466 1467 1468
	}

	/*
	 * Do not trust the IO-APIC being empty at bootup
	 */
	clear_IO_APIC();
}

1469
void native_disable_io_apic(void)
L
Linus Torvalds 已提交
1470
{
1471
	/*
1472
	 * If the i8259 is routed through an IOAPIC
1473
	 * Put that IOAPIC in virtual wire mode
1474
	 * so legacy interrupts can be delivered.
1475
	 */
1476
	if (ioapic_i8259.pin != -1) {
1477 1478 1479 1480 1481 1482 1483 1484 1485
		struct IO_APIC_route_entry entry;

		memset(&entry, 0, sizeof(entry));
		entry.mask            = 0; /* Enabled */
		entry.trigger         = 0; /* Edge */
		entry.irr             = 0;
		entry.polarity        = 0; /* High */
		entry.delivery_status = 0;
		entry.dest_mode       = 0; /* Physical */
1486
		entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1487
		entry.vector          = 0;
1488
		entry.dest            = read_apic_id();
1489 1490 1491 1492

		/*
		 * Add it to the IO-APIC irq-routing table:
		 */
1493
		ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1494
	}
1495

1496 1497 1498 1499 1500 1501 1502 1503 1504 1505
	if (cpu_has_apic || apic_from_smp_config())
		disconnect_bsp_APIC(ioapic_i8259.pin != -1);

}

/*
 * Not an __init, needed by the reboot code
 */
void disable_IO_APIC(void)
{
1506
	/*
1507
	 * Clear the IO-APIC before rebooting:
1508
	 */
1509 1510
	clear_IO_APIC();

1511
	if (!nr_legacy_irqs())
1512 1513 1514
		return;

	x86_io_apic_ops.disable();
L
Linus Torvalds 已提交
1515 1516
}

1517
#ifdef CONFIG_X86_32
L
Linus Torvalds 已提交
1518 1519 1520 1521 1522 1523
/*
 * function to set the IO-APIC physical IDs based on the
 * values stored in the MPC table.
 *
 * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
 */
1524
void __init setup_ioapic_ids_from_mpc_nocheck(void)
L
Linus Torvalds 已提交
1525 1526 1527
{
	union IO_APIC_reg_00 reg_00;
	physid_mask_t phys_id_present_map;
1528
	int ioapic_idx;
L
Linus Torvalds 已提交
1529 1530 1531 1532 1533 1534 1535 1536
	int i;
	unsigned char old_id;
	unsigned long flags;

	/*
	 * This is broken; anything with a real cpu count has to
	 * circumvent this idiocy regardless.
	 */
1537
	apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
L
Linus Torvalds 已提交
1538 1539 1540 1541

	/*
	 * Set the IOAPIC ID to the value stored in the MPC table.
	 */
1542
	for_each_ioapic(ioapic_idx) {
L
Linus Torvalds 已提交
1543
		/* Read the register 0 value */
1544
		raw_spin_lock_irqsave(&ioapic_lock, flags);
1545
		reg_00.raw = io_apic_read(ioapic_idx, 0);
1546
		raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1547

1548
		old_id = mpc_ioapic_id(ioapic_idx);
L
Linus Torvalds 已提交
1549

1550
		if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
L
Linus Torvalds 已提交
1551
			printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1552
				ioapic_idx, mpc_ioapic_id(ioapic_idx));
L
Linus Torvalds 已提交
1553 1554
			printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
				reg_00.bits.ID);
1555
			ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
L
Linus Torvalds 已提交
1556 1557 1558 1559 1560 1561 1562
		}

		/*
		 * Sanity check, is the ID really free? Every APIC in a
		 * system must have a unique ID or we get lots of nice
		 * 'stuck on smp_invalidate_needed IPI wait' messages.
		 */
1563
		if (apic->check_apicid_used(&phys_id_present_map,
1564
					    mpc_ioapic_id(ioapic_idx))) {
L
Linus Torvalds 已提交
1565
			printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1566
				ioapic_idx, mpc_ioapic_id(ioapic_idx));
L
Linus Torvalds 已提交
1567 1568 1569 1570 1571 1572 1573 1574
			for (i = 0; i < get_physical_broadcast(); i++)
				if (!physid_isset(i, phys_id_present_map))
					break;
			if (i >= get_physical_broadcast())
				panic("Max APIC ID exceeded!\n");
			printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
				i);
			physid_set(i, phys_id_present_map);
1575
			ioapics[ioapic_idx].mp_config.apicid = i;
L
Linus Torvalds 已提交
1576 1577
		} else {
			physid_mask_t tmp;
1578
			apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
1579
						    &tmp);
L
Linus Torvalds 已提交
1580 1581
			apic_printk(APIC_VERBOSE, "Setting %d in the "
					"phys_id_present_map\n",
1582
					mpc_ioapic_id(ioapic_idx));
L
Linus Torvalds 已提交
1583 1584 1585 1586 1587 1588 1589
			physids_or(phys_id_present_map, phys_id_present_map, tmp);
		}

		/*
		 * We need to adjust the IRQ routing table
		 * if the ID changed.
		 */
1590
		if (old_id != mpc_ioapic_id(ioapic_idx))
L
Linus Torvalds 已提交
1591
			for (i = 0; i < mp_irq_entries; i++)
1592 1593
				if (mp_irqs[i].dstapic == old_id)
					mp_irqs[i].dstapic
1594
						= mpc_ioapic_id(ioapic_idx);
L
Linus Torvalds 已提交
1595 1596

		/*
1597 1598
		 * Update the ID register according to the right value
		 * from the MPC table if they are different.
1599
		 */
1600
		if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
1601 1602
			continue;

L
Linus Torvalds 已提交
1603 1604
		apic_printk(APIC_VERBOSE, KERN_INFO
			"...changing IO-APIC physical APIC ID to %d ...",
1605
			mpc_ioapic_id(ioapic_idx));
L
Linus Torvalds 已提交
1606

1607
		reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
1608
		raw_spin_lock_irqsave(&ioapic_lock, flags);
1609
		io_apic_write(ioapic_idx, 0, reg_00.raw);
1610
		raw_spin_unlock_irqrestore(&ioapic_lock, flags);
L
Linus Torvalds 已提交
1611 1612 1613 1614

		/*
		 * Sanity check
		 */
1615
		raw_spin_lock_irqsave(&ioapic_lock, flags);
1616
		reg_00.raw = io_apic_read(ioapic_idx, 0);
1617
		raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1618
		if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
1619
			pr_cont("could not set ID!\n");
L
Linus Torvalds 已提交
1620 1621 1622 1623
		else
			apic_printk(APIC_VERBOSE, " ok.\n");
	}
}
1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638

void __init setup_ioapic_ids_from_mpc(void)
{

	if (acpi_ioapic)
		return;
	/*
	 * Don't check I/O APIC IDs for xAPIC systems.  They have
	 * no meaning without the serial APIC bus.
	 */
	if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
		|| APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
		return;
	setup_ioapic_ids_from_mpc_nocheck();
}
1639
#endif
L
Linus Torvalds 已提交
1640

1641
int no_timer_check __initdata;
1642 1643 1644 1645 1646 1647 1648 1649

static int __init notimercheck(char *s)
{
	no_timer_check = 1;
	return 1;
}
__setup("no_timer_check", notimercheck);

L
Linus Torvalds 已提交
1650 1651 1652 1653 1654 1655 1656 1657
/*
 * There is a nasty bug in some older SMP boards, their mptable lies
 * about the timer IRQ. We do the following to work around the situation:
 *
 *	- timer IRQ defaults to IO-APIC IRQ
 *	- if this function detects that timer IRQs are defunct, then we fall
 *	  back to ISA timer IRQs
 */
1658
static int __init timer_irq_works(void)
L
Linus Torvalds 已提交
1659 1660
{
	unsigned long t1 = jiffies;
1661
	unsigned long flags;
L
Linus Torvalds 已提交
1662

1663 1664 1665
	if (no_timer_check)
		return 1;

1666
	local_save_flags(flags);
L
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1667 1668 1669
	local_irq_enable();
	/* Let ten ticks pass... */
	mdelay((10 * 1000) / HZ);
1670
	local_irq_restore(flags);
L
Linus Torvalds 已提交
1671 1672 1673 1674 1675 1676 1677 1678

	/*
	 * Expect a few ticks at least, to be sure some possible
	 * glue logic does not lock up after one or two first
	 * ticks in a non-ExtINT mode.  Also the local APIC
	 * might have cached one ExtINT interrupt.  Finally, at
	 * least one tick may be lost due to delays.
	 */
1679 1680

	/* jiffies wrap? */
1681
	if (time_after(jiffies, t1 + 4))
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1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707
		return 1;
	return 0;
}

/*
 * In the SMP+IOAPIC case it might happen that there are an unspecified
 * number of pending IRQ events unhandled. These cases are very rare,
 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
 * better to do it this way as thus we do not have to be aware of
 * 'pending' interrupts in the IRQ path, except at this point.
 */
/*
 * Edge triggered needs to resend any interrupt
 * that was delayed but this is now handled in the device
 * independent code.
 */

/*
 * Starting up a edge-triggered IO-APIC interrupt is
 * nasty - we need to make sure that we get the edge.
 * If it is already asserted for some reason, we need
 * return 1 to indicate that is was pending.
 *
 * This is not complete - we should be able to fake
 * an edge even if it isn't on the 8259A...
 */
1708
static unsigned int startup_ioapic_irq(struct irq_data *data)
L
Linus Torvalds 已提交
1709
{
1710
	int was_pending = 0, irq = data->irq;
L
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1711 1712
	unsigned long flags;

1713
	raw_spin_lock_irqsave(&ioapic_lock, flags);
1714
	if (irq < nr_legacy_irqs()) {
1715
		legacy_pic->mask(irq);
1716
		if (legacy_pic->irq_pending(irq))
L
Linus Torvalds 已提交
1717 1718
			was_pending = 1;
	}
1719
	__unmask_ioapic(data->chip_data);
1720
	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
L
Linus Torvalds 已提交
1721 1722 1723 1724

	return was_pending;
}

Y
Yinghai Lu 已提交
1725 1726
atomic_t irq_mis_count;

1727
#ifdef CONFIG_GENERIC_PENDING_IRQ
1728
static bool io_apic_level_ack_pending(struct mp_chip_data *data)
1729 1730 1731 1732 1733
{
	struct irq_pin_list *entry;
	unsigned long flags;

	raw_spin_lock_irqsave(&ioapic_lock, flags);
1734
	for_each_irq_pin(entry, data->irq_2_pin) {
1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750
		unsigned int reg;
		int pin;

		pin = entry->pin;
		reg = io_apic_read(entry->apic, 0x10 + pin*2);
		/* Is the remote IRR bit set? */
		if (reg & IO_APIC_REDIR_REMOTE_IRR) {
			raw_spin_unlock_irqrestore(&ioapic_lock, flags);
			return true;
		}
	}
	raw_spin_unlock_irqrestore(&ioapic_lock, flags);

	return false;
}

1751
static inline bool ioapic_irqd_mask(struct irq_data *data)
1752
{
1753
	/* If we are moving the irq we need to mask it */
1754
	if (unlikely(irqd_is_setaffinity_pending(data))) {
1755
		mask_ioapic_irq(data);
1756
		return true;
1757
	}
1758 1759 1760
	return false;
}

1761
static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789
{
	if (unlikely(masked)) {
		/* Only migrate the irq if the ack has been received.
		 *
		 * On rare occasions the broadcast level triggered ack gets
		 * delayed going to ioapics, and if we reprogram the
		 * vector while Remote IRR is still set the irq will never
		 * fire again.
		 *
		 * To prevent this scenario we read the Remote IRR bit
		 * of the ioapic.  This has two effects.
		 * - On any sane system the read of the ioapic will
		 *   flush writes (and acks) going to the ioapic from
		 *   this cpu.
		 * - We get to see if the ACK has actually been delivered.
		 *
		 * Based on failed experiments of reprogramming the
		 * ioapic entry from outside of irq context starting
		 * with masking the ioapic entry and then polling until
		 * Remote IRR was clear before reprogramming the
		 * ioapic I don't trust the Remote IRR bit to be
		 * completey accurate.
		 *
		 * However there appears to be no other way to plug
		 * this race, so if the Remote IRR bit is not
		 * accurate and is causing problems then it is a hardware bug
		 * and you can go talk to the chipset vendor about it.
		 */
1790
		if (!io_apic_level_ack_pending(data->chip_data))
1791
			irq_move_masked_irq(data);
1792
		unmask_ioapic_irq(data);
1793 1794 1795
	}
}
#else
1796
static inline bool ioapic_irqd_mask(struct irq_data *data)
1797 1798 1799
{
	return false;
}
1800
static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
1801 1802
{
}
1803 1804
#endif

1805
static void ioapic_ack_level(struct irq_data *irq_data)
1806
{
1807
	struct irq_cfg *cfg = irqd_cfg(irq_data);
1808 1809
	unsigned long v;
	bool masked;
1810
	int i;
1811 1812

	irq_complete_move(cfg);
1813
	masked = ioapic_irqd_mask(irq_data);
1814

Y
Yinghai Lu 已提交
1815
	/*
1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832
	 * It appears there is an erratum which affects at least version 0x11
	 * of I/O APIC (that's the 82093AA and cores integrated into various
	 * chipsets).  Under certain conditions a level-triggered interrupt is
	 * erroneously delivered as edge-triggered one but the respective IRR
	 * bit gets set nevertheless.  As a result the I/O unit expects an EOI
	 * message but it will never arrive and further interrupts are blocked
	 * from the source.  The exact reason is so far unknown, but the
	 * phenomenon was observed when two consecutive interrupt requests
	 * from a given source get delivered to the same CPU and the source is
	 * temporarily disabled in between.
	 *
	 * A workaround is to simulate an EOI message manually.  We achieve it
	 * by setting the trigger mode to edge and then to level when the edge
	 * trigger mode gets detected in the TMR of a local APIC for a
	 * level-triggered interrupt.  We mask the source for the time of the
	 * operation to prevent an edge-triggered interrupt escaping meanwhile.
	 * The idea is from Manfred Spraul.  --macro
1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845
	 *
	 * Also in the case when cpu goes offline, fixup_irqs() will forward
	 * any unhandled interrupt on the offlined cpu to the new cpu
	 * destination that is handling the corresponding interrupt. This
	 * interrupt forwarding is done via IPI's. Hence, in this case also
	 * level-triggered io-apic interrupt will be seen as an edge
	 * interrupt in the IRR. And we can't rely on the cpu's EOI
	 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
	 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
	 * supporting EOI register, we do an explicit EOI to clear the
	 * remote IRR and on IO-APIC's which don't have an EOI register,
	 * we use the above logic (mask+edge followed by unmask+level) from
	 * Manfred Spraul to clear the remote IRR.
1846
	 */
Y
Yinghai Lu 已提交
1847
	i = cfg->vector;
Y
Yinghai Lu 已提交
1848 1849
	v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));

1850 1851 1852 1853 1854 1855
	/*
	 * We must acknowledge the irq before we move it or the acknowledge will
	 * not propagate properly.
	 */
	ack_APIC_irq();

1856 1857 1858 1859 1860 1861 1862
	/*
	 * Tail end of clearing remote IRR bit (either by delivering the EOI
	 * message via io-apic EOI register write or simulating it using
	 * mask+edge followed by unnask+level logic) manually when the
	 * level triggered interrupt is seen as the edge triggered interrupt
	 * at the cpu.
	 */
1863 1864
	if (!(v & (1 << (i & 0x1f)))) {
		atomic_inc(&irq_mis_count);
1865
		eoi_ioapic_pin(cfg->vector, irq_data->chip_data);
1866 1867
	}

1868
	ioapic_irqd_unmask(irq_data, masked);
Y
Yinghai Lu 已提交
1869
}
1870

1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881
static void ioapic_ir_ack_level(struct irq_data *irq_data)
{
	struct mp_chip_data *data = irq_data->chip_data;

	/*
	 * Intr-remapping uses pin number as the virtual vector
	 * in the RTE. Actual vector is programmed in
	 * intr-remapping table entry. Hence for the io-apic
	 * EOI we use the pin number.
	 */
	ack_APIC_irq();
1882
	eoi_ioapic_pin(data->entry.vector, data);
1883 1884 1885 1886 1887 1888 1889
}

static int ioapic_set_affinity(struct irq_data *irq_data,
			       const struct cpumask *mask, bool force)
{
	struct irq_data *parent = irq_data->parent_data;
	struct mp_chip_data *data = irq_data->chip_data;
1890
	struct irq_pin_list *entry;
1891 1892 1893 1894 1895 1896 1897 1898 1899 1900
	struct irq_cfg *cfg;
	unsigned long flags;
	int ret;

	ret = parent->chip->irq_set_affinity(parent, mask, force);
	raw_spin_lock_irqsave(&ioapic_lock, flags);
	if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) {
		cfg = irqd_cfg(irq_data);
		data->entry.dest = cfg->dest_apicid;
		data->entry.vector = cfg->vector;
1901 1902 1903
		for_each_irq_pin(entry, data->irq_2_pin)
			__ioapic_write_entry(entry->apic, entry->pin,
					     data->entry);
1904 1905 1906 1907 1908 1909
	}
	raw_spin_unlock_irqrestore(&ioapic_lock, flags);

	return ret;
}

1910
static struct irq_chip ioapic_chip __read_mostly = {
1911 1912 1913 1914
	.name			= "IO-APIC",
	.irq_startup		= startup_ioapic_irq,
	.irq_mask		= mask_ioapic_irq,
	.irq_unmask		= unmask_ioapic_irq,
1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928
	.irq_ack		= irq_chip_ack_parent,
	.irq_eoi		= ioapic_ack_level,
	.irq_set_affinity	= ioapic_set_affinity,
	.flags			= IRQCHIP_SKIP_SET_WAKE,
};

static struct irq_chip ioapic_ir_chip __read_mostly = {
	.name			= "IR-IO-APIC",
	.irq_startup		= startup_ioapic_irq,
	.irq_mask		= mask_ioapic_irq,
	.irq_unmask		= unmask_ioapic_irq,
	.irq_ack		= irq_chip_ack_parent,
	.irq_eoi		= ioapic_ir_ack_level,
	.irq_set_affinity	= ioapic_set_affinity,
1929
	.flags			= IRQCHIP_SKIP_SET_WAKE,
L
Linus Torvalds 已提交
1930 1931 1932 1933
};

static inline void init_IO_APIC_traps(void)
{
1934
	struct irq_cfg *cfg;
T
Thomas Gleixner 已提交
1935
	unsigned int irq;
L
Linus Torvalds 已提交
1936

T
Thomas Gleixner 已提交
1937
	for_each_active_irq(irq) {
1938
		cfg = irq_cfg(irq);
1939
		if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
L
Linus Torvalds 已提交
1940 1941 1942 1943 1944
			/*
			 * Hmm.. We don't have an entry for this,
			 * so default to an old-fashioned 8259
			 * interrupt if we can..
			 */
1945
			if (irq < nr_legacy_irqs())
1946
				legacy_pic->make_irq(irq);
1947
			else
L
Linus Torvalds 已提交
1948
				/* Strange. Oh, well.. */
1949
				irq_set_chip(irq, &no_irq_chip);
L
Linus Torvalds 已提交
1950 1951 1952 1953
		}
	}
}

1954 1955 1956
/*
 * The local APIC irq-chip implementation:
 */
L
Linus Torvalds 已提交
1957

1958
static void mask_lapic_irq(struct irq_data *data)
L
Linus Torvalds 已提交
1959 1960 1961 1962
{
	unsigned long v;

	v = apic_read(APIC_LVT0);
1963
	apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
L
Linus Torvalds 已提交
1964 1965
}

1966
static void unmask_lapic_irq(struct irq_data *data)
L
Linus Torvalds 已提交
1967
{
1968
	unsigned long v;
L
Linus Torvalds 已提交
1969

1970
	v = apic_read(APIC_LVT0);
1971
	apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1972
}
L
Linus Torvalds 已提交
1973

1974
static void ack_lapic_irq(struct irq_data *data)
1975 1976 1977 1978
{
	ack_APIC_irq();
}

1979
static struct irq_chip lapic_chip __read_mostly = {
1980
	.name		= "local-APIC",
1981 1982 1983
	.irq_mask	= mask_lapic_irq,
	.irq_unmask	= unmask_lapic_irq,
	.irq_ack	= ack_lapic_irq,
L
Linus Torvalds 已提交
1984 1985
};

1986
static void lapic_register_intr(int irq)
1987
{
1988
	irq_clear_status_flags(irq, IRQ_LEVEL);
1989
	irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
1990 1991 1992
				      "edge");
}

L
Linus Torvalds 已提交
1993 1994 1995 1996 1997 1998 1999
/*
 * This looks a bit hackish but it's about the only one way of sending
 * a few INTA cycles to 8259As and any associated glue logic.  ICR does
 * not support the ExtINT mode, unfortunately.  We need to send these
 * cycles as some i82489DX-based boards have glue logic that keeps the
 * 8259A interrupt line asserted until INTA.  --macro
 */
2000
static inline void __init unlock_ExtINT_logic(void)
L
Linus Torvalds 已提交
2001
{
2002
	int apic, pin, i;
L
Linus Torvalds 已提交
2003 2004 2005
	struct IO_APIC_route_entry entry0, entry1;
	unsigned char save_control, save_freq_select;

2006
	pin  = find_isa_irq_pin(8, mp_INT);
2007 2008 2009 2010
	if (pin == -1) {
		WARN_ON_ONCE(1);
		return;
	}
2011
	apic = find_isa_irq_apic(8, mp_INT);
2012 2013
	if (apic == -1) {
		WARN_ON_ONCE(1);
L
Linus Torvalds 已提交
2014
		return;
2015
	}
L
Linus Torvalds 已提交
2016

2017
	entry0 = ioapic_read_entry(apic, pin);
2018
	clear_IO_APIC_pin(apic, pin);
L
Linus Torvalds 已提交
2019 2020 2021 2022 2023

	memset(&entry1, 0, sizeof(entry1));

	entry1.dest_mode = 0;			/* physical delivery */
	entry1.mask = 0;			/* unmask IRQ now */
2024
	entry1.dest = hard_smp_processor_id();
L
Linus Torvalds 已提交
2025 2026 2027 2028 2029
	entry1.delivery_mode = dest_ExtINT;
	entry1.polarity = entry0.polarity;
	entry1.trigger = 0;
	entry1.vector = 0;

2030
	ioapic_write_entry(apic, pin, entry1);
L
Linus Torvalds 已提交
2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046

	save_control = CMOS_READ(RTC_CONTROL);
	save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
	CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
		   RTC_FREQ_SELECT);
	CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);

	i = 100;
	while (i-- > 0) {
		mdelay(10);
		if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
			i -= 10;
	}

	CMOS_WRITE(save_control, RTC_CONTROL);
	CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2047
	clear_IO_APIC_pin(apic, pin);
L
Linus Torvalds 已提交
2048

2049
	ioapic_write_entry(apic, pin, entry0);
L
Linus Torvalds 已提交
2050 2051
}

Y
Yinghai Lu 已提交
2052
static int disable_timer_pin_1 __initdata;
2053
/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2054
static int __init disable_timer_pin_setup(char *arg)
Y
Yinghai Lu 已提交
2055 2056 2057 2058
{
	disable_timer_pin_1 = 1;
	return 0;
}
2059
early_param("disable_timer_pin_1", disable_timer_pin_setup);
Y
Yinghai Lu 已提交
2060

2061 2062 2063 2064 2065 2066
static int mp_alloc_timer_irq(int ioapic, int pin)
{
	int irq = -1;
	struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);

	if (domain) {
2067 2068
		struct irq_alloc_info info;

2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079
		ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0);
		info.ioapic_id = mpc_ioapic_id(ioapic);
		info.ioapic_pin = pin;
		mutex_lock(&ioapic_mutex);
		irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info);
		mutex_unlock(&ioapic_mutex);
	}

	return irq;
}

L
Linus Torvalds 已提交
2080 2081 2082 2083 2084
/*
 * This code may look a bit paranoid, but it's supposed to cooperate with
 * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
 * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
 * fanatically on his truly buggy board.
2085 2086
 *
 * FIXME: really need to revamp this for all platforms.
L
Linus Torvalds 已提交
2087
 */
2088
static inline void __init check_timer(void)
L
Linus Torvalds 已提交
2089
{
2090 2091 2092
	struct irq_data *irq_data = irq_get_irq_data(0);
	struct mp_chip_data *data = irq_data->chip_data;
	struct irq_cfg *cfg = irqd_cfg(irq_data);
2093
	int node = cpu_to_node(0);
2094
	int apic1, pin1, apic2, pin2;
2095
	unsigned long flags;
2096
	int no_pin1 = 0;
2097 2098

	local_irq_save(flags);
2099

L
Linus Torvalds 已提交
2100 2101 2102
	/*
	 * get/set the timer IRQ vector:
	 */
2103
	legacy_pic->mask(0);
L
Linus Torvalds 已提交
2104 2105

	/*
2106 2107 2108 2109 2110 2111 2112
	 * As IRQ0 is to be enabled in the 8259A, the virtual
	 * wire has to be disabled in the local APIC.  Also
	 * timer interrupts need to be acknowledged manually in
	 * the 8259A for the i82489DX when using the NMI
	 * watchdog as that APIC treats NMIs as level-triggered.
	 * The AEOI mode will finish them in the 8259A
	 * automatically.
L
Linus Torvalds 已提交
2113
	 */
2114
	apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2115
	legacy_pic->init(1);
L
Linus Torvalds 已提交
2116

2117 2118 2119 2120
	pin1  = find_isa_irq_pin(0, mp_INT);
	apic1 = find_isa_irq_apic(0, mp_INT);
	pin2  = ioapic_i8259.pin;
	apic2 = ioapic_i8259.apic;
L
Linus Torvalds 已提交
2121

2122 2123
	apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
		    "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2124
		    cfg->vector, apic1, pin1, apic2, pin2);
L
Linus Torvalds 已提交
2125

2126 2127 2128 2129 2130 2131 2132 2133
	/*
	 * Some BIOS writers are clueless and report the ExtINTA
	 * I/O APIC input from the cascaded 8259A as the timer
	 * interrupt input.  So just in case, if only one pin
	 * was found above, try it both directly and through the
	 * 8259A.
	 */
	if (pin1 == -1) {
2134
		panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2135 2136 2137 2138 2139 2140 2141 2142
		pin1 = pin2;
		apic1 = apic2;
		no_pin1 = 1;
	} else if (pin2 == -1) {
		pin2 = pin1;
		apic2 = apic1;
	}

L
Linus Torvalds 已提交
2143
	if (pin1 != -1) {
2144
		/* Ok, does IRQ0 through the IOAPIC work? */
2145
		if (no_pin1) {
2146
			mp_alloc_timer_irq(apic1, pin1);
Y
Yinghai Lu 已提交
2147
		} else {
2148 2149
			/*
			 * for edge trigger, it's already unmasked,
Y
Yinghai Lu 已提交
2150 2151 2152 2153 2154 2155
			 * so only need to unmask if it is level-trigger
			 * do we really have level trigger timer?
			 */
			int idx;
			idx = find_irq_entry(apic1, pin1, mp_INT);
			if (idx != -1 && irq_trigger(idx))
2156
				unmask_ioapic_irq(irq_get_chip_data(0));
2157
		}
2158
		irq_domain_activate_irq(irq_data);
L
Linus Torvalds 已提交
2159
		if (timer_irq_works()) {
2160 2161
			if (disable_timer_pin_1 > 0)
				clear_IO_APIC_pin(0, pin1);
2162
			goto out;
L
Linus Torvalds 已提交
2163
		}
2164
		panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
Y
Yinghai Lu 已提交
2165
		local_irq_disable();
2166
		clear_IO_APIC_pin(apic1, pin1);
2167
		if (!no_pin1)
2168 2169
			apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
				    "8254 timer not connected to IO-APIC\n");
L
Linus Torvalds 已提交
2170

2171 2172 2173 2174
		apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
			    "(IRQ0) through the 8259A ...\n");
		apic_printk(APIC_QUIET, KERN_INFO
			    "..... (found apic %d pin %d) ...\n", apic2, pin2);
L
Linus Torvalds 已提交
2175 2176 2177
		/*
		 * legacy devices should be connected to IO APIC #0
		 */
2178 2179
		replace_pin_at_irq_node(data, node, apic1, pin1, apic2, pin2);
		irq_domain_activate_irq(irq_data);
2180
		legacy_pic->unmask(0);
L
Linus Torvalds 已提交
2181
		if (timer_irq_works()) {
2182
			apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2183
			goto out;
L
Linus Torvalds 已提交
2184 2185 2186 2187
		}
		/*
		 * Cleanup, just in case ...
		 */
Y
Yinghai Lu 已提交
2188
		local_irq_disable();
2189
		legacy_pic->mask(0);
2190
		clear_IO_APIC_pin(apic2, pin2);
2191
		apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
L
Linus Torvalds 已提交
2192 2193
	}

2194 2195
	apic_printk(APIC_QUIET, KERN_INFO
		    "...trying to set up timer as Virtual Wire IRQ...\n");
L
Linus Torvalds 已提交
2196

2197
	lapic_register_intr(0);
2198
	apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector);	/* Fixed mode */
2199
	legacy_pic->unmask(0);
L
Linus Torvalds 已提交
2200 2201

	if (timer_irq_works()) {
2202
		apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2203
		goto out;
L
Linus Torvalds 已提交
2204
	}
Y
Yinghai Lu 已提交
2205
	local_irq_disable();
2206
	legacy_pic->mask(0);
2207
	apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2208
	apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
L
Linus Torvalds 已提交
2209

2210 2211
	apic_printk(APIC_QUIET, KERN_INFO
		    "...trying to set up timer as ExtINT IRQ...\n");
L
Linus Torvalds 已提交
2212

2213 2214
	legacy_pic->init(0);
	legacy_pic->make_irq(0);
2215
	apic_write(APIC_LVT0, APIC_DM_EXTINT);
L
Linus Torvalds 已提交
2216 2217 2218 2219

	unlock_ExtINT_logic();

	if (timer_irq_works()) {
2220
		apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2221
		goto out;
L
Linus Torvalds 已提交
2222
	}
Y
Yinghai Lu 已提交
2223
	local_irq_disable();
2224
	apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2225
	if (apic_is_x2apic_enabled())
2226 2227 2228
		apic_printk(APIC_QUIET, KERN_INFO
			    "Perhaps problem with the pre-enabled x2apic mode\n"
			    "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
L
Linus Torvalds 已提交
2229
	panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2230
		"report.  Then try booting with the 'noapic' option.\n");
2231 2232
out:
	local_irq_restore(flags);
L
Linus Torvalds 已提交
2233 2234 2235
}

/*
2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250
 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
 * to devices.  However there may be an I/O APIC pin available for
 * this interrupt regardless.  The pin may be left unconnected, but
 * typically it will be reused as an ExtINT cascade interrupt for
 * the master 8259A.  In the MPS case such a pin will normally be
 * reported as an ExtINT interrupt in the MP table.  With ACPI
 * there is no provision for ExtINT interrupts, and in the absence
 * of an override it would be treated as an ordinary ISA I/O APIC
 * interrupt, that is edge-triggered and unmasked by default.  We
 * used to do this, but it caused problems on some systems because
 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
 * the same ExtINT cascade interrupt to drive the local APIC of the
 * bootstrap processor.  Therefore we refrain from routing IRQ2 to
 * the I/O APIC in all cases now.  No actual device should request
 * it anyway.  --macro
L
Linus Torvalds 已提交
2251
 */
2252
#define PIC_IRQS	(1UL << PIC_CASCADE_IR)
L
Linus Torvalds 已提交
2253

2254 2255
static int mp_irqdomain_create(int ioapic)
{
2256 2257
	struct irq_alloc_info info;
	struct irq_domain *parent;
2258 2259 2260 2261 2262 2263 2264 2265
	int hwirqs = mp_ioapic_pin_count(ioapic);
	struct ioapic *ip = &ioapics[ioapic];
	struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
	struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);

	if (cfg->type == IOAPIC_DOMAIN_INVALID)
		return 0;

2266 2267 2268 2269 2270 2271 2272
	init_irq_alloc_info(&info, NULL);
	info.type = X86_IRQ_ALLOC_TYPE_IOAPIC;
	info.ioapic_id = mpc_ioapic_id(ioapic);
	parent = irq_remapping_get_ir_irq_domain(&info);
	if (!parent)
		parent = x86_vector_domain;

2273 2274
	ip->irqdomain = irq_domain_add_linear(cfg->dev, hwirqs, cfg->ops,
					      (void *)(long)ioapic);
2275
	if (!ip->irqdomain)
2276
		return -ENOMEM;
2277 2278

	ip->irqdomain->parent = parent;
2279 2280 2281 2282 2283 2284 2285 2286 2287

	if (cfg->type == IOAPIC_DOMAIN_LEGACY ||
	    cfg->type == IOAPIC_DOMAIN_STRICT)
		ioapic_dynirq_base = max(ioapic_dynirq_base,
					 gsi_cfg->gsi_end + 1);

	return 0;
}

2288 2289 2290 2291 2292 2293 2294 2295
static void ioapic_destroy_irqdomain(int idx)
{
	if (ioapics[idx].irqdomain) {
		irq_domain_remove(ioapics[idx].irqdomain);
		ioapics[idx].irqdomain = NULL;
	}
}

L
Linus Torvalds 已提交
2296 2297
void __init setup_IO_APIC(void)
{
2298
	int ioapic;
2299

2300 2301 2302
	if (skip_ioapic_setup || !nr_ioapics)
		return;

2303
	io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL;
L
Linus Torvalds 已提交
2304

2305
	apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2306 2307 2308
	for_each_ioapic(ioapic)
		BUG_ON(mp_irqdomain_create(ioapic));

T
Thomas Gleixner 已提交
2309
	/*
2310 2311
         * Set up IO-APIC IRQ routing.
         */
2312 2313
	x86_init.mpparse.setup_ioapic_ids();

L
Linus Torvalds 已提交
2314 2315 2316
	sync_Arb_IDs();
	setup_IO_APIC_irqs();
	init_IO_APIC_traps();
2317
	if (nr_legacy_irqs())
2318
		check_timer();
2319 2320

	ioapic_initialized = 1;
L
Linus Torvalds 已提交
2321 2322 2323
}

/*
L
Lucas De Marchi 已提交
2324
 *      Called after all the initialization is done. If we didn't find any
2325
 *      APIC bugs then we can allow the modify fast path
L
Linus Torvalds 已提交
2326
 */
2327

L
Linus Torvalds 已提交
2328 2329
static int __init io_apic_bug_finalize(void)
{
T
Thomas Gleixner 已提交
2330 2331 2332
	if (sis_apic_bug == -1)
		sis_apic_bug = 0;
	return 0;
L
Linus Torvalds 已提交
2333 2334 2335 2336
}

late_initcall(io_apic_bug_finalize);

2337
static void resume_ioapic_id(int ioapic_idx)
L
Linus Torvalds 已提交
2338 2339 2340
{
	unsigned long flags;
	union IO_APIC_reg_00 reg_00;
2341

2342
	raw_spin_lock_irqsave(&ioapic_lock, flags);
2343 2344 2345 2346
	reg_00.raw = io_apic_read(ioapic_idx, 0);
	if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
		reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
		io_apic_write(ioapic_idx, 0, reg_00.raw);
L
Linus Torvalds 已提交
2347
	}
2348
	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2349
}
L
Linus Torvalds 已提交
2350

2351 2352
static void ioapic_resume(void)
{
2353
	int ioapic_idx;
2354

2355
	for_each_ioapic_reverse(ioapic_idx)
2356
		resume_ioapic_id(ioapic_idx);
2357 2358

	restore_ioapic_entries();
L
Linus Torvalds 已提交
2359 2360
}

2361
static struct syscore_ops ioapic_syscore_ops = {
2362
	.suspend = save_ioapic_entries,
L
Linus Torvalds 已提交
2363 2364 2365
	.resume = ioapic_resume,
};

2366
static int __init ioapic_init_ops(void)
L
Linus Torvalds 已提交
2367
{
2368 2369
	register_syscore_ops(&ioapic_syscore_ops);

L
Linus Torvalds 已提交
2370 2371 2372
	return 0;
}

2373
device_initcall(ioapic_init_ops);
L
Linus Torvalds 已提交
2374

2375
static int io_apic_get_redir_entries(int ioapic)
2376 2377 2378 2379
{
	union IO_APIC_reg_01	reg_01;
	unsigned long flags;

2380
	raw_spin_lock_irqsave(&ioapic_lock, flags);
2381
	reg_01.raw = io_apic_read(ioapic, 1);
2382
	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2383

2384 2385 2386 2387 2388
	/* The register returns the maximum index redir index
	 * supported, which is one less than the total number of redir
	 * entries.
	 */
	return reg_01.bits.entries + 1;
2389 2390
}

2391 2392
unsigned int arch_dynirq_lower_bound(unsigned int from)
{
2393 2394 2395 2396 2397
	/*
	 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
	 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
	 */
	return ioapic_initialized ? ioapic_dynirq_base : gsi_top;
2398 2399
}

2400
#ifdef CONFIG_X86_32
2401
static int io_apic_get_unique_id(int ioapic, int apic_id)
L
Linus Torvalds 已提交
2402 2403 2404 2405 2406 2407 2408 2409
{
	union IO_APIC_reg_00 reg_00;
	static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
	physid_mask_t tmp;
	unsigned long flags;
	int i = 0;

	/*
2410 2411
	 * The P4 platform supports up to 256 APIC IDs on two separate APIC
	 * buses (one for LAPICs, one for IOAPICs), where predecessors only
L
Linus Torvalds 已提交
2412
	 * supports up to 16 on one shared APIC bus.
2413
	 *
L
Linus Torvalds 已提交
2414 2415 2416 2417 2418
	 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
	 *      advantage of new APIC bus architecture.
	 */

	if (physids_empty(apic_id_map))
2419
		apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
L
Linus Torvalds 已提交
2420

2421
	raw_spin_lock_irqsave(&ioapic_lock, flags);
L
Linus Torvalds 已提交
2422
	reg_00.raw = io_apic_read(ioapic, 0);
2423
	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
L
Linus Torvalds 已提交
2424 2425 2426 2427 2428 2429 2430 2431

	if (apic_id >= get_physical_broadcast()) {
		printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
			"%d\n", ioapic, apic_id, reg_00.bits.ID);
		apic_id = reg_00.bits.ID;
	}

	/*
2432
	 * Every APIC in a system must have a unique ID or we get lots of nice
L
Linus Torvalds 已提交
2433 2434
	 * 'stuck on smp_invalidate_needed IPI wait' messages.
	 */
2435
	if (apic->check_apicid_used(&apic_id_map, apic_id)) {
L
Linus Torvalds 已提交
2436 2437

		for (i = 0; i < get_physical_broadcast(); i++) {
2438
			if (!apic->check_apicid_used(&apic_id_map, i))
L
Linus Torvalds 已提交
2439 2440 2441 2442 2443 2444 2445 2446 2447 2448
				break;
		}

		if (i == get_physical_broadcast())
			panic("Max apic_id exceeded!\n");

		printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
			"trying %d\n", ioapic, apic_id, i);

		apic_id = i;
2449
	}
L
Linus Torvalds 已提交
2450

2451
	apic->apicid_to_cpu_present(apic_id, &tmp);
L
Linus Torvalds 已提交
2452 2453 2454 2455 2456
	physids_or(apic_id_map, apic_id_map, tmp);

	if (reg_00.bits.ID != apic_id) {
		reg_00.bits.ID = apic_id;

2457
		raw_spin_lock_irqsave(&ioapic_lock, flags);
L
Linus Torvalds 已提交
2458 2459
		io_apic_write(ioapic, 0, reg_00.raw);
		reg_00.raw = io_apic_read(ioapic, 0);
2460
		raw_spin_unlock_irqrestore(&ioapic_lock, flags);
L
Linus Torvalds 已提交
2461 2462

		/* Sanity check */
2463
		if (reg_00.bits.ID != apic_id) {
2464 2465
			pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
			       ioapic);
2466 2467
			return -1;
		}
L
Linus Torvalds 已提交
2468 2469 2470 2471 2472 2473 2474
	}

	apic_printk(APIC_VERBOSE, KERN_INFO
			"IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);

	return apic_id;
}
2475

2476
static u8 io_apic_unique_id(int idx, u8 id)
2477 2478 2479
{
	if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
	    !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2480
		return io_apic_get_unique_id(idx, id);
2481 2482 2483 2484
	else
		return id;
}
#else
2485
static u8 io_apic_unique_id(int idx, u8 id)
2486
{
2487
	union IO_APIC_reg_00 reg_00;
2488
	DECLARE_BITMAP(used, 256);
2489 2490 2491
	unsigned long flags;
	u8 new_id;
	int i;
2492 2493

	bitmap_zero(used, 256);
2494
	for_each_ioapic(i)
2495
		__set_bit(mpc_ioapic_id(i), used);
2496 2497

	/* Hand out the requested id if available */
2498 2499
	if (!test_bit(id, used))
		return id;
2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528

	/*
	 * Read the current id from the ioapic and keep it if
	 * available.
	 */
	raw_spin_lock_irqsave(&ioapic_lock, flags);
	reg_00.raw = io_apic_read(idx, 0);
	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
	new_id = reg_00.bits.ID;
	if (!test_bit(new_id, used)) {
		apic_printk(APIC_VERBOSE, KERN_INFO
			"IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
			 idx, new_id, id);
		return new_id;
	}

	/*
	 * Get the next free id and write it to the ioapic.
	 */
	new_id = find_first_zero_bit(used, 256);
	reg_00.bits.ID = new_id;
	raw_spin_lock_irqsave(&ioapic_lock, flags);
	io_apic_write(idx, 0, reg_00.raw);
	reg_00.raw = io_apic_read(idx, 0);
	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
	/* Sanity check */
	BUG_ON(reg_00.bits.ID != new_id);

	return new_id;
2529
}
2530
#endif
L
Linus Torvalds 已提交
2531

2532
static int io_apic_get_version(int ioapic)
L
Linus Torvalds 已提交
2533 2534 2535 2536
{
	union IO_APIC_reg_01	reg_01;
	unsigned long flags;

2537
	raw_spin_lock_irqsave(&ioapic_lock, flags);
L
Linus Torvalds 已提交
2538
	reg_01.raw = io_apic_read(ioapic, 1);
2539
	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
L
Linus Torvalds 已提交
2540 2541 2542 2543

	return reg_01.bits.version;
}

2544
int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
2545
{
2546
	int ioapic, pin, idx;
2547 2548 2549 2550

	if (skip_ioapic_setup)
		return -1;

2551 2552
	ioapic = mp_find_ioapic(gsi);
	if (ioapic < 0)
2553 2554
		return -1;

2555 2556 2557 2558 2559 2560
	pin = mp_find_ioapic_pin(ioapic, gsi);
	if (pin < 0)
		return -1;

	idx = find_irq_entry(ioapic, pin, mp_INT);
	if (idx < 0)
2561 2562
		return -1;

2563 2564
	*trigger = irq_trigger(idx);
	*polarity = irq_polarity(idx);
2565 2566 2567
	return 0;
}

2568 2569 2570
/*
 * This function currently is only a helper for the i386 smp boot process where
 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2571
 * so mask in all cases should simply be apic->target_cpus()
2572 2573 2574 2575
 */
#ifdef CONFIG_SMP
void __init setup_ioapic_dest(void)
{
E
Eric W. Biederman 已提交
2576
	int pin, ioapic, irq, irq_entry;
2577
	const struct cpumask *mask;
2578
	struct irq_data *idata;
2579 2580 2581 2582

	if (skip_ioapic_setup == 1)
		return;

2583
	for_each_ioapic_pin(ioapic, pin) {
2584 2585 2586
		irq_entry = find_irq_entry(ioapic, pin, mp_INT);
		if (irq_entry == -1)
			continue;
2587

2588 2589
		irq = pin_2_irq(irq_entry, ioapic, pin, 0);
		if (irq < 0 || !mp_init_irq_at_boot(ioapic, irq))
E
Eric W. Biederman 已提交
2590 2591
			continue;

2592
		idata = irq_get_irq_data(irq);
2593

2594 2595 2596
		/*
		 * Honour affinities which have been set in early boot
		 */
2597 2598
		if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
			mask = idata->affinity;
2599 2600
		else
			mask = apic->target_cpus();
2601

2602
		irq_set_affinity(irq, mask);
2603
	}
2604

2605 2606 2607
}
#endif

2608 2609 2610 2611
#define IOAPIC_RESOURCE_NAME_SIZE 11

static struct resource *ioapic_resources;

2612
static struct resource * __init ioapic_setup_resources(void)
2613 2614 2615 2616
{
	unsigned long n;
	struct resource *res;
	char *mem;
2617
	int i, num = 0;
2618

2619 2620 2621
	for_each_ioapic(i)
		num++;
	if (num == 0)
2622 2623 2624
		return NULL;

	n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2625
	n *= num;
2626 2627 2628 2629

	mem = alloc_bootmem(n);
	res = (void *)mem;

2630
	mem += sizeof(struct resource) * num;
2631

2632 2633 2634 2635
	num = 0;
	for_each_ioapic(i) {
		res[num].name = mem;
		res[num].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2636
		snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
2637
		mem += IOAPIC_RESOURCE_NAME_SIZE;
2638
		num++;
2639
		ioapics[i].iomem_res = res;
2640 2641 2642 2643 2644 2645 2646
	}

	ioapic_resources = res;

	return res;
}

2647
void __init io_apic_init_mappings(void)
2648 2649
{
	unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2650
	struct resource *ioapic_res;
T
Thomas Gleixner 已提交
2651
	int i;
2652

2653 2654
	ioapic_res = ioapic_setup_resources();
	for_each_ioapic(i) {
2655
		if (smp_found_config) {
2656
			ioapic_phys = mpc_ioapic_addr(i);
2657
#ifdef CONFIG_X86_32
T
Thomas Gleixner 已提交
2658 2659 2660 2661 2662 2663 2664 2665 2666
			if (!ioapic_phys) {
				printk(KERN_ERR
				       "WARNING: bogus zero IO-APIC "
				       "address found in MPTABLE, "
				       "disabling IO/APIC support!\n");
				smp_found_config = 0;
				skip_ioapic_setup = 1;
				goto fake_ioapic_page;
			}
2667
#endif
2668
		} else {
2669
#ifdef CONFIG_X86_32
2670
fake_ioapic_page:
2671
#endif
2672
			ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
2673 2674 2675
			ioapic_phys = __pa(ioapic_phys);
		}
		set_fixmap_nocache(idx, ioapic_phys);
2676 2677 2678
		apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
			__fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
			ioapic_phys);
2679
		idx++;
2680

2681
		ioapic_res->start = ioapic_phys;
2682
		ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
2683
		ioapic_res++;
2684 2685 2686
	}
}

2687
void __init ioapic_insert_resources(void)
2688 2689 2690 2691 2692
{
	int i;
	struct resource *r = ioapic_resources;

	if (!r) {
2693
		if (nr_ioapics > 0)
2694 2695
			printk(KERN_ERR
				"IO APIC resources couldn't be allocated.\n");
2696
		return;
2697 2698
	}

2699
	for_each_ioapic(i) {
2700 2701 2702 2703
		insert_resource(&iomem_resource, r);
		r++;
	}
}
2704

2705
int mp_find_ioapic(u32 gsi)
2706
{
2707
	int i;
2708

2709 2710 2711
	if (nr_ioapics == 0)
		return -1;

2712
	/* Find the IOAPIC that manages this GSI. */
2713
	for_each_ioapic(i) {
2714
		struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
2715
		if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end)
2716 2717
			return i;
	}
2718

2719 2720 2721 2722
	printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
	return -1;
}

2723
int mp_find_ioapic_pin(int ioapic, u32 gsi)
2724
{
2725 2726
	struct mp_ioapic_gsi *gsi_cfg;

2727
	if (WARN_ON(ioapic < 0))
2728
		return -1;
2729 2730 2731

	gsi_cfg = mp_ioapic_gsi_routing(ioapic);
	if (WARN_ON(gsi > gsi_cfg->gsi_end))
2732 2733
		return -1;

2734
	return gsi - gsi_cfg->gsi_base;
2735 2736
}

2737
static int bad_ioapic_register(int idx)
2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755
{
	union IO_APIC_reg_00 reg_00;
	union IO_APIC_reg_01 reg_01;
	union IO_APIC_reg_02 reg_02;

	reg_00.raw = io_apic_read(idx, 0);
	reg_01.raw = io_apic_read(idx, 1);
	reg_02.raw = io_apic_read(idx, 2);

	if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
		pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
			mpc_ioapic_addr(idx));
		return 1;
	}

	return 0;
}

2756 2757
static int find_free_ioapic_entry(void)
{
2758 2759 2760 2761 2762 2763 2764
	int idx;

	for (idx = 0; idx < MAX_IO_APICS; idx++)
		if (ioapics[idx].nr_registers == 0)
			return idx;

	return MAX_IO_APICS;
2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775
}

/**
 * mp_register_ioapic - Register an IOAPIC device
 * @id:		hardware IOAPIC ID
 * @address:	physical address of IOAPIC register area
 * @gsi_base:	base of GSI associated with the IOAPIC
 * @cfg:	configuration information for the IOAPIC
 */
int mp_register_ioapic(int id, u32 address, u32 gsi_base,
		       struct ioapic_domain_cfg *cfg)
2776
{
2777
	bool hotplug = !!ioapic_initialized;
2778
	struct mp_ioapic_gsi *gsi_cfg;
2779 2780
	int idx, ioapic, entries;
	u32 gsi_end;
2781

2782 2783 2784 2785 2786 2787 2788 2789 2790 2791
	if (!address) {
		pr_warn("Bogus (zero) I/O APIC address found, skipping!\n");
		return -EINVAL;
	}
	for_each_ioapic(ioapic)
		if (ioapics[ioapic].mp_config.apicaddr == address) {
			pr_warn("address 0x%x conflicts with IOAPIC%d\n",
				address, ioapic);
			return -EEXIST;
		}
2792

2793 2794 2795 2796 2797 2798
	idx = find_free_ioapic_entry();
	if (idx >= MAX_IO_APICS) {
		pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
			MAX_IO_APICS, idx);
		return -ENOSPC;
	}
2799

2800 2801 2802
	ioapics[idx].mp_config.type = MP_IOAPIC;
	ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
	ioapics[idx].mp_config.apicaddr = address;
2803 2804

	set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
2805 2806
	if (bad_ioapic_register(idx)) {
		clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2807
		return -ENODEV;
2808 2809
	}

2810
	ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id);
2811
	ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
2812 2813 2814 2815 2816

	/*
	 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
	 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
	 */
2817
	entries = io_apic_get_redir_entries(idx);
2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831
	gsi_end = gsi_base + entries - 1;
	for_each_ioapic(ioapic) {
		gsi_cfg = mp_ioapic_gsi_routing(ioapic);
		if ((gsi_base >= gsi_cfg->gsi_base &&
		     gsi_base <= gsi_cfg->gsi_end) ||
		    (gsi_end >= gsi_cfg->gsi_base &&
		     gsi_end <= gsi_cfg->gsi_end)) {
			pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n",
				gsi_base, gsi_end,
				gsi_cfg->gsi_base, gsi_cfg->gsi_end);
			clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
			return -ENOSPC;
		}
	}
2832 2833
	gsi_cfg = mp_ioapic_gsi_routing(idx);
	gsi_cfg->gsi_base = gsi_base;
2834
	gsi_cfg->gsi_end = gsi_end;
2835

2836 2837
	ioapics[idx].irqdomain = NULL;
	ioapics[idx].irqdomain_cfg = *cfg;
2838

2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851
	/*
	 * If mp_register_ioapic() is called during early boot stage when
	 * walking ACPI/SFI/DT tables, it's too early to create irqdomain,
	 * we are still using bootmem allocator. So delay it to setup_IO_APIC().
	 */
	if (hotplug) {
		if (mp_irqdomain_create(idx)) {
			clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
			return -ENOMEM;
		}
		alloc_ioapic_saved_registers(idx);
	}

2852 2853
	if (gsi_cfg->gsi_end >= gsi_top)
		gsi_top = gsi_cfg->gsi_end + 1;
2854 2855 2856 2857 2858
	if (nr_ioapics <= idx)
		nr_ioapics = idx + 1;

	/* Set nr_registers to mark entry present */
	ioapics[idx].nr_registers = entries;
2859

2860 2861 2862 2863
	pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
		idx, mpc_ioapic_id(idx),
		mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
		gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2864

2865
	return 0;
2866
}
2867

2868 2869 2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883
int mp_unregister_ioapic(u32 gsi_base)
{
	int ioapic, pin;
	int found = 0;

	for_each_ioapic(ioapic)
		if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) {
			found = 1;
			break;
		}
	if (!found) {
		pr_warn("can't find IOAPIC for GSI %d\n", gsi_base);
		return -ENODEV;
	}

	for_each_pin(ioapic, pin) {
2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894
		u32 gsi = mp_pin_to_gsi(ioapic, pin);
		int irq = mp_map_gsi_to_irq(gsi, 0, NULL);
		struct mp_chip_data *data;

		if (irq >= 0) {
			data = irq_get_chip_data(irq);
			if (data && data->count) {
				pr_warn("pin%d on IOAPIC%d is still in use.\n",
					pin, ioapic);
				return -EBUSY;
			}
2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909
		}
	}

	/* Mark entry not present */
	ioapics[ioapic].nr_registers  = 0;
	ioapic_destroy_irqdomain(ioapic);
	free_ioapic_saved_registers(ioapic);
	if (ioapics[ioapic].iomem_res)
		release_resource(ioapics[ioapic].iomem_res);
	clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic);
	memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic]));

	return 0;
}

2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920
int mp_ioapic_registered(u32 gsi_base)
{
	int ioapic;

	for_each_ioapic(ioapic)
		if (ioapics[ioapic].gsi_config.gsi_base == gsi_base)
			return 1;

	return 0;
}

2921
static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data,
2922
				  struct irq_alloc_info *info)
2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984
{
	if (info && info->ioapic_valid) {
		data->trigger = info->ioapic_trigger;
		data->polarity = info->ioapic_polarity;
	} else if (acpi_get_override_irq(gsi, &data->trigger,
					 &data->polarity) < 0) {
		/* PCI interrupts are always polarity one level triggered. */
		data->trigger = 1;
		data->polarity = 1;
	}
}

static void mp_setup_entry(struct irq_cfg *cfg, struct mp_chip_data *data,
			   struct IO_APIC_route_entry *entry)
{
	memset(entry, 0, sizeof(*entry));
	entry->delivery_mode = apic->irq_delivery_mode;
	entry->dest_mode     = apic->irq_dest_mode;
	entry->dest	     = cfg->dest_apicid;
	entry->vector	     = cfg->vector;
	entry->mask	     = 0;	/* enable IRQ */
	entry->trigger	     = data->trigger;
	entry->polarity	     = data->polarity;
	/*
	 * Mask level triggered irqs.
	 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
	 */
	if (data->trigger)
		entry->mask = 1;
}

int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
		       unsigned int nr_irqs, void *arg)
{
	int ret, ioapic, pin;
	struct irq_cfg *cfg;
	struct irq_data *irq_data;
	struct mp_chip_data *data;
	struct irq_alloc_info *info = arg;

	if (!info || nr_irqs > 1)
		return -EINVAL;
	irq_data = irq_domain_get_irq_data(domain, virq);
	if (!irq_data)
		return -EINVAL;

	ioapic = mp_irqdomain_ioapic_idx(domain);
	pin = info->ioapic_pin;
	if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0)
		return -EEXIST;

	data = kzalloc(sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	info->ioapic_entry = &data->entry;
	ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info);
	if (ret < 0) {
		kfree(data);
		return ret;
	}

2985
	INIT_LIST_HEAD(&data->irq_2_pin);
2986
	irq_data->hwirq = info->ioapic_pin;
2987 2988
	irq_data->chip = (domain->parent == x86_vector_domain) ?
			  &ioapic_chip : &ioapic_ir_chip;
2989 2990 2991 2992
	irq_data->chip_data = data;
	mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info);

	cfg = irqd_cfg(irq_data);
2993
	add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin);
2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011
	if (info->ioapic_entry)
		mp_setup_entry(cfg, data, info->ioapic_entry);
	mp_register_handler(virq, data->trigger);
	if (virq < nr_legacy_irqs())
		legacy_pic->mask(virq);

	apic_printk(APIC_VERBOSE, KERN_DEBUG
		    "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i Dest:%d)\n",
		    ioapic, mpc_ioapic_id(ioapic), pin, cfg->vector,
		    virq, data->trigger, data->polarity, cfg->dest_apicid);

	return 0;
}

void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
		       unsigned int nr_irqs)
{
	struct irq_data *irq_data;
3012
	struct mp_chip_data *data;
3013 3014 3015 3016

	BUG_ON(nr_irqs != 1);
	irq_data = irq_domain_get_irq_data(domain, virq);
	if (irq_data && irq_data->chip_data) {
3017 3018
		data = irq_data->chip_data;
		__remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain),
3019
				      (int)irq_data->hwirq);
3020
		WARN_ON(!list_empty(&data->irq_2_pin));
3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033
		kfree(irq_data->chip_data);
	}
	irq_domain_free_irqs_top(domain, virq, nr_irqs);
}

void mp_irqdomain_activate(struct irq_domain *domain,
			   struct irq_data *irq_data)
{
	unsigned long flags;
	struct irq_pin_list *entry;
	struct mp_chip_data *data = irq_data->chip_data;

	raw_spin_lock_irqsave(&ioapic_lock, flags);
3034
	for_each_irq_pin(entry, data->irq_2_pin)
3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050
		__ioapic_write_entry(entry->apic, entry->pin, data->entry);
	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
}

void mp_irqdomain_deactivate(struct irq_domain *domain,
			     struct irq_data *irq_data)
{
	/* It won't be called for IRQ with multiple IOAPIC pins associated */
	ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain),
			  (int)irq_data->hwirq);
}

int mp_irqdomain_ioapic_idx(struct irq_domain *domain)
{
	return (int)(long)domain->host_data;
}