apic.c 67.6 KB
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/*
 *	Local APIC handling, local APIC timers
 *
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 *	(c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
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 *
 *	Fixes
 *	Maciej W. Rozycki	:	Bits for genuine 82489DX APICs;
 *					thanks to Eric Gilmore
 *					and Rolf G. Tews
 *					for testing these extensively.
 *	Maciej W. Rozycki	:	Various updates and fixes.
 *	Mikael Pettersson	:	Power Management for UP-APIC.
 *	Pavel Machek and
 *	Mikael Pettersson	:	PM converted to driver model.
 */

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#include <linux/perf_event.h>
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#include <linux/kernel_stat.h>
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#include <linux/mc146818rtc.h>
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#include <linux/acpi_pmtmr.h>
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#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/bootmem.h>
#include <linux/ftrace.h>
#include <linux/ioport.h>
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#include <linux/export.h>
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#include <linux/syscore_ops.h>
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#include <linux/delay.h>
#include <linux/timex.h>
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#include <linux/i8253.h>
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#include <linux/dmar.h>
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#include <linux/init.h>
#include <linux/cpu.h>
#include <linux/dmi.h>
#include <linux/smp.h>
#include <linux/mm.h>
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#include <asm/trace/irq_vectors.h>
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#include <asm/irq_remapping.h>
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#include <asm/perf_event.h>
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#include <asm/x86_init.h>
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#include <asm/pgalloc.h>
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#include <linux/atomic.h>
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#include <asm/mpspec.h>
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#include <asm/i8259.h>
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#include <asm/proto.h>
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#include <asm/apic.h>
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#include <asm/io_apic.h>
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#include <asm/desc.h>
#include <asm/hpet.h>
#include <asm/mtrr.h>
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#include <asm/time.h>
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#include <asm/smp.h>
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#include <asm/mce.h>
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#include <asm/tsc.h>
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#include <asm/hypervisor.h>
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#include <asm/cpu_device_id.h>
#include <asm/intel-family.h>
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unsigned int num_processors;
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unsigned disabled_cpus;
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/* Processor that is doing the boot up */
unsigned int boot_cpu_physical_apicid = -1U;
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EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
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u8 boot_cpu_apic_version;

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/*
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 * The highest APIC ID seen during enumeration.
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 */
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static unsigned int max_physical_apicid;
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/*
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 * Bitmask of physically existing CPUs:
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 */
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physid_mask_t phys_cpu_present_map;

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/*
 * Processor to be disabled specified by kernel parameter
 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
 * avoid undefined behaviour caused by sending INIT from AP to BSP.
 */
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static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID;
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/*
 * This variable controls which CPUs receive external NMIs.  By default,
 * external NMIs are delivered only to the BSP.
 */
static int apic_extnmi = APIC_EXTNMI_BSP;

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/*
 * Map cpu index to physical APIC ID
 */
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DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
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DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX);
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EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
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EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid);
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#ifdef CONFIG_X86_32
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/*
 * On x86_32, the mapping between cpu and logical apicid may vary
 * depending on apic in use.  The following early percpu variable is
 * used for the mapping.  This is where the behaviors of x86_64 and 32
 * actually diverge.  Let's keep it ugly for now.
 */
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DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
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/* Local APIC was disabled by the BIOS and enabled by the kernel */
static int enabled_via_apicbase;

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/*
 * Handle interrupt mode configuration register (IMCR).
 * This register controls whether the interrupt signals
 * that reach the BSP come from the master PIC or from the
 * local APIC. Before entering Symmetric I/O Mode, either
 * the BIOS or the operating system must switch out of
 * PIC Mode by changing the IMCR.
 */
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static inline void imcr_pic_to_apic(void)
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{
	/* select IMCR register */
	outb(0x70, 0x22);
	/* NMI and 8259 INTR go through APIC */
	outb(0x01, 0x23);
}

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static inline void imcr_apic_to_pic(void)
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{
	/* select IMCR register */
	outb(0x70, 0x22);
	/* NMI and 8259 INTR go directly to BSP */
	outb(0x00, 0x23);
}
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#endif

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/*
 * Knob to control our willingness to enable the local APIC.
 *
 * +1=force-enable
 */
static int force_enable_local_apic __initdata;
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/*
 * APIC command line parameters
 */
static int __init parse_lapic(char *arg)
{
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	if (IS_ENABLED(CONFIG_X86_32) && !arg)
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		force_enable_local_apic = 1;
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	else if (arg && !strncmp(arg, "notscdeadline", 13))
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		setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
	return 0;
}
early_param("lapic", parse_lapic);

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#ifdef CONFIG_X86_64
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static int apic_calibrate_pmtmr __initdata;
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static __init int setup_apicpmtimer(char *s)
{
	apic_calibrate_pmtmr = 1;
	notsc_setup(NULL);
	return 0;
}
__setup("apicpmtimer", setup_apicpmtimer);
#endif

unsigned long mp_lapic_addr;
int disable_apic;
/* Disable local APIC timer from the kernel commandline or via dmi quirk */
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static int disable_apic_timer __initdata;
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/* Local APIC timer works in C2 */
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int local_apic_timer_c2_ok;
EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);

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/*
 * Debug level, exported for io_apic.c
 */
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unsigned int apic_verbosity;
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int pic_mode;

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/* Have we found an MP table */
int smp_found_config;

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static struct resource lapic_resource = {
	.name = "Local APIC",
	.flags = IORESOURCE_MEM | IORESOURCE_BUSY,
};

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unsigned int lapic_timer_frequency = 0;
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static void apic_pm_activate(void);
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static unsigned long apic_phys;

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/*
 * Get the LAPIC version
 */
static inline int lapic_get_version(void)
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{
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	return GET_APIC_VERSION(apic_read(APIC_LVR));
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}

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/*
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 * Check, if the APIC is integrated or a separate chip
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 */
static inline int lapic_is_integrated(void)
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{
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#ifdef CONFIG_X86_64
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	return 1;
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#else
	return APIC_INTEGRATED(lapic_get_version());
#endif
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}

/*
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 * Check, whether this is a modern or a first generation APIC
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 */
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static int modern_apic(void)
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{
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	/* AMD systems use old APIC versions, so check the CPU */
	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
	    boot_cpu_data.x86 >= 0xf)
		return 1;
	return lapic_get_version() >= 0x14;
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}

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/*
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 * right after this call apic become NOOP driven
 * so apic->write/read doesn't do anything
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 */
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static void __init apic_disable(void)
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{
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	pr_info("APIC: switched to apic NOOP\n");
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	apic = &apic_noop;
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}

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void native_apic_wait_icr_idle(void)
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{
	while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
		cpu_relax();
}

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u32 native_safe_apic_wait_icr_idle(void)
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{
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	u32 send_status;
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	int timeout;

	timeout = 0;
	do {
		send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
		if (!send_status)
			break;
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		inc_irq_stat(icr_read_retry_count);
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		udelay(100);
	} while (timeout++ < 1000);

	return send_status;
}

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void native_apic_icr_write(u32 low, u32 id)
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{
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	unsigned long flags;

	local_irq_save(flags);
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	apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
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	apic_write(APIC_ICR, low);
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	local_irq_restore(flags);
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}

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u64 native_apic_icr_read(void)
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{
	u32 icr1, icr2;

	icr2 = apic_read(APIC_ICR2);
	icr1 = apic_read(APIC_ICR);

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	return icr1 | ((u64)icr2 << 32);
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}

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#ifdef CONFIG_X86_32
/**
 * get_physical_broadcast - Get number of physical broadcast IDs
 */
int get_physical_broadcast(void)
{
	return modern_apic() ? 0xff : 0xf;
}
#endif

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/**
 * lapic_get_maxlvt - get the maximum number of local vector table entries
 */
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int lapic_get_maxlvt(void)
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{
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	unsigned int v;
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	v = apic_read(APIC_LVR);
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	/*
	 * - we always have APIC integrated on 64bit mode
	 * - 82489DXs do not report # of LVT entries
	 */
	return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
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}

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/*
 * Local APIC timer
 */

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/* Clock divisor */
#define APIC_DIVISOR 16
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#define TSC_DIVISOR  8
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/*
 * This function sets up the local APIC timer, with a timeout of
 * 'clocks' APIC bus clock. During calibration we actually call
 * this function twice on the boot CPU, once with a bogus timeout
 * value, second time for real. The other (noncalibrating) CPUs
 * call this function only once, with the real, calibrated value.
 *
 * We do reads before writes even if unnecessary, to get around the
 * P5 APIC double write bug.
 */
static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
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{
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	unsigned int lvtt_value, tmp_value;
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	lvtt_value = LOCAL_TIMER_VECTOR;
	if (!oneshot)
		lvtt_value |= APIC_LVT_TIMER_PERIODIC;
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	else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
		lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;

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	if (!lapic_is_integrated())
		lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);

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	if (!irqen)
		lvtt_value |= APIC_LVT_MASKED;
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	apic_write(APIC_LVTT, lvtt_value);
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	if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
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		/*
		 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
		 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
		 * According to Intel, MFENCE can do the serialization here.
		 */
		asm volatile("mfence" : : : "memory");

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		printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
		return;
	}

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	/*
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	 * Divide PICLK by 16
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	 */
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	tmp_value = apic_read(APIC_TDCR);
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	apic_write(APIC_TDCR,
		(tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
		APIC_TDR_DIV_16);
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	if (!oneshot)
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		apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
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}

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/*
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 * Setup extended LVT, AMD specific
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 *
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 * Software should use the LVT offsets the BIOS provides.  The offsets
 * are determined by the subsystems using it like those for MCE
 * threshold or IBS.  On K8 only offset 0 (APIC500) and MCE interrupts
 * are supported. Beginning with family 10h at least 4 offsets are
 * available.
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 *
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 * Since the offsets must be consistent for all cores, we keep track
 * of the LVT offsets in software and reserve the offset for the same
 * vector also to be used on other cores. An offset is freed by
 * setting the entry to APIC_EILVT_MASKED.
 *
 * If the BIOS is right, there should be no conflicts. Otherwise a
 * "[Firmware Bug]: ..." error message is generated. However, if
 * software does not properly determines the offsets, it is not
 * necessarily a BIOS bug.
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 */
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static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];

static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
{
	return (old & APIC_EILVT_MASKED)
		|| (new == APIC_EILVT_MASKED)
		|| ((new & ~APIC_EILVT_MASKED) == old);
}

static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
{
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	unsigned int rsvd, vector;
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	if (offset >= APIC_EILVT_NR_MAX)
		return ~0;

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	rsvd = atomic_read(&eilvt_offsets[offset]);
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	do {
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		vector = rsvd & ~APIC_EILVT_MASKED;	/* 0: unassigned */
		if (vector && !eilvt_entry_is_changeable(vector, new))
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			/* may not change if vectors are different */
			return rsvd;
		rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
	} while (rsvd != new);

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	rsvd &= ~APIC_EILVT_MASKED;
	if (rsvd && rsvd != vector)
		pr_info("LVT offset %d assigned for vector 0x%02x\n",
			offset, rsvd);

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	return new;
}

/*
 * If mask=1, the LVT entry does not generate interrupts while mask=0
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 * enables the vector. See also the BKDGs. Must be called with
 * preemption disabled.
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 */

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int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
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{
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	unsigned long reg = APIC_EILVTn(offset);
	unsigned int new, old, reserved;

	new = (mask << 16) | (msg_type << 8) | vector;
	old = apic_read(reg);
	reserved = reserve_eilvt_offset(offset, new);

	if (reserved != new) {
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		pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
		       "vector 0x%x, but the register is already in use for "
		       "vector 0x%x on another cpu\n",
		       smp_processor_id(), reg, offset, new, reserved);
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		return -EINVAL;
	}

	if (!eilvt_entry_is_changeable(old, new)) {
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		pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
		       "vector 0x%x, but the register is already in use for "
		       "vector 0x%x on this cpu\n",
		       smp_processor_id(), reg, offset, new, old);
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		return -EBUSY;
	}

	apic_write(reg, new);
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	return 0;
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}
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EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
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/*
 * Program the next event, relative to now
 */
static int lapic_next_event(unsigned long delta,
			    struct clock_event_device *evt)
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{
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	apic_write(APIC_TMICT, delta);
	return 0;
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}

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static int lapic_next_deadline(unsigned long delta,
			       struct clock_event_device *evt)
{
	u64 tsc;

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	tsc = rdtsc();
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	wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
	return 0;
}

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static int lapic_timer_shutdown(struct clock_event_device *evt)
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{
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	unsigned int v;
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	/* Lapic used as dummy for broadcast ? */
	if (evt->features & CLOCK_EVT_FEAT_DUMMY)
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		return 0;
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	v = apic_read(APIC_LVTT);
	v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
	apic_write(APIC_LVTT, v);
	apic_write(APIC_TMICT, 0);
	return 0;
}
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static inline int
lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot)
{
	/* Lapic used as dummy for broadcast ? */
	if (evt->features & CLOCK_EVT_FEAT_DUMMY)
		return 0;
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	__setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1);
	return 0;
}

static int lapic_timer_set_periodic(struct clock_event_device *evt)
{
	return lapic_timer_set_periodic_oneshot(evt, false);
}

static int lapic_timer_set_oneshot(struct clock_event_device *evt)
{
	return lapic_timer_set_periodic_oneshot(evt, true);
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}

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/*
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 * Local APIC timer broadcast function
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 */
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static void lapic_timer_broadcast(const struct cpumask *mask)
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{
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#ifdef CONFIG_SMP
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	apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
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#endif
}
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/*
 * The local apic timer can be used for any function which is CPU local.
 */
static struct clock_event_device lapic_clockevent = {
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	.name				= "lapic",
	.features			= CLOCK_EVT_FEAT_PERIODIC |
					  CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP
					  | CLOCK_EVT_FEAT_DUMMY,
	.shift				= 32,
	.set_state_shutdown		= lapic_timer_shutdown,
	.set_state_periodic		= lapic_timer_set_periodic,
	.set_state_oneshot		= lapic_timer_set_oneshot,
	.set_state_oneshot_stopped	= lapic_timer_shutdown,
	.set_next_event			= lapic_next_event,
	.broadcast			= lapic_timer_broadcast,
	.rating				= 100,
	.irq				= -1,
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};
static DEFINE_PER_CPU(struct clock_event_device, lapic_events);

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#define DEADLINE_MODEL_MATCH_FUNC(model, func)	\
	{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func }

#define DEADLINE_MODEL_MATCH_REV(model, rev)	\
	{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev }

static u32 hsx_deadline_rev(void)
{
	switch (boot_cpu_data.x86_mask) {
	case 0x02: return 0x3a; /* EP */
	case 0x04: return 0x0f; /* EX */
	}

	return ~0U;
}

static u32 bdx_deadline_rev(void)
{
	switch (boot_cpu_data.x86_mask) {
	case 0x02: return 0x00000011;
	case 0x03: return 0x0700000e;
	case 0x04: return 0x0f00000c;
	case 0x05: return 0x0e000003;
	}

	return ~0U;
}

static const struct x86_cpu_id deadline_match[] = {
	DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X,	hsx_deadline_rev),
	DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X,	0x0b000020),
	DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_XEON_D,	bdx_deadline_rev),
	DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_X,	0x02000014),

	DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_CORE,	0x22),
	DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_ULT,	0x20),
	DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E,	0x17),

	DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_CORE,	0x25),
	DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E,	0x17),

	DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE,	0xb2),
	DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP,	0xb2),

	DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE,	0x52),
	DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP,	0x52),

	{},
};

static void apic_check_deadline_errata(void)
{
600
	const struct x86_cpu_id *m;
601 602
	u32 rev;

603 604 605 606
	if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
		return;

	m = x86_match_cpu(deadline_match);
607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626
	if (!m)
		return;

	/*
	 * Function pointers will have the MSB set due to address layout,
	 * immediate revisions will not.
	 */
	if ((long)m->driver_data < 0)
		rev = ((u32 (*)(void))(m->driver_data))();
	else
		rev = (u32)m->driver_data;

	if (boot_cpu_data.microcode >= rev)
		return;

	setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
	pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; "
	       "please update microcode to version: 0x%x (or later)\n", rev);
}

627
/*
628
 * Setup the local APIC timer for this CPU. Copy the initialized values
629 630
 * of the boot CPU and register the clock event in the framework.
 */
631
static void setup_APIC_timer(void)
632
{
633
	struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
L
Linus Torvalds 已提交
634

635
	if (this_cpu_has(X86_FEATURE_ARAT)) {
636 637 638 639 640
		lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
		/* Make LAPIC timer preferrable over percpu HPET */
		lapic_clockevent.rating = 150;
	}

641
	memcpy(levt, &lapic_clockevent, sizeof(*levt));
642
	levt->cpumask = cpumask_of(smp_processor_id());
L
Linus Torvalds 已提交
643

644
	if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
645
		levt->name = "lapic-deadline";
646 647 648 649
		levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
				    CLOCK_EVT_FEAT_DUMMY);
		levt->set_next_event = lapic_next_deadline;
		clockevents_config_and_register(levt,
650
						tsc_khz * (1000 / TSC_DIVISOR),
651 652 653
						0xF, ~0UL);
	} else
		clockevents_register_device(levt);
654
}
L
Linus Torvalds 已提交
655

656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679
/*
 * Install the updated TSC frequency from recalibration at the TSC
 * deadline clockevent devices.
 */
static void __lapic_update_tsc_freq(void *info)
{
	struct clock_event_device *levt = this_cpu_ptr(&lapic_events);

	if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
		return;

	clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR));
}

void lapic_update_tsc_freq(void)
{
	/*
	 * The clockevent device's ->mult and ->shift can both be
	 * changed. In order to avoid races, schedule the frequency
	 * update code on each CPU.
	 */
	on_each_cpu(__lapic_update_tsc_freq, NULL, 0);
}

680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717
/*
 * In this functions we calibrate APIC bus clocks to the external timer.
 *
 * We want to do the calibration only once since we want to have local timer
 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
 * frequency.
 *
 * This was previously done by reading the PIT/HPET and waiting for a wrap
 * around to find out, that a tick has elapsed. I have a box, where the PIT
 * readout is broken, so it never gets out of the wait loop again. This was
 * also reported by others.
 *
 * Monitoring the jiffies value is inaccurate and the clockevents
 * infrastructure allows us to do a simple substitution of the interrupt
 * handler.
 *
 * The calibration routine also uses the pm_timer when possible, as the PIT
 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
 * back to normal later in the boot process).
 */

#define LAPIC_CAL_LOOPS		(HZ/10)

static __initdata int lapic_cal_loops = -1;
static __initdata long lapic_cal_t1, lapic_cal_t2;
static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;

/*
 * Temporary interrupt handler.
 */
static void __init lapic_cal_handler(struct clock_event_device *dev)
{
	unsigned long long tsc = 0;
	long tapic = apic_read(APIC_TMCCT);
	unsigned long pm = acpi_pm_read_early();

718
	if (boot_cpu_has(X86_FEATURE_TSC))
719
		tsc = rdtsc();
720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739

	switch (lapic_cal_loops++) {
	case 0:
		lapic_cal_t1 = tapic;
		lapic_cal_tsc1 = tsc;
		lapic_cal_pm1 = pm;
		lapic_cal_j1 = jiffies;
		break;

	case LAPIC_CAL_LOOPS:
		lapic_cal_t2 = tapic;
		lapic_cal_tsc2 = tsc;
		if (pm < lapic_cal_pm1)
			pm += ACPI_PM_OVRRUN;
		lapic_cal_pm2 = pm;
		lapic_cal_j2 = jiffies;
		break;
	}
}

740 741
static int __init
calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
742 743 744 745 746 747 748 749 750 751
{
	const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
	const long pm_thresh = pm_100ms / 100;
	unsigned long mult;
	u64 res;

#ifndef CONFIG_X86_PM_TIMER
	return -1;
#endif

Y
Yasuaki Ishimatsu 已提交
752
	apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
753 754 755 756 757 758 759 760 761

	/* Check, if the PM timer is available */
	if (!deltapm)
		return -1;

	mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);

	if (deltapm > (pm_100ms - pm_thresh) &&
	    deltapm < (pm_100ms + pm_thresh)) {
Y
Yasuaki Ishimatsu 已提交
762
		apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
763 764 765 766 767 768
		return 0;
	}

	res = (((u64)deltapm) *  mult) >> 22;
	do_div(res, 1000000);
	pr_warning("APIC calibration not consistent "
Y
Yasuaki Ishimatsu 已提交
769
		   "with PM-Timer: %ldms instead of 100ms\n",(long)res);
770 771 772 773 774 775 776 777 778

	/* Correct the lapic counter value */
	res = (((u64)(*delta)) * pm_100ms);
	do_div(res, deltapm);
	pr_info("APIC delta adjusted to PM-Timer: "
		"%lu (%ld)\n", (unsigned long)res, *delta);
	*delta = (long)res;

	/* Correct the tsc counter value */
779
	if (boot_cpu_has(X86_FEATURE_TSC)) {
780
		res = (((u64)(*deltatsc)) * pm_100ms);
781
		do_div(res, deltapm);
782
		apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
783
					  "PM-Timer: %lu (%ld)\n",
784 785
					(unsigned long)res, *deltatsc);
		*deltatsc = (long)res;
786 787 788 789 790
	}

	return 0;
}

791 792
static int __init calibrate_APIC_clock(void)
{
793
	struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
794 795
	void (*real_handler)(struct clock_event_device *dev);
	unsigned long deltaj;
796
	long delta, deltatsc;
797 798
	int pm_referenced = 0;

799 800 801 802 803 804
	/**
	 * check if lapic timer has already been calibrated by platform
	 * specific routine, such as tsc calibration code. if so, we just fill
	 * in the clockevent structure and return.
	 */

805 806 807
	if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
		return 0;
	} else if (lapic_timer_frequency) {
808 809 810 811 812 813
		apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
				lapic_timer_frequency);
		lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
					TICK_NSEC, lapic_clockevent.shift);
		lapic_clockevent.max_delta_ns =
			clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
814
		lapic_clockevent.max_delta_ticks = 0x7FFFFF;
815 816
		lapic_clockevent.min_delta_ns =
			clockevent_delta2ns(0xF, &lapic_clockevent);
817
		lapic_clockevent.min_delta_ticks = 0xF;
818 819 820 821
		lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
		return 0;
	}

822 823 824
	apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
		    "calibrating APIC timer ...\n");

825 826 827 828 829 830 831
	local_irq_disable();

	/* Replace the global interrupt handler */
	real_handler = global_clock_event->event_handler;
	global_clock_event->event_handler = lapic_cal_handler;

	/*
C
Cyrill Gorcunov 已提交
832
	 * Setup the APIC counter to maximum. There is no way the lapic
833 834
	 * can underflow in the 100ms detection time frame
	 */
C
Cyrill Gorcunov 已提交
835
	__setup_APIC_LVTT(0xffffffff, 0, 0);
836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851

	/* Let the interrupts run */
	local_irq_enable();

	while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
		cpu_relax();

	local_irq_disable();

	/* Restore the real event handler */
	global_clock_event->event_handler = real_handler;

	/* Build delta t1-t2 as apic timer counts down */
	delta = lapic_cal_t1 - lapic_cal_t2;
	apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);

852 853
	deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);

854 855
	/* we trust the PM based calibration if possible */
	pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
856
					&delta, &deltatsc);
857 858 859 860 861

	/* Calculate the scaled math multiplication factor */
	lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
				       lapic_clockevent.shift);
	lapic_clockevent.max_delta_ns =
862
		clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
863
	lapic_clockevent.max_delta_ticks = 0x7FFFFFFF;
864 865
	lapic_clockevent.min_delta_ns =
		clockevent_delta2ns(0xF, &lapic_clockevent);
866
	lapic_clockevent.min_delta_ticks = 0xF;
867

868
	lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
869 870

	apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
871
	apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
872
	apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
873
		    lapic_timer_frequency);
874

875
	if (boot_cpu_has(X86_FEATURE_TSC)) {
876 877
		apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
			    "%ld.%04ld MHz.\n",
878 879
			    (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
			    (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
880 881 882 883
	}

	apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
		    "%u.%04u MHz.\n",
884 885
		    lapic_timer_frequency / (1000000 / HZ),
		    lapic_timer_frequency % (1000000 / HZ));
886 887 888 889

	/*
	 * Do a sanity check on the APIC calibration result
	 */
890
	if (lapic_timer_frequency < (1000000 / HZ)) {
891
		local_irq_enable();
892
		pr_warning("APIC frequency too slow, disabling apic timer\n");
893 894 895 896 897
		return -1;
	}

	levt->features &= ~CLOCK_EVT_FEAT_DUMMY;

898 899 900 901
	/*
	 * PM timer calibration failed or not turned on
	 * so lets try APIC timer based calibration
	 */
902 903 904 905 906 907 908
	if (!pm_referenced) {
		apic_printk(APIC_VERBOSE, "... verify APIC timer\n");

		/*
		 * Setup the apic timer manually
		 */
		levt->event_handler = lapic_cal_handler;
909
		lapic_timer_set_periodic(levt);
910 911 912 913 914 915 916 917 918
		lapic_cal_loops = -1;

		/* Let the interrupts run */
		local_irq_enable();

		while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
			cpu_relax();

		/* Stop the lapic timer */
919
		local_irq_disable();
920
		lapic_timer_shutdown(levt);
921 922 923 924 925 926 927 928 929 930

		/* Jiffies delta */
		deltaj = lapic_cal_j2 - lapic_cal_j1;
		apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);

		/* Check, if the jiffies result is consistent */
		if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
			apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
		else
			levt->features |= CLOCK_EVT_FEAT_DUMMY;
931 932
	}
	local_irq_enable();
933 934

	if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
935
		pr_warning("APIC timer disabled due to verification failure\n");
936 937 938 939 940 941
			return -1;
	}

	return 0;
}

H
Hiroshi Shimamoto 已提交
942 943 944 945 946
/*
 * Setup the boot APIC
 *
 * Calibrate and verify the result.
 */
947 948 949
void __init setup_boot_APIC_clock(void)
{
	/*
950 951 952 953
	 * The local apic timer can be disabled via the kernel
	 * commandline or from the CPU detection code. Register the lapic
	 * timer as a dummy clock event source on SMP systems, so the
	 * broadcast mechanism is used. On UP systems simply ignore it.
954 955
	 */
	if (disable_apic_timer) {
956
		pr_info("Disabling APIC timer\n");
957
		/* No broadcast on UP ! */
958 959
		if (num_possible_cpus() > 1) {
			lapic_clockevent.mult = 1;
960
			setup_APIC_timer();
961
		}
962 963 964
		return;
	}

965
	if (calibrate_APIC_clock()) {
966 967 968 969 970 971
		/* No broadcast on UP ! */
		if (num_possible_cpus() > 1)
			setup_APIC_timer();
		return;
	}

972 973 974 975 976
	/*
	 * If nmi_watchdog is set to IO_APIC, we need the
	 * PIT/HPET going.  Otherwise register lapic as a dummy
	 * device.
	 */
977
	lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
978

979
	/* Setup the lapic or request the broadcast */
980
	setup_APIC_timer();
981
	amd_e400_c1e_apic_setup();
982 983
}

984
void setup_secondary_APIC_clock(void)
985 986
{
	setup_APIC_timer();
987
	amd_e400_c1e_apic_setup();
988 989 990 991 992 993 994
}

/*
 * The guts of the apic timer interrupt
 */
static void local_apic_timer_interrupt(void)
{
995
	struct clock_event_device *evt = this_cpu_ptr(&lapic_events);
996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008

	/*
	 * Normally we should not be here till LAPIC has been initialized but
	 * in some cases like kdump, its possible that there is a pending LAPIC
	 * timer interrupt from previous kernel's context and is delivered in
	 * new kernel the moment interrupts are enabled.
	 *
	 * Interrupts are enabled early and LAPIC is setup much later, hence
	 * its possible that when we get here evt->event_handler is NULL.
	 * Check for event_handler being NULL and discard the interrupt as
	 * spurious.
	 */
	if (!evt->event_handler) {
1009 1010
		pr_warning("Spurious LAPIC timer interrupt on cpu %d\n",
			   smp_processor_id());
1011
		/* Switch it off */
1012
		lapic_timer_shutdown(evt);
1013 1014 1015 1016 1017 1018
		return;
	}

	/*
	 * the NMI deadlock-detector uses this.
	 */
1019
	inc_irq_stat(apic_timer_irqs);
1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031

	evt->event_handler(evt);
}

/*
 * Local APIC timer interrupt. This is the most natural way for doing
 * local interrupts, but local timer interrupts can be emulated by
 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
 *
 * [ if a single-CPU system runs an SMP kernel then we call the local
 *   interrupt as well. Thus we cannot inline the local irq ... ]
 */
1032
__visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
1033 1034 1035 1036 1037 1038
{
	struct pt_regs *old_regs = set_irq_regs(regs);

	/*
	 * NOTE! We'd better ACK the irq immediately,
	 * because timer handling can be slow.
1039
	 *
1040 1041 1042 1043
	 * update_process_times() expects us to have done irq_enter().
	 * Besides, if we don't timer interrupts ignore the global
	 * interrupt lock, which is the WrongThing (tm) to do.
	 */
1044 1045
	entering_ack_irq();
	trace_local_timer_entry(LOCAL_TIMER_VECTOR);
1046
	local_apic_timer_interrupt();
1047 1048
	trace_local_timer_exit(LOCAL_TIMER_VECTOR);
	exiting_irq();
1049

1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070
	set_irq_regs(old_regs);
}

int setup_profiling_timer(unsigned int multiplier)
{
	return -EINVAL;
}

/*
 * Local APIC start and shutdown
 */

/**
 * clear_local_APIC - shutdown the local APIC
 *
 * This is called, when a CPU is disabled and before rebooting, so the state of
 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
 * leftovers during boot.
 */
void clear_local_APIC(void)
{
1071
	int maxlvt;
1072 1073
	u32 v;

1074
	/* APIC hasn't been mapped yet */
1075
	if (!x2apic_mode && !apic_phys)
1076 1077 1078
		return;

	maxlvt = lapic_get_maxlvt();
1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101
	/*
	 * Masking an LVT entry can trigger a local APIC error
	 * if the vector is zero. Mask LVTERR first to prevent this.
	 */
	if (maxlvt >= 3) {
		v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
		apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
	}
	/*
	 * Careful: we have to set masks only first to deassert
	 * any level-triggered sources.
	 */
	v = apic_read(APIC_LVTT);
	apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
	v = apic_read(APIC_LVT0);
	apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
	v = apic_read(APIC_LVT1);
	apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
	if (maxlvt >= 4) {
		v = apic_read(APIC_LVTPC);
		apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
	}

1102
	/* lets not touch this if we didn't frob it */
1103
#ifdef CONFIG_X86_THERMAL_VECTOR
1104 1105 1106 1107 1108
	if (maxlvt >= 5) {
		v = apic_read(APIC_LVTTHMR);
		apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
	}
#endif
1109 1110 1111 1112 1113 1114 1115 1116
#ifdef CONFIG_X86_MCE_INTEL
	if (maxlvt >= 6) {
		v = apic_read(APIC_LVTCMCI);
		if (!(v & APIC_LVT_MASKED))
			apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
	}
#endif

1117 1118 1119 1120 1121 1122 1123 1124 1125 1126
	/*
	 * Clean APIC state for other OSs:
	 */
	apic_write(APIC_LVTT, APIC_LVT_MASKED);
	apic_write(APIC_LVT0, APIC_LVT_MASKED);
	apic_write(APIC_LVT1, APIC_LVT_MASKED);
	if (maxlvt >= 3)
		apic_write(APIC_LVTERR, APIC_LVT_MASKED);
	if (maxlvt >= 4)
		apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1127 1128 1129 1130 1131 1132 1133 1134

	/* Integrated APIC (!82489DX) ? */
	if (lapic_is_integrated()) {
		if (maxlvt > 3)
			/* Clear ESR due to Pentium errata 3AP and 11AP */
			apic_write(APIC_ESR, 0);
		apic_read(APIC_ESR);
	}
1135 1136 1137 1138 1139 1140 1141 1142 1143
}

/**
 * disable_local_APIC - clear and disable the local APIC
 */
void disable_local_APIC(void)
{
	unsigned int value;

1144
	/* APIC hasn't been mapped yet */
1145
	if (!x2apic_mode && !apic_phys)
1146 1147
		return;

1148 1149 1150 1151 1152 1153 1154 1155 1156
	clear_local_APIC();

	/*
	 * Disable APIC (implies clearing of registers
	 * for 82489DX!).
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_SPIV_APIC_ENABLED;
	apic_write(APIC_SPIV, value);
1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170

#ifdef CONFIG_X86_32
	/*
	 * When LAPIC was disabled by the BIOS and enabled by the kernel,
	 * restore the disabled state.
	 */
	if (enabled_via_apicbase) {
		unsigned int l, h;

		rdmsr(MSR_IA32_APICBASE, l, h);
		l &= ~MSR_IA32_APICBASE_ENABLE;
		wrmsr(MSR_IA32_APICBASE, l, h);
	}
#endif
1171 1172
}

1173 1174 1175 1176 1177 1178
/*
 * If Linux enabled the LAPIC against the BIOS default disable it down before
 * re-entering the BIOS on shutdown.  Otherwise the BIOS may get confused and
 * not power-off.  Additionally clear all LVT entries before disable_local_APIC
 * for the case where Linux didn't enable the LAPIC.
 */
1179 1180 1181 1182
void lapic_shutdown(void)
{
	unsigned long flags;

1183
	if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1184 1185 1186 1187
		return;

	local_irq_save(flags);

1188 1189 1190 1191 1192 1193 1194
#ifdef CONFIG_X86_32
	if (!enabled_via_apicbase)
		clear_local_APIC();
	else
#endif
		disable_local_APIC();

1195 1196 1197 1198 1199 1200 1201

	local_irq_restore(flags);
}

/**
 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
 */
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void __init sync_Arb_IDs(void)
{
C
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1204 1205 1206 1207 1208
	/*
	 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
	 * needed on AMD.
	 */
	if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
L
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1209 1210 1211 1212 1213 1214 1215 1216
		return;

	/*
	 * Wait for idle.
	 */
	apic_wait_icr_idle();

	apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1217 1218
	apic_write(APIC_ICR, APIC_DEST_ALLINC |
			APIC_INT_LEVELTRIG | APIC_DM_INIT);
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1219 1220
}

1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272
enum apic_intr_mode {
	APIC_PIC,
	APIC_VIRTUAL_WIRE,
	APIC_SYMMETRIC_IO,
};

static int __init apic_intr_mode_select(void)
{
	/* Check kernel option */
	if (disable_apic) {
		pr_info("APIC disabled via kernel command line\n");
		return APIC_PIC;
	}

	/* Check BIOS */
#ifdef CONFIG_X86_64
	/* On 64-bit, the APIC must be integrated, Check local APIC only */
	if (!boot_cpu_has(X86_FEATURE_APIC)) {
		disable_apic = 1;
		pr_info("APIC disabled by BIOS\n");
		return APIC_PIC;
	}
#else
	/* On 32-bit, the APIC may be integrated APIC or 82489DX */

	/* Neither 82489DX nor integrated APIC ? */
	if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) {
		disable_apic = 1;
		return APIC_PIC;
	}

	/* If the BIOS pretends there is an integrated APIC ? */
	if (!boot_cpu_has(X86_FEATURE_APIC) &&
		APIC_INTEGRATED(boot_cpu_apic_version)) {
		disable_apic = 1;
		pr_err(FW_BUG "Local APIC %d not detected, force emulation\n",
				       boot_cpu_physical_apicid);
		return APIC_PIC;
	}
#endif

	/* Check MP table or ACPI MADT configuration */
	if (!smp_found_config) {
		disable_ioapic_support();
		if (!acpi_lapic)
			pr_info("APIC: ACPI MADT or MP tables are not detected\n");
		return APIC_VIRTUAL_WIRE;
	}

	return APIC_SYMMETRIC_IO;
}

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/*
 * An initial setup of the virtual wire mode.
 */
void __init init_bsp_APIC(void)
{
1278
	unsigned int value;
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	/*
	 * Don't do the setup now if we have a SMP BIOS as the
	 * through-I/O-APIC virtual wire mode might be active.
	 */
1284
	if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC))
L
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1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297
		return;

	/*
	 * Do not trust the local APIC being empty at bootup.
	 */
	clear_local_APIC();

	/*
	 * Enable APIC.
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	value |= APIC_SPIV_APIC_ENABLED;
1298 1299 1300 1301 1302 1303 1304 1305 1306

#ifdef CONFIG_X86_32
	/* This bit is reserved on P4/Xeon and should be cleared */
	if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
	    (boot_cpu_data.x86 == 15))
		value &= ~APIC_SPIV_FOCUS_DISABLED;
	else
#endif
		value |= APIC_SPIV_FOCUS_DISABLED;
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	value |= SPURIOUS_APIC_VECTOR;
1308
	apic_write(APIC_SPIV, value);
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	/*
	 * Set up the virtual wire mode.
	 */
1313
	apic_write(APIC_LVT0, APIC_DM_EXTINT);
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Linus Torvalds 已提交
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	value = APIC_DM_NMI;
1315 1316
	if (!lapic_is_integrated())		/* 82489DX */
		value |= APIC_LVT_LEVEL_TRIGGER;
1317 1318
	if (apic_extnmi == APIC_EXTNMI_NONE)
		value |= APIC_LVT_MASKED;
1319
	apic_write(APIC_LVT1, value);
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Linus Torvalds 已提交
1320 1321
}

1322
static void lapic_setup_esr(void)
1323
{
1324 1325 1326
	unsigned int oldvalue, value, maxlvt;

	if (!lapic_is_integrated()) {
1327
		pr_info("No ESR for 82489DX.\n");
1328 1329
		return;
	}
1330

1331
	if (apic->disable_esr) {
1332
		/*
1333 1334 1335 1336
		 * Something untraceable is creating bad interrupts on
		 * secondary quads ... for the moment, just leave the
		 * ESR disabled - we can't do anything useful with the
		 * errors anyway - mbligh
1337
		 */
1338
		pr_info("Leaving ESR disabled.\n");
1339
		return;
1340
	}
1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360

	maxlvt = lapic_get_maxlvt();
	if (maxlvt > 3)		/* Due to the Pentium erratum 3AP. */
		apic_write(APIC_ESR, 0);
	oldvalue = apic_read(APIC_ESR);

	/* enables sending errors */
	value = ERROR_APIC_VECTOR;
	apic_write(APIC_LVTERR, value);

	/*
	 * spec says clear errors after enabling vector.
	 */
	if (maxlvt > 3)
		apic_write(APIC_ESR, 0);
	value = apic_read(APIC_ESR);
	if (value != oldvalue)
		apic_printk(APIC_VERBOSE, "ESR value before enabling "
			"vector: 0x%08x  after: 0x%08x\n",
			oldvalue, value);
1361 1362
}

1363 1364
/**
 * setup_local_APIC - setup the local APIC
1365
 *
1366
 * Used to setup local APIC while initializing BSP or bringing up APs.
1367
 * Always called with preemption disabled.
1368
 */
1369
void setup_local_APIC(void)
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Linus Torvalds 已提交
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{
1371
	int cpu = smp_processor_id();
1372 1373 1374
	unsigned int value, queued;
	int i, j, acked = 0;
	unsigned long long tsc = 0, ntsc;
1375
	long long max_loops = cpu_khz ? cpu_khz : 1000000;
1376

1377
	if (boot_cpu_has(X86_FEATURE_TSC))
1378
		tsc = rdtsc();
L
Linus Torvalds 已提交
1379

J
Jan Beulich 已提交
1380
	if (disable_apic) {
1381
		disable_ioapic_support();
J
Jan Beulich 已提交
1382 1383 1384
		return;
	}

1385 1386
#ifdef CONFIG_X86_32
	/* Pound the ESR really hard over the head with a big hammer - mbligh */
1387
	if (lapic_is_integrated() && apic->disable_esr) {
1388 1389 1390 1391 1392 1393
		apic_write(APIC_ESR, 0);
		apic_write(APIC_ESR, 0);
		apic_write(APIC_ESR, 0);
		apic_write(APIC_ESR, 0);
	}
#endif
1394
	perf_events_lapic_init();
1395

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Linus Torvalds 已提交
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	/*
	 * Double-check whether this APIC is really registered.
	 * This is meaningless in clustered apic mode, so we skip it.
	 */
1400
	BUG_ON(!apic->apic_id_registered());
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	/*
	 * Intel recommends to set DFR, LDR and TPR before enabling
	 * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
	 * document number 292116).  So here it goes...
	 */
1407
	apic->init_apic_ldr();
L
Linus Torvalds 已提交
1408

1409 1410
#ifdef CONFIG_X86_32
	/*
1411 1412 1413
	 * APIC LDR is initialized.  If logical_apicid mapping was
	 * initialized during get_smp_config(), make sure it matches the
	 * actual value.
1414
	 */
1415 1416 1417
	i = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
	WARN_ON(i != BAD_APICID && i != logical_smp_processor_id());
	/* always use the value from LDR */
1418 1419 1420 1421
	early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
		logical_smp_processor_id();
#endif

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	/*
	 * Set Task Priority to 'accept all'. We never change this
	 * later on.
	 */
	value = apic_read(APIC_TASKPRI);
	value &= ~APIC_TPRI_MASK;
1428
	apic_write(APIC_TASKPRI, value);
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Linus Torvalds 已提交
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1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440
	/*
	 * After a crash, we no longer service the interrupts and a pending
	 * interrupt from previous kernel might still have ISR bit set.
	 *
	 * Most probably by now CPU has serviced that pending interrupt and
	 * it might not have done the ack_APIC_irq() because it thought,
	 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
	 * does not clear the ISR bit and cpu thinks it has already serivced
	 * the interrupt. Hence a vector might get locked. It was noticed
	 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
	 */
1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453
	do {
		queued = 0;
		for (i = APIC_ISR_NR - 1; i >= 0; i--)
			queued |= apic_read(APIC_IRR + i*0x10);

		for (i = APIC_ISR_NR - 1; i >= 0; i--) {
			value = apic_read(APIC_ISR + i*0x10);
			for (j = 31; j >= 0; j--) {
				if (value & (1<<j)) {
					ack_APIC_irq();
					acked++;
				}
			}
1454
		}
1455 1456 1457 1458 1459
		if (acked > 256) {
			printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
			       acked);
			break;
		}
1460
		if (queued) {
1461
			if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) {
1462
				ntsc = rdtsc();
1463 1464 1465 1466
				max_loops = (cpu_khz << 10) - (ntsc - tsc);
			} else
				max_loops--;
		}
1467 1468
	} while (queued && max_loops > 0);
	WARN_ON(max_loops <= 0);
1469

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Linus Torvalds 已提交
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	/*
	 * Now that we are all set up, enable the APIC
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	/*
	 * Enable APIC
	 */
	value |= APIC_SPIV_APIC_ENABLED;

1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506
#ifdef CONFIG_X86_32
	/*
	 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
	 * certain networking cards. If high frequency interrupts are
	 * happening on a particular IOAPIC pin, plus the IOAPIC routing
	 * entry is masked/unmasked at a high rate as well then sooner or
	 * later IOAPIC line gets 'stuck', no more interrupts are received
	 * from the device. If focus CPU is disabled then the hang goes
	 * away, oh well :-(
	 *
	 * [ This bug can be reproduced easily with a level-triggered
	 *   PCI Ne2000 networking cards and PII/PIII processors, dual
	 *   BX chipset. ]
	 */
	/*
	 * Actually disabling the focus CPU check just makes the hang less
	 * frequent as it makes the interrupt distributon model be more
	 * like LRU than MRU (the short-term load is more even across CPUs).
	 */

	/*
	 * - enable focus processor (bit==0)
	 * - 64bit mode always use processor focus
	 *   so no need to set it
	 */
	value &= ~APIC_SPIV_FOCUS_DISABLED;
#endif
1507

L
Linus Torvalds 已提交
1508 1509 1510 1511
	/*
	 * Set spurious IRQ vector
	 */
	value |= SPURIOUS_APIC_VECTOR;
1512
	apic_write(APIC_SPIV, value);
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Linus Torvalds 已提交
1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524

	/*
	 * Set up LVT0, LVT1:
	 *
	 * set up through-local-APIC on the BP's LINT0. This is not
	 * strictly necessary in pure symmetric-IO mode, but sometimes
	 * we delegate interrupts to the 8259A.
	 */
	/*
	 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
	 */
	value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1525
	if (!cpu && (pic_mode || !value)) {
L
Linus Torvalds 已提交
1526
		value = APIC_DM_EXTINT;
1527
		apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
L
Linus Torvalds 已提交
1528 1529
	} else {
		value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1530
		apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
L
Linus Torvalds 已提交
1531
	}
1532
	apic_write(APIC_LVT0, value);
L
Linus Torvalds 已提交
1533 1534

	/*
1535 1536
	 * Only the BSP sees the LINT1 NMI signal by default. This can be
	 * modified by apic_extnmi= boot option.
L
Linus Torvalds 已提交
1537
	 */
1538 1539
	if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) ||
	    apic_extnmi == APIC_EXTNMI_ALL)
L
Linus Torvalds 已提交
1540 1541 1542
		value = APIC_DM_NMI;
	else
		value = APIC_DM_NMI | APIC_LVT_MASKED;
1543 1544
	if (!lapic_is_integrated())		/* 82489DX */
		value |= APIC_LVT_LEVEL_TRIGGER;
1545
	apic_write(APIC_LVT1, value);
1546

1547 1548
#ifdef CONFIG_X86_MCE_INTEL
	/* Recheck CMCI information after local APIC is up on CPU #0 */
1549
	if (!cpu)
1550 1551
		cmci_recheck();
#endif
1552
}
L
Linus Torvalds 已提交
1553

1554
static void end_local_APIC_setup(void)
1555 1556
{
	lapic_setup_esr();
1557 1558

#ifdef CONFIG_X86_32
1559 1560 1561 1562 1563 1564 1565
	{
		unsigned int value;
		/* Disable the local apic timer */
		value = apic_read(APIC_LVTT);
		value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
		apic_write(APIC_LVTT, value);
	}
1566 1567
#endif

1568
	apic_pm_activate();
1569 1570
}

1571 1572 1573 1574
/*
 * APIC setup function for application processors. Called from smpboot.c
 */
void apic_ap_setup(void)
1575
{
1576
	setup_local_APIC();
1577
	end_local_APIC_setup();
L
Linus Torvalds 已提交
1578 1579
}

Y
Yinghai Lu 已提交
1580
#ifdef CONFIG_X86_X2APIC
1581
int x2apic_mode;
1582 1583 1584 1585 1586 1587 1588 1589

enum {
	X2APIC_OFF,
	X2APIC_ON,
	X2APIC_DISABLED,
};
static int x2apic_state;

1590
static void __x2apic_disable(void)
1591 1592 1593
{
	u64 msr;

1594
	if (!boot_cpu_has(X86_FEATURE_APIC))
1595 1596
		return;

1597 1598 1599 1600 1601 1602 1603 1604 1605
	rdmsrl(MSR_IA32_APICBASE, msr);
	if (!(msr & X2APIC_ENABLE))
		return;
	/* Disable xapic and x2apic first and then reenable xapic mode */
	wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
	wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
	printk_once(KERN_INFO "x2apic disabled\n");
}

1606
static void __x2apic_enable(void)
1607 1608 1609 1610 1611 1612 1613 1614 1615 1616
{
	u64 msr;

	rdmsrl(MSR_IA32_APICBASE, msr);
	if (msr & X2APIC_ENABLE)
		return;
	wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
	printk_once(KERN_INFO "x2apic enabled\n");
}

1617 1618 1619 1620 1621 1622 1623 1624 1625 1626
static int __init setup_nox2apic(char *str)
{
	if (x2apic_enabled()) {
		int apicid = native_apic_msr_read(APIC_ID);

		if (apicid >= 255) {
			pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
				   apicid);
			return 0;
		}
1627 1628 1629 1630
		pr_warning("x2apic already enabled.\n");
		__x2apic_disable();
	}
	setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1631
	x2apic_state = X2APIC_DISABLED;
1632
	x2apic_mode = 0;
1633 1634 1635 1636
	return 0;
}
early_param("nox2apic", setup_nox2apic);

1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650
/* Called from cpu_init() to enable x2apic on (secondary) cpus */
void x2apic_setup(void)
{
	/*
	 * If x2apic is not in ON state, disable it if already enabled
	 * from BIOS.
	 */
	if (x2apic_state != X2APIC_ON) {
		__x2apic_disable();
		return;
	}
	__x2apic_enable();
}

1651
static __init void x2apic_disable(void)
1652
{
1653
	u32 x2apic_id, state = x2apic_state;
1654

1655 1656 1657 1658 1659
	x2apic_mode = 0;
	x2apic_state = X2APIC_DISABLED;

	if (state != X2APIC_ON)
		return;
1660

1661 1662 1663
	x2apic_id = read_apic_id();
	if (x2apic_id >= 255)
		panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1664

1665 1666
	__x2apic_disable();
	register_lapic_address(mp_lapic_addr);
1667 1668
}

1669
static __init void x2apic_enable(void)
1670
{
1671
	if (x2apic_state != X2APIC_OFF)
Y
Yinghai Lu 已提交
1672 1673
		return;

1674
	x2apic_mode = 1;
1675
	x2apic_state = X2APIC_ON;
1676
	__x2apic_enable();
1677
}
T
Thomas Gleixner 已提交
1678

1679
static __init void try_to_enable_x2apic(int remap_mode)
1680
{
1681
	if (x2apic_state == X2APIC_DISABLED)
1682 1683
		return;

1684
	if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
1685 1686 1687 1688
		/* IR is required if there is APIC ID > 255 even when running
		 * under KVM
		 */
		if (max_physical_apicid > 255 ||
1689
		    !hypervisor_x2apic_available()) {
1690
			pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1691
			x2apic_disable();
1692 1693 1694 1695 1696 1697 1698
			return;
		}

		/*
		 * without IR all CPUs can be addressed by IOAPIC/MSI
		 * only in physical mode
		 */
1699
		x2apic_phys = 1;
1700
	}
1701
	x2apic_enable();
1702 1703 1704 1705 1706 1707 1708
}

void __init check_x2apic(void)
{
	if (x2apic_enabled()) {
		pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
		x2apic_mode = 1;
1709
		x2apic_state = X2APIC_ON;
1710
	} else if (!boot_cpu_has(X86_FEATURE_X2APIC)) {
1711
		x2apic_state = X2APIC_DISABLED;
1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725
	}
}
#else /* CONFIG_X86_X2APIC */
static int __init validate_x2apic(void)
{
	if (!apic_is_x2apic_enabled())
		return 0;
	/*
	 * Checkme: Can we simply turn off x2apic here instead of panic?
	 */
	panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
}
early_initcall(validate_x2apic);

1726
static inline void try_to_enable_x2apic(int remap_mode) { }
1727
static inline void __x2apic_enable(void) { }
1728 1729
#endif /* !CONFIG_X86_X2APIC */

1730 1731 1732
void __init enable_IR_x2apic(void)
{
	unsigned long flags;
1733
	int ret, ir_stat;
1734

1735 1736
	if (skip_ioapic_setup) {
		pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1737
		return;
1738
	}
1739

1740 1741
	ir_stat = irq_remapping_prepare();
	if (ir_stat < 0 && !x2apic_supported())
Y
Yinghai Lu 已提交
1742
		return;
1743

1744
	ret = save_ioapic_entries();
1745
	if (ret) {
1746
		pr_info("Saving IO-APIC state failed: %d\n", ret);
1747
		return;
1748
	}
1749

1750
	local_irq_save(flags);
1751
	legacy_pic->mask_all();
1752
	mask_ioapic_entries();
1753

1754
	/* If irq_remapping_prepare() succeeded, try to enable it */
1755
	if (ir_stat >= 0)
1756
		ir_stat = irq_remapping_enable();
1757 1758
	/* ir_stat contains the remap mode or an error code */
	try_to_enable_x2apic(ir_stat);
1759

1760
	if (ir_stat < 0)
1761
		restore_ioapic_entries();
1762
	legacy_pic->restore_mask();
1763 1764
	local_irq_restore(flags);
}
1765

1766
#ifdef CONFIG_X86_64
L
Linus Torvalds 已提交
1767 1768 1769 1770
/*
 * Detect and enable local APICs on non-SMP boards.
 * Original code written by Keir Fraser.
 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1771
 * not correctly set up (usually the APIC timer won't work etc.)
L
Linus Torvalds 已提交
1772
 */
1773
static int __init detect_init_APIC(void)
L
Linus Torvalds 已提交
1774
{
1775
	if (!boot_cpu_has(X86_FEATURE_APIC)) {
1776
		pr_info("No local APIC present\n");
L
Linus Torvalds 已提交
1777 1778 1779 1780 1781 1782
		return -1;
	}

	mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
	return 0;
}
1783
#else
1784

1785
static int __init apic_verify(void)
1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801
{
	u32 features, h, l;

	/*
	 * The APIC feature bit should now be enabled
	 * in `cpuid'
	 */
	features = cpuid_edx(1);
	if (!(features & (1 << X86_FEATURE_APIC))) {
		pr_warning("Could not enable APIC!\n");
		return -1;
	}
	set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
	mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;

	/* The BIOS may have set up the APIC at some other address */
1802 1803 1804 1805 1806
	if (boot_cpu_data.x86 >= 6) {
		rdmsr(MSR_IA32_APICBASE, l, h);
		if (l & MSR_IA32_APICBASE_ENABLE)
			mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
	}
1807 1808 1809 1810 1811

	pr_info("Found and enabled local APIC!\n");
	return 0;
}

1812
int __init apic_force_enable(unsigned long addr)
1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823
{
	u32 h, l;

	if (disable_apic)
		return -1;

	/*
	 * Some BIOSes disable the local APIC in the APIC_BASE
	 * MSR. This can only be done in software for Intel P6 or later
	 * and AMD K7 (Model > 1) or later.
	 */
1824 1825 1826 1827 1828 1829 1830 1831 1832
	if (boot_cpu_data.x86 >= 6) {
		rdmsr(MSR_IA32_APICBASE, l, h);
		if (!(l & MSR_IA32_APICBASE_ENABLE)) {
			pr_info("Local APIC disabled by BIOS -- reenabling.\n");
			l &= ~MSR_IA32_APICBASE_BASE;
			l |= MSR_IA32_APICBASE_ENABLE | addr;
			wrmsr(MSR_IA32_APICBASE, l, h);
			enabled_via_apicbase = 1;
		}
1833 1834 1835 1836
	}
	return apic_verify();
}

1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848
/*
 * Detect and initialize APIC
 */
static int __init detect_init_APIC(void)
{
	/* Disabled by kernel option? */
	if (disable_apic)
		return -1;

	switch (boot_cpu_data.x86_vendor) {
	case X86_VENDOR_AMD:
		if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1849
		    (boot_cpu_data.x86 >= 15))
1850 1851 1852 1853
			break;
		goto no_apic;
	case X86_VENDOR_INTEL:
		if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1854
		    (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC)))
1855 1856 1857 1858 1859 1860
			break;
		goto no_apic;
	default:
		goto no_apic;
	}

1861
	if (!boot_cpu_has(X86_FEATURE_APIC)) {
1862 1863 1864 1865 1866
		/*
		 * Over-ride BIOS and try to enable the local APIC only if
		 * "lapic" specified.
		 */
		if (!force_enable_local_apic) {
1867 1868
			pr_info("Local APIC disabled by BIOS -- "
				"you can enable it with \"lapic\"\n");
1869 1870
			return -1;
		}
1871
		if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1872 1873 1874 1875
			return -1;
	} else {
		if (apic_verify())
			return -1;
1876 1877 1878 1879 1880 1881 1882
	}

	apic_pm_activate();

	return 0;

no_apic:
1883
	pr_info("No local APIC present or hardware disabled\n");
1884 1885 1886
	return -1;
}
#endif
L
Linus Torvalds 已提交
1887

1888 1889 1890
/**
 * init_apic_mappings - initialize APIC mappings
 */
L
Linus Torvalds 已提交
1891 1892
void __init init_apic_mappings(void)
{
1893 1894
	unsigned int new_apicid;

1895 1896
	apic_check_deadline_errata();

1897
	if (x2apic_mode) {
1898
		boot_cpu_physical_apicid = read_apic_id();
1899 1900 1901
		return;
	}

1902
	/* If no local APIC can be found return early */
L
Linus Torvalds 已提交
1903
	if (!smp_found_config && detect_init_APIC()) {
1904 1905 1906 1907
		/* lets NOP'ify apic operations */
		pr_info("APIC: disable apic facility\n");
		apic_disable();
	} else {
L
Linus Torvalds 已提交
1908 1909
		apic_phys = mp_lapic_addr;

1910
		/*
1911 1912
		 * If the system has ACPI MADT tables or MP info, the LAPIC
		 * address is already registered.
1913
		 */
1914
		if (!acpi_lapic && !smp_found_config)
1915
			register_lapic_address(apic_phys);
1916
	}
L
Linus Torvalds 已提交
1917 1918 1919 1920 1921

	/*
	 * Fetch the APIC ID of the BSP in case we have a
	 * default configuration (or the MP table is broken).
	 */
1922 1923 1924
	new_apicid = read_apic_id();
	if (boot_cpu_physical_apicid != new_apicid) {
		boot_cpu_physical_apicid = new_apicid;
1925 1926 1927 1928 1929 1930 1931
		/*
		 * yeah -- we lie about apic_version
		 * in case if apic was disabled via boot option
		 * but it's not a problem for SMP compiled kernel
		 * since smp_sanity_check is prepared for such a case
		 * and disable smp mode
		 */
1932
		boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
1933
	}
L
Linus Torvalds 已提交
1934 1935
}

1936 1937 1938 1939
void __init register_lapic_address(unsigned long address)
{
	mp_lapic_addr = address;

1940 1941 1942
	if (!x2apic_mode) {
		set_fixmap_nocache(FIX_APIC_BASE, address);
		apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1943
			    APIC_BASE, address);
1944
	}
1945 1946
	if (boot_cpu_physical_apicid == -1U) {
		boot_cpu_physical_apicid  = read_apic_id();
1947
		boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
1948 1949 1950
	}
}

L
Linus Torvalds 已提交
1951
/*
1952
 * Local APIC interrupts
L
Linus Torvalds 已提交
1953 1954
 */

1955 1956 1957
/*
 * This interrupt should _never_ happen with our APIC/SMP architecture
 */
1958
__visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs)
L
Linus Torvalds 已提交
1959
{
1960
	u8 vector = ~regs->orig_ax;
1961 1962
	u32 v;

1963 1964 1965
	entering_irq();
	trace_spurious_apic_entry(vector);

L
Linus Torvalds 已提交
1966
	/*
1967 1968 1969
	 * Check if this really is a spurious interrupt and ACK it
	 * if it is a vectored one.  Just in case...
	 * Spurious interrupts should not be ACKed.
L
Linus Torvalds 已提交
1970
	 */
1971 1972
	v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
	if (v & (1 << (vector & 0x1f)))
1973
		ack_APIC_irq();
1974

1975 1976
	inc_irq_stat(irq_spurious_count);

1977
	/* see sw-dev-man vol 3, chapter 7.4.13.5 */
1978 1979
	pr_info("spurious APIC interrupt through vector %02x on CPU#%d, "
		"should never happen.\n", vector, smp_processor_id());
1980

1981
	trace_spurious_apic_exit(vector);
1982
	exiting_irq();
1983
}
L
Linus Torvalds 已提交
1984

1985 1986 1987
/*
 * This interrupt should never happen with our APIC/SMP architecture
 */
1988
__visible void __irq_entry smp_error_interrupt(struct pt_regs *regs)
1989
{
1990 1991 1992 1993 1994 1995 1996 1997 1998 1999
	static const char * const error_interrupt_reason[] = {
		"Send CS error",		/* APIC Error Bit 0 */
		"Receive CS error",		/* APIC Error Bit 1 */
		"Send accept error",		/* APIC Error Bit 2 */
		"Receive accept error",		/* APIC Error Bit 3 */
		"Redirectable IPI",		/* APIC Error Bit 4 */
		"Send illegal vector",		/* APIC Error Bit 5 */
		"Received illegal vector",	/* APIC Error Bit 6 */
		"Illegal register address",	/* APIC Error Bit 7 */
	};
2000 2001 2002 2003
	u32 v, i = 0;

	entering_irq();
	trace_error_apic_entry(ERROR_APIC_VECTOR);
L
Linus Torvalds 已提交
2004

2005
	/* First tickle the hardware, only then report what went on. -- REW */
2006 2007
	if (lapic_get_maxlvt() > 3)	/* Due to the Pentium erratum 3AP. */
		apic_write(APIC_ESR, 0);
2008
	v = apic_read(APIC_ESR);
2009 2010
	ack_APIC_irq();
	atomic_inc(&irq_err_count);
2011

2012 2013
	apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
		    smp_processor_id(), v);
2014

2015 2016 2017
	v &= 0xff;
	while (v) {
		if (v & 0x1)
2018 2019
			apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
		i++;
2020
		v >>= 1;
2021
	}
2022 2023 2024

	apic_printk(APIC_DEBUG, KERN_CONT "\n");

2025 2026
	trace_error_apic_exit(ERROR_APIC_VECTOR);
	exiting_irq();
L
Linus Torvalds 已提交
2027 2028
}

2029
/**
2030 2031
 * connect_bsp_APIC - attach the APIC to the interrupt system
 */
2032
static void __init connect_bsp_APIC(void)
2033
{
2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045
#ifdef CONFIG_X86_32
	if (pic_mode) {
		/*
		 * Do not trust the local APIC being empty at bootup.
		 */
		clear_local_APIC();
		/*
		 * PIC mode, enable APIC mode in the IMCR, i.e.  connect BSP's
		 * local APIC to INT and NMI lines.
		 */
		apic_printk(APIC_VERBOSE, "leaving PIC mode, "
				"enabling APIC mode.\n");
2046
		imcr_pic_to_apic();
2047 2048
	}
#endif
2049 2050
}

2051 2052 2053 2054 2055 2056 2057
/**
 * disconnect_bsp_APIC - detach the APIC from the interrupt system
 * @virt_wire_setup:	indicates, whether virtual wire mode is selected
 *
 * Virtual wire mode is necessary to deliver legacy interrupts even when the
 * APIC is disabled.
 */
2058
void disconnect_bsp_APIC(int virt_wire_setup)
L
Linus Torvalds 已提交
2059
{
2060 2061
	unsigned int value;

2062 2063 2064 2065 2066 2067 2068 2069 2070 2071
#ifdef CONFIG_X86_32
	if (pic_mode) {
		/*
		 * Put the board back into PIC mode (has an effect only on
		 * certain older boards).  Note that APIC interrupts, including
		 * IPIs, won't work beyond this point!  The only exception are
		 * INIT IPIs.
		 */
		apic_printk(APIC_VERBOSE, "disabling APIC mode, "
				"entering PIC mode.\n");
2072
		imcr_apic_to_pic();
2073 2074 2075 2076
		return;
	}
#endif

2077
	/* Go back to Virtual Wire compatibility mode */
L
Linus Torvalds 已提交
2078

2079 2080 2081 2082 2083 2084
	/* For the spurious interrupt use vector F, and enable it */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	value |= APIC_SPIV_APIC_ENABLED;
	value |= 0xf;
	apic_write(APIC_SPIV, value);
T
Thomas Gleixner 已提交
2085

2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101
	if (!virt_wire_setup) {
		/*
		 * For LVT0 make it edge triggered, active high,
		 * external and enabled
		 */
		value = apic_read(APIC_LVT0);
		value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
		value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
		value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
		apic_write(APIC_LVT0, value);
	} else {
		/* Disable LVT0 */
		apic_write(APIC_LVT0, APIC_LVT_MASKED);
	}
T
Thomas Gleixner 已提交
2102

2103 2104 2105 2106
	/*
	 * For LVT1 make it edge triggered, active high,
	 * nmi and enabled
	 */
2107 2108 2109 2110 2111 2112 2113
	value = apic_read(APIC_LVT1);
	value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
	value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
	value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
	apic_write(APIC_LVT1, value);
L
Linus Torvalds 已提交
2114 2115
}

2116 2117 2118
/*
 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated
 * contiguously, it equals to current allocated max logical CPU ID plus 1.
D
Dou Liyang 已提交
2119 2120
 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range,
 * so the maximum of nr_logical_cpuids is nr_cpu_ids.
2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151
 *
 * NOTE: Reserve 0 for BSP.
 */
static int nr_logical_cpuids = 1;

/*
 * Used to store mapping between logical CPU IDs and APIC IDs.
 */
static int cpuid_to_apicid[] = {
	[0 ... NR_CPUS - 1] = -1,
};

/*
 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids
 * and cpuid_to_apicid[] synchronized.
 */
static int allocate_logical_cpuid(int apicid)
{
	int i;

	/*
	 * cpuid <-> apicid mapping is persistent, so when a cpu is up,
	 * check if the kernel has allocated a cpuid for it.
	 */
	for (i = 0; i < nr_logical_cpuids; i++) {
		if (cpuid_to_apicid[i] == apicid)
			return i;
	}

	/* Allocate a new cpuid. */
	if (nr_logical_cpuids >= nr_cpu_ids) {
2152
		WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. "
2153
			     "Processor %d/0x%x and the rest are ignored.\n",
2154 2155
			     nr_cpu_ids, nr_logical_cpuids, apicid);
		return -EINVAL;
2156 2157 2158 2159 2160 2161
	}

	cpuid_to_apicid[nr_logical_cpuids] = apicid;
	return nr_logical_cpuids++;
}

2162
int generic_processor_info(int apicid, int version)
2163
{
2164 2165 2166 2167
	int cpu, max = nr_cpu_ids;
	bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
				phys_cpu_present_map);

2168 2169 2170 2171
	/*
	 * boot_cpu_physical_apicid is designed to have the apicid
	 * returned by read_apic_id(), i.e, the apicid of the
	 * currently booting-up processor. However, on some platforms,
2172
	 * it is temporarily modified by the apicid reported as BSP
2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184
	 * through MP table. Concretely:
	 *
	 * - arch/x86/kernel/mpparse.c: MP_processor_info()
	 * - arch/x86/mm/amdtopology.c: amd_numa_init()
	 *
	 * This function is executed with the modified
	 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
	 * parameter doesn't work to disable APs on kdump 2nd kernel.
	 *
	 * Since fixing handling of boot_cpu_physical_apicid requires
	 * another discussion and tests on each platform, we leave it
	 * for now and here we use read_apic_id() directly in this
2185
	 * function, generic_processor_info().
2186 2187 2188 2189 2190 2191
	 */
	if (disabled_cpu_apicid != BAD_APICID &&
	    disabled_cpu_apicid != read_apic_id() &&
	    disabled_cpu_apicid == apicid) {
		int thiscpu = num_processors + disabled_cpus;

2192
		pr_warning("APIC: Disabling requested cpu."
2193 2194 2195 2196 2197 2198 2199
			   " Processor %d/0x%x ignored.\n",
			   thiscpu, apicid);

		disabled_cpus++;
		return -ENODEV;
	}

2200 2201 2202 2203 2204 2205 2206 2207 2208
	/*
	 * If boot cpu has not been detected yet, then only allow upto
	 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
	 */
	if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
	    apicid != boot_cpu_physical_apicid) {
		int thiscpu = max + disabled_cpus - 1;

		pr_warning(
C
Claudio Fontana 已提交
2209
			"APIC: NR_CPUS/possible_cpus limit of %i almost"
2210 2211 2212 2213
			" reached. Keeping one slot for boot cpu."
			"  Processor %d/0x%x ignored.\n", max, thiscpu, apicid);

		disabled_cpus++;
2214
		return -ENODEV;
2215
	}
2216

2217 2218 2219
	if (num_processors >= nr_cpu_ids) {
		int thiscpu = max + disabled_cpus;

2220 2221 2222
		pr_warning("APIC: NR_CPUS/possible_cpus limit of %i "
			   "reached. Processor %d/0x%x ignored.\n",
			   max, thiscpu, apicid);
2223 2224

		disabled_cpus++;
2225
		return -EINVAL;
2226 2227 2228 2229 2230 2231 2232
	}

	if (apicid == boot_cpu_physical_apicid) {
		/*
		 * x86_bios_cpu_apicid is required to have processors listed
		 * in same order as logical cpu numbers. Hence the first
		 * entry is BSP, and so on.
2233 2234
		 * boot_cpu_init() already hold bit 0 in cpu_present_mask
		 * for BSP.
2235 2236
		 */
		cpu = 0;
2237 2238 2239 2240 2241 2242 2243 2244 2245 2246

		/* Logical cpuid 0 is reserved for BSP. */
		cpuid_to_apicid[0] = apicid;
	} else {
		cpu = allocate_logical_cpuid(apicid);
		if (cpu < 0) {
			disabled_cpus++;
			return -EINVAL;
		}
	}
2247 2248 2249 2250 2251 2252 2253 2254

	/*
	 * Validate version
	 */
	if (version == 0x0) {
		pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
			   cpu, apicid);
		version = 0x10;
2255
	}
2256

2257
	if (version != boot_cpu_apic_version) {
2258
		pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2259
			boot_cpu_apic_version, cpu, version);
2260 2261
	}

2262 2263 2264
	if (apicid > max_physical_apicid)
		max_physical_apicid = apicid;

2265
#if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2266 2267
	early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
	early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2268
#endif
2269 2270 2271 2272
#ifdef CONFIG_X86_32
	early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
		apic->x86_32_early_logical_apicid(cpu);
#endif
2273
	set_cpu_possible(cpu, true);
2274 2275 2276
	physid_set(apicid, phys_cpu_present_map);
	set_cpu_present(cpu, true);
	num_processors++;
2277 2278

	return cpu;
2279 2280
}

2281 2282 2283 2284
int hard_smp_processor_id(void)
{
	return read_apic_id();
}
I
Ingo Molnar 已提交
2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295

void default_init_apic_ldr(void)
{
	unsigned long val;

	apic_write(APIC_DFR, APIC_DFR_VALUE);
	val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
	val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
	apic_write(APIC_LDR, val);
}

2296 2297 2298
int default_cpu_mask_to_apicid(const struct cpumask *mask,
			       struct irq_data *irqdata,
			       unsigned int *apicid)
2299
{
2300
	unsigned int cpu = cpumask_first(mask);
2301

2302 2303 2304
	if (cpu >= nr_cpu_ids)
		return -EINVAL;
	*apicid = per_cpu(x86_cpu_to_apicid, cpu);
2305
	irq_data_update_effective_affinity(irqdata, cpumask_of(cpu));
2306
	return 0;
2307 2308
}

2309 2310 2311 2312
int flat_cpu_mask_to_apicid(const struct cpumask *mask,
			    struct irq_data *irqdata,
			    unsigned int *apicid)

2313
{
2314
	struct cpumask *effmsk = irq_data_get_effective_affinity_mask(irqdata);
2315
	unsigned long cpu_mask = cpumask_bits(mask)[0] & APIC_ALL_CPUS;
2316

2317 2318 2319
	if (!cpu_mask)
		return -EINVAL;
	*apicid = (unsigned int)cpu_mask;
2320
	cpumask_bits(effmsk)[0] = cpu_mask;
2321
	return 0;
2322 2323
}

2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336
/*
 * Override the generic EOI implementation with an optimized version.
 * Only called during early boot when only one CPU is active and with
 * interrupts disabled, so we know this does not race with actual APIC driver
 * use.
 */
void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
{
	struct apic **drv;

	for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
		/* Should happen once for each apic */
		WARN_ON((*drv)->eoi_write == eoi_write);
2337
		(*drv)->native_eoi_write = (*drv)->eoi_write;
2338 2339 2340 2341
		(*drv)->eoi_write = eoi_write;
	}
}

2342
static void __init apic_bsp_up_setup(void)
2343
{
2344
#ifdef CONFIG_X86_64
2345
	apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid));
2346
#else
2347
	/*
2348 2349 2350
	 * Hack: In case of kdump, after a crash, kernel might be booting
	 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
	 * might be zero if read from MP tables. Get it from LAPIC.
2351
	 */
2352 2353 2354 2355 2356
# ifdef CONFIG_CRASH_DUMP
	boot_cpu_physical_apicid = read_apic_id();
# endif
#endif
	physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
2357 2358 2359 2360
}

/**
 * apic_bsp_setup - Setup function for local apic and io-apic
2361
 * @upmode:		Force UP mode (for APIC_init_uniprocessor)
2362 2363 2364 2365
 *
 * Returns:
 * apic_id of BSP APIC
 */
2366
int __init apic_bsp_setup(bool upmode)
2367 2368 2369 2370
{
	int id;

	connect_bsp_APIC();
2371 2372
	if (upmode)
		apic_bsp_up_setup();
2373 2374 2375 2376 2377 2378 2379 2380
	setup_local_APIC();

	if (x2apic_mode)
		id = apic_read(APIC_LDR);
	else
		id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));

	enable_IO_APIC();
2381 2382
	end_local_APIC_setup();
	irq_remap_enable_fault_handling();
2383
	setup_IO_APIC();
2384 2385
	/* Setup local timer */
	x86_init.timers.setup_percpu_clockev();
2386 2387 2388
	return id;
}

2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399
/*
 * This initializes the IO-APIC and APIC hardware if this is
 * a UP kernel.
 */
int __init APIC_init_uniprocessor(void)
{
	if (disable_apic) {
		pr_info("Apic disabled\n");
		return -1;
	}
#ifdef CONFIG_X86_64
2400
	if (!boot_cpu_has(X86_FEATURE_APIC)) {
2401 2402 2403 2404 2405
		disable_apic = 1;
		pr_info("Apic disabled by BIOS\n");
		return -1;
	}
#else
2406
	if (!smp_found_config && !boot_cpu_has(X86_FEATURE_APIC))
2407 2408 2409 2410 2411
		return -1;

	/*
	 * Complain if the BIOS pretends there is one.
	 */
2412
	if (!boot_cpu_has(X86_FEATURE_APIC) &&
2413
	    APIC_INTEGRATED(boot_cpu_apic_version)) {
2414 2415 2416 2417 2418 2419
		pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
			boot_cpu_physical_apicid);
		return -1;
	}
#endif

2420 2421
	if (!smp_found_config)
		disable_ioapic_support();
2422

2423 2424
	default_setup_apic_routing();
	apic_bsp_setup(true);
2425 2426 2427
	return 0;
}

T
Thomas Gleixner 已提交
2428 2429 2430 2431 2432 2433 2434
#ifdef CONFIG_UP_LATE_INIT
void __init up_late_init(void)
{
	APIC_init_uniprocessor();
}
#endif

2435
/*
2436
 * Power management
2437
 */
2438 2439 2440
#ifdef CONFIG_PM

static struct {
2441 2442 2443 2444 2445
	/*
	 * 'active' is true if the local APIC was enabled by us and
	 * not the BIOS; this signifies that we are also responsible
	 * for disabling it before entering apm/acpi suspend
	 */
2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460
	int active;
	/* r/w apic fields */
	unsigned int apic_id;
	unsigned int apic_taskpri;
	unsigned int apic_ldr;
	unsigned int apic_dfr;
	unsigned int apic_spiv;
	unsigned int apic_lvtt;
	unsigned int apic_lvtpc;
	unsigned int apic_lvt0;
	unsigned int apic_lvt1;
	unsigned int apic_lvterr;
	unsigned int apic_tmict;
	unsigned int apic_tdcr;
	unsigned int apic_thmr;
2461
	unsigned int apic_cmci;
2462 2463
} apic_pm_state;

2464
static int lapic_suspend(void)
2465 2466 2467
{
	unsigned long flags;
	int maxlvt;
2468

2469 2470
	if (!apic_pm_state.active)
		return 0;
2471

2472
	maxlvt = lapic_get_maxlvt();
2473

2474
	apic_pm_state.apic_id = apic_read(APIC_ID);
2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486
	apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
	apic_pm_state.apic_ldr = apic_read(APIC_LDR);
	apic_pm_state.apic_dfr = apic_read(APIC_DFR);
	apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
	apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
	if (maxlvt >= 4)
		apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
	apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
	apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
	apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
	apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
	apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2487
#ifdef CONFIG_X86_THERMAL_VECTOR
2488 2489 2490
	if (maxlvt >= 5)
		apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
#endif
2491 2492 2493 2494
#ifdef CONFIG_X86_MCE_INTEL
	if (maxlvt >= 6)
		apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI);
#endif
2495

2496 2497
	local_irq_save(flags);
	disable_local_APIC();
2498

2499
	irq_remapping_disable();
2500

2501 2502
	local_irq_restore(flags);
	return 0;
L
Linus Torvalds 已提交
2503 2504
}

2505
static void lapic_resume(void)
L
Linus Torvalds 已提交
2506
{
2507 2508
	unsigned int l, h;
	unsigned long flags;
2509
	int maxlvt;
2510

2511
	if (!apic_pm_state.active)
2512
		return;
2513

2514
	local_irq_save(flags);
2515 2516 2517 2518 2519 2520 2521 2522 2523

	/*
	 * IO-APIC and PIC have their own resume routines.
	 * We just mask them here to make sure the interrupt
	 * subsystem is completely quiet while we enable x2apic
	 * and interrupt-remapping.
	 */
	mask_ioapic_entries();
	legacy_pic->mask_all();
C
Cyrill Gorcunov 已提交
2524

2525 2526 2527
	if (x2apic_mode) {
		__x2apic_enable();
	} else {
C
Cyrill Gorcunov 已提交
2528 2529 2530 2531 2532 2533
		/*
		 * Make sure the APICBASE points to the right address
		 *
		 * FIXME! This will be wrong if we ever support suspend on
		 * SMP! We'll need to do this as part of the CPU restore!
		 */
2534 2535 2536 2537 2538 2539
		if (boot_cpu_data.x86 >= 6) {
			rdmsr(MSR_IA32_APICBASE, l, h);
			l &= ~MSR_IA32_APICBASE_BASE;
			l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
			wrmsr(MSR_IA32_APICBASE, l, h);
		}
2540
	}
2541

2542
	maxlvt = lapic_get_maxlvt();
2543 2544 2545 2546 2547 2548 2549 2550
	apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
	apic_write(APIC_ID, apic_pm_state.apic_id);
	apic_write(APIC_DFR, apic_pm_state.apic_dfr);
	apic_write(APIC_LDR, apic_pm_state.apic_ldr);
	apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
	apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
	apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
	apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2551
#ifdef CONFIG_X86_THERMAL_VECTOR
2552 2553
	if (maxlvt >= 5)
		apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2554 2555 2556 2557
#endif
#ifdef CONFIG_X86_MCE_INTEL
	if (maxlvt >= 6)
		apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci);
2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568
#endif
	if (maxlvt >= 4)
		apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
	apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
	apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
	apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
	apic_write(APIC_ESR, 0);
	apic_read(APIC_ESR);
	apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
	apic_write(APIC_ESR, 0);
	apic_read(APIC_ESR);
C
Cyrill Gorcunov 已提交
2569

2570
	irq_remapping_reenable(x2apic_mode);
2571

2572 2573
	local_irq_restore(flags);
}
T
Thomas Gleixner 已提交
2574

2575 2576 2577 2578 2579
/*
 * This device has no shutdown method - fully functioning local APICs
 * are needed on every CPU up until machine_halt/restart/poweroff.
 */

2580
static struct syscore_ops lapic_syscore_ops = {
2581 2582 2583
	.resume		= lapic_resume,
	.suspend	= lapic_suspend,
};
T
Thomas Gleixner 已提交
2584

2585
static void apic_pm_activate(void)
2586 2587
{
	apic_pm_state.active = 1;
L
Linus Torvalds 已提交
2588 2589
}

2590
static int __init init_lapic_sysfs(void)
L
Linus Torvalds 已提交
2591
{
2592
	/* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2593
	if (boot_cpu_has(X86_FEATURE_APIC))
2594
		register_syscore_ops(&lapic_syscore_ops);
H
Hiroshi Shimamoto 已提交
2595

2596
	return 0;
L
Linus Torvalds 已提交
2597
}
2598 2599 2600

/* local apic needs to resume before other devices access its registers. */
core_initcall(init_lapic_sysfs);
2601 2602 2603 2604 2605 2606

#else	/* CONFIG_PM */

static void apic_pm_activate(void) { }

#endif	/* CONFIG_PM */
L
Linus Torvalds 已提交
2607

Y
Yinghai Lu 已提交
2608
#ifdef CONFIG_X86_64
2609

2610 2611
static int multi_checked;
static int multi;
2612

2613
static int set_multi(const struct dmi_system_id *d)
2614 2615 2616
{
	if (multi)
		return 0;
C
Cyrill Gorcunov 已提交
2617
	pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2618 2619 2620 2621
	multi = 1;
	return 0;
}

2622
static const struct dmi_system_id multi_dmi_table[] = {
2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633
	{
		.callback = set_multi,
		.ident = "IBM System Summit2",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
		},
	},
	{}
};

2634
static void dmi_check_multi(void)
2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650
{
	if (multi_checked)
		return;

	dmi_check_system(multi_dmi_table);
	multi_checked = 1;
}

/*
 * apic_is_clustered_box() -- Check if we can expect good TSC
 *
 * Thus far, the major user of this is IBM's Summit2 series:
 * Clustered boxes may have unsynced TSC problems if they are
 * multi-chassis.
 * Use DMI to check them
 */
2651
int apic_is_clustered_box(void)
2652 2653
{
	dmi_check_multi();
2654
	return multi;
L
Linus Torvalds 已提交
2655
}
Y
Yinghai Lu 已提交
2656
#endif
L
Linus Torvalds 已提交
2657 2658

/*
2659
 * APIC command line parameters
L
Linus Torvalds 已提交
2660
 */
2661
static int __init setup_disableapic(char *arg)
2662
{
L
Linus Torvalds 已提交
2663
	disable_apic = 1;
2664
	setup_clear_cpu_cap(X86_FEATURE_APIC);
2665 2666 2667
	return 0;
}
early_param("disableapic", setup_disableapic);
L
Linus Torvalds 已提交
2668

2669
/* same as disableapic, for compatibility */
2670
static int __init setup_nolapic(char *arg)
2671
{
2672
	return setup_disableapic(arg);
2673
}
2674
early_param("nolapic", setup_nolapic);
L
Linus Torvalds 已提交
2675

2676 2677 2678 2679 2680 2681 2682
static int __init parse_lapic_timer_c2_ok(char *arg)
{
	local_apic_timer_c2_ok = 1;
	return 0;
}
early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);

2683
static int __init parse_disable_apic_timer(char *arg)
2684
{
L
Linus Torvalds 已提交
2685
	disable_apic_timer = 1;
2686
	return 0;
2687
}
2688 2689 2690 2691 2692 2693
early_param("noapictimer", parse_disable_apic_timer);

static int __init parse_nolapic_timer(char *arg)
{
	disable_apic_timer = 1;
	return 0;
2694
}
2695
early_param("nolapic_timer", parse_nolapic_timer);
2696

2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711
static int __init apic_set_verbosity(char *arg)
{
	if (!arg)  {
#ifdef CONFIG_X86_64
		skip_ioapic_setup = 0;
		return 0;
#endif
		return -EINVAL;
	}

	if (strcmp("debug", arg) == 0)
		apic_verbosity = APIC_DEBUG;
	else if (strcmp("verbose", arg) == 0)
		apic_verbosity = APIC_VERBOSE;
	else {
2712
		pr_warning("APIC Verbosity level %s not recognised"
2713 2714 2715 2716 2717 2718 2719 2720
			" use apic=verbose or apic=debug\n", arg);
		return -EINVAL;
	}

	return 0;
}
early_param("apic", apic_set_verbosity);

2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734
static int __init lapic_insert_resource(void)
{
	if (!apic_phys)
		return -1;

	/* Put local APIC into the resource map. */
	lapic_resource.start = apic_phys;
	lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
	insert_resource(&iomem_resource, &lapic_resource);

	return 0;
}

/*
2735
 * need call insert after e820__reserve_resources()
2736 2737 2738
 * that is using request_resource
 */
late_initcall(lapic_insert_resource);
2739 2740 2741 2742 2743 2744 2745 2746 2747

static int __init apic_set_disabled_cpu_apicid(char *arg)
{
	if (!arg || !get_option(&arg, &disabled_cpu_apicid))
		return -EINVAL;

	return 0;
}
early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid);
2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767

static int __init apic_set_extnmi(char *arg)
{
	if (!arg)
		return -EINVAL;

	if (!strncmp("all", arg, 3))
		apic_extnmi = APIC_EXTNMI_ALL;
	else if (!strncmp("none", arg, 4))
		apic_extnmi = APIC_EXTNMI_NONE;
	else if (!strncmp("bsp", arg, 3))
		apic_extnmi = APIC_EXTNMI_BSP;
	else {
		pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg);
		return -EINVAL;
	}

	return 0;
}
early_param("apic_extnmi", apic_set_extnmi);