apic.c 64.8 KB
Newer Older
L
Linus Torvalds 已提交
1 2 3
/*
 *	Local APIC handling, local APIC timers
 *
I
Ingo Molnar 已提交
4
 *	(c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
L
Linus Torvalds 已提交
5 6 7 8 9 10 11 12 13 14 15 16
 *
 *	Fixes
 *	Maciej W. Rozycki	:	Bits for genuine 82489DX APICs;
 *					thanks to Eric Gilmore
 *					and Rolf G. Tews
 *					for testing these extensively.
 *	Maciej W. Rozycki	:	Various updates and fixes.
 *	Mikael Pettersson	:	Power Management for UP-APIC.
 *	Pavel Machek and
 *	Mikael Pettersson	:	PM converted to driver model.
 */

17
#include <linux/perf_event.h>
L
Linus Torvalds 已提交
18
#include <linux/kernel_stat.h>
I
Ingo Molnar 已提交
19
#include <linux/mc146818rtc.h>
20
#include <linux/acpi_pmtmr.h>
I
Ingo Molnar 已提交
21 22 23 24 25
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/bootmem.h>
#include <linux/ftrace.h>
#include <linux/ioport.h>
26
#include <linux/export.h>
27
#include <linux/syscore_ops.h>
I
Ingo Molnar 已提交
28 29
#include <linux/delay.h>
#include <linux/timex.h>
30
#include <linux/i8253.h>
31
#include <linux/dmar.h>
I
Ingo Molnar 已提交
32 33 34 35 36
#include <linux/init.h>
#include <linux/cpu.h>
#include <linux/dmi.h>
#include <linux/smp.h>
#include <linux/mm.h>
L
Linus Torvalds 已提交
37

38
#include <asm/trace/irq_vectors.h>
39
#include <asm/irq_remapping.h>
40
#include <asm/perf_event.h>
41
#include <asm/x86_init.h>
L
Linus Torvalds 已提交
42
#include <asm/pgalloc.h>
A
Arun Sharma 已提交
43
#include <linux/atomic.h>
L
Linus Torvalds 已提交
44
#include <asm/mpspec.h>
I
Ingo Molnar 已提交
45
#include <asm/i8259.h>
46
#include <asm/proto.h>
47
#include <asm/apic.h>
48
#include <asm/io_apic.h>
I
Ingo Molnar 已提交
49 50 51
#include <asm/desc.h>
#include <asm/hpet.h>
#include <asm/mtrr.h>
52
#include <asm/time.h>
53
#include <asm/smp.h>
54
#include <asm/mce.h>
55
#include <asm/tsc.h>
56
#include <asm/hypervisor.h>
L
Linus Torvalds 已提交
57

B
Brian Gerst 已提交
58
unsigned int num_processors;
59

60
unsigned disabled_cpus;
61

B
Brian Gerst 已提交
62 63
/* Processor that is doing the boot up */
unsigned int boot_cpu_physical_apicid = -1U;
64
EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
65

66 67
u8 boot_cpu_apic_version;

68
/*
69
 * The highest APIC ID seen during enumeration.
70
 */
71
static unsigned int max_physical_apicid;
72

73
/*
74
 * Bitmask of physically existing CPUs:
75
 */
B
Brian Gerst 已提交
76 77
physid_mask_t phys_cpu_present_map;

78 79 80 81 82
/*
 * Processor to be disabled specified by kernel parameter
 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
 * avoid undefined behaviour caused by sending INIT from AP to BSP.
 */
83
static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID;
84

85 86 87 88 89 90
/*
 * This variable controls which CPUs receive external NMIs.  By default,
 * external NMIs are delivered only to the BSP.
 */
static int apic_extnmi = APIC_EXTNMI_BSP;

B
Brian Gerst 已提交
91 92 93
/*
 * Map cpu index to physical APIC ID
 */
94 95
DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
96
DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX);
B
Brian Gerst 已提交
97 98
EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
99
EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid);
100

Y
Yinghai Lu 已提交
101
#ifdef CONFIG_X86_32
102 103 104 105 106 107 108

/*
 * On x86_32, the mapping between cpu and logical apicid may vary
 * depending on apic in use.  The following early percpu variable is
 * used for the mapping.  This is where the behaviors of x86_64 and 32
 * actually diverge.  Let's keep it ugly for now.
 */
109
DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
110

Y
Yinghai Lu 已提交
111 112 113
/* Local APIC was disabled by the BIOS and enabled by the kernel */
static int enabled_via_apicbase;

114 115 116 117 118 119 120 121
/*
 * Handle interrupt mode configuration register (IMCR).
 * This register controls whether the interrupt signals
 * that reach the BSP come from the master PIC or from the
 * local APIC. Before entering Symmetric I/O Mode, either
 * the BIOS or the operating system must switch out of
 * PIC Mode by changing the IMCR.
 */
122
static inline void imcr_pic_to_apic(void)
123 124 125 126 127 128 129
{
	/* select IMCR register */
	outb(0x70, 0x22);
	/* NMI and 8259 INTR go through APIC */
	outb(0x01, 0x23);
}

130
static inline void imcr_apic_to_pic(void)
131 132 133 134 135 136
{
	/* select IMCR register */
	outb(0x70, 0x22);
	/* NMI and 8259 INTR go directly to BSP */
	outb(0x00, 0x23);
}
Y
Yinghai Lu 已提交
137 138
#endif

139 140 141 142 143 144
/*
 * Knob to control our willingness to enable the local APIC.
 *
 * +1=force-enable
 */
static int force_enable_local_apic __initdata;
145

146 147 148 149 150
/*
 * APIC command line parameters
 */
static int __init parse_lapic(char *arg)
{
151
	if (IS_ENABLED(CONFIG_X86_32) && !arg)
152
		force_enable_local_apic = 1;
153
	else if (arg && !strncmp(arg, "notscdeadline", 13))
154 155 156 157 158
		setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
	return 0;
}
early_param("lapic", parse_lapic);

Y
Yinghai Lu 已提交
159
#ifdef CONFIG_X86_64
160
static int apic_calibrate_pmtmr __initdata;
Y
Yinghai Lu 已提交
161 162 163 164 165 166 167 168 169 170 171 172
static __init int setup_apicpmtimer(char *s)
{
	apic_calibrate_pmtmr = 1;
	notsc_setup(NULL);
	return 0;
}
__setup("apicpmtimer", setup_apicpmtimer);
#endif

unsigned long mp_lapic_addr;
int disable_apic;
/* Disable local APIC timer from the kernel commandline or via dmi quirk */
173
static int disable_apic_timer __initdata;
H
Hiroshi Shimamoto 已提交
174
/* Local APIC timer works in C2 */
175 176 177
int local_apic_timer_c2_ok;
EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);

178
int first_system_vector = FIRST_SYSTEM_VECTOR;
Y
Yinghai Lu 已提交
179

H
Hiroshi Shimamoto 已提交
180 181 182
/*
 * Debug level, exported for io_apic.c
 */
183
unsigned int apic_verbosity;
H
Hiroshi Shimamoto 已提交
184

185 186
int pic_mode;

A
Alexey Starikovskiy 已提交
187 188 189
/* Have we found an MP table */
int smp_found_config;

190 191 192 193 194
static struct resource lapic_resource = {
	.name = "Local APIC",
	.flags = IORESOURCE_MEM | IORESOURCE_BUSY,
};

195
unsigned int lapic_timer_frequency = 0;
196

197
static void apic_pm_activate(void);
198

199 200
static unsigned long apic_phys;

201 202 203 204
/*
 * Get the LAPIC version
 */
static inline int lapic_get_version(void)
205
{
206
	return GET_APIC_VERSION(apic_read(APIC_LVR));
207 208
}

209
/*
210
 * Check, if the APIC is integrated or a separate chip
211 212
 */
static inline int lapic_is_integrated(void)
213
{
214
#ifdef CONFIG_X86_64
215
	return 1;
216 217 218
#else
	return APIC_INTEGRATED(lapic_get_version());
#endif
219 220 221
}

/*
222
 * Check, whether this is a modern or a first generation APIC
223
 */
224
static int modern_apic(void)
225
{
226 227 228 229 230
	/* AMD systems use old APIC versions, so check the CPU */
	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
	    boot_cpu_data.x86 >= 0xf)
		return 1;
	return lapic_get_version() >= 0x14;
231 232
}

233
/*
C
Cyrill Gorcunov 已提交
234 235
 * right after this call apic become NOOP driven
 * so apic->write/read doesn't do anything
236
 */
237
static void __init apic_disable(void)
238
{
239
	pr_info("APIC: switched to apic NOOP\n");
C
Cyrill Gorcunov 已提交
240
	apic = &apic_noop;
241 242
}

Y
Yinghai Lu 已提交
243
void native_apic_wait_icr_idle(void)
244 245 246 247 248
{
	while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
		cpu_relax();
}

Y
Yinghai Lu 已提交
249
u32 native_safe_apic_wait_icr_idle(void)
250
{
251
	u32 send_status;
252 253 254 255 256 257 258
	int timeout;

	timeout = 0;
	do {
		send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
		if (!send_status)
			break;
259
		inc_irq_stat(icr_read_retry_count);
260 261 262 263 264 265
		udelay(100);
	} while (timeout++ < 1000);

	return send_status;
}

Y
Yinghai Lu 已提交
266
void native_apic_icr_write(u32 low, u32 id)
267
{
268 269 270
	unsigned long flags;

	local_irq_save(flags);
271
	apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
272
	apic_write(APIC_ICR, low);
273
	local_irq_restore(flags);
274 275
}

Y
Yinghai Lu 已提交
276
u64 native_apic_icr_read(void)
277 278 279 280 281 282
{
	u32 icr1, icr2;

	icr2 = apic_read(APIC_ICR2);
	icr1 = apic_read(APIC_ICR);

283
	return icr1 | ((u64)icr2 << 32);
284 285
}

286 287 288 289 290 291 292 293 294 295
#ifdef CONFIG_X86_32
/**
 * get_physical_broadcast - Get number of physical broadcast IDs
 */
int get_physical_broadcast(void)
{
	return modern_apic() ? 0xff : 0xf;
}
#endif

296 297 298
/**
 * lapic_get_maxlvt - get the maximum number of local vector table entries
 */
299
int lapic_get_maxlvt(void)
L
Linus Torvalds 已提交
300
{
301
	unsigned int v;
L
Linus Torvalds 已提交
302 303

	v = apic_read(APIC_LVR);
304 305 306 307 308
	/*
	 * - we always have APIC integrated on 64bit mode
	 * - 82489DXs do not report # of LVT entries
	 */
	return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
L
Linus Torvalds 已提交
309 310
}

311 312 313 314
/*
 * Local APIC timer
 */

315 316
/* Clock divisor */
#define APIC_DIVISOR 16
317
#define TSC_DIVISOR  8
318

319 320 321 322 323 324 325 326 327 328 329
/*
 * This function sets up the local APIC timer, with a timeout of
 * 'clocks' APIC bus clock. During calibration we actually call
 * this function twice on the boot CPU, once with a bogus timeout
 * value, second time for real. The other (noncalibrating) CPUs
 * call this function only once, with the real, calibrated value.
 *
 * We do reads before writes even if unnecessary, to get around the
 * P5 APIC double write bug.
 */
static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
L
Linus Torvalds 已提交
330
{
331
	unsigned int lvtt_value, tmp_value;
L
Linus Torvalds 已提交
332

333 334 335
	lvtt_value = LOCAL_TIMER_VECTOR;
	if (!oneshot)
		lvtt_value |= APIC_LVT_TIMER_PERIODIC;
336 337 338
	else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
		lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;

339 340 341
	if (!lapic_is_integrated())
		lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);

342 343
	if (!irqen)
		lvtt_value |= APIC_LVT_MASKED;
L
Linus Torvalds 已提交
344

345
	apic_write(APIC_LVTT, lvtt_value);
L
Linus Torvalds 已提交
346

347
	if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
348 349 350 351 352 353 354
		/*
		 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
		 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
		 * According to Intel, MFENCE can do the serialization here.
		 */
		asm volatile("mfence" : : : "memory");

355 356 357 358
		printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
		return;
	}

L
Linus Torvalds 已提交
359
	/*
360
	 * Divide PICLK by 16
L
Linus Torvalds 已提交
361
	 */
362
	tmp_value = apic_read(APIC_TDCR);
363 364 365
	apic_write(APIC_TDCR,
		(tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
		APIC_TDR_DIV_16);
366 367

	if (!oneshot)
368
		apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
L
Linus Torvalds 已提交
369 370
}

371
/*
372
 * Setup extended LVT, AMD specific
373
 *
374 375 376 377 378
 * Software should use the LVT offsets the BIOS provides.  The offsets
 * are determined by the subsystems using it like those for MCE
 * threshold or IBS.  On K8 only offset 0 (APIC500) and MCE interrupts
 * are supported. Beginning with family 10h at least 4 offsets are
 * available.
379
 *
380 381 382 383 384 385 386 387 388
 * Since the offsets must be consistent for all cores, we keep track
 * of the LVT offsets in software and reserve the offset for the same
 * vector also to be used on other cores. An offset is freed by
 * setting the entry to APIC_EILVT_MASKED.
 *
 * If the BIOS is right, there should be no conflicts. Otherwise a
 * "[Firmware Bug]: ..." error message is generated. However, if
 * software does not properly determines the offsets, it is not
 * necessarily a BIOS bug.
389
 */
390

391 392 393 394 395 396 397 398 399 400 401
static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];

static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
{
	return (old & APIC_EILVT_MASKED)
		|| (new == APIC_EILVT_MASKED)
		|| ((new & ~APIC_EILVT_MASKED) == old);
}

static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
{
402
	unsigned int rsvd, vector;
403 404 405 406

	if (offset >= APIC_EILVT_NR_MAX)
		return ~0;

407
	rsvd = atomic_read(&eilvt_offsets[offset]);
408
	do {
409 410
		vector = rsvd & ~APIC_EILVT_MASKED;	/* 0: unassigned */
		if (vector && !eilvt_entry_is_changeable(vector, new))
411 412 413 414 415
			/* may not change if vectors are different */
			return rsvd;
		rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
	} while (rsvd != new);

416 417 418 419 420
	rsvd &= ~APIC_EILVT_MASKED;
	if (rsvd && rsvd != vector)
		pr_info("LVT offset %d assigned for vector 0x%02x\n",
			offset, rsvd);

421 422 423 424 425
	return new;
}

/*
 * If mask=1, the LVT entry does not generate interrupts while mask=0
426 427
 * enables the vector. See also the BKDGs. Must be called with
 * preemption disabled.
428 429
 */

430
int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
L
Linus Torvalds 已提交
431
{
432 433 434 435 436 437 438 439
	unsigned long reg = APIC_EILVTn(offset);
	unsigned int new, old, reserved;

	new = (mask << 16) | (msg_type << 8) | vector;
	old = apic_read(reg);
	reserved = reserve_eilvt_offset(offset, new);

	if (reserved != new) {
440 441 442 443
		pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
		       "vector 0x%x, but the register is already in use for "
		       "vector 0x%x on another cpu\n",
		       smp_processor_id(), reg, offset, new, reserved);
444 445 446 447
		return -EINVAL;
	}

	if (!eilvt_entry_is_changeable(old, new)) {
448 449 450 451
		pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
		       "vector 0x%x, but the register is already in use for "
		       "vector 0x%x on this cpu\n",
		       smp_processor_id(), reg, offset, new, old);
452 453 454 455
		return -EBUSY;
	}

	apic_write(reg, new);
A
Andi Kleen 已提交
456

457
	return 0;
L
Linus Torvalds 已提交
458
}
459
EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
460

461 462 463 464 465
/*
 * Program the next event, relative to now
 */
static int lapic_next_event(unsigned long delta,
			    struct clock_event_device *evt)
L
Linus Torvalds 已提交
466
{
467 468
	apic_write(APIC_TMICT, delta);
	return 0;
L
Linus Torvalds 已提交
469 470
}

471 472 473 474 475
static int lapic_next_deadline(unsigned long delta,
			       struct clock_event_device *evt)
{
	u64 tsc;

476
	tsc = rdtsc();
477 478 479 480
	wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
	return 0;
}

481
static int lapic_timer_shutdown(struct clock_event_device *evt)
482
{
483
	unsigned int v;
484

485 486
	/* Lapic used as dummy for broadcast ? */
	if (evt->features & CLOCK_EVT_FEAT_DUMMY)
487
		return 0;
488

489 490 491 492 493 494
	v = apic_read(APIC_LVTT);
	v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
	apic_write(APIC_LVTT, v);
	apic_write(APIC_TMICT, 0);
	return 0;
}
495

496 497 498 499 500 501
static inline int
lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot)
{
	/* Lapic used as dummy for broadcast ? */
	if (evt->features & CLOCK_EVT_FEAT_DUMMY)
		return 0;
502

503 504 505 506 507 508 509 510 511 512 513 514
	__setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1);
	return 0;
}

static int lapic_timer_set_periodic(struct clock_event_device *evt)
{
	return lapic_timer_set_periodic_oneshot(evt, false);
}

static int lapic_timer_set_oneshot(struct clock_event_device *evt)
{
	return lapic_timer_set_periodic_oneshot(evt, true);
515 516
}

L
Linus Torvalds 已提交
517
/*
518
 * Local APIC timer broadcast function
L
Linus Torvalds 已提交
519
 */
520
static void lapic_timer_broadcast(const struct cpumask *mask)
L
Linus Torvalds 已提交
521
{
522
#ifdef CONFIG_SMP
523
	apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
524 525
#endif
}
L
Linus Torvalds 已提交
526

527 528 529 530 531

/*
 * The local apic timer can be used for any function which is CPU local.
 */
static struct clock_event_device lapic_clockevent = {
532 533 534 535 536 537 538 539 540 541 542 543
	.name			= "lapic",
	.features		= CLOCK_EVT_FEAT_PERIODIC |
				  CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP
				  | CLOCK_EVT_FEAT_DUMMY,
	.shift			= 32,
	.set_state_shutdown	= lapic_timer_shutdown,
	.set_state_periodic	= lapic_timer_set_periodic,
	.set_state_oneshot	= lapic_timer_set_oneshot,
	.set_next_event		= lapic_next_event,
	.broadcast		= lapic_timer_broadcast,
	.rating			= 100,
	.irq			= -1,
544 545 546
};
static DEFINE_PER_CPU(struct clock_event_device, lapic_events);

547
/*
548
 * Setup the local APIC timer for this CPU. Copy the initialized values
549 550
 * of the boot CPU and register the clock event in the framework.
 */
551
static void setup_APIC_timer(void)
552
{
553
	struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
L
Linus Torvalds 已提交
554

555
	if (this_cpu_has(X86_FEATURE_ARAT)) {
556 557 558 559 560
		lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
		/* Make LAPIC timer preferrable over percpu HPET */
		lapic_clockevent.rating = 150;
	}

561
	memcpy(levt, &lapic_clockevent, sizeof(*levt));
562
	levt->cpumask = cpumask_of(smp_processor_id());
L
Linus Torvalds 已提交
563

564 565 566 567 568
	if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
		levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
				    CLOCK_EVT_FEAT_DUMMY);
		levt->set_next_event = lapic_next_deadline;
		clockevents_config_and_register(levt,
569
						tsc_khz * (1000 / TSC_DIVISOR),
570 571 572
						0xF, ~0UL);
	} else
		clockevents_register_device(levt);
573
}
L
Linus Torvalds 已提交
574

575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598
/*
 * Install the updated TSC frequency from recalibration at the TSC
 * deadline clockevent devices.
 */
static void __lapic_update_tsc_freq(void *info)
{
	struct clock_event_device *levt = this_cpu_ptr(&lapic_events);

	if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
		return;

	clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR));
}

void lapic_update_tsc_freq(void)
{
	/*
	 * The clockevent device's ->mult and ->shift can both be
	 * changed. In order to avoid races, schedule the frequency
	 * update code on each CPU.
	 */
	on_each_cpu(__lapic_update_tsc_freq, NULL, 0);
}

599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636
/*
 * In this functions we calibrate APIC bus clocks to the external timer.
 *
 * We want to do the calibration only once since we want to have local timer
 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
 * frequency.
 *
 * This was previously done by reading the PIT/HPET and waiting for a wrap
 * around to find out, that a tick has elapsed. I have a box, where the PIT
 * readout is broken, so it never gets out of the wait loop again. This was
 * also reported by others.
 *
 * Monitoring the jiffies value is inaccurate and the clockevents
 * infrastructure allows us to do a simple substitution of the interrupt
 * handler.
 *
 * The calibration routine also uses the pm_timer when possible, as the PIT
 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
 * back to normal later in the boot process).
 */

#define LAPIC_CAL_LOOPS		(HZ/10)

static __initdata int lapic_cal_loops = -1;
static __initdata long lapic_cal_t1, lapic_cal_t2;
static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;

/*
 * Temporary interrupt handler.
 */
static void __init lapic_cal_handler(struct clock_event_device *dev)
{
	unsigned long long tsc = 0;
	long tapic = apic_read(APIC_TMCCT);
	unsigned long pm = acpi_pm_read_early();

637
	if (boot_cpu_has(X86_FEATURE_TSC))
638
		tsc = rdtsc();
639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658

	switch (lapic_cal_loops++) {
	case 0:
		lapic_cal_t1 = tapic;
		lapic_cal_tsc1 = tsc;
		lapic_cal_pm1 = pm;
		lapic_cal_j1 = jiffies;
		break;

	case LAPIC_CAL_LOOPS:
		lapic_cal_t2 = tapic;
		lapic_cal_tsc2 = tsc;
		if (pm < lapic_cal_pm1)
			pm += ACPI_PM_OVRRUN;
		lapic_cal_pm2 = pm;
		lapic_cal_j2 = jiffies;
		break;
	}
}

659 660
static int __init
calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
661 662 663 664 665 666 667 668 669 670
{
	const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
	const long pm_thresh = pm_100ms / 100;
	unsigned long mult;
	u64 res;

#ifndef CONFIG_X86_PM_TIMER
	return -1;
#endif

Y
Yasuaki Ishimatsu 已提交
671
	apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
672 673 674 675 676 677 678 679 680

	/* Check, if the PM timer is available */
	if (!deltapm)
		return -1;

	mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);

	if (deltapm > (pm_100ms - pm_thresh) &&
	    deltapm < (pm_100ms + pm_thresh)) {
Y
Yasuaki Ishimatsu 已提交
681
		apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
682 683 684 685 686 687
		return 0;
	}

	res = (((u64)deltapm) *  mult) >> 22;
	do_div(res, 1000000);
	pr_warning("APIC calibration not consistent "
Y
Yasuaki Ishimatsu 已提交
688
		   "with PM-Timer: %ldms instead of 100ms\n",(long)res);
689 690 691 692 693 694 695 696 697

	/* Correct the lapic counter value */
	res = (((u64)(*delta)) * pm_100ms);
	do_div(res, deltapm);
	pr_info("APIC delta adjusted to PM-Timer: "
		"%lu (%ld)\n", (unsigned long)res, *delta);
	*delta = (long)res;

	/* Correct the tsc counter value */
698
	if (boot_cpu_has(X86_FEATURE_TSC)) {
699
		res = (((u64)(*deltatsc)) * pm_100ms);
700
		do_div(res, deltapm);
701
		apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
702
					  "PM-Timer: %lu (%ld)\n",
703 704
					(unsigned long)res, *deltatsc);
		*deltatsc = (long)res;
705 706 707 708 709
	}

	return 0;
}

710 711
static int __init calibrate_APIC_clock(void)
{
712
	struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
713 714
	void (*real_handler)(struct clock_event_device *dev);
	unsigned long deltaj;
715
	long delta, deltatsc;
716 717
	int pm_referenced = 0;

718 719 720 721 722 723
	/**
	 * check if lapic timer has already been calibrated by platform
	 * specific routine, such as tsc calibration code. if so, we just fill
	 * in the clockevent structure and return.
	 */

724 725 726
	if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
		return 0;
	} else if (lapic_timer_frequency) {
727 728 729 730 731 732 733 734 735 736 737 738
		apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
				lapic_timer_frequency);
		lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
					TICK_NSEC, lapic_clockevent.shift);
		lapic_clockevent.max_delta_ns =
			clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
		lapic_clockevent.min_delta_ns =
			clockevent_delta2ns(0xF, &lapic_clockevent);
		lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
		return 0;
	}

739 740 741
	apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
		    "calibrating APIC timer ...\n");

742 743 744 745 746 747 748
	local_irq_disable();

	/* Replace the global interrupt handler */
	real_handler = global_clock_event->event_handler;
	global_clock_event->event_handler = lapic_cal_handler;

	/*
C
Cyrill Gorcunov 已提交
749
	 * Setup the APIC counter to maximum. There is no way the lapic
750 751
	 * can underflow in the 100ms detection time frame
	 */
C
Cyrill Gorcunov 已提交
752
	__setup_APIC_LVTT(0xffffffff, 0, 0);
753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768

	/* Let the interrupts run */
	local_irq_enable();

	while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
		cpu_relax();

	local_irq_disable();

	/* Restore the real event handler */
	global_clock_event->event_handler = real_handler;

	/* Build delta t1-t2 as apic timer counts down */
	delta = lapic_cal_t1 - lapic_cal_t2;
	apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);

769 770
	deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);

771 772
	/* we trust the PM based calibration if possible */
	pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
773
					&delta, &deltatsc);
774 775 776 777 778

	/* Calculate the scaled math multiplication factor */
	lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
				       lapic_clockevent.shift);
	lapic_clockevent.max_delta_ns =
779
		clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
780 781 782
	lapic_clockevent.min_delta_ns =
		clockevent_delta2ns(0xF, &lapic_clockevent);

783
	lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
784 785

	apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
786
	apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
787
	apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
788
		    lapic_timer_frequency);
789

790
	if (boot_cpu_has(X86_FEATURE_TSC)) {
791 792
		apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
			    "%ld.%04ld MHz.\n",
793 794
			    (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
			    (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
795 796 797 798
	}

	apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
		    "%u.%04u MHz.\n",
799 800
		    lapic_timer_frequency / (1000000 / HZ),
		    lapic_timer_frequency % (1000000 / HZ));
801 802 803 804

	/*
	 * Do a sanity check on the APIC calibration result
	 */
805
	if (lapic_timer_frequency < (1000000 / HZ)) {
806
		local_irq_enable();
807
		pr_warning("APIC frequency too slow, disabling apic timer\n");
808 809 810 811 812
		return -1;
	}

	levt->features &= ~CLOCK_EVT_FEAT_DUMMY;

813 814 815 816
	/*
	 * PM timer calibration failed or not turned on
	 * so lets try APIC timer based calibration
	 */
817 818 819 820 821 822 823
	if (!pm_referenced) {
		apic_printk(APIC_VERBOSE, "... verify APIC timer\n");

		/*
		 * Setup the apic timer manually
		 */
		levt->event_handler = lapic_cal_handler;
824
		lapic_timer_set_periodic(levt);
825 826 827 828 829 830 831 832 833
		lapic_cal_loops = -1;

		/* Let the interrupts run */
		local_irq_enable();

		while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
			cpu_relax();

		/* Stop the lapic timer */
834
		local_irq_disable();
835
		lapic_timer_shutdown(levt);
836 837 838 839 840 841 842 843 844 845

		/* Jiffies delta */
		deltaj = lapic_cal_j2 - lapic_cal_j1;
		apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);

		/* Check, if the jiffies result is consistent */
		if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
			apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
		else
			levt->features |= CLOCK_EVT_FEAT_DUMMY;
846 847
	}
	local_irq_enable();
848 849

	if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
850
		pr_warning("APIC timer disabled due to verification failure\n");
851 852 853 854 855 856
			return -1;
	}

	return 0;
}

H
Hiroshi Shimamoto 已提交
857 858 859 860 861
/*
 * Setup the boot APIC
 *
 * Calibrate and verify the result.
 */
862 863 864
void __init setup_boot_APIC_clock(void)
{
	/*
865 866 867 868
	 * The local apic timer can be disabled via the kernel
	 * commandline or from the CPU detection code. Register the lapic
	 * timer as a dummy clock event source on SMP systems, so the
	 * broadcast mechanism is used. On UP systems simply ignore it.
869 870
	 */
	if (disable_apic_timer) {
871
		pr_info("Disabling APIC timer\n");
872
		/* No broadcast on UP ! */
873 874
		if (num_possible_cpus() > 1) {
			lapic_clockevent.mult = 1;
875
			setup_APIC_timer();
876
		}
877 878 879
		return;
	}

880
	if (calibrate_APIC_clock()) {
881 882 883 884 885 886
		/* No broadcast on UP ! */
		if (num_possible_cpus() > 1)
			setup_APIC_timer();
		return;
	}

887 888 889 890 891
	/*
	 * If nmi_watchdog is set to IO_APIC, we need the
	 * PIT/HPET going.  Otherwise register lapic as a dummy
	 * device.
	 */
892
	lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
893

894
	/* Setup the lapic or request the broadcast */
895
	setup_APIC_timer();
896
	amd_e400_c1e_apic_setup();
897 898
}

899
void setup_secondary_APIC_clock(void)
900 901
{
	setup_APIC_timer();
902
	amd_e400_c1e_apic_setup();
903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924
}

/*
 * The guts of the apic timer interrupt
 */
static void local_apic_timer_interrupt(void)
{
	int cpu = smp_processor_id();
	struct clock_event_device *evt = &per_cpu(lapic_events, cpu);

	/*
	 * Normally we should not be here till LAPIC has been initialized but
	 * in some cases like kdump, its possible that there is a pending LAPIC
	 * timer interrupt from previous kernel's context and is delivered in
	 * new kernel the moment interrupts are enabled.
	 *
	 * Interrupts are enabled early and LAPIC is setup much later, hence
	 * its possible that when we get here evt->event_handler is NULL.
	 * Check for event_handler being NULL and discard the interrupt as
	 * spurious.
	 */
	if (!evt->event_handler) {
925
		pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
926
		/* Switch it off */
927
		lapic_timer_shutdown(evt);
928 929 930 931 932 933
		return;
	}

	/*
	 * the NMI deadlock-detector uses this.
	 */
934
	inc_irq_stat(apic_timer_irqs);
935 936 937 938 939 940 941 942 943 944 945 946

	evt->event_handler(evt);
}

/*
 * Local APIC timer interrupt. This is the most natural way for doing
 * local interrupts, but local timer interrupts can be emulated by
 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
 *
 * [ if a single-CPU system runs an SMP kernel then we call the local
 *   interrupt as well. Thus we cannot inline the local irq ... ]
 */
947
__visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
948 949 950 951 952 953
{
	struct pt_regs *old_regs = set_irq_regs(regs);

	/*
	 * NOTE! We'd better ACK the irq immediately,
	 * because timer handling can be slow.
954
	 *
955 956 957 958
	 * update_process_times() expects us to have done irq_enter().
	 * Besides, if we don't timer interrupts ignore the global
	 * interrupt lock, which is the WrongThing (tm) to do.
	 */
959
	entering_ack_irq();
960
	local_apic_timer_interrupt();
961
	exiting_irq();
962

963 964 965
	set_irq_regs(old_regs);
}

966
__visible void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs)
967 968 969
{
	struct pt_regs *old_regs = set_irq_regs(regs);

970
	/*
971 972 973
	 * NOTE! We'd better ACK the irq immediately,
	 * because timer handling can be slow.
	 *
974 975 976 977
	 * update_process_times() expects us to have done irq_enter().
	 * Besides, if we don't timer interrupts ignore the global
	 * interrupt lock, which is the WrongThing (tm) to do.
	 */
978 979
	entering_ack_irq();
	trace_local_timer_entry(LOCAL_TIMER_VECTOR);
980
	local_apic_timer_interrupt();
981 982
	trace_local_timer_exit(LOCAL_TIMER_VECTOR);
	exiting_irq();
983

984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004
	set_irq_regs(old_regs);
}

int setup_profiling_timer(unsigned int multiplier)
{
	return -EINVAL;
}

/*
 * Local APIC start and shutdown
 */

/**
 * clear_local_APIC - shutdown the local APIC
 *
 * This is called, when a CPU is disabled and before rebooting, so the state of
 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
 * leftovers during boot.
 */
void clear_local_APIC(void)
{
1005
	int maxlvt;
1006 1007
	u32 v;

1008
	/* APIC hasn't been mapped yet */
1009
	if (!x2apic_mode && !apic_phys)
1010 1011 1012
		return;

	maxlvt = lapic_get_maxlvt();
1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035
	/*
	 * Masking an LVT entry can trigger a local APIC error
	 * if the vector is zero. Mask LVTERR first to prevent this.
	 */
	if (maxlvt >= 3) {
		v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
		apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
	}
	/*
	 * Careful: we have to set masks only first to deassert
	 * any level-triggered sources.
	 */
	v = apic_read(APIC_LVTT);
	apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
	v = apic_read(APIC_LVT0);
	apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
	v = apic_read(APIC_LVT1);
	apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
	if (maxlvt >= 4) {
		v = apic_read(APIC_LVTPC);
		apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
	}

1036
	/* lets not touch this if we didn't frob it */
1037
#ifdef CONFIG_X86_THERMAL_VECTOR
1038 1039 1040 1041 1042
	if (maxlvt >= 5) {
		v = apic_read(APIC_LVTTHMR);
		apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
	}
#endif
1043 1044 1045 1046 1047 1048 1049 1050
#ifdef CONFIG_X86_MCE_INTEL
	if (maxlvt >= 6) {
		v = apic_read(APIC_LVTCMCI);
		if (!(v & APIC_LVT_MASKED))
			apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
	}
#endif

1051 1052 1053 1054 1055 1056 1057 1058 1059 1060
	/*
	 * Clean APIC state for other OSs:
	 */
	apic_write(APIC_LVTT, APIC_LVT_MASKED);
	apic_write(APIC_LVT0, APIC_LVT_MASKED);
	apic_write(APIC_LVT1, APIC_LVT_MASKED);
	if (maxlvt >= 3)
		apic_write(APIC_LVTERR, APIC_LVT_MASKED);
	if (maxlvt >= 4)
		apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1061 1062 1063 1064 1065 1066 1067 1068

	/* Integrated APIC (!82489DX) ? */
	if (lapic_is_integrated()) {
		if (maxlvt > 3)
			/* Clear ESR due to Pentium errata 3AP and 11AP */
			apic_write(APIC_ESR, 0);
		apic_read(APIC_ESR);
	}
1069 1070 1071 1072 1073 1074 1075 1076 1077
}

/**
 * disable_local_APIC - clear and disable the local APIC
 */
void disable_local_APIC(void)
{
	unsigned int value;

1078
	/* APIC hasn't been mapped yet */
1079
	if (!x2apic_mode && !apic_phys)
1080 1081
		return;

1082 1083 1084 1085 1086 1087 1088 1089 1090
	clear_local_APIC();

	/*
	 * Disable APIC (implies clearing of registers
	 * for 82489DX!).
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_SPIV_APIC_ENABLED;
	apic_write(APIC_SPIV, value);
1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104

#ifdef CONFIG_X86_32
	/*
	 * When LAPIC was disabled by the BIOS and enabled by the kernel,
	 * restore the disabled state.
	 */
	if (enabled_via_apicbase) {
		unsigned int l, h;

		rdmsr(MSR_IA32_APICBASE, l, h);
		l &= ~MSR_IA32_APICBASE_ENABLE;
		wrmsr(MSR_IA32_APICBASE, l, h);
	}
#endif
1105 1106
}

1107 1108 1109 1110 1111 1112
/*
 * If Linux enabled the LAPIC against the BIOS default disable it down before
 * re-entering the BIOS on shutdown.  Otherwise the BIOS may get confused and
 * not power-off.  Additionally clear all LVT entries before disable_local_APIC
 * for the case where Linux didn't enable the LAPIC.
 */
1113 1114 1115 1116
void lapic_shutdown(void)
{
	unsigned long flags;

1117
	if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1118 1119 1120 1121
		return;

	local_irq_save(flags);

1122 1123 1124 1125 1126 1127 1128
#ifdef CONFIG_X86_32
	if (!enabled_via_apicbase)
		clear_local_APIC();
	else
#endif
		disable_local_APIC();

1129 1130 1131 1132 1133 1134 1135

	local_irq_restore(flags);
}

/**
 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
 */
L
Linus Torvalds 已提交
1136 1137
void __init sync_Arb_IDs(void)
{
C
Cyrill Gorcunov 已提交
1138 1139 1140 1141 1142
	/*
	 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
	 * needed on AMD.
	 */
	if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
L
Linus Torvalds 已提交
1143 1144 1145 1146 1147 1148 1149 1150
		return;

	/*
	 * Wait for idle.
	 */
	apic_wait_icr_idle();

	apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1151 1152
	apic_write(APIC_ICR, APIC_DEST_ALLINC |
			APIC_INT_LEVELTRIG | APIC_DM_INIT);
L
Linus Torvalds 已提交
1153 1154 1155 1156 1157 1158 1159
}

/*
 * An initial setup of the virtual wire mode.
 */
void __init init_bsp_APIC(void)
{
1160
	unsigned int value;
L
Linus Torvalds 已提交
1161 1162 1163 1164 1165

	/*
	 * Don't do the setup now if we have a SMP BIOS as the
	 * through-I/O-APIC virtual wire mode might be active.
	 */
1166
	if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC))
L
Linus Torvalds 已提交
1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179
		return;

	/*
	 * Do not trust the local APIC being empty at bootup.
	 */
	clear_local_APIC();

	/*
	 * Enable APIC.
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	value |= APIC_SPIV_APIC_ENABLED;
1180 1181 1182 1183 1184 1185 1186 1187 1188

#ifdef CONFIG_X86_32
	/* This bit is reserved on P4/Xeon and should be cleared */
	if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
	    (boot_cpu_data.x86 == 15))
		value &= ~APIC_SPIV_FOCUS_DISABLED;
	else
#endif
		value |= APIC_SPIV_FOCUS_DISABLED;
L
Linus Torvalds 已提交
1189
	value |= SPURIOUS_APIC_VECTOR;
1190
	apic_write(APIC_SPIV, value);
L
Linus Torvalds 已提交
1191 1192 1193 1194

	/*
	 * Set up the virtual wire mode.
	 */
1195
	apic_write(APIC_LVT0, APIC_DM_EXTINT);
L
Linus Torvalds 已提交
1196
	value = APIC_DM_NMI;
1197 1198
	if (!lapic_is_integrated())		/* 82489DX */
		value |= APIC_LVT_LEVEL_TRIGGER;
1199 1200
	if (apic_extnmi == APIC_EXTNMI_NONE)
		value |= APIC_LVT_MASKED;
1201
	apic_write(APIC_LVT1, value);
L
Linus Torvalds 已提交
1202 1203
}

1204
static void lapic_setup_esr(void)
1205
{
1206 1207 1208
	unsigned int oldvalue, value, maxlvt;

	if (!lapic_is_integrated()) {
1209
		pr_info("No ESR for 82489DX.\n");
1210 1211
		return;
	}
1212

1213
	if (apic->disable_esr) {
1214
		/*
1215 1216 1217 1218
		 * Something untraceable is creating bad interrupts on
		 * secondary quads ... for the moment, just leave the
		 * ESR disabled - we can't do anything useful with the
		 * errors anyway - mbligh
1219
		 */
1220
		pr_info("Leaving ESR disabled.\n");
1221
		return;
1222
	}
1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242

	maxlvt = lapic_get_maxlvt();
	if (maxlvt > 3)		/* Due to the Pentium erratum 3AP. */
		apic_write(APIC_ESR, 0);
	oldvalue = apic_read(APIC_ESR);

	/* enables sending errors */
	value = ERROR_APIC_VECTOR;
	apic_write(APIC_LVTERR, value);

	/*
	 * spec says clear errors after enabling vector.
	 */
	if (maxlvt > 3)
		apic_write(APIC_ESR, 0);
	value = apic_read(APIC_ESR);
	if (value != oldvalue)
		apic_printk(APIC_VERBOSE, "ESR value before enabling "
			"vector: 0x%08x  after: 0x%08x\n",
			oldvalue, value);
1243 1244
}

1245 1246
/**
 * setup_local_APIC - setup the local APIC
1247 1248 1249
 *
 * Used to setup local APIC while initializing BSP or bringin up APs.
 * Always called with preemption disabled.
1250
 */
1251
void setup_local_APIC(void)
L
Linus Torvalds 已提交
1252
{
1253
	int cpu = smp_processor_id();
1254 1255 1256
	unsigned int value, queued;
	int i, j, acked = 0;
	unsigned long long tsc = 0, ntsc;
1257
	long long max_loops = cpu_khz ? cpu_khz : 1000000;
1258

1259
	if (boot_cpu_has(X86_FEATURE_TSC))
1260
		tsc = rdtsc();
L
Linus Torvalds 已提交
1261

J
Jan Beulich 已提交
1262
	if (disable_apic) {
1263
		disable_ioapic_support();
J
Jan Beulich 已提交
1264 1265 1266
		return;
	}

1267 1268
#ifdef CONFIG_X86_32
	/* Pound the ESR really hard over the head with a big hammer - mbligh */
1269
	if (lapic_is_integrated() && apic->disable_esr) {
1270 1271 1272 1273 1274 1275
		apic_write(APIC_ESR, 0);
		apic_write(APIC_ESR, 0);
		apic_write(APIC_ESR, 0);
		apic_write(APIC_ESR, 0);
	}
#endif
1276
	perf_events_lapic_init();
1277

L
Linus Torvalds 已提交
1278 1279 1280 1281
	/*
	 * Double-check whether this APIC is really registered.
	 * This is meaningless in clustered apic mode, so we skip it.
	 */
1282
	BUG_ON(!apic->apic_id_registered());
L
Linus Torvalds 已提交
1283 1284 1285 1286 1287 1288

	/*
	 * Intel recommends to set DFR, LDR and TPR before enabling
	 * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
	 * document number 292116).  So here it goes...
	 */
1289
	apic->init_apic_ldr();
L
Linus Torvalds 已提交
1290

1291 1292
#ifdef CONFIG_X86_32
	/*
1293 1294 1295
	 * APIC LDR is initialized.  If logical_apicid mapping was
	 * initialized during get_smp_config(), make sure it matches the
	 * actual value.
1296
	 */
1297 1298 1299
	i = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
	WARN_ON(i != BAD_APICID && i != logical_smp_processor_id());
	/* always use the value from LDR */
1300 1301 1302 1303
	early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
		logical_smp_processor_id();
#endif

L
Linus Torvalds 已提交
1304 1305 1306 1307 1308 1309
	/*
	 * Set Task Priority to 'accept all'. We never change this
	 * later on.
	 */
	value = apic_read(APIC_TASKPRI);
	value &= ~APIC_TPRI_MASK;
1310
	apic_write(APIC_TASKPRI, value);
L
Linus Torvalds 已提交
1311

1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322
	/*
	 * After a crash, we no longer service the interrupts and a pending
	 * interrupt from previous kernel might still have ISR bit set.
	 *
	 * Most probably by now CPU has serviced that pending interrupt and
	 * it might not have done the ack_APIC_irq() because it thought,
	 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
	 * does not clear the ISR bit and cpu thinks it has already serivced
	 * the interrupt. Hence a vector might get locked. It was noticed
	 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
	 */
1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335
	do {
		queued = 0;
		for (i = APIC_ISR_NR - 1; i >= 0; i--)
			queued |= apic_read(APIC_IRR + i*0x10);

		for (i = APIC_ISR_NR - 1; i >= 0; i--) {
			value = apic_read(APIC_ISR + i*0x10);
			for (j = 31; j >= 0; j--) {
				if (value & (1<<j)) {
					ack_APIC_irq();
					acked++;
				}
			}
1336
		}
1337 1338 1339 1340 1341
		if (acked > 256) {
			printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
			       acked);
			break;
		}
1342
		if (queued) {
1343
			if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) {
1344
				ntsc = rdtsc();
1345 1346 1347 1348
				max_loops = (cpu_khz << 10) - (ntsc - tsc);
			} else
				max_loops--;
		}
1349 1350
	} while (queued && max_loops > 0);
	WARN_ON(max_loops <= 0);
1351

L
Linus Torvalds 已提交
1352 1353 1354 1355 1356 1357 1358 1359 1360 1361
	/*
	 * Now that we are all set up, enable the APIC
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	/*
	 * Enable APIC
	 */
	value |= APIC_SPIV_APIC_ENABLED;

1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388
#ifdef CONFIG_X86_32
	/*
	 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
	 * certain networking cards. If high frequency interrupts are
	 * happening on a particular IOAPIC pin, plus the IOAPIC routing
	 * entry is masked/unmasked at a high rate as well then sooner or
	 * later IOAPIC line gets 'stuck', no more interrupts are received
	 * from the device. If focus CPU is disabled then the hang goes
	 * away, oh well :-(
	 *
	 * [ This bug can be reproduced easily with a level-triggered
	 *   PCI Ne2000 networking cards and PII/PIII processors, dual
	 *   BX chipset. ]
	 */
	/*
	 * Actually disabling the focus CPU check just makes the hang less
	 * frequent as it makes the interrupt distributon model be more
	 * like LRU than MRU (the short-term load is more even across CPUs).
	 */

	/*
	 * - enable focus processor (bit==0)
	 * - 64bit mode always use processor focus
	 *   so no need to set it
	 */
	value &= ~APIC_SPIV_FOCUS_DISABLED;
#endif
1389

L
Linus Torvalds 已提交
1390 1391 1392 1393
	/*
	 * Set spurious IRQ vector
	 */
	value |= SPURIOUS_APIC_VECTOR;
1394
	apic_write(APIC_SPIV, value);
L
Linus Torvalds 已提交
1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406

	/*
	 * Set up LVT0, LVT1:
	 *
	 * set up through-local-APIC on the BP's LINT0. This is not
	 * strictly necessary in pure symmetric-IO mode, but sometimes
	 * we delegate interrupts to the 8259A.
	 */
	/*
	 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
	 */
	value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1407
	if (!cpu && (pic_mode || !value)) {
L
Linus Torvalds 已提交
1408
		value = APIC_DM_EXTINT;
1409
		apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
L
Linus Torvalds 已提交
1410 1411
	} else {
		value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1412
		apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
L
Linus Torvalds 已提交
1413
	}
1414
	apic_write(APIC_LVT0, value);
L
Linus Torvalds 已提交
1415 1416

	/*
1417 1418
	 * Only the BSP sees the LINT1 NMI signal by default. This can be
	 * modified by apic_extnmi= boot option.
L
Linus Torvalds 已提交
1419
	 */
1420 1421
	if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) ||
	    apic_extnmi == APIC_EXTNMI_ALL)
L
Linus Torvalds 已提交
1422 1423 1424
		value = APIC_DM_NMI;
	else
		value = APIC_DM_NMI | APIC_LVT_MASKED;
1425 1426
	if (!lapic_is_integrated())		/* 82489DX */
		value |= APIC_LVT_LEVEL_TRIGGER;
1427
	apic_write(APIC_LVT1, value);
1428

1429 1430
#ifdef CONFIG_X86_MCE_INTEL
	/* Recheck CMCI information after local APIC is up on CPU #0 */
1431
	if (!cpu)
1432 1433
		cmci_recheck();
#endif
1434
}
L
Linus Torvalds 已提交
1435

1436
static void end_local_APIC_setup(void)
1437 1438
{
	lapic_setup_esr();
1439 1440

#ifdef CONFIG_X86_32
1441 1442 1443 1444 1445 1446 1447
	{
		unsigned int value;
		/* Disable the local apic timer */
		value = apic_read(APIC_LVTT);
		value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
		apic_write(APIC_LVTT, value);
	}
1448 1449
#endif

1450
	apic_pm_activate();
1451 1452
}

1453 1454 1455 1456
/*
 * APIC setup function for application processors. Called from smpboot.c
 */
void apic_ap_setup(void)
1457
{
1458
	setup_local_APIC();
1459
	end_local_APIC_setup();
L
Linus Torvalds 已提交
1460 1461
}

Y
Yinghai Lu 已提交
1462
#ifdef CONFIG_X86_X2APIC
1463
int x2apic_mode;
1464 1465 1466 1467 1468 1469 1470 1471

enum {
	X2APIC_OFF,
	X2APIC_ON,
	X2APIC_DISABLED,
};
static int x2apic_state;

1472
static void __x2apic_disable(void)
1473 1474 1475
{
	u64 msr;

1476
	if (!boot_cpu_has(X86_FEATURE_APIC))
1477 1478
		return;

1479 1480 1481 1482 1483 1484 1485 1486 1487
	rdmsrl(MSR_IA32_APICBASE, msr);
	if (!(msr & X2APIC_ENABLE))
		return;
	/* Disable xapic and x2apic first and then reenable xapic mode */
	wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
	wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
	printk_once(KERN_INFO "x2apic disabled\n");
}

1488
static void __x2apic_enable(void)
1489 1490 1491 1492 1493 1494 1495 1496 1497 1498
{
	u64 msr;

	rdmsrl(MSR_IA32_APICBASE, msr);
	if (msr & X2APIC_ENABLE)
		return;
	wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
	printk_once(KERN_INFO "x2apic enabled\n");
}

1499 1500 1501 1502 1503 1504 1505 1506 1507 1508
static int __init setup_nox2apic(char *str)
{
	if (x2apic_enabled()) {
		int apicid = native_apic_msr_read(APIC_ID);

		if (apicid >= 255) {
			pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
				   apicid);
			return 0;
		}
1509 1510 1511 1512
		pr_warning("x2apic already enabled.\n");
		__x2apic_disable();
	}
	setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1513
	x2apic_state = X2APIC_DISABLED;
1514
	x2apic_mode = 0;
1515 1516 1517 1518
	return 0;
}
early_param("nox2apic", setup_nox2apic);

1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532
/* Called from cpu_init() to enable x2apic on (secondary) cpus */
void x2apic_setup(void)
{
	/*
	 * If x2apic is not in ON state, disable it if already enabled
	 * from BIOS.
	 */
	if (x2apic_state != X2APIC_ON) {
		__x2apic_disable();
		return;
	}
	__x2apic_enable();
}

1533
static __init void x2apic_disable(void)
1534
{
1535
	u32 x2apic_id, state = x2apic_state;
1536

1537 1538 1539 1540 1541
	x2apic_mode = 0;
	x2apic_state = X2APIC_DISABLED;

	if (state != X2APIC_ON)
		return;
1542

1543 1544 1545
	x2apic_id = read_apic_id();
	if (x2apic_id >= 255)
		panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1546

1547 1548
	__x2apic_disable();
	register_lapic_address(mp_lapic_addr);
1549 1550
}

1551
static __init void x2apic_enable(void)
1552
{
1553
	if (x2apic_state != X2APIC_OFF)
Y
Yinghai Lu 已提交
1554 1555
		return;

1556
	x2apic_mode = 1;
1557
	x2apic_state = X2APIC_ON;
1558
	__x2apic_enable();
1559
}
T
Thomas Gleixner 已提交
1560

1561
static __init void try_to_enable_x2apic(int remap_mode)
1562
{
1563
	if (x2apic_state == X2APIC_DISABLED)
1564 1565
		return;

1566
	if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
1567 1568 1569 1570
		/* IR is required if there is APIC ID > 255 even when running
		 * under KVM
		 */
		if (max_physical_apicid > 255 ||
1571
		    !hypervisor_x2apic_available()) {
1572
			pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1573
			x2apic_disable();
1574 1575 1576 1577 1578 1579 1580
			return;
		}

		/*
		 * without IR all CPUs can be addressed by IOAPIC/MSI
		 * only in physical mode
		 */
1581
		x2apic_phys = 1;
1582
	}
1583
	x2apic_enable();
1584 1585 1586 1587 1588 1589 1590
}

void __init check_x2apic(void)
{
	if (x2apic_enabled()) {
		pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
		x2apic_mode = 1;
1591
		x2apic_state = X2APIC_ON;
1592
	} else if (!boot_cpu_has(X86_FEATURE_X2APIC)) {
1593
		x2apic_state = X2APIC_DISABLED;
1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607
	}
}
#else /* CONFIG_X86_X2APIC */
static int __init validate_x2apic(void)
{
	if (!apic_is_x2apic_enabled())
		return 0;
	/*
	 * Checkme: Can we simply turn off x2apic here instead of panic?
	 */
	panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
}
early_initcall(validate_x2apic);

1608
static inline void try_to_enable_x2apic(int remap_mode) { }
1609
static inline void __x2apic_enable(void) { }
1610 1611 1612 1613 1614 1615 1616 1617 1618
#endif /* !CONFIG_X86_X2APIC */

static int __init try_to_enable_IR(void)
{
#ifdef CONFIG_X86_IO_APIC
	if (!x2apic_enabled() && skip_ioapic_setup) {
		pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
		return -1;
	}
1619
#endif
1620
	return irq_remapping_enable();
1621 1622 1623 1624 1625
}

void __init enable_IR_x2apic(void)
{
	unsigned long flags;
1626
	int ret, ir_stat;
1627

1628 1629 1630
	if (skip_ioapic_setup)
		return;

1631 1632
	ir_stat = irq_remapping_prepare();
	if (ir_stat < 0 && !x2apic_supported())
Y
Yinghai Lu 已提交
1633
		return;
1634

1635
	ret = save_ioapic_entries();
1636
	if (ret) {
1637
		pr_info("Saving IO-APIC state failed: %d\n", ret);
1638
		return;
1639
	}
1640

1641
	local_irq_save(flags);
1642
	legacy_pic->mask_all();
1643
	mask_ioapic_entries();
1644

1645
	/* If irq_remapping_prepare() succeeded, try to enable it */
1646 1647 1648 1649
	if (ir_stat >= 0)
		ir_stat = try_to_enable_IR();
	/* ir_stat contains the remap mode or an error code */
	try_to_enable_x2apic(ir_stat);
1650

1651
	if (ir_stat < 0)
1652
		restore_ioapic_entries();
1653
	legacy_pic->restore_mask();
1654 1655
	local_irq_restore(flags);
}
1656

1657
#ifdef CONFIG_X86_64
L
Linus Torvalds 已提交
1658 1659 1660 1661
/*
 * Detect and enable local APICs on non-SMP boards.
 * Original code written by Keir Fraser.
 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1662
 * not correctly set up (usually the APIC timer won't work etc.)
L
Linus Torvalds 已提交
1663
 */
1664
static int __init detect_init_APIC(void)
L
Linus Torvalds 已提交
1665
{
1666
	if (!boot_cpu_has(X86_FEATURE_APIC)) {
1667
		pr_info("No local APIC present\n");
L
Linus Torvalds 已提交
1668 1669 1670 1671 1672 1673
		return -1;
	}

	mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
	return 0;
}
1674
#else
1675

1676
static int __init apic_verify(void)
1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692
{
	u32 features, h, l;

	/*
	 * The APIC feature bit should now be enabled
	 * in `cpuid'
	 */
	features = cpuid_edx(1);
	if (!(features & (1 << X86_FEATURE_APIC))) {
		pr_warning("Could not enable APIC!\n");
		return -1;
	}
	set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
	mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;

	/* The BIOS may have set up the APIC at some other address */
1693 1694 1695 1696 1697
	if (boot_cpu_data.x86 >= 6) {
		rdmsr(MSR_IA32_APICBASE, l, h);
		if (l & MSR_IA32_APICBASE_ENABLE)
			mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
	}
1698 1699 1700 1701 1702

	pr_info("Found and enabled local APIC!\n");
	return 0;
}

1703
int __init apic_force_enable(unsigned long addr)
1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714
{
	u32 h, l;

	if (disable_apic)
		return -1;

	/*
	 * Some BIOSes disable the local APIC in the APIC_BASE
	 * MSR. This can only be done in software for Intel P6 or later
	 * and AMD K7 (Model > 1) or later.
	 */
1715 1716 1717 1718 1719 1720 1721 1722 1723
	if (boot_cpu_data.x86 >= 6) {
		rdmsr(MSR_IA32_APICBASE, l, h);
		if (!(l & MSR_IA32_APICBASE_ENABLE)) {
			pr_info("Local APIC disabled by BIOS -- reenabling.\n");
			l &= ~MSR_IA32_APICBASE_BASE;
			l |= MSR_IA32_APICBASE_ENABLE | addr;
			wrmsr(MSR_IA32_APICBASE, l, h);
			enabled_via_apicbase = 1;
		}
1724 1725 1726 1727
	}
	return apic_verify();
}

1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739
/*
 * Detect and initialize APIC
 */
static int __init detect_init_APIC(void)
{
	/* Disabled by kernel option? */
	if (disable_apic)
		return -1;

	switch (boot_cpu_data.x86_vendor) {
	case X86_VENDOR_AMD:
		if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1740
		    (boot_cpu_data.x86 >= 15))
1741 1742 1743 1744
			break;
		goto no_apic;
	case X86_VENDOR_INTEL:
		if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1745
		    (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC)))
1746 1747 1748 1749 1750 1751
			break;
		goto no_apic;
	default:
		goto no_apic;
	}

1752
	if (!boot_cpu_has(X86_FEATURE_APIC)) {
1753 1754 1755 1756 1757
		/*
		 * Over-ride BIOS and try to enable the local APIC only if
		 * "lapic" specified.
		 */
		if (!force_enable_local_apic) {
1758 1759
			pr_info("Local APIC disabled by BIOS -- "
				"you can enable it with \"lapic\"\n");
1760 1761
			return -1;
		}
1762
		if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1763 1764 1765 1766
			return -1;
	} else {
		if (apic_verify())
			return -1;
1767 1768 1769 1770 1771 1772 1773
	}

	apic_pm_activate();

	return 0;

no_apic:
1774
	pr_info("No local APIC present or hardware disabled\n");
1775 1776 1777
	return -1;
}
#endif
L
Linus Torvalds 已提交
1778

1779 1780 1781
/**
 * init_apic_mappings - initialize APIC mappings
 */
L
Linus Torvalds 已提交
1782 1783
void __init init_apic_mappings(void)
{
1784 1785
	unsigned int new_apicid;

1786
	if (x2apic_mode) {
1787
		boot_cpu_physical_apicid = read_apic_id();
1788 1789 1790
		return;
	}

1791
	/* If no local APIC can be found return early */
L
Linus Torvalds 已提交
1792
	if (!smp_found_config && detect_init_APIC()) {
1793 1794 1795 1796
		/* lets NOP'ify apic operations */
		pr_info("APIC: disable apic facility\n");
		apic_disable();
	} else {
L
Linus Torvalds 已提交
1797 1798
		apic_phys = mp_lapic_addr;

1799 1800 1801 1802
		/*
		 * acpi lapic path already maps that address in
		 * acpi_register_lapic_address()
		 */
1803
		if (!acpi_lapic && !smp_found_config)
1804
			register_lapic_address(apic_phys);
1805
	}
L
Linus Torvalds 已提交
1806 1807 1808 1809 1810

	/*
	 * Fetch the APIC ID of the BSP in case we have a
	 * default configuration (or the MP table is broken).
	 */
1811 1812 1813
	new_apicid = read_apic_id();
	if (boot_cpu_physical_apicid != new_apicid) {
		boot_cpu_physical_apicid = new_apicid;
1814 1815 1816 1817 1818 1819 1820
		/*
		 * yeah -- we lie about apic_version
		 * in case if apic was disabled via boot option
		 * but it's not a problem for SMP compiled kernel
		 * since smp_sanity_check is prepared for such a case
		 * and disable smp mode
		 */
1821
		boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
1822
	}
L
Linus Torvalds 已提交
1823 1824
}

1825 1826 1827 1828
void __init register_lapic_address(unsigned long address)
{
	mp_lapic_addr = address;

1829 1830 1831
	if (!x2apic_mode) {
		set_fixmap_nocache(FIX_APIC_BASE, address);
		apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1832
			    APIC_BASE, address);
1833
	}
1834 1835
	if (boot_cpu_physical_apicid == -1U) {
		boot_cpu_physical_apicid  = read_apic_id();
1836
		boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
1837 1838 1839
	}
}

L
Linus Torvalds 已提交
1840
/*
1841
 * Local APIC interrupts
L
Linus Torvalds 已提交
1842 1843
 */

1844 1845 1846
/*
 * This interrupt should _never_ happen with our APIC/SMP architecture
 */
1847
static void __smp_spurious_interrupt(u8 vector)
L
Linus Torvalds 已提交
1848
{
1849 1850
	u32 v;

L
Linus Torvalds 已提交
1851
	/*
1852 1853 1854
	 * Check if this really is a spurious interrupt and ACK it
	 * if it is a vectored one.  Just in case...
	 * Spurious interrupts should not be ACKed.
L
Linus Torvalds 已提交
1855
	 */
1856 1857
	v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
	if (v & (1 << (vector & 0x1f)))
1858
		ack_APIC_irq();
1859

1860 1861
	inc_irq_stat(irq_spurious_count);

1862
	/* see sw-dev-man vol 3, chapter 7.4.13.5 */
1863 1864
	pr_info("spurious APIC interrupt through vector %02x on CPU#%d, "
		"should never happen.\n", vector, smp_processor_id());
1865 1866
}

1867
__visible void smp_spurious_interrupt(struct pt_regs *regs)
1868 1869
{
	entering_irq();
1870
	__smp_spurious_interrupt(~regs->orig_ax);
1871
	exiting_irq();
1872
}
L
Linus Torvalds 已提交
1873

1874
__visible void smp_trace_spurious_interrupt(struct pt_regs *regs)
1875
{
1876 1877
	u8 vector = ~regs->orig_ax;

1878
	entering_irq();
1879 1880 1881
	trace_spurious_apic_entry(vector);
	__smp_spurious_interrupt(vector);
	trace_spurious_apic_exit(vector);
1882
	exiting_irq();
1883
}
L
Linus Torvalds 已提交
1884

1885 1886 1887
/*
 * This interrupt should never happen with our APIC/SMP architecture
 */
1888
static void __smp_error_interrupt(struct pt_regs *regs)
1889
{
1890
	u32 v;
1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901
	u32 i = 0;
	static const char * const error_interrupt_reason[] = {
		"Send CS error",		/* APIC Error Bit 0 */
		"Receive CS error",		/* APIC Error Bit 1 */
		"Send accept error",		/* APIC Error Bit 2 */
		"Receive accept error",		/* APIC Error Bit 3 */
		"Redirectable IPI",		/* APIC Error Bit 4 */
		"Send illegal vector",		/* APIC Error Bit 5 */
		"Received illegal vector",	/* APIC Error Bit 6 */
		"Illegal register address",	/* APIC Error Bit 7 */
	};
L
Linus Torvalds 已提交
1902

1903
	/* First tickle the hardware, only then report what went on. -- REW */
1904 1905
	if (lapic_get_maxlvt() > 3)	/* Due to the Pentium erratum 3AP. */
		apic_write(APIC_ESR, 0);
1906
	v = apic_read(APIC_ESR);
1907 1908
	ack_APIC_irq();
	atomic_inc(&irq_err_count);
1909

1910 1911
	apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
		    smp_processor_id(), v);
1912

1913 1914 1915
	v &= 0xff;
	while (v) {
		if (v & 0x1)
1916 1917
			apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
		i++;
1918
		v >>= 1;
1919
	}
1920 1921 1922

	apic_printk(APIC_DEBUG, KERN_CONT "\n");

1923 1924
}

1925
__visible void smp_error_interrupt(struct pt_regs *regs)
1926 1927 1928 1929
{
	entering_irq();
	__smp_error_interrupt(regs);
	exiting_irq();
L
Linus Torvalds 已提交
1930 1931
}

1932
__visible void smp_trace_error_interrupt(struct pt_regs *regs)
1933 1934 1935 1936 1937 1938
{
	entering_irq();
	trace_error_apic_entry(ERROR_APIC_VECTOR);
	__smp_error_interrupt(regs);
	trace_error_apic_exit(ERROR_APIC_VECTOR);
	exiting_irq();
L
Linus Torvalds 已提交
1939 1940
}

1941
/**
1942 1943
 * connect_bsp_APIC - attach the APIC to the interrupt system
 */
1944
static void __init connect_bsp_APIC(void)
1945
{
1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957
#ifdef CONFIG_X86_32
	if (pic_mode) {
		/*
		 * Do not trust the local APIC being empty at bootup.
		 */
		clear_local_APIC();
		/*
		 * PIC mode, enable APIC mode in the IMCR, i.e.  connect BSP's
		 * local APIC to INT and NMI lines.
		 */
		apic_printk(APIC_VERBOSE, "leaving PIC mode, "
				"enabling APIC mode.\n");
1958
		imcr_pic_to_apic();
1959 1960
	}
#endif
1961 1962
}

1963 1964 1965 1966 1967 1968 1969
/**
 * disconnect_bsp_APIC - detach the APIC from the interrupt system
 * @virt_wire_setup:	indicates, whether virtual wire mode is selected
 *
 * Virtual wire mode is necessary to deliver legacy interrupts even when the
 * APIC is disabled.
 */
1970
void disconnect_bsp_APIC(int virt_wire_setup)
L
Linus Torvalds 已提交
1971
{
1972 1973
	unsigned int value;

1974 1975 1976 1977 1978 1979 1980 1981 1982 1983
#ifdef CONFIG_X86_32
	if (pic_mode) {
		/*
		 * Put the board back into PIC mode (has an effect only on
		 * certain older boards).  Note that APIC interrupts, including
		 * IPIs, won't work beyond this point!  The only exception are
		 * INIT IPIs.
		 */
		apic_printk(APIC_VERBOSE, "disabling APIC mode, "
				"entering PIC mode.\n");
1984
		imcr_apic_to_pic();
1985 1986 1987 1988
		return;
	}
#endif

1989
	/* Go back to Virtual Wire compatibility mode */
L
Linus Torvalds 已提交
1990

1991 1992 1993 1994 1995 1996
	/* For the spurious interrupt use vector F, and enable it */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	value |= APIC_SPIV_APIC_ENABLED;
	value |= 0xf;
	apic_write(APIC_SPIV, value);
T
Thomas Gleixner 已提交
1997

1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013
	if (!virt_wire_setup) {
		/*
		 * For LVT0 make it edge triggered, active high,
		 * external and enabled
		 */
		value = apic_read(APIC_LVT0);
		value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
		value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
		value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
		apic_write(APIC_LVT0, value);
	} else {
		/* Disable LVT0 */
		apic_write(APIC_LVT0, APIC_LVT_MASKED);
	}
T
Thomas Gleixner 已提交
2014

2015 2016 2017 2018
	/*
	 * For LVT1 make it edge triggered, active high,
	 * nmi and enabled
	 */
2019 2020 2021 2022 2023 2024 2025
	value = apic_read(APIC_LVT1);
	value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
	value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
	value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
	apic_write(APIC_LVT1, value);
L
Linus Torvalds 已提交
2026 2027
}

2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074
/*
 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated
 * contiguously, it equals to current allocated max logical CPU ID plus 1.
 * All allocated CPU ID should be in [0, nr_logical_cpuidi), so the maximum of
 * nr_logical_cpuids is nr_cpu_ids.
 *
 * NOTE: Reserve 0 for BSP.
 */
static int nr_logical_cpuids = 1;

/*
 * Used to store mapping between logical CPU IDs and APIC IDs.
 */
static int cpuid_to_apicid[] = {
	[0 ... NR_CPUS - 1] = -1,
};

/*
 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids
 * and cpuid_to_apicid[] synchronized.
 */
static int allocate_logical_cpuid(int apicid)
{
	int i;

	/*
	 * cpuid <-> apicid mapping is persistent, so when a cpu is up,
	 * check if the kernel has allocated a cpuid for it.
	 */
	for (i = 0; i < nr_logical_cpuids; i++) {
		if (cpuid_to_apicid[i] == apicid)
			return i;
	}

	/* Allocate a new cpuid. */
	if (nr_logical_cpuids >= nr_cpu_ids) {
		WARN_ONCE(1, "Only %d processors supported."
			     "Processor %d/0x%x and the rest are ignored.\n",
			     nr_cpu_ids - 1, nr_logical_cpuids, apicid);
		return -1;
	}

	cpuid_to_apicid[nr_logical_cpuids] = apicid;
	return nr_logical_cpuids++;
}

int __generic_processor_info(int apicid, int version, bool enabled)
2075
{
2076 2077 2078 2079
	int cpu, max = nr_cpu_ids;
	bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
				phys_cpu_present_map);

2080 2081 2082 2083
	/*
	 * boot_cpu_physical_apicid is designed to have the apicid
	 * returned by read_apic_id(), i.e, the apicid of the
	 * currently booting-up processor. However, on some platforms,
2084
	 * it is temporarily modified by the apicid reported as BSP
2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103
	 * through MP table. Concretely:
	 *
	 * - arch/x86/kernel/mpparse.c: MP_processor_info()
	 * - arch/x86/mm/amdtopology.c: amd_numa_init()
	 *
	 * This function is executed with the modified
	 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
	 * parameter doesn't work to disable APs on kdump 2nd kernel.
	 *
	 * Since fixing handling of boot_cpu_physical_apicid requires
	 * another discussion and tests on each platform, we leave it
	 * for now and here we use read_apic_id() directly in this
	 * function, generic_processor_info().
	 */
	if (disabled_cpu_apicid != BAD_APICID &&
	    disabled_cpu_apicid != read_apic_id() &&
	    disabled_cpu_apicid == apicid) {
		int thiscpu = num_processors + disabled_cpus;

2104
		pr_warning("APIC: Disabling requested cpu."
2105 2106 2107 2108 2109 2110 2111
			   " Processor %d/0x%x ignored.\n",
			   thiscpu, apicid);

		disabled_cpus++;
		return -ENODEV;
	}

2112 2113 2114 2115 2116 2117 2118 2119 2120
	/*
	 * If boot cpu has not been detected yet, then only allow upto
	 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
	 */
	if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
	    apicid != boot_cpu_physical_apicid) {
		int thiscpu = max + disabled_cpus - 1;

		pr_warning(
C
Claudio Fontana 已提交
2121
			"APIC: NR_CPUS/possible_cpus limit of %i almost"
2122 2123 2124 2125
			" reached. Keeping one slot for boot cpu."
			"  Processor %d/0x%x ignored.\n", max, thiscpu, apicid);

		disabled_cpus++;
2126
		return -ENODEV;
2127
	}
2128

2129 2130 2131
	if (num_processors >= nr_cpu_ids) {
		int thiscpu = max + disabled_cpus;

2132 2133 2134 2135 2136
		if (enabled) {
			pr_warning("APIC: NR_CPUS/possible_cpus limit of %i "
				   "reached. Processor %d/0x%x ignored.\n",
				   max, thiscpu, apicid);
		}
2137 2138

		disabled_cpus++;
2139
		return -EINVAL;
2140 2141 2142 2143 2144 2145 2146
	}

	if (apicid == boot_cpu_physical_apicid) {
		/*
		 * x86_bios_cpu_apicid is required to have processors listed
		 * in same order as logical cpu numbers. Hence the first
		 * entry is BSP, and so on.
2147 2148
		 * boot_cpu_init() already hold bit 0 in cpu_present_mask
		 * for BSP.
2149 2150
		 */
		cpu = 0;
2151 2152 2153 2154 2155 2156 2157 2158 2159 2160

		/* Logical cpuid 0 is reserved for BSP. */
		cpuid_to_apicid[0] = apicid;
	} else {
		cpu = allocate_logical_cpuid(apicid);
		if (cpu < 0) {
			disabled_cpus++;
			return -EINVAL;
		}
	}
2161 2162 2163 2164 2165 2166 2167 2168

	/*
	 * Validate version
	 */
	if (version == 0x0) {
		pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
			   cpu, apicid);
		version = 0x10;
2169
	}
2170

2171
	if (version != boot_cpu_apic_version) {
2172
		pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2173
			boot_cpu_apic_version, cpu, version);
2174 2175
	}

2176 2177 2178
	if (apicid > max_physical_apicid)
		max_physical_apicid = apicid;

2179
#if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2180 2181
	early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
	early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2182
#endif
2183 2184 2185 2186
#ifdef CONFIG_X86_32
	early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
		apic->x86_32_early_logical_apicid(cpu);
#endif
2187
	set_cpu_possible(cpu, true);
2188 2189 2190 2191 2192 2193 2194 2195

	if (enabled) {
		num_processors++;
		physid_set(apicid, phys_cpu_present_map);
		set_cpu_present(cpu, true);
	} else {
		disabled_cpus++;
	}
2196 2197

	return cpu;
2198 2199
}

2200 2201 2202 2203 2204
int generic_processor_info(int apicid, int version)
{
	return __generic_processor_info(apicid, version, true);
}

2205 2206 2207 2208
int hard_smp_processor_id(void)
{
	return read_apic_id();
}
I
Ingo Molnar 已提交
2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219

void default_init_apic_ldr(void)
{
	unsigned long val;

	apic_write(APIC_DFR, APIC_DFR_VALUE);
	val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
	val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
	apic_write(APIC_LDR, val);
}

2220 2221 2222
int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
				   const struct cpumask *andmask,
				   unsigned int *apicid)
2223
{
2224
	unsigned int cpu;
2225 2226 2227 2228 2229

	for_each_cpu_and(cpu, cpumask, andmask) {
		if (cpumask_test_cpu(cpu, cpu_online_mask))
			break;
	}
2230

2231
	if (likely(cpu < nr_cpu_ids)) {
2232 2233 2234
		*apicid = per_cpu(x86_cpu_to_apicid, cpu);
		return 0;
	}
2235 2236

	return -EINVAL;
2237 2238
}

2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251
/*
 * Override the generic EOI implementation with an optimized version.
 * Only called during early boot when only one CPU is active and with
 * interrupts disabled, so we know this does not race with actual APIC driver
 * use.
 */
void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
{
	struct apic **drv;

	for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
		/* Should happen once for each apic */
		WARN_ON((*drv)->eoi_write == eoi_write);
2252
		(*drv)->native_eoi_write = (*drv)->eoi_write;
2253 2254 2255 2256
		(*drv)->eoi_write = eoi_write;
	}
}

2257
static void __init apic_bsp_up_setup(void)
2258
{
2259 2260 2261
#ifdef CONFIG_X86_64
	apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
#else
2262
	/*
2263 2264 2265
	 * Hack: In case of kdump, after a crash, kernel might be booting
	 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
	 * might be zero if read from MP tables. Get it from LAPIC.
2266
	 */
2267 2268 2269 2270 2271
# ifdef CONFIG_CRASH_DUMP
	boot_cpu_physical_apicid = read_apic_id();
# endif
#endif
	physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
2272 2273 2274 2275
}

/**
 * apic_bsp_setup - Setup function for local apic and io-apic
2276
 * @upmode:		Force UP mode (for APIC_init_uniprocessor)
2277 2278 2279 2280
 *
 * Returns:
 * apic_id of BSP APIC
 */
2281
int __init apic_bsp_setup(bool upmode)
2282 2283 2284 2285
{
	int id;

	connect_bsp_APIC();
2286 2287
	if (upmode)
		apic_bsp_up_setup();
2288 2289 2290 2291 2292 2293 2294 2295
	setup_local_APIC();

	if (x2apic_mode)
		id = apic_read(APIC_LDR);
	else
		id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));

	enable_IO_APIC();
2296 2297
	end_local_APIC_setup();
	irq_remap_enable_fault_handling();
2298
	setup_IO_APIC();
2299 2300
	/* Setup local timer */
	x86_init.timers.setup_percpu_clockev();
2301 2302 2303
	return id;
}

2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314
/*
 * This initializes the IO-APIC and APIC hardware if this is
 * a UP kernel.
 */
int __init APIC_init_uniprocessor(void)
{
	if (disable_apic) {
		pr_info("Apic disabled\n");
		return -1;
	}
#ifdef CONFIG_X86_64
2315
	if (!boot_cpu_has(X86_FEATURE_APIC)) {
2316 2317 2318 2319 2320
		disable_apic = 1;
		pr_info("Apic disabled by BIOS\n");
		return -1;
	}
#else
2321
	if (!smp_found_config && !boot_cpu_has(X86_FEATURE_APIC))
2322 2323 2324 2325 2326
		return -1;

	/*
	 * Complain if the BIOS pretends there is one.
	 */
2327
	if (!boot_cpu_has(X86_FEATURE_APIC) &&
2328
	    APIC_INTEGRATED(boot_cpu_apic_version)) {
2329 2330 2331 2332 2333 2334
		pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
			boot_cpu_physical_apicid);
		return -1;
	}
#endif

2335 2336
	if (!smp_found_config)
		disable_ioapic_support();
2337

2338 2339
	default_setup_apic_routing();
	apic_bsp_setup(true);
2340 2341 2342
	return 0;
}

T
Thomas Gleixner 已提交
2343 2344 2345 2346 2347 2348 2349
#ifdef CONFIG_UP_LATE_INIT
void __init up_late_init(void)
{
	APIC_init_uniprocessor();
}
#endif

2350
/*
2351
 * Power management
2352
 */
2353 2354 2355
#ifdef CONFIG_PM

static struct {
2356 2357 2358 2359 2360
	/*
	 * 'active' is true if the local APIC was enabled by us and
	 * not the BIOS; this signifies that we are also responsible
	 * for disabling it before entering apm/acpi suspend
	 */
2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375
	int active;
	/* r/w apic fields */
	unsigned int apic_id;
	unsigned int apic_taskpri;
	unsigned int apic_ldr;
	unsigned int apic_dfr;
	unsigned int apic_spiv;
	unsigned int apic_lvtt;
	unsigned int apic_lvtpc;
	unsigned int apic_lvt0;
	unsigned int apic_lvt1;
	unsigned int apic_lvterr;
	unsigned int apic_tmict;
	unsigned int apic_tdcr;
	unsigned int apic_thmr;
2376
	unsigned int apic_cmci;
2377 2378
} apic_pm_state;

2379
static int lapic_suspend(void)
2380 2381 2382
{
	unsigned long flags;
	int maxlvt;
2383

2384 2385
	if (!apic_pm_state.active)
		return 0;
2386

2387
	maxlvt = lapic_get_maxlvt();
2388

2389
	apic_pm_state.apic_id = apic_read(APIC_ID);
2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401
	apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
	apic_pm_state.apic_ldr = apic_read(APIC_LDR);
	apic_pm_state.apic_dfr = apic_read(APIC_DFR);
	apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
	apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
	if (maxlvt >= 4)
		apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
	apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
	apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
	apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
	apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
	apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2402
#ifdef CONFIG_X86_THERMAL_VECTOR
2403 2404 2405
	if (maxlvt >= 5)
		apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
#endif
2406 2407 2408 2409
#ifdef CONFIG_X86_MCE_INTEL
	if (maxlvt >= 6)
		apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI);
#endif
2410

2411 2412
	local_irq_save(flags);
	disable_local_APIC();
2413

2414
	irq_remapping_disable();
2415

2416 2417
	local_irq_restore(flags);
	return 0;
L
Linus Torvalds 已提交
2418 2419
}

2420
static void lapic_resume(void)
L
Linus Torvalds 已提交
2421
{
2422 2423
	unsigned int l, h;
	unsigned long flags;
2424
	int maxlvt;
2425

2426
	if (!apic_pm_state.active)
2427
		return;
2428

2429
	local_irq_save(flags);
2430 2431 2432 2433 2434 2435 2436 2437 2438

	/*
	 * IO-APIC and PIC have their own resume routines.
	 * We just mask them here to make sure the interrupt
	 * subsystem is completely quiet while we enable x2apic
	 * and interrupt-remapping.
	 */
	mask_ioapic_entries();
	legacy_pic->mask_all();
C
Cyrill Gorcunov 已提交
2439

2440 2441 2442
	if (x2apic_mode) {
		__x2apic_enable();
	} else {
C
Cyrill Gorcunov 已提交
2443 2444 2445 2446 2447 2448
		/*
		 * Make sure the APICBASE points to the right address
		 *
		 * FIXME! This will be wrong if we ever support suspend on
		 * SMP! We'll need to do this as part of the CPU restore!
		 */
2449 2450 2451 2452 2453 2454
		if (boot_cpu_data.x86 >= 6) {
			rdmsr(MSR_IA32_APICBASE, l, h);
			l &= ~MSR_IA32_APICBASE_BASE;
			l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
			wrmsr(MSR_IA32_APICBASE, l, h);
		}
2455
	}
2456

2457
	maxlvt = lapic_get_maxlvt();
2458 2459 2460 2461 2462 2463 2464 2465
	apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
	apic_write(APIC_ID, apic_pm_state.apic_id);
	apic_write(APIC_DFR, apic_pm_state.apic_dfr);
	apic_write(APIC_LDR, apic_pm_state.apic_ldr);
	apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
	apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
	apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
	apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2466
#ifdef CONFIG_X86_THERMAL_VECTOR
2467 2468
	if (maxlvt >= 5)
		apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2469 2470 2471 2472
#endif
#ifdef CONFIG_X86_MCE_INTEL
	if (maxlvt >= 6)
		apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci);
2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483
#endif
	if (maxlvt >= 4)
		apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
	apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
	apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
	apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
	apic_write(APIC_ESR, 0);
	apic_read(APIC_ESR);
	apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
	apic_write(APIC_ESR, 0);
	apic_read(APIC_ESR);
C
Cyrill Gorcunov 已提交
2484

2485
	irq_remapping_reenable(x2apic_mode);
2486

2487 2488
	local_irq_restore(flags);
}
T
Thomas Gleixner 已提交
2489

2490 2491 2492 2493 2494
/*
 * This device has no shutdown method - fully functioning local APICs
 * are needed on every CPU up until machine_halt/restart/poweroff.
 */

2495
static struct syscore_ops lapic_syscore_ops = {
2496 2497 2498
	.resume		= lapic_resume,
	.suspend	= lapic_suspend,
};
T
Thomas Gleixner 已提交
2499

2500
static void apic_pm_activate(void)
2501 2502
{
	apic_pm_state.active = 1;
L
Linus Torvalds 已提交
2503 2504
}

2505
static int __init init_lapic_sysfs(void)
L
Linus Torvalds 已提交
2506
{
2507
	/* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2508
	if (boot_cpu_has(X86_FEATURE_APIC))
2509
		register_syscore_ops(&lapic_syscore_ops);
H
Hiroshi Shimamoto 已提交
2510

2511
	return 0;
L
Linus Torvalds 已提交
2512
}
2513 2514 2515

/* local apic needs to resume before other devices access its registers. */
core_initcall(init_lapic_sysfs);
2516 2517 2518 2519 2520 2521

#else	/* CONFIG_PM */

static void apic_pm_activate(void) { }

#endif	/* CONFIG_PM */
L
Linus Torvalds 已提交
2522

Y
Yinghai Lu 已提交
2523
#ifdef CONFIG_X86_64
2524

2525 2526
static int multi_checked;
static int multi;
2527

2528
static int set_multi(const struct dmi_system_id *d)
2529 2530 2531
{
	if (multi)
		return 0;
C
Cyrill Gorcunov 已提交
2532
	pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2533 2534 2535 2536
	multi = 1;
	return 0;
}

2537
static const struct dmi_system_id multi_dmi_table[] = {
2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548
	{
		.callback = set_multi,
		.ident = "IBM System Summit2",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
		},
	},
	{}
};

2549
static void dmi_check_multi(void)
2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565
{
	if (multi_checked)
		return;

	dmi_check_system(multi_dmi_table);
	multi_checked = 1;
}

/*
 * apic_is_clustered_box() -- Check if we can expect good TSC
 *
 * Thus far, the major user of this is IBM's Summit2 series:
 * Clustered boxes may have unsynced TSC problems if they are
 * multi-chassis.
 * Use DMI to check them
 */
2566
int apic_is_clustered_box(void)
2567 2568
{
	dmi_check_multi();
2569
	return multi;
L
Linus Torvalds 已提交
2570
}
Y
Yinghai Lu 已提交
2571
#endif
L
Linus Torvalds 已提交
2572 2573

/*
2574
 * APIC command line parameters
L
Linus Torvalds 已提交
2575
 */
2576
static int __init setup_disableapic(char *arg)
2577
{
L
Linus Torvalds 已提交
2578
	disable_apic = 1;
2579
	setup_clear_cpu_cap(X86_FEATURE_APIC);
2580 2581 2582
	return 0;
}
early_param("disableapic", setup_disableapic);
L
Linus Torvalds 已提交
2583

2584
/* same as disableapic, for compatibility */
2585
static int __init setup_nolapic(char *arg)
2586
{
2587
	return setup_disableapic(arg);
2588
}
2589
early_param("nolapic", setup_nolapic);
L
Linus Torvalds 已提交
2590

2591 2592 2593 2594 2595 2596 2597
static int __init parse_lapic_timer_c2_ok(char *arg)
{
	local_apic_timer_c2_ok = 1;
	return 0;
}
early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);

2598
static int __init parse_disable_apic_timer(char *arg)
2599
{
L
Linus Torvalds 已提交
2600
	disable_apic_timer = 1;
2601
	return 0;
2602
}
2603 2604 2605 2606 2607 2608
early_param("noapictimer", parse_disable_apic_timer);

static int __init parse_nolapic_timer(char *arg)
{
	disable_apic_timer = 1;
	return 0;
2609
}
2610
early_param("nolapic_timer", parse_nolapic_timer);
2611

2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626
static int __init apic_set_verbosity(char *arg)
{
	if (!arg)  {
#ifdef CONFIG_X86_64
		skip_ioapic_setup = 0;
		return 0;
#endif
		return -EINVAL;
	}

	if (strcmp("debug", arg) == 0)
		apic_verbosity = APIC_DEBUG;
	else if (strcmp("verbose", arg) == 0)
		apic_verbosity = APIC_VERBOSE;
	else {
2627
		pr_warning("APIC Verbosity level %s not recognised"
2628 2629 2630 2631 2632 2633 2634 2635
			" use apic=verbose or apic=debug\n", arg);
		return -EINVAL;
	}

	return 0;
}
early_param("apic", apic_set_verbosity);

2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653
static int __init lapic_insert_resource(void)
{
	if (!apic_phys)
		return -1;

	/* Put local APIC into the resource map. */
	lapic_resource.start = apic_phys;
	lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
	insert_resource(&iomem_resource, &lapic_resource);

	return 0;
}

/*
 * need call insert after e820_reserve_resources()
 * that is using request_resource
 */
late_initcall(lapic_insert_resource);
2654 2655 2656 2657 2658 2659 2660 2661 2662

static int __init apic_set_disabled_cpu_apicid(char *arg)
{
	if (!arg || !get_option(&arg, &disabled_cpu_apicid))
		return -EINVAL;

	return 0;
}
early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid);
2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682

static int __init apic_set_extnmi(char *arg)
{
	if (!arg)
		return -EINVAL;

	if (!strncmp("all", arg, 3))
		apic_extnmi = APIC_EXTNMI_ALL;
	else if (!strncmp("none", arg, 4))
		apic_extnmi = APIC_EXTNMI_NONE;
	else if (!strncmp("bsp", arg, 3))
		apic_extnmi = APIC_EXTNMI_BSP;
	else {
		pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg);
		return -EINVAL;
	}

	return 0;
}
early_param("apic_extnmi", apic_set_extnmi);