apic.c 57.9 KB
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/*
 *	Local APIC handling, local APIC timers
 *
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 *	(c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
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 *
 *	Fixes
 *	Maciej W. Rozycki	:	Bits for genuine 82489DX APICs;
 *					thanks to Eric Gilmore
 *					and Rolf G. Tews
 *					for testing these extensively.
 *	Maciej W. Rozycki	:	Various updates and fixes.
 *	Mikael Pettersson	:	Power Management for UP-APIC.
 *	Pavel Machek and
 *	Mikael Pettersson	:	PM converted to driver model.
 */

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#include <linux/perf_event.h>
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#include <linux/kernel_stat.h>
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#include <linux/mc146818rtc.h>
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#include <linux/acpi_pmtmr.h>
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#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/bootmem.h>
#include <linux/ftrace.h>
#include <linux/ioport.h>
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#include <linux/module.h>
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#include <linux/syscore_ops.h>
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#include <linux/delay.h>
#include <linux/timex.h>
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#include <linux/i8253.h>
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#include <linux/dmar.h>
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#include <linux/init.h>
#include <linux/cpu.h>
#include <linux/dmi.h>
#include <linux/smp.h>
#include <linux/mm.h>
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#include <asm/perf_event.h>
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#include <asm/x86_init.h>
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#include <asm/pgalloc.h>
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#include <linux/atomic.h>
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#include <asm/mpspec.h>
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#include <asm/i8259.h>
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#include <asm/proto.h>
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#include <asm/apic.h>
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#include <asm/io_apic.h>
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#include <asm/desc.h>
#include <asm/hpet.h>
#include <asm/idle.h>
#include <asm/mtrr.h>
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#include <asm/time.h>
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#include <asm/smp.h>
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#include <asm/mce.h>
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#include <asm/tsc.h>
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#include <asm/hypervisor.h>
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unsigned int num_processors;
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unsigned disabled_cpus __cpuinitdata;
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/* Processor that is doing the boot up */
unsigned int boot_cpu_physical_apicid = -1U;
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/*
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 * The highest APIC ID seen during enumeration.
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 */
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unsigned int max_physical_apicid;
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/*
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 * Bitmask of physically existing CPUs:
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 */
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physid_mask_t phys_cpu_present_map;

/*
 * Map cpu index to physical APIC ID
 */
DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID);
DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID);
EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
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/*
 * ICR read retry counter
 */
DEFINE_PER_CPU(unsigned, icr_read_retry_count);

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#ifdef CONFIG_X86_32
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/*
 * On x86_32, the mapping between cpu and logical apicid may vary
 * depending on apic in use.  The following early percpu variable is
 * used for the mapping.  This is where the behaviors of x86_64 and 32
 * actually diverge.  Let's keep it ugly for now.
 */
DEFINE_EARLY_PER_CPU(int, x86_cpu_to_logical_apicid, BAD_APICID);

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/*
 * Knob to control our willingness to enable the local APIC.
 *
 * +1=force-enable
 */
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static int force_enable_local_apic __initdata;
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/*
 * APIC command line parameters
 */
static int __init parse_lapic(char *arg)
{
	force_enable_local_apic = 1;
	return 0;
}
early_param("lapic", parse_lapic);
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/* Local APIC was disabled by the BIOS and enabled by the kernel */
static int enabled_via_apicbase;

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/*
 * Handle interrupt mode configuration register (IMCR).
 * This register controls whether the interrupt signals
 * that reach the BSP come from the master PIC or from the
 * local APIC. Before entering Symmetric I/O Mode, either
 * the BIOS or the operating system must switch out of
 * PIC Mode by changing the IMCR.
 */
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static inline void imcr_pic_to_apic(void)
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{
	/* select IMCR register */
	outb(0x70, 0x22);
	/* NMI and 8259 INTR go through APIC */
	outb(0x01, 0x23);
}

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static inline void imcr_apic_to_pic(void)
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{
	/* select IMCR register */
	outb(0x70, 0x22);
	/* NMI and 8259 INTR go directly to BSP */
	outb(0x00, 0x23);
}
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#endif

#ifdef CONFIG_X86_64
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static int apic_calibrate_pmtmr __initdata;
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static __init int setup_apicpmtimer(char *s)
{
	apic_calibrate_pmtmr = 1;
	notsc_setup(NULL);
	return 0;
}
__setup("apicpmtimer", setup_apicpmtimer);
#endif

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int x2apic_mode;
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#ifdef CONFIG_X86_X2APIC
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/* x2apic enabled before OS handover */
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static int x2apic_preenabled;
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static __init int setup_nox2apic(char *str)
{
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	if (x2apic_enabled()) {
		pr_warning("Bios already enabled x2apic, "
			   "can't enforce nox2apic");
		return 0;
	}

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	setup_clear_cpu_cap(X86_FEATURE_X2APIC);
	return 0;
}
early_param("nox2apic", setup_nox2apic);
#endif
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unsigned long mp_lapic_addr;
int disable_apic;
/* Disable local APIC timer from the kernel commandline or via dmi quirk */
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static int disable_apic_timer __initdata;
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/* Local APIC timer works in C2 */
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int local_apic_timer_c2_ok;
EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);

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int first_system_vector = 0xfe;

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/*
 * Debug level, exported for io_apic.c
 */
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unsigned int apic_verbosity;
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int pic_mode;

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/* Have we found an MP table */
int smp_found_config;

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static struct resource lapic_resource = {
	.name = "Local APIC",
	.flags = IORESOURCE_MEM | IORESOURCE_BUSY,
};

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unsigned int lapic_timer_frequency = 0;
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static void apic_pm_activate(void);
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static unsigned long apic_phys;

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/*
 * Get the LAPIC version
 */
static inline int lapic_get_version(void)
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{
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	return GET_APIC_VERSION(apic_read(APIC_LVR));
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}

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/*
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 * Check, if the APIC is integrated or a separate chip
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 */
static inline int lapic_is_integrated(void)
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{
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#ifdef CONFIG_X86_64
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	return 1;
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#else
	return APIC_INTEGRATED(lapic_get_version());
#endif
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}

/*
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 * Check, whether this is a modern or a first generation APIC
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 */
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static int modern_apic(void)
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{
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	/* AMD systems use old APIC versions, so check the CPU */
	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
	    boot_cpu_data.x86 >= 0xf)
		return 1;
	return lapic_get_version() >= 0x14;
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}

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/*
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 * right after this call apic become NOOP driven
 * so apic->write/read doesn't do anything
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 */
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static void __init apic_disable(void)
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{
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	pr_info("APIC: switched to apic NOOP\n");
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	apic = &apic_noop;
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}

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void native_apic_wait_icr_idle(void)
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{
	while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
		cpu_relax();
}

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u32 native_safe_apic_wait_icr_idle(void)
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{
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	u32 send_status;
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	int timeout;

	timeout = 0;
	do {
		send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
		if (!send_status)
			break;
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		percpu_inc(icr_read_retry_count);
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		udelay(100);
	} while (timeout++ < 1000);

	return send_status;
}

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void native_apic_icr_write(u32 low, u32 id)
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{
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	apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
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	apic_write(APIC_ICR, low);
}

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u64 native_apic_icr_read(void)
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{
	u32 icr1, icr2;

	icr2 = apic_read(APIC_ICR2);
	icr1 = apic_read(APIC_ICR);

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	return icr1 | ((u64)icr2 << 32);
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}

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#ifdef CONFIG_X86_32
/**
 * get_physical_broadcast - Get number of physical broadcast IDs
 */
int get_physical_broadcast(void)
{
	return modern_apic() ? 0xff : 0xf;
}
#endif

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/**
 * lapic_get_maxlvt - get the maximum number of local vector table entries
 */
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int lapic_get_maxlvt(void)
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{
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	unsigned int v;
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	v = apic_read(APIC_LVR);
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	/*
	 * - we always have APIC integrated on 64bit mode
	 * - 82489DXs do not report # of LVT entries
	 */
	return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
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}

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/*
 * Local APIC timer
 */

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/* Clock divisor */
#define APIC_DIVISOR 16
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/*
 * This function sets up the local APIC timer, with a timeout of
 * 'clocks' APIC bus clock. During calibration we actually call
 * this function twice on the boot CPU, once with a bogus timeout
 * value, second time for real. The other (noncalibrating) CPUs
 * call this function only once, with the real, calibrated value.
 *
 * We do reads before writes even if unnecessary, to get around the
 * P5 APIC double write bug.
 */
static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
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{
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	unsigned int lvtt_value, tmp_value;
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	lvtt_value = LOCAL_TIMER_VECTOR;
	if (!oneshot)
		lvtt_value |= APIC_LVT_TIMER_PERIODIC;
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	if (!lapic_is_integrated())
		lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);

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	if (!irqen)
		lvtt_value |= APIC_LVT_MASKED;
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	apic_write(APIC_LVTT, lvtt_value);
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	/*
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	 * Divide PICLK by 16
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	 */
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	tmp_value = apic_read(APIC_TDCR);
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	apic_write(APIC_TDCR,
		(tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
		APIC_TDR_DIV_16);
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	if (!oneshot)
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		apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
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}

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/*
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 * Setup extended LVT, AMD specific
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 *
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 * Software should use the LVT offsets the BIOS provides.  The offsets
 * are determined by the subsystems using it like those for MCE
 * threshold or IBS.  On K8 only offset 0 (APIC500) and MCE interrupts
 * are supported. Beginning with family 10h at least 4 offsets are
 * available.
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 *
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 * Since the offsets must be consistent for all cores, we keep track
 * of the LVT offsets in software and reserve the offset for the same
 * vector also to be used on other cores. An offset is freed by
 * setting the entry to APIC_EILVT_MASKED.
 *
 * If the BIOS is right, there should be no conflicts. Otherwise a
 * "[Firmware Bug]: ..." error message is generated. However, if
 * software does not properly determines the offsets, it is not
 * necessarily a BIOS bug.
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 */
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static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];

static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
{
	return (old & APIC_EILVT_MASKED)
		|| (new == APIC_EILVT_MASKED)
		|| ((new & ~APIC_EILVT_MASKED) == old);
}

static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
{
	unsigned int rsvd;			/* 0: uninitialized */

	if (offset >= APIC_EILVT_NR_MAX)
		return ~0;

	rsvd = atomic_read(&eilvt_offsets[offset]) & ~APIC_EILVT_MASKED;
	do {
		if (rsvd &&
		    !eilvt_entry_is_changeable(rsvd, new))
			/* may not change if vectors are different */
			return rsvd;
		rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
	} while (rsvd != new);

	return new;
}

/*
 * If mask=1, the LVT entry does not generate interrupts while mask=0
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 * enables the vector. See also the BKDGs. Must be called with
 * preemption disabled.
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 */

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int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
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{
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	unsigned long reg = APIC_EILVTn(offset);
	unsigned int new, old, reserved;

	new = (mask << 16) | (msg_type << 8) | vector;
	old = apic_read(reg);
	reserved = reserve_eilvt_offset(offset, new);

	if (reserved != new) {
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		pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
		       "vector 0x%x, but the register is already in use for "
		       "vector 0x%x on another cpu\n",
		       smp_processor_id(), reg, offset, new, reserved);
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		return -EINVAL;
	}

	if (!eilvt_entry_is_changeable(old, new)) {
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		pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
		       "vector 0x%x, but the register is already in use for "
		       "vector 0x%x on this cpu\n",
		       smp_processor_id(), reg, offset, new, old);
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		return -EBUSY;
	}

	apic_write(reg, new);
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	return 0;
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}
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EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
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/*
 * Program the next event, relative to now
 */
static int lapic_next_event(unsigned long delta,
			    struct clock_event_device *evt)
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{
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	apic_write(APIC_TMICT, delta);
	return 0;
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}

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/*
 * Setup the lapic timer in periodic or oneshot mode
 */
static void lapic_timer_setup(enum clock_event_mode mode,
			      struct clock_event_device *evt)
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{
	unsigned long flags;
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	unsigned int v;
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	/* Lapic used as dummy for broadcast ? */
	if (evt->features & CLOCK_EVT_FEAT_DUMMY)
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		return;

	local_irq_save(flags);

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	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
	case CLOCK_EVT_MODE_ONESHOT:
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		__setup_APIC_LVTT(lapic_timer_frequency,
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				  mode != CLOCK_EVT_MODE_PERIODIC, 1);
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		v = apic_read(APIC_LVTT);
		v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
		apic_write(APIC_LVTT, v);
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		apic_write(APIC_TMICT, 0);
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		break;
	case CLOCK_EVT_MODE_RESUME:
		/* Nothing to do here */
		break;
	}
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	local_irq_restore(flags);
}

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/*
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 * Local APIC timer broadcast function
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 */
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static void lapic_timer_broadcast(const struct cpumask *mask)
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{
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#ifdef CONFIG_SMP
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	apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
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#endif
}
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/*
 * The local apic timer can be used for any function which is CPU local.
 */
static struct clock_event_device lapic_clockevent = {
	.name		= "lapic",
	.features	= CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
			| CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
	.shift		= 32,
	.set_mode	= lapic_timer_setup,
	.set_next_event	= lapic_next_event,
	.broadcast	= lapic_timer_broadcast,
	.rating		= 100,
	.irq		= -1,
};
static DEFINE_PER_CPU(struct clock_event_device, lapic_events);

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/*
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 * Setup the local APIC timer for this CPU. Copy the initialized values
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 * of the boot CPU and register the clock event in the framework.
 */
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static void __cpuinit setup_APIC_timer(void)
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{
	struct clock_event_device *levt = &__get_cpu_var(lapic_events);
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	if (this_cpu_has(X86_FEATURE_ARAT)) {
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		lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
		/* Make LAPIC timer preferrable over percpu HPET */
		lapic_clockevent.rating = 150;
	}

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	memcpy(levt, &lapic_clockevent, sizeof(*levt));
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	levt->cpumask = cpumask_of(smp_processor_id());
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	clockevents_register_device(levt);
}
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/*
 * In this functions we calibrate APIC bus clocks to the external timer.
 *
 * We want to do the calibration only once since we want to have local timer
 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
 * frequency.
 *
 * This was previously done by reading the PIT/HPET and waiting for a wrap
 * around to find out, that a tick has elapsed. I have a box, where the PIT
 * readout is broken, so it never gets out of the wait loop again. This was
 * also reported by others.
 *
 * Monitoring the jiffies value is inaccurate and the clockevents
 * infrastructure allows us to do a simple substitution of the interrupt
 * handler.
 *
 * The calibration routine also uses the pm_timer when possible, as the PIT
 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
 * back to normal later in the boot process).
 */

#define LAPIC_CAL_LOOPS		(HZ/10)

static __initdata int lapic_cal_loops = -1;
static __initdata long lapic_cal_t1, lapic_cal_t2;
static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;

/*
 * Temporary interrupt handler.
 */
static void __init lapic_cal_handler(struct clock_event_device *dev)
{
	unsigned long long tsc = 0;
	long tapic = apic_read(APIC_TMCCT);
	unsigned long pm = acpi_pm_read_early();

	if (cpu_has_tsc)
		rdtscll(tsc);

	switch (lapic_cal_loops++) {
	case 0:
		lapic_cal_t1 = tapic;
		lapic_cal_tsc1 = tsc;
		lapic_cal_pm1 = pm;
		lapic_cal_j1 = jiffies;
		break;

	case LAPIC_CAL_LOOPS:
		lapic_cal_t2 = tapic;
		lapic_cal_tsc2 = tsc;
		if (pm < lapic_cal_pm1)
			pm += ACPI_PM_OVRRUN;
		lapic_cal_pm2 = pm;
		lapic_cal_j2 = jiffies;
		break;
	}
}

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static int __init
calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
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{
	const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
	const long pm_thresh = pm_100ms / 100;
	unsigned long mult;
	u64 res;

#ifndef CONFIG_X86_PM_TIMER
	return -1;
#endif

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	apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
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	/* Check, if the PM timer is available */
	if (!deltapm)
		return -1;

	mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);

	if (deltapm > (pm_100ms - pm_thresh) &&
	    deltapm < (pm_100ms + pm_thresh)) {
Y
Yasuaki Ishimatsu 已提交
610
		apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
611 612 613 614 615 616
		return 0;
	}

	res = (((u64)deltapm) *  mult) >> 22;
	do_div(res, 1000000);
	pr_warning("APIC calibration not consistent "
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Yasuaki Ishimatsu 已提交
617
		   "with PM-Timer: %ldms instead of 100ms\n",(long)res);
618 619 620 621 622 623 624 625 626 627 628

	/* Correct the lapic counter value */
	res = (((u64)(*delta)) * pm_100ms);
	do_div(res, deltapm);
	pr_info("APIC delta adjusted to PM-Timer: "
		"%lu (%ld)\n", (unsigned long)res, *delta);
	*delta = (long)res;

	/* Correct the tsc counter value */
	if (cpu_has_tsc) {
		res = (((u64)(*deltatsc)) * pm_100ms);
629
		do_div(res, deltapm);
630
		apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
631
					  "PM-Timer: %lu (%ld)\n",
632 633
					(unsigned long)res, *deltatsc);
		*deltatsc = (long)res;
634 635 636 637 638
	}

	return 0;
}

639 640 641 642 643
static int __init calibrate_APIC_clock(void)
{
	struct clock_event_device *levt = &__get_cpu_var(lapic_events);
	void (*real_handler)(struct clock_event_device *dev);
	unsigned long deltaj;
644
	long delta, deltatsc;
645 646
	int pm_referenced = 0;

647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665
	/**
	 * check if lapic timer has already been calibrated by platform
	 * specific routine, such as tsc calibration code. if so, we just fill
	 * in the clockevent structure and return.
	 */

	if (lapic_timer_frequency) {
		apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
				lapic_timer_frequency);
		lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
					TICK_NSEC, lapic_clockevent.shift);
		lapic_clockevent.max_delta_ns =
			clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
		lapic_clockevent.min_delta_ns =
			clockevent_delta2ns(0xF, &lapic_clockevent);
		lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
		return 0;
	}

666 667 668 669 670 671 672
	local_irq_disable();

	/* Replace the global interrupt handler */
	real_handler = global_clock_event->event_handler;
	global_clock_event->event_handler = lapic_cal_handler;

	/*
C
Cyrill Gorcunov 已提交
673
	 * Setup the APIC counter to maximum. There is no way the lapic
674 675
	 * can underflow in the 100ms detection time frame
	 */
C
Cyrill Gorcunov 已提交
676
	__setup_APIC_LVTT(0xffffffff, 0, 0);
677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692

	/* Let the interrupts run */
	local_irq_enable();

	while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
		cpu_relax();

	local_irq_disable();

	/* Restore the real event handler */
	global_clock_event->event_handler = real_handler;

	/* Build delta t1-t2 as apic timer counts down */
	delta = lapic_cal_t1 - lapic_cal_t2;
	apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);

693 694
	deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);

695 696
	/* we trust the PM based calibration if possible */
	pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
697
					&delta, &deltatsc);
698 699 700 701 702

	/* Calculate the scaled math multiplication factor */
	lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
				       lapic_clockevent.shift);
	lapic_clockevent.max_delta_ns =
703
		clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
704 705 706
	lapic_clockevent.min_delta_ns =
		clockevent_delta2ns(0xF, &lapic_clockevent);

707
	lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
708 709

	apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
710
	apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
711
	apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
712
		    lapic_timer_frequency);
713 714 715 716

	if (cpu_has_tsc) {
		apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
			    "%ld.%04ld MHz.\n",
717 718
			    (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
			    (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
719 720 721 722
	}

	apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
		    "%u.%04u MHz.\n",
723 724
		    lapic_timer_frequency / (1000000 / HZ),
		    lapic_timer_frequency % (1000000 / HZ));
725 726 727 728

	/*
	 * Do a sanity check on the APIC calibration result
	 */
729
	if (lapic_timer_frequency < (1000000 / HZ)) {
730
		local_irq_enable();
731
		pr_warning("APIC frequency too slow, disabling apic timer\n");
732 733 734 735 736
		return -1;
	}

	levt->features &= ~CLOCK_EVT_FEAT_DUMMY;

737 738 739 740
	/*
	 * PM timer calibration failed or not turned on
	 * so lets try APIC timer based calibration
	 */
741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772
	if (!pm_referenced) {
		apic_printk(APIC_VERBOSE, "... verify APIC timer\n");

		/*
		 * Setup the apic timer manually
		 */
		levt->event_handler = lapic_cal_handler;
		lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
		lapic_cal_loops = -1;

		/* Let the interrupts run */
		local_irq_enable();

		while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
			cpu_relax();

		/* Stop the lapic timer */
		lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);

		/* Jiffies delta */
		deltaj = lapic_cal_j2 - lapic_cal_j1;
		apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);

		/* Check, if the jiffies result is consistent */
		if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
			apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
		else
			levt->features |= CLOCK_EVT_FEAT_DUMMY;
	} else
		local_irq_enable();

	if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
773
		pr_warning("APIC timer disabled due to verification failure\n");
774 775 776 777 778 779
			return -1;
	}

	return 0;
}

H
Hiroshi Shimamoto 已提交
780 781 782 783 784
/*
 * Setup the boot APIC
 *
 * Calibrate and verify the result.
 */
785 786 787
void __init setup_boot_APIC_clock(void)
{
	/*
788 789 790 791
	 * The local apic timer can be disabled via the kernel
	 * commandline or from the CPU detection code. Register the lapic
	 * timer as a dummy clock event source on SMP systems, so the
	 * broadcast mechanism is used. On UP systems simply ignore it.
792 793
	 */
	if (disable_apic_timer) {
794
		pr_info("Disabling APIC timer\n");
795
		/* No broadcast on UP ! */
796 797
		if (num_possible_cpus() > 1) {
			lapic_clockevent.mult = 1;
798
			setup_APIC_timer();
799
		}
800 801 802
		return;
	}

803 804 805
	apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
		    "calibrating APIC timer ...\n");

806
	if (calibrate_APIC_clock()) {
807 808 809 810 811 812
		/* No broadcast on UP ! */
		if (num_possible_cpus() > 1)
			setup_APIC_timer();
		return;
	}

813 814 815 816 817
	/*
	 * If nmi_watchdog is set to IO_APIC, we need the
	 * PIT/HPET going.  Otherwise register lapic as a dummy
	 * device.
	 */
818
	lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
819

820
	/* Setup the lapic or request the broadcast */
821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848
	setup_APIC_timer();
}

void __cpuinit setup_secondary_APIC_clock(void)
{
	setup_APIC_timer();
}

/*
 * The guts of the apic timer interrupt
 */
static void local_apic_timer_interrupt(void)
{
	int cpu = smp_processor_id();
	struct clock_event_device *evt = &per_cpu(lapic_events, cpu);

	/*
	 * Normally we should not be here till LAPIC has been initialized but
	 * in some cases like kdump, its possible that there is a pending LAPIC
	 * timer interrupt from previous kernel's context and is delivered in
	 * new kernel the moment interrupts are enabled.
	 *
	 * Interrupts are enabled early and LAPIC is setup much later, hence
	 * its possible that when we get here evt->event_handler is NULL.
	 * Check for event_handler being NULL and discard the interrupt as
	 * spurious.
	 */
	if (!evt->event_handler) {
849
		pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
850 851 852 853 854 855 856 857
		/* Switch it off */
		lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
		return;
	}

	/*
	 * the NMI deadlock-detector uses this.
	 */
858
	inc_irq_stat(apic_timer_irqs);
859 860 861 862 863 864 865 866 867 868 869 870

	evt->event_handler(evt);
}

/*
 * Local APIC timer interrupt. This is the most natural way for doing
 * local interrupts, but local timer interrupts can be emulated by
 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
 *
 * [ if a single-CPU system runs an SMP kernel then we call the local
 *   interrupt as well. Thus we cannot inline the local irq ... ]
 */
871
void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888
{
	struct pt_regs *old_regs = set_irq_regs(regs);

	/*
	 * NOTE! We'd better ACK the irq immediately,
	 * because timer handling can be slow.
	 */
	ack_APIC_irq();
	/*
	 * update_process_times() expects us to have done irq_enter().
	 * Besides, if we don't timer interrupts ignore the global
	 * interrupt lock, which is the WrongThing (tm) to do.
	 */
	exit_idle();
	irq_enter();
	local_apic_timer_interrupt();
	irq_exit();
889

890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910
	set_irq_regs(old_regs);
}

int setup_profiling_timer(unsigned int multiplier)
{
	return -EINVAL;
}

/*
 * Local APIC start and shutdown
 */

/**
 * clear_local_APIC - shutdown the local APIC
 *
 * This is called, when a CPU is disabled and before rebooting, so the state of
 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
 * leftovers during boot.
 */
void clear_local_APIC(void)
{
911
	int maxlvt;
912 913
	u32 v;

914
	/* APIC hasn't been mapped yet */
915
	if (!x2apic_mode && !apic_phys)
916 917 918
		return;

	maxlvt = lapic_get_maxlvt();
919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941
	/*
	 * Masking an LVT entry can trigger a local APIC error
	 * if the vector is zero. Mask LVTERR first to prevent this.
	 */
	if (maxlvt >= 3) {
		v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
		apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
	}
	/*
	 * Careful: we have to set masks only first to deassert
	 * any level-triggered sources.
	 */
	v = apic_read(APIC_LVTT);
	apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
	v = apic_read(APIC_LVT0);
	apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
	v = apic_read(APIC_LVT1);
	apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
	if (maxlvt >= 4) {
		v = apic_read(APIC_LVTPC);
		apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
	}

942
	/* lets not touch this if we didn't frob it */
943
#ifdef CONFIG_X86_THERMAL_VECTOR
944 945 946 947 948
	if (maxlvt >= 5) {
		v = apic_read(APIC_LVTTHMR);
		apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
	}
#endif
949 950 951 952 953 954 955 956
#ifdef CONFIG_X86_MCE_INTEL
	if (maxlvt >= 6) {
		v = apic_read(APIC_LVTCMCI);
		if (!(v & APIC_LVT_MASKED))
			apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
	}
#endif

957 958 959 960 961 962 963 964 965 966
	/*
	 * Clean APIC state for other OSs:
	 */
	apic_write(APIC_LVTT, APIC_LVT_MASKED);
	apic_write(APIC_LVT0, APIC_LVT_MASKED);
	apic_write(APIC_LVT1, APIC_LVT_MASKED);
	if (maxlvt >= 3)
		apic_write(APIC_LVTERR, APIC_LVT_MASKED);
	if (maxlvt >= 4)
		apic_write(APIC_LVTPC, APIC_LVT_MASKED);
967 968 969 970 971 972 973 974

	/* Integrated APIC (!82489DX) ? */
	if (lapic_is_integrated()) {
		if (maxlvt > 3)
			/* Clear ESR due to Pentium errata 3AP and 11AP */
			apic_write(APIC_ESR, 0);
		apic_read(APIC_ESR);
	}
975 976 977 978 979 980 981 982 983
}

/**
 * disable_local_APIC - clear and disable the local APIC
 */
void disable_local_APIC(void)
{
	unsigned int value;

984
	/* APIC hasn't been mapped yet */
985
	if (!x2apic_mode && !apic_phys)
986 987
		return;

988 989 990 991 992 993 994 995 996
	clear_local_APIC();

	/*
	 * Disable APIC (implies clearing of registers
	 * for 82489DX!).
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_SPIV_APIC_ENABLED;
	apic_write(APIC_SPIV, value);
997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010

#ifdef CONFIG_X86_32
	/*
	 * When LAPIC was disabled by the BIOS and enabled by the kernel,
	 * restore the disabled state.
	 */
	if (enabled_via_apicbase) {
		unsigned int l, h;

		rdmsr(MSR_IA32_APICBASE, l, h);
		l &= ~MSR_IA32_APICBASE_ENABLE;
		wrmsr(MSR_IA32_APICBASE, l, h);
	}
#endif
1011 1012
}

1013 1014 1015 1016 1017 1018
/*
 * If Linux enabled the LAPIC against the BIOS default disable it down before
 * re-entering the BIOS on shutdown.  Otherwise the BIOS may get confused and
 * not power-off.  Additionally clear all LVT entries before disable_local_APIC
 * for the case where Linux didn't enable the LAPIC.
 */
1019 1020 1021 1022
void lapic_shutdown(void)
{
	unsigned long flags;

1023
	if (!cpu_has_apic && !apic_from_smp_config())
1024 1025 1026 1027
		return;

	local_irq_save(flags);

1028 1029 1030 1031 1032 1033 1034
#ifdef CONFIG_X86_32
	if (!enabled_via_apicbase)
		clear_local_APIC();
	else
#endif
		disable_local_APIC();

1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077

	local_irq_restore(flags);
}

/*
 * This is to verify that we're looking at a real local APIC.
 * Check these against your board if the CPUs aren't getting
 * started for no apparent reason.
 */
int __init verify_local_APIC(void)
{
	unsigned int reg0, reg1;

	/*
	 * The version register is read-only in a real APIC.
	 */
	reg0 = apic_read(APIC_LVR);
	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
	apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
	reg1 = apic_read(APIC_LVR);
	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);

	/*
	 * The two version reads above should print the same
	 * numbers.  If the second one is different, then we
	 * poke at a non-APIC.
	 */
	if (reg1 != reg0)
		return 0;

	/*
	 * Check if the version looks reasonably.
	 */
	reg1 = GET_APIC_VERSION(reg0);
	if (reg1 == 0x00 || reg1 == 0xff)
		return 0;
	reg1 = lapic_get_maxlvt();
	if (reg1 < 0x02 || reg1 == 0xff)
		return 0;

	/*
	 * The ID register is read/write in a real APIC.
	 */
1078
	reg0 = apic_read(APIC_ID);
1079
	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
1080
	apic_write(APIC_ID, reg0 ^ apic->apic_id_mask);
1081
	reg1 = apic_read(APIC_ID);
1082 1083
	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
	apic_write(APIC_ID, reg0);
1084
	if (reg1 != (reg0 ^ apic->apic_id_mask))
1085 1086 1087
		return 0;

	/*
L
Linus Torvalds 已提交
1088 1089 1090 1091 1092
	 * The next two are just to see if we have sane values.
	 * They're only really relevant if we're in Virtual Wire
	 * compatibility mode, but most boxes are anymore.
	 */
	reg0 = apic_read(APIC_LVT0);
1093
	apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
L
Linus Torvalds 已提交
1094 1095 1096 1097 1098 1099
	reg1 = apic_read(APIC_LVT1);
	apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);

	return 1;
}

1100 1101 1102
/**
 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
 */
L
Linus Torvalds 已提交
1103 1104
void __init sync_Arb_IDs(void)
{
C
Cyrill Gorcunov 已提交
1105 1106 1107 1108 1109
	/*
	 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
	 * needed on AMD.
	 */
	if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
L
Linus Torvalds 已提交
1110 1111 1112 1113 1114 1115 1116 1117
		return;

	/*
	 * Wait for idle.
	 */
	apic_wait_icr_idle();

	apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1118 1119
	apic_write(APIC_ICR, APIC_DEST_ALLINC |
			APIC_INT_LEVELTRIG | APIC_DM_INIT);
L
Linus Torvalds 已提交
1120 1121 1122 1123 1124 1125 1126
}

/*
 * An initial setup of the virtual wire mode.
 */
void __init init_bsp_APIC(void)
{
1127
	unsigned int value;
L
Linus Torvalds 已提交
1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146

	/*
	 * Don't do the setup now if we have a SMP BIOS as the
	 * through-I/O-APIC virtual wire mode might be active.
	 */
	if (smp_found_config || !cpu_has_apic)
		return;

	/*
	 * Do not trust the local APIC being empty at bootup.
	 */
	clear_local_APIC();

	/*
	 * Enable APIC.
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	value |= APIC_SPIV_APIC_ENABLED;
1147 1148 1149 1150 1151 1152 1153 1154 1155

#ifdef CONFIG_X86_32
	/* This bit is reserved on P4/Xeon and should be cleared */
	if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
	    (boot_cpu_data.x86 == 15))
		value &= ~APIC_SPIV_FOCUS_DISABLED;
	else
#endif
		value |= APIC_SPIV_FOCUS_DISABLED;
L
Linus Torvalds 已提交
1156
	value |= SPURIOUS_APIC_VECTOR;
1157
	apic_write(APIC_SPIV, value);
L
Linus Torvalds 已提交
1158 1159 1160 1161

	/*
	 * Set up the virtual wire mode.
	 */
1162
	apic_write(APIC_LVT0, APIC_DM_EXTINT);
L
Linus Torvalds 已提交
1163
	value = APIC_DM_NMI;
1164 1165
	if (!lapic_is_integrated())		/* 82489DX */
		value |= APIC_LVT_LEVEL_TRIGGER;
1166
	apic_write(APIC_LVT1, value);
L
Linus Torvalds 已提交
1167 1168
}

1169 1170
static void __cpuinit lapic_setup_esr(void)
{
1171 1172 1173
	unsigned int oldvalue, value, maxlvt;

	if (!lapic_is_integrated()) {
1174
		pr_info("No ESR for 82489DX.\n");
1175 1176
		return;
	}
1177

1178
	if (apic->disable_esr) {
1179
		/*
1180 1181 1182 1183
		 * Something untraceable is creating bad interrupts on
		 * secondary quads ... for the moment, just leave the
		 * ESR disabled - we can't do anything useful with the
		 * errors anyway - mbligh
1184
		 */
1185
		pr_info("Leaving ESR disabled.\n");
1186
		return;
1187
	}
1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207

	maxlvt = lapic_get_maxlvt();
	if (maxlvt > 3)		/* Due to the Pentium erratum 3AP. */
		apic_write(APIC_ESR, 0);
	oldvalue = apic_read(APIC_ESR);

	/* enables sending errors */
	value = ERROR_APIC_VECTOR;
	apic_write(APIC_LVTERR, value);

	/*
	 * spec says clear errors after enabling vector.
	 */
	if (maxlvt > 3)
		apic_write(APIC_ESR, 0);
	value = apic_read(APIC_ESR);
	if (value != oldvalue)
		apic_printk(APIC_VERBOSE, "ESR value before enabling "
			"vector: 0x%08x  after: 0x%08x\n",
			oldvalue, value);
1208 1209
}

1210 1211
/**
 * setup_local_APIC - setup the local APIC
1212 1213 1214
 *
 * Used to setup local APIC while initializing BSP or bringin up APs.
 * Always called with preemption disabled.
1215 1216
 */
void __cpuinit setup_local_APIC(void)
L
Linus Torvalds 已提交
1217
{
1218
	int cpu = smp_processor_id();
1219 1220 1221 1222 1223 1224 1225
	unsigned int value, queued;
	int i, j, acked = 0;
	unsigned long long tsc = 0, ntsc;
	long long max_loops = cpu_khz;

	if (cpu_has_tsc)
		rdtscll(tsc);
L
Linus Torvalds 已提交
1226

J
Jan Beulich 已提交
1227
	if (disable_apic) {
1228
		disable_ioapic_support();
J
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1229 1230 1231
		return;
	}

1232 1233
#ifdef CONFIG_X86_32
	/* Pound the ESR really hard over the head with a big hammer - mbligh */
1234
	if (lapic_is_integrated() && apic->disable_esr) {
1235 1236 1237 1238 1239 1240
		apic_write(APIC_ESR, 0);
		apic_write(APIC_ESR, 0);
		apic_write(APIC_ESR, 0);
		apic_write(APIC_ESR, 0);
	}
#endif
1241
	perf_events_lapic_init();
1242

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1243 1244 1245 1246
	/*
	 * Double-check whether this APIC is really registered.
	 * This is meaningless in clustered apic mode, so we skip it.
	 */
1247
	BUG_ON(!apic->apic_id_registered());
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1248 1249 1250 1251 1252 1253

	/*
	 * Intel recommends to set DFR, LDR and TPR before enabling
	 * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
	 * document number 292116).  So here it goes...
	 */
1254
	apic->init_apic_ldr();
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1255

1256 1257
#ifdef CONFIG_X86_32
	/*
1258 1259 1260
	 * APIC LDR is initialized.  If logical_apicid mapping was
	 * initialized during get_smp_config(), make sure it matches the
	 * actual value.
1261
	 */
1262 1263 1264
	i = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
	WARN_ON(i != BAD_APICID && i != logical_smp_processor_id());
	/* always use the value from LDR */
1265 1266
	early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
		logical_smp_processor_id();
1267 1268 1269 1270 1271 1272 1273 1274

	/*
	 * Some NUMA implementations (NUMAQ) don't initialize apicid to
	 * node mapping during NUMA init.  Now that logical apicid is
	 * guaranteed to be known, give it another chance.  This is already
	 * a bit too late - percpu allocation has already happened without
	 * proper NUMA affinity.
	 */
1275 1276 1277
	if (apic->x86_32_numa_cpu_node)
		set_apicid_to_node(early_per_cpu(x86_cpu_to_apicid, cpu),
				   apic->x86_32_numa_cpu_node(cpu));
1278 1279
#endif

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1280 1281 1282 1283 1284 1285
	/*
	 * Set Task Priority to 'accept all'. We never change this
	 * later on.
	 */
	value = apic_read(APIC_TASKPRI);
	value &= ~APIC_TPRI_MASK;
1286
	apic_write(APIC_TASKPRI, value);
L
Linus Torvalds 已提交
1287

1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298
	/*
	 * After a crash, we no longer service the interrupts and a pending
	 * interrupt from previous kernel might still have ISR bit set.
	 *
	 * Most probably by now CPU has serviced that pending interrupt and
	 * it might not have done the ack_APIC_irq() because it thought,
	 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
	 * does not clear the ISR bit and cpu thinks it has already serivced
	 * the interrupt. Hence a vector might get locked. It was noticed
	 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
	 */
1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311
	do {
		queued = 0;
		for (i = APIC_ISR_NR - 1; i >= 0; i--)
			queued |= apic_read(APIC_IRR + i*0x10);

		for (i = APIC_ISR_NR - 1; i >= 0; i--) {
			value = apic_read(APIC_ISR + i*0x10);
			for (j = 31; j >= 0; j--) {
				if (value & (1<<j)) {
					ack_APIC_irq();
					acked++;
				}
			}
1312
		}
1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324
		if (acked > 256) {
			printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
			       acked);
			break;
		}
		if (cpu_has_tsc) {
			rdtscll(ntsc);
			max_loops = (cpu_khz << 10) - (ntsc - tsc);
		} else
			max_loops--;
	} while (queued && max_loops > 0);
	WARN_ON(max_loops <= 0);
1325

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1326 1327 1328 1329 1330 1331 1332 1333 1334 1335
	/*
	 * Now that we are all set up, enable the APIC
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	/*
	 * Enable APIC
	 */
	value |= APIC_SPIV_APIC_ENABLED;

1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363
#ifdef CONFIG_X86_32
	/*
	 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
	 * certain networking cards. If high frequency interrupts are
	 * happening on a particular IOAPIC pin, plus the IOAPIC routing
	 * entry is masked/unmasked at a high rate as well then sooner or
	 * later IOAPIC line gets 'stuck', no more interrupts are received
	 * from the device. If focus CPU is disabled then the hang goes
	 * away, oh well :-(
	 *
	 * [ This bug can be reproduced easily with a level-triggered
	 *   PCI Ne2000 networking cards and PII/PIII processors, dual
	 *   BX chipset. ]
	 */
	/*
	 * Actually disabling the focus CPU check just makes the hang less
	 * frequent as it makes the interrupt distributon model be more
	 * like LRU than MRU (the short-term load is more even across CPUs).
	 * See also the comment in end_level_ioapic_irq().  --macro
	 */

	/*
	 * - enable focus processor (bit==0)
	 * - 64bit mode always use processor focus
	 *   so no need to set it
	 */
	value &= ~APIC_SPIV_FOCUS_DISABLED;
#endif
1364

L
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1365 1366 1367 1368
	/*
	 * Set spurious IRQ vector
	 */
	value |= SPURIOUS_APIC_VECTOR;
1369
	apic_write(APIC_SPIV, value);
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Linus Torvalds 已提交
1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381

	/*
	 * Set up LVT0, LVT1:
	 *
	 * set up through-local-APIC on the BP's LINT0. This is not
	 * strictly necessary in pure symmetric-IO mode, but sometimes
	 * we delegate interrupts to the 8259A.
	 */
	/*
	 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
	 */
	value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1382
	if (!cpu && (pic_mode || !value)) {
L
Linus Torvalds 已提交
1383
		value = APIC_DM_EXTINT;
1384
		apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
L
Linus Torvalds 已提交
1385 1386
	} else {
		value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1387
		apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
L
Linus Torvalds 已提交
1388
	}
1389
	apic_write(APIC_LVT0, value);
L
Linus Torvalds 已提交
1390 1391 1392 1393

	/*
	 * only the BP should see the LINT1 NMI signal, obviously.
	 */
1394
	if (!cpu)
L
Linus Torvalds 已提交
1395 1396 1397
		value = APIC_DM_NMI;
	else
		value = APIC_DM_NMI | APIC_LVT_MASKED;
1398 1399
	if (!lapic_is_integrated())		/* 82489DX */
		value |= APIC_LVT_LEVEL_TRIGGER;
1400
	apic_write(APIC_LVT1, value);
1401

1402 1403
#ifdef CONFIG_X86_MCE_INTEL
	/* Recheck CMCI information after local APIC is up on CPU #0 */
1404
	if (!cpu)
1405 1406
		cmci_recheck();
#endif
1407
}
L
Linus Torvalds 已提交
1408

1409 1410 1411
void __cpuinit end_local_APIC_setup(void)
{
	lapic_setup_esr();
1412 1413

#ifdef CONFIG_X86_32
1414 1415 1416 1417 1418 1419 1420
	{
		unsigned int value;
		/* Disable the local apic timer */
		value = apic_read(APIC_LVTT);
		value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
		apic_write(APIC_LVTT, value);
	}
1421 1422
#endif

1423
	apic_pm_activate();
1424 1425 1426 1427 1428
}

void __init bsp_end_local_APIC_setup(void)
{
	end_local_APIC_setup();
1429 1430 1431 1432 1433

	/*
	 * Now that local APIC setup is completed for BP, configure the fault
	 * handling for interrupt remapping.
	 */
1434
	if (intr_remapping_enabled)
1435 1436
		enable_drhd_fault_handling();

L
Linus Torvalds 已提交
1437 1438
}

Y
Yinghai Lu 已提交
1439
#ifdef CONFIG_X86_X2APIC
1440 1441
void check_x2apic(void)
{
1442
	if (x2apic_enabled()) {
1443
		pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1444
		x2apic_preenabled = x2apic_mode = 1;
1445 1446 1447 1448 1449 1450 1451
	}
}

void enable_x2apic(void)
{
	int msr, msr2;

1452
	if (!x2apic_mode)
Y
Yinghai Lu 已提交
1453 1454
		return;

1455 1456
	rdmsr(MSR_IA32_APICBASE, msr, msr2);
	if (!(msr & X2APIC_ENABLE)) {
1457
		printk_once(KERN_INFO "Enabling x2apic\n");
1458
		wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, msr2);
1459 1460
	}
}
1461
#endif /* CONFIG_X86_X2APIC */
1462

1463
int __init enable_IR(void)
1464
{
1465
#ifdef CONFIG_IRQ_REMAP
1466 1467
	if (!intr_remapping_supported()) {
		pr_debug("intr-remapping not supported\n");
1468
		return -1;
1469 1470
	}

1471 1472 1473
	if (!x2apic_preenabled && skip_ioapic_setup) {
		pr_info("Skipped enabling intr-remap because of skipping "
			"io-apic setup\n");
1474
		return -1;
1475 1476
	}

1477
	return enable_intr_remapping();
1478
#endif
1479
	return -1;
1480 1481 1482 1483 1484 1485
}

void __init enable_IR_x2apic(void)
{
	unsigned long flags;
	int ret, x2apic_enabled = 0;
Y
Yinghai Lu 已提交
1486
	int dmar_table_init_ret;
1487 1488

	dmar_table_init_ret = dmar_table_init();
Y
Yinghai Lu 已提交
1489 1490
	if (dmar_table_init_ret && !x2apic_supported())
		return;
1491

1492
	ret = save_ioapic_entries();
1493
	if (ret) {
1494
		pr_info("Saving IO-APIC state failed: %d\n", ret);
1495
		goto out;
1496
	}
1497

1498
	local_irq_save(flags);
1499
	legacy_pic->mask_all();
1500
	mask_ioapic_entries();
1501

1502
	if (dmar_table_init_ret)
1503
		ret = -1;
1504 1505 1506
	else
		ret = enable_IR();

1507
	if (ret < 0) {
1508 1509 1510
		/* IR is required if there is APIC ID > 255 even when running
		 * under KVM
		 */
1511 1512
		if (max_physical_apicid > 255 ||
		    !hypervisor_x2apic_available())
1513 1514 1515 1516 1517 1518 1519
			goto nox2apic;
		/*
		 * without IR all CPUs can be addressed by IOAPIC/MSI
		 * only in physical mode
		 */
		x2apic_force_phys();
	}
1520

1521 1522 1523
	if (ret == IRQ_REMAP_XAPIC_MODE)
		goto nox2apic;

1524
	x2apic_enabled = 1;
1525

1526 1527
	if (x2apic_supported() && !x2apic_mode) {
		x2apic_mode = 1;
1528
		enable_x2apic();
1529
		pr_info("Enabled x2apic\n");
1530
	}
1531

1532
nox2apic:
1533
	if (ret < 0) /* IR enabling failed */
1534
		restore_ioapic_entries();
1535
	legacy_pic->restore_mask();
1536 1537
	local_irq_restore(flags);

1538
out:
1539
	if (x2apic_enabled || !x2apic_supported())
1540 1541 1542
		return;

	if (x2apic_preenabled)
1543
		panic("x2apic: enabled by BIOS but kernel init failed.");
1544 1545 1546 1547
	else if (ret == IRQ_REMAP_XAPIC_MODE)
		pr_info("x2apic not enabled, IRQ remapping is in xapic mode\n");
	else if (ret < 0)
		pr_info("x2apic not enabled, IRQ remapping init failed\n");
1548
}
1549

1550
#ifdef CONFIG_X86_64
L
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1551 1552 1553 1554
/*
 * Detect and enable local APICs on non-SMP boards.
 * Original code written by Keir Fraser.
 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1555
 * not correctly set up (usually the APIC timer won't work etc.)
L
Linus Torvalds 已提交
1556
 */
1557
static int __init detect_init_APIC(void)
L
Linus Torvalds 已提交
1558 1559
{
	if (!cpu_has_apic) {
1560
		pr_info("No local APIC present\n");
L
Linus Torvalds 已提交
1561 1562 1563 1564 1565 1566
		return -1;
	}

	mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
	return 0;
}
1567
#else
1568

1569
static int __init apic_verify(void)
1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593
{
	u32 features, h, l;

	/*
	 * The APIC feature bit should now be enabled
	 * in `cpuid'
	 */
	features = cpuid_edx(1);
	if (!(features & (1 << X86_FEATURE_APIC))) {
		pr_warning("Could not enable APIC!\n");
		return -1;
	}
	set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
	mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;

	/* The BIOS may have set up the APIC at some other address */
	rdmsr(MSR_IA32_APICBASE, l, h);
	if (l & MSR_IA32_APICBASE_ENABLE)
		mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;

	pr_info("Found and enabled local APIC!\n");
	return 0;
}

1594
int __init apic_force_enable(unsigned long addr)
1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609
{
	u32 h, l;

	if (disable_apic)
		return -1;

	/*
	 * Some BIOSes disable the local APIC in the APIC_BASE
	 * MSR. This can only be done in software for Intel P6 or later
	 * and AMD K7 (Model > 1) or later.
	 */
	rdmsr(MSR_IA32_APICBASE, l, h);
	if (!(l & MSR_IA32_APICBASE_ENABLE)) {
		pr_info("Local APIC disabled by BIOS -- reenabling.\n");
		l &= ~MSR_IA32_APICBASE_BASE;
1610
		l |= MSR_IA32_APICBASE_ENABLE | addr;
1611 1612 1613 1614 1615 1616
		wrmsr(MSR_IA32_APICBASE, l, h);
		enabled_via_apicbase = 1;
	}
	return apic_verify();
}

1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628
/*
 * Detect and initialize APIC
 */
static int __init detect_init_APIC(void)
{
	/* Disabled by kernel option? */
	if (disable_apic)
		return -1;

	switch (boot_cpu_data.x86_vendor) {
	case X86_VENDOR_AMD:
		if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1629
		    (boot_cpu_data.x86 >= 15))
1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646
			break;
		goto no_apic;
	case X86_VENDOR_INTEL:
		if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
		    (boot_cpu_data.x86 == 5 && cpu_has_apic))
			break;
		goto no_apic;
	default:
		goto no_apic;
	}

	if (!cpu_has_apic) {
		/*
		 * Over-ride BIOS and try to enable the local APIC only if
		 * "lapic" specified.
		 */
		if (!force_enable_local_apic) {
1647 1648
			pr_info("Local APIC disabled by BIOS -- "
				"you can enable it with \"lapic\"\n");
1649 1650
			return -1;
		}
1651
		if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1652 1653 1654 1655
			return -1;
	} else {
		if (apic_verify())
			return -1;
1656 1657 1658 1659 1660 1661 1662
	}

	apic_pm_activate();

	return 0;

no_apic:
1663
	pr_info("No local APIC present or hardware disabled\n");
1664 1665 1666
	return -1;
}
#endif
L
Linus Torvalds 已提交
1667

1668 1669 1670
/**
 * init_apic_mappings - initialize APIC mappings
 */
L
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1671 1672
void __init init_apic_mappings(void)
{
1673 1674
	unsigned int new_apicid;

1675
	if (x2apic_mode) {
1676
		boot_cpu_physical_apicid = read_apic_id();
1677 1678 1679
		return;
	}

1680
	/* If no local APIC can be found return early */
L
Linus Torvalds 已提交
1681
	if (!smp_found_config && detect_init_APIC()) {
1682 1683 1684 1685
		/* lets NOP'ify apic operations */
		pr_info("APIC: disable apic facility\n");
		apic_disable();
	} else {
L
Linus Torvalds 已提交
1686 1687
		apic_phys = mp_lapic_addr;

1688 1689 1690 1691
		/*
		 * acpi lapic path already maps that address in
		 * acpi_register_lapic_address()
		 */
1692
		if (!acpi_lapic && !smp_found_config)
1693
			register_lapic_address(apic_phys);
1694
	}
L
Linus Torvalds 已提交
1695 1696 1697 1698 1699

	/*
	 * Fetch the APIC ID of the BSP in case we have a
	 * default configuration (or the MP table is broken).
	 */
1700 1701 1702
	new_apicid = read_apic_id();
	if (boot_cpu_physical_apicid != new_apicid) {
		boot_cpu_physical_apicid = new_apicid;
1703 1704 1705 1706 1707 1708 1709
		/*
		 * yeah -- we lie about apic_version
		 * in case if apic was disabled via boot option
		 * but it's not a problem for SMP compiled kernel
		 * since smp_sanity_check is prepared for such a case
		 * and disable smp mode
		 */
1710 1711
		apic_version[new_apicid] =
			 GET_APIC_VERSION(apic_read(APIC_LVR));
1712
	}
L
Linus Torvalds 已提交
1713 1714
}

1715 1716 1717 1718
void __init register_lapic_address(unsigned long address)
{
	mp_lapic_addr = address;

1719 1720 1721 1722 1723
	if (!x2apic_mode) {
		set_fixmap_nocache(FIX_APIC_BASE, address);
		apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
			    APIC_BASE, mp_lapic_addr);
	}
1724 1725 1726 1727 1728 1729 1730
	if (boot_cpu_physical_apicid == -1U) {
		boot_cpu_physical_apicid  = read_apic_id();
		apic_version[boot_cpu_physical_apicid] =
			 GET_APIC_VERSION(apic_read(APIC_LVR));
	}
}

L
Linus Torvalds 已提交
1731
/*
1732 1733
 * This initializes the IO-APIC and APIC hardware if this is
 * a UP kernel.
L
Linus Torvalds 已提交
1734
 */
1735
int apic_version[MAX_LOCAL_APIC];
1736

1737
int __init APIC_init_uniprocessor(void)
L
Linus Torvalds 已提交
1738
{
1739
	if (disable_apic) {
1740
		pr_info("Apic disabled\n");
1741 1742
		return -1;
	}
J
Jan Beulich 已提交
1743
#ifdef CONFIG_X86_64
1744 1745
	if (!cpu_has_apic) {
		disable_apic = 1;
1746
		pr_info("Apic disabled by BIOS\n");
1747 1748
		return -1;
	}
Y
Yinghai Lu 已提交
1749 1750 1751 1752 1753 1754 1755 1756 1757
#else
	if (!smp_found_config && !cpu_has_apic)
		return -1;

	/*
	 * Complain if the BIOS pretends there is one.
	 */
	if (!cpu_has_apic &&
	    APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1758 1759
		pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
			boot_cpu_physical_apicid);
Y
Yinghai Lu 已提交
1760 1761 1762 1763
		return -1;
	}
#endif

1764
	default_setup_apic_routing();
1765

1766
	verify_local_APIC();
1767 1768
	connect_bsp_APIC();

Y
Yinghai Lu 已提交
1769
#ifdef CONFIG_X86_64
1770
	apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
Y
Yinghai Lu 已提交
1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781
#else
	/*
	 * Hack: In case of kdump, after a crash, kernel might be booting
	 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
	 * might be zero if read from MP tables. Get it from LAPIC.
	 */
# ifdef CONFIG_CRASH_DUMP
	boot_cpu_physical_apicid = read_apic_id();
# endif
#endif
	physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1782
	setup_local_APIC();
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Linus Torvalds 已提交
1783

1784
#ifdef CONFIG_X86_IO_APIC
1785 1786
	/*
	 * Now enable IO-APICs, actually call clear_IO_APIC
1787
	 * We need clear_IO_APIC before enabling error vector
1788 1789 1790
	 */
	if (!skip_ioapic_setup && nr_ioapics)
		enable_IO_APIC();
Y
Yinghai Lu 已提交
1791
#endif
1792

1793
	bsp_end_local_APIC_setup();
1794

Y
Yinghai Lu 已提交
1795
#ifdef CONFIG_X86_IO_APIC
1796 1797
	if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
		setup_IO_APIC();
1798
	else {
1799
		nr_ioapics = 0;
1800
	}
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Yinghai Lu 已提交
1801 1802
#endif

1803
	x86_init.timers.setup_percpu_clockev();
1804
	return 0;
L
Linus Torvalds 已提交
1805 1806 1807
}

/*
1808
 * Local APIC interrupts
L
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1809 1810
 */

1811 1812 1813
/*
 * This interrupt should _never_ happen with our APIC/SMP architecture
 */
1814
void smp_spurious_interrupt(struct pt_regs *regs)
L
Linus Torvalds 已提交
1815
{
1816 1817
	u32 v;

1818 1819
	exit_idle();
	irq_enter();
L
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1820
	/*
1821 1822 1823
	 * Check if this really is a spurious interrupt and ACK it
	 * if it is a vectored one.  Just in case...
	 * Spurious interrupts should not be ACKed.
L
Linus Torvalds 已提交
1824
	 */
1825 1826 1827
	v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
	if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
		ack_APIC_irq();
1828

1829 1830
	inc_irq_stat(irq_spurious_count);

1831
	/* see sw-dev-man vol 3, chapter 7.4.13.5 */
1832 1833
	pr_info("spurious APIC interrupt on CPU#%d, "
		"should never happen.\n", smp_processor_id());
1834 1835
	irq_exit();
}
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Linus Torvalds 已提交
1836

1837 1838 1839
/*
 * This interrupt should never happen with our APIC/SMP architecture
 */
1840
void smp_error_interrupt(struct pt_regs *regs)
1841
{
1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853
	u32 v0, v1;
	u32 i = 0;
	static const char * const error_interrupt_reason[] = {
		"Send CS error",		/* APIC Error Bit 0 */
		"Receive CS error",		/* APIC Error Bit 1 */
		"Send accept error",		/* APIC Error Bit 2 */
		"Receive accept error",		/* APIC Error Bit 3 */
		"Redirectable IPI",		/* APIC Error Bit 4 */
		"Send illegal vector",		/* APIC Error Bit 5 */
		"Received illegal vector",	/* APIC Error Bit 6 */
		"Illegal register address",	/* APIC Error Bit 7 */
	};
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1854

1855 1856 1857
	exit_idle();
	irq_enter();
	/* First tickle the hardware, only then report what went on. -- REW */
1858
	v0 = apic_read(APIC_ESR);
1859 1860 1861 1862
	apic_write(APIC_ESR, 0);
	v1 = apic_read(APIC_ESR);
	ack_APIC_irq();
	atomic_inc(&irq_err_count);
1863

1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876
	apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x(%02x)",
		    smp_processor_id(), v0 , v1);

	v1 = v1 & 0xff;
	while (v1) {
		if (v1 & 0x1)
			apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
		i++;
		v1 >>= 1;
	};

	apic_printk(APIC_DEBUG, KERN_CONT "\n");

1877
	irq_exit();
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1878 1879
}

1880
/**
1881 1882
 * connect_bsp_APIC - attach the APIC to the interrupt system
 */
1883 1884
void __init connect_bsp_APIC(void)
{
1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896
#ifdef CONFIG_X86_32
	if (pic_mode) {
		/*
		 * Do not trust the local APIC being empty at bootup.
		 */
		clear_local_APIC();
		/*
		 * PIC mode, enable APIC mode in the IMCR, i.e.  connect BSP's
		 * local APIC to INT and NMI lines.
		 */
		apic_printk(APIC_VERBOSE, "leaving PIC mode, "
				"enabling APIC mode.\n");
1897
		imcr_pic_to_apic();
1898 1899
	}
#endif
1900 1901
	if (apic->enable_apic_mode)
		apic->enable_apic_mode();
1902 1903
}

1904 1905 1906 1907 1908 1909 1910
/**
 * disconnect_bsp_APIC - detach the APIC from the interrupt system
 * @virt_wire_setup:	indicates, whether virtual wire mode is selected
 *
 * Virtual wire mode is necessary to deliver legacy interrupts even when the
 * APIC is disabled.
 */
1911
void disconnect_bsp_APIC(int virt_wire_setup)
L
Linus Torvalds 已提交
1912
{
1913 1914
	unsigned int value;

1915 1916 1917 1918 1919 1920 1921 1922 1923 1924
#ifdef CONFIG_X86_32
	if (pic_mode) {
		/*
		 * Put the board back into PIC mode (has an effect only on
		 * certain older boards).  Note that APIC interrupts, including
		 * IPIs, won't work beyond this point!  The only exception are
		 * INIT IPIs.
		 */
		apic_printk(APIC_VERBOSE, "disabling APIC mode, "
				"entering PIC mode.\n");
1925
		imcr_apic_to_pic();
1926 1927 1928 1929
		return;
	}
#endif

1930
	/* Go back to Virtual Wire compatibility mode */
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Linus Torvalds 已提交
1931

1932 1933 1934 1935 1936 1937
	/* For the spurious interrupt use vector F, and enable it */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	value |= APIC_SPIV_APIC_ENABLED;
	value |= 0xf;
	apic_write(APIC_SPIV, value);
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Thomas Gleixner 已提交
1938

1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954
	if (!virt_wire_setup) {
		/*
		 * For LVT0 make it edge triggered, active high,
		 * external and enabled
		 */
		value = apic_read(APIC_LVT0);
		value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
		value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
		value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
		apic_write(APIC_LVT0, value);
	} else {
		/* Disable LVT0 */
		apic_write(APIC_LVT0, APIC_LVT_MASKED);
	}
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Thomas Gleixner 已提交
1955

1956 1957 1958 1959
	/*
	 * For LVT1 make it edge triggered, active high,
	 * nmi and enabled
	 */
1960 1961 1962 1963 1964 1965 1966
	value = apic_read(APIC_LVT1);
	value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
	value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
	value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
	apic_write(APIC_LVT1, value);
L
Linus Torvalds 已提交
1967 1968
}

1969 1970
void __cpuinit generic_processor_info(int apicid, int version)
{
1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990
	int cpu, max = nr_cpu_ids;
	bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
				phys_cpu_present_map);

	/*
	 * If boot cpu has not been detected yet, then only allow upto
	 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
	 */
	if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
	    apicid != boot_cpu_physical_apicid) {
		int thiscpu = max + disabled_cpus - 1;

		pr_warning(
			"ACPI: NR_CPUS/possible_cpus limit of %i almost"
			" reached. Keeping one slot for boot cpu."
			"  Processor %d/0x%x ignored.\n", max, thiscpu, apicid);

		disabled_cpus++;
		return;
	}
1991

1992 1993 1994 1995 1996 1997 1998 1999
	if (num_processors >= nr_cpu_ids) {
		int thiscpu = max + disabled_cpus;

		pr_warning(
			"ACPI: NR_CPUS/possible_cpus limit of %i reached."
			"  Processor %d/0x%x ignored.\n", max, thiscpu, apicid);

		disabled_cpus++;
2000 2001 2002 2003 2004 2005 2006 2007 2008
		return;
	}

	num_processors++;
	if (apicid == boot_cpu_physical_apicid) {
		/*
		 * x86_bios_cpu_apicid is required to have processors listed
		 * in same order as logical cpu numbers. Hence the first
		 * entry is BSP, and so on.
2009 2010
		 * boot_cpu_init() already hold bit 0 in cpu_present_mask
		 * for BSP.
2011 2012
		 */
		cpu = 0;
2013 2014 2015 2016 2017 2018 2019 2020 2021 2022
	} else
		cpu = cpumask_next_zero(-1, cpu_present_mask);

	/*
	 * Validate version
	 */
	if (version == 0x0) {
		pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
			   cpu, apicid);
		version = 0x10;
2023
	}
2024 2025 2026 2027 2028 2029 2030 2031
	apic_version[apicid] = version;

	if (version != apic_version[boot_cpu_physical_apicid]) {
		pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
			apic_version[boot_cpu_physical_apicid], cpu, version);
	}

	physid_set(apicid, phys_cpu_present_map);
2032 2033 2034
	if (apicid > max_physical_apicid)
		max_physical_apicid = apicid;

2035
#if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2036 2037
	early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
	early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2038
#endif
2039 2040 2041 2042
#ifdef CONFIG_X86_32
	early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
		apic->x86_32_early_logical_apicid(cpu);
#endif
2043 2044
	set_cpu_possible(cpu, true);
	set_cpu_present(cpu, true);
2045 2046
}

2047 2048 2049 2050
int hard_smp_processor_id(void)
{
	return read_apic_id();
}
I
Ingo Molnar 已提交
2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061

void default_init_apic_ldr(void)
{
	unsigned long val;

	apic_write(APIC_DFR, APIC_DFR_VALUE);
	val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
	val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
	apic_write(APIC_LDR, val);
}

2062
/*
2063
 * Power management
2064
 */
2065 2066 2067
#ifdef CONFIG_PM

static struct {
2068 2069 2070 2071 2072
	/*
	 * 'active' is true if the local APIC was enabled by us and
	 * not the BIOS; this signifies that we are also responsible
	 * for disabling it before entering apm/acpi suspend
	 */
2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089
	int active;
	/* r/w apic fields */
	unsigned int apic_id;
	unsigned int apic_taskpri;
	unsigned int apic_ldr;
	unsigned int apic_dfr;
	unsigned int apic_spiv;
	unsigned int apic_lvtt;
	unsigned int apic_lvtpc;
	unsigned int apic_lvt0;
	unsigned int apic_lvt1;
	unsigned int apic_lvterr;
	unsigned int apic_tmict;
	unsigned int apic_tdcr;
	unsigned int apic_thmr;
} apic_pm_state;

2090
static int lapic_suspend(void)
2091 2092 2093
{
	unsigned long flags;
	int maxlvt;
2094

2095 2096
	if (!apic_pm_state.active)
		return 0;
2097

2098
	maxlvt = lapic_get_maxlvt();
2099

2100
	apic_pm_state.apic_id = apic_read(APIC_ID);
2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112
	apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
	apic_pm_state.apic_ldr = apic_read(APIC_LDR);
	apic_pm_state.apic_dfr = apic_read(APIC_DFR);
	apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
	apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
	if (maxlvt >= 4)
		apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
	apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
	apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
	apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
	apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
	apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2113
#ifdef CONFIG_X86_THERMAL_VECTOR
2114 2115 2116
	if (maxlvt >= 5)
		apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
#endif
2117

2118 2119
	local_irq_save(flags);
	disable_local_APIC();
2120

2121 2122
	if (intr_remapping_enabled)
		disable_intr_remapping();
2123

2124 2125
	local_irq_restore(flags);
	return 0;
L
Linus Torvalds 已提交
2126 2127
}

2128
static void lapic_resume(void)
L
Linus Torvalds 已提交
2129
{
2130 2131
	unsigned int l, h;
	unsigned long flags;
2132
	int maxlvt;
2133

2134
	if (!apic_pm_state.active)
2135
		return;
2136

2137
	local_irq_save(flags);
2138
	if (intr_remapping_enabled) {
2139 2140 2141 2142 2143 2144 2145
		/*
		 * IO-APIC and PIC have their own resume routines.
		 * We just mask them here to make sure the interrupt
		 * subsystem is completely quiet while we enable x2apic
		 * and interrupt-remapping.
		 */
		mask_ioapic_entries();
2146
		legacy_pic->mask_all();
2147
	}
C
Cyrill Gorcunov 已提交
2148

2149
	if (x2apic_mode)
C
Cyrill Gorcunov 已提交
2150
		enable_x2apic();
2151
	else {
C
Cyrill Gorcunov 已提交
2152 2153 2154 2155 2156 2157
		/*
		 * Make sure the APICBASE points to the right address
		 *
		 * FIXME! This will be wrong if we ever support suspend on
		 * SMP! We'll need to do this as part of the CPU restore!
		 */
2158 2159 2160 2161
		rdmsr(MSR_IA32_APICBASE, l, h);
		l &= ~MSR_IA32_APICBASE_BASE;
		l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
		wrmsr(MSR_IA32_APICBASE, l, h);
2162
	}
2163

2164
	maxlvt = lapic_get_maxlvt();
2165 2166 2167 2168 2169 2170 2171 2172
	apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
	apic_write(APIC_ID, apic_pm_state.apic_id);
	apic_write(APIC_DFR, apic_pm_state.apic_dfr);
	apic_write(APIC_LDR, apic_pm_state.apic_ldr);
	apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
	apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
	apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
	apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
C
Cyrill Gorcunov 已提交
2173
#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186
	if (maxlvt >= 5)
		apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
#endif
	if (maxlvt >= 4)
		apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
	apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
	apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
	apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
	apic_write(APIC_ESR, 0);
	apic_read(APIC_ESR);
	apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
	apic_write(APIC_ESR, 0);
	apic_read(APIC_ESR);
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Cyrill Gorcunov 已提交
2187

2188
	if (intr_remapping_enabled)
2189
		reenable_intr_remapping(x2apic_mode);
2190

2191 2192
	local_irq_restore(flags);
}
T
Thomas Gleixner 已提交
2193

2194 2195 2196 2197 2198
/*
 * This device has no shutdown method - fully functioning local APICs
 * are needed on every CPU up until machine_halt/restart/poweroff.
 */

2199
static struct syscore_ops lapic_syscore_ops = {
2200 2201 2202
	.resume		= lapic_resume,
	.suspend	= lapic_suspend,
};
T
Thomas Gleixner 已提交
2203

2204 2205 2206
static void __cpuinit apic_pm_activate(void)
{
	apic_pm_state.active = 1;
L
Linus Torvalds 已提交
2207 2208
}

2209
static int __init init_lapic_sysfs(void)
L
Linus Torvalds 已提交
2210
{
2211
	/* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2212 2213
	if (cpu_has_apic)
		register_syscore_ops(&lapic_syscore_ops);
H
Hiroshi Shimamoto 已提交
2214

2215
	return 0;
L
Linus Torvalds 已提交
2216
}
2217 2218 2219

/* local apic needs to resume before other devices access its registers. */
core_initcall(init_lapic_sysfs);
2220 2221 2222 2223 2224 2225

#else	/* CONFIG_PM */

static void apic_pm_activate(void) { }

#endif	/* CONFIG_PM */
L
Linus Torvalds 已提交
2226

Y
Yinghai Lu 已提交
2227
#ifdef CONFIG_X86_64
2228 2229

static int __cpuinit apic_cluster_num(void)
L
Linus Torvalds 已提交
2230 2231 2232
{
	int i, clusters, zeros;
	unsigned id;
2233
	u16 *bios_cpu_apicid;
L
Linus Torvalds 已提交
2234 2235
	DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);

2236
	bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
2237
	bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
L
Linus Torvalds 已提交
2238

2239
	for (i = 0; i < nr_cpu_ids; i++) {
2240
		/* are we being called early in kernel startup? */
2241 2242
		if (bios_cpu_apicid) {
			id = bios_cpu_apicid[i];
2243
		} else if (i < nr_cpu_ids) {
2244 2245 2246 2247
			if (cpu_present(i))
				id = per_cpu(x86_bios_cpu_apicid, i);
			else
				continue;
2248
		} else
2249 2250
			break;

L
Linus Torvalds 已提交
2251 2252 2253 2254 2255 2256
		if (id != BAD_APICID)
			__set_bit(APIC_CLUSTERID(id), clustermap);
	}

	/* Problem:  Partially populated chassis may not have CPUs in some of
	 * the APIC clusters they have been allocated.  Only present CPUs have
2257 2258 2259
	 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
	 * Since clusters are allocated sequentially, count zeros only if
	 * they are bounded by ones.
L
Linus Torvalds 已提交
2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270
	 */
	clusters = 0;
	zeros = 0;
	for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
		if (test_bit(i, clustermap)) {
			clusters += 1 + zeros;
			zeros = 0;
		} else
			++zeros;
	}

2271 2272 2273 2274 2275 2276 2277 2278 2279 2280
	return clusters;
}

static int __cpuinitdata multi_checked;
static int __cpuinitdata multi;

static int __cpuinit set_multi(const struct dmi_system_id *d)
{
	if (multi)
		return 0;
C
Cyrill Gorcunov 已提交
2281
	pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318
	multi = 1;
	return 0;
}

static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = {
	{
		.callback = set_multi,
		.ident = "IBM System Summit2",
		.matches = {
			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
			DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
		},
	},
	{}
};

static void __cpuinit dmi_check_multi(void)
{
	if (multi_checked)
		return;

	dmi_check_system(multi_dmi_table);
	multi_checked = 1;
}

/*
 * apic_is_clustered_box() -- Check if we can expect good TSC
 *
 * Thus far, the major user of this is IBM's Summit2 series:
 * Clustered boxes may have unsynced TSC problems if they are
 * multi-chassis.
 * Use DMI to check them
 */
__cpuinit int apic_is_clustered_box(void)
{
	dmi_check_multi();
	if (multi)
2319 2320
		return 1;

2321 2322 2323
	if (!is_vsmp_box())
		return 0;

L
Linus Torvalds 已提交
2324
	/*
2325 2326
	 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are
	 * not guaranteed to be synced between boards
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	 */
2328 2329 2330 2331
	if (apic_cluster_num() > 1)
		return 1;

	return 0;
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}
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#endif
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/*
2336
 * APIC command line parameters
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 */
2338
static int __init setup_disableapic(char *arg)
2339
{
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	disable_apic = 1;
2341
	setup_clear_cpu_cap(X86_FEATURE_APIC);
2342 2343 2344
	return 0;
}
early_param("disableapic", setup_disableapic);
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2346
/* same as disableapic, for compatibility */
2347
static int __init setup_nolapic(char *arg)
2348
{
2349
	return setup_disableapic(arg);
2350
}
2351
early_param("nolapic", setup_nolapic);
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2353 2354 2355 2356 2357 2358 2359
static int __init parse_lapic_timer_c2_ok(char *arg)
{
	local_apic_timer_c2_ok = 1;
	return 0;
}
early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);

2360
static int __init parse_disable_apic_timer(char *arg)
2361
{
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	disable_apic_timer = 1;
2363
	return 0;
2364
}
2365 2366 2367 2368 2369 2370
early_param("noapictimer", parse_disable_apic_timer);

static int __init parse_nolapic_timer(char *arg)
{
	disable_apic_timer = 1;
	return 0;
2371
}
2372
early_param("nolapic_timer", parse_nolapic_timer);
2373

2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388
static int __init apic_set_verbosity(char *arg)
{
	if (!arg)  {
#ifdef CONFIG_X86_64
		skip_ioapic_setup = 0;
		return 0;
#endif
		return -EINVAL;
	}

	if (strcmp("debug", arg) == 0)
		apic_verbosity = APIC_DEBUG;
	else if (strcmp("verbose", arg) == 0)
		apic_verbosity = APIC_VERBOSE;
	else {
2389
		pr_warning("APIC Verbosity level %s not recognised"
2390 2391 2392 2393 2394 2395 2396 2397
			" use apic=verbose or apic=debug\n", arg);
		return -EINVAL;
	}

	return 0;
}
early_param("apic", apic_set_verbosity);

2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415
static int __init lapic_insert_resource(void)
{
	if (!apic_phys)
		return -1;

	/* Put local APIC into the resource map. */
	lapic_resource.start = apic_phys;
	lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
	insert_resource(&iomem_resource, &lapic_resource);

	return 0;
}

/*
 * need call insert after e820_reserve_resources()
 * that is using request_resource
 */
late_initcall(lapic_insert_resource);