risc_axi_v5_top.protoinst

{
	"version": "1.0",
	"modules": {
		"risc_axi_v5_top": {
			"proto_instances": {
				"/axi_uartlite_0/S_AXI": {
					"interface": "xilinx.com:interface:aximm:1.0",
					"ports": {
						"ACLK": { "actual": "s_axi_aclk"},
						"ARADDR": { "actual": "s_axi_araddr"},
						"ARESETN": { "actual": "s_axi_aresetn"},
						"ARREADY": { "actual": "s_axi_arready"},
						"ARVALID": { "actual": "s_axi_arvalid"},
						"AWADDR": { "actual": "s_axi_awaddr"},
						"AWREADY": { "actual": "s_axi_awready"},
						"AWVALID": { "actual": "s_axi_awvalid"},
						"BREADY": { "actual": "s_axi_bready"},
						"BRESP": { "actual": "s_axi_bresp"},
						"BVALID": { "actual": "s_axi_bvalid"},
						"RDATA": { "actual": "s_axi_rdata"},
						"RREADY": { "actual": "s_axi_rready"},
						"RRESP": { "actual": "s_axi_rresp"},
						"RVALID": { "actual": "s_axi_rvalid"},
						"WDATA": { "actual": "s_axi_wdata"},
						"WREADY": { "actual": "s_axi_wready"},
						"WSTRB": { "actual": "s_axi_wstrb"},
						"WVALID": { "actual": "s_axi_wvalid"}
					}
				},
				"/led_key_0/s00_axi": {
					"interface": "xilinx.com:interface:aximm:1.0",
					"ports": {
						"ACLK": { "actual": "s00_axi_aclk"},
						"ARADDR": { "actual": "s00_axi_araddr"},
						"ARESETN": { "actual": "s00_axi_aresetn"},
						"ARPROT": { "actual": "s00_axi_arprot"},
						"ARREADY": { "actual": "s00_axi_arready"},
						"ARVALID": { "actual": "s00_axi_arvalid"},
						"AWADDR": { "actual": "s00_axi_awaddr"},
						"AWPROT": { "actual": "s00_axi_awprot"},
						"AWREADY": { "actual": "s00_axi_awready"},
						"AWVALID": { "actual": "s00_axi_awvalid"},
						"BREADY": { "actual": "s00_axi_bready"},
						"BRESP": { "actual": "s00_axi_bresp"},
						"BVALID": { "actual": "s00_axi_bvalid"},
						"RDATA": { "actual": "s00_axi_rdata"},
						"RREADY": { "actual": "s00_axi_rready"},
						"RRESP": { "actual": "s00_axi_rresp"},
						"RVALID": { "actual": "s00_axi_rvalid"},
						"WDATA": { "actual": "s00_axi_wdata"},
						"WREADY": { "actual": "s00_axi_wready"},
						"WSTRB": { "actual": "s00_axi_wstrb"},
						"WVALID": { "actual": "s00_axi_wvalid"}
					}
				},
				"/riscv_core_with_axi_0/m00_axi": {
					"interface": "xilinx.com:interface:aximm:1.0",
					"ports": {
						"ACLK": { "actual": "m00_axi_aclk"},
						"ARADDR": { "actual": "m00_axi_araddr"},
						"ARESETN": { "actual": "m00_axi_aresetn"},
						"ARPROT": { "actual": "m00_axi_arprot"},
						"ARREADY": { "actual": "m00_axi_arready"},
						"ARVALID": { "actual": "m00_axi_arvalid"},
						"AWADDR": { "actual": "m00_axi_awaddr"},
						"AWPROT": { "actual": "m00_axi_awprot"},
						"AWREADY": { "actual": "m00_axi_awready"},
						"AWVALID": { "actual": "m00_axi_awvalid"},
						"BREADY": { "actual": "m00_axi_bready"},
						"BRESP": { "actual": "m00_axi_bresp"},
						"BVALID": { "actual": "m00_axi_bvalid"},
						"RDATA": { "actual": "m00_axi_rdata"},
						"RREADY": { "actual": "m00_axi_rready"},
						"RRESP": { "actual": "m00_axi_rresp"},
						"RVALID": { "actual": "m00_axi_rvalid"},
						"WDATA": { "actual": "m00_axi_wdata"},
						"WREADY": { "actual": "m00_axi_wready"},
						"WSTRB": { "actual": "m00_axi_wstrb"},
						"WVALID": { "actual": "m00_axi_wvalid"}
					}
				},
				"/riscv_core_with_axi_0_axi_periph/M00_AXI": {
					"interface": "xilinx.com:interface:aximm:1.0",
					"ports": {
						"ACLK": { "actual": "M00_ACLK"},
						"ARADDR": { "actual": "M00_AXI_araddr[31:0]"},
						"ARESETN": { "actual": "ARESETN"},
						"ARREADY": { "actual": "M00_AXI_arready"},
						"ARVALID": { "actual": "M00_AXI_arvalid"},
						"AWADDR": { "actual": "M00_AXI_awaddr[31:0]"},
						"AWREADY": { "actual": "M00_AXI_awready"},
						"AWVALID": { "actual": "M00_AXI_awvalid"},
						"BREADY": { "actual": "M00_AXI_bready"},
						"BRESP": { "actual": "M00_AXI_bresp[1:0]"},
						"BVALID": { "actual": "M00_AXI_bvalid"},
						"RDATA": { "actual": "M00_AXI_rdata[31:0]"},
						"RREADY": { "actual": "M00_AXI_rready"},
						"RRESP": { "actual": "M00_AXI_rresp[1:0]"},
						"RVALID": { "actual": "M00_AXI_rvalid"},
						"WDATA": { "actual": "M00_AXI_wdata[31:0]"},
						"WREADY": { "actual": "M00_AXI_wready"},
						"WSTRB": { "actual": "M00_AXI_wstrb[3:0]"},
						"WVALID": { "actual": "M00_AXI_wvalid"}
					}
				},
				"/riscv_core_with_axi_0_axi_periph/M01_AXI": {
					"interface": "xilinx.com:interface:aximm:1.0",
					"ports": {
						"ACLK": { "actual": "M01_ACLK"},
						"ARADDR": { "actual": "M01_AXI_araddr[63:32]"},
						"ARESETN": { "actual": "ARESETN"},
						"ARPROT": { "actual": "M01_AXI_arprot[5:3]"},
						"ARREADY": { "actual": "M01_AXI_arready"},
						"ARVALID": { "actual": "M01_AXI_arvalid"},
						"AWADDR": { "actual": "M01_AXI_awaddr[63:32]"},
						"AWPROT": { "actual": "M01_AXI_awprot[5:3]"},
						"AWREADY": { "actual": "M01_AXI_awready"},
						"AWVALID": { "actual": "M01_AXI_awvalid"},
						"BREADY": { "actual": "M01_AXI_bready"},
						"BRESP": { "actual": "M01_AXI_bresp[3:2]"},
						"BVALID": { "actual": "M01_AXI_bvalid"},
						"RDATA": { "actual": "M01_AXI_rdata[63:32]"},
						"RREADY": { "actual": "M01_AXI_rready"},
						"RRESP": { "actual": "M01_AXI_rresp[3:2]"},
						"RVALID": { "actual": "M01_AXI_rvalid"},
						"WDATA": { "actual": "M01_AXI_wdata[63:32]"},
						"WREADY": { "actual": "M01_AXI_wready"},
						"WSTRB": { "actual": "M01_AXI_wstrb[7:4]"},
						"WVALID": { "actual": "M01_AXI_wvalid"}
					}
				},
				"/riscv_core_with_axi_0_axi_periph/S00_AXI": {
					"interface": "xilinx.com:interface:aximm:1.0",
					"ports": {
						"ACLK": { "actual": "S00_ACLK"},
						"ARADDR": { "actual": "S00_AXI_araddr[31:0]"},
						"ARESETN": { "actual": "ARESETN"},
						"ARPROT": { "actual": "S00_AXI_arprot[2:0]"},
						"ARREADY": { "actual": "S00_AXI_arready"},
						"ARVALID": { "actual": "S00_AXI_arvalid"},
						"AWADDR": { "actual": "S00_AXI_awaddr[31:0]"},
						"AWPROT": { "actual": "S00_AXI_awprot[2:0]"},
						"AWREADY": { "actual": "S00_AXI_awready"},
						"AWVALID": { "actual": "S00_AXI_awvalid"},
						"BREADY": { "actual": "S00_AXI_bready"},
						"BRESP": { "actual": "S00_AXI_bresp[1:0]"},
						"BVALID": { "actual": "S00_AXI_bvalid"},
						"RDATA": { "actual": "S00_AXI_rdata[31:0]"},
						"RREADY": { "actual": "S00_AXI_rready"},
						"RRESP": { "actual": "S00_AXI_rresp[1:0]"},
						"RVALID": { "actual": "S00_AXI_rvalid"},
						"WDATA": { "actual": "S00_AXI_wdata[31:0]"},
						"WREADY": { "actual": "S00_AXI_wready"},
						"WSTRB": { "actual": "S00_AXI_wstrb[3:0]"},
						"WVALID": { "actual": "S00_AXI_wvalid"}
					}
				},
				"/riscv_core_with_axi_0_axi_periph/m00_couplers/M_AXI": {
					"interface": "xilinx.com:interface:aximm:1.0",
					"ports": {
						"ACLK": { "actual": "M_ACLK"},
						"ARADDR": { "actual": "M_AXI_araddr[31:0]"},
						"ARESETN": { "actual": "M_ARESETN"},
						"ARREADY": { "actual": "M_AXI_arready"},
						"ARVALID": { "actual": "M_AXI_arvalid"},
						"AWADDR": { "actual": "M_AXI_awaddr[31:0]"},
						"AWREADY": { "actual": "M_AXI_awready"},
						"AWVALID": { "actual": "M_AXI_awvalid"},
						"BREADY": { "actual": "M_AXI_bready"},
						"BRESP": { "actual": "M_AXI_bresp[1:0]"},
						"BVALID": { "actual": "M_AXI_bvalid"},
						"RDATA": { "actual": "M_AXI_rdata[31:0]"},
						"RREADY": { "actual": "M_AXI_rready"},
						"RRESP": { "actual": "M_AXI_rresp[1:0]"},
						"RVALID": { "actual": "M_AXI_rvalid"},
						"WDATA": { "actual": "M_AXI_wdata[31:0]"},
						"WREADY": { "actual": "M_AXI_wready"},
						"WSTRB": { "actual": "M_AXI_wstrb[3:0]"},
						"WVALID": { "actual": "M_AXI_wvalid"}
					}
				},
				"/riscv_core_with_axi_0_axi_periph/m00_couplers/S_AXI": {
					"interface": "xilinx.com:interface:aximm:1.0",
					"ports": {
						"ACLK": { "actual": "S_ACLK"},
						"ARADDR": { "actual": "S_AXI_araddr[31:0]"},
						"ARESETN": { "actual": "S_ARESETN"},
						"ARREADY": { "actual": "S_AXI_arready"},
						"ARVALID": { "actual": "S_AXI_arvalid"},
						"AWADDR": { "actual": "S_AXI_awaddr[31:0]"},
						"AWREADY": { "actual": "S_AXI_awready"},
						"AWVALID": { "actual": "S_AXI_awvalid"},
						"BREADY": { "actual": "S_AXI_bready"},
						"BRESP": { "actual": "S_AXI_bresp[1:0]"},
						"BVALID": { "actual": "S_AXI_bvalid"},
						"RDATA": { "actual": "S_AXI_rdata[31:0]"},
						"RREADY": { "actual": "S_AXI_rready"},
						"RRESP": { "actual": "S_AXI_rresp[1:0]"},
						"RVALID": { "actual": "S_AXI_rvalid"},
						"WDATA": { "actual": "S_AXI_wdata[31:0]"},
						"WREADY": { "actual": "S_AXI_wready"},
						"WSTRB": { "actual": "S_AXI_wstrb[3:0]"},
						"WVALID": { "actual": "S_AXI_wvalid"}
					}
				},
				"/riscv_core_with_axi_0_axi_periph/m01_couplers/M_AXI": {
					"interface": "xilinx.com:interface:aximm:1.0",
					"ports": {
						"ACLK": { "actual": "M_ACLK"},
						"ARADDR": { "actual": "M_AXI_araddr[63:32]"},
						"ARESETN": { "actual": "M_ARESETN"},
						"ARPROT": { "actual": "M_AXI_arprot[5:3]"},
						"ARREADY": { "actual": "M_AXI_arready"},
						"ARVALID": { "actual": "M_AXI_arvalid"},
						"AWADDR": { "actual": "M_AXI_awaddr[63:32]"},
						"AWPROT": { "actual": "M_AXI_awprot[5:3]"},
						"AWREADY": { "actual": "M_AXI_awready"},
						"AWVALID": { "actual": "M_AXI_awvalid"},
						"BREADY": { "actual": "M_AXI_bready"},
						"BRESP": { "actual": "M_AXI_bresp[3:2]"},
						"BVALID": { "actual": "M_AXI_bvalid"},
						"RDATA": { "actual": "M_AXI_rdata[63:32]"},
						"RREADY": { "actual": "M_AXI_rready"},
						"RRESP": { "actual": "M_AXI_rresp[3:2]"},
						"RVALID": { "actual": "M_AXI_rvalid"},
						"WDATA": { "actual": "M_AXI_wdata[63:32]"},
						"WREADY": { "actual": "M_AXI_wready"},
						"WSTRB": { "actual": "M_AXI_wstrb[7:4]"},
						"WVALID": { "actual": "M_AXI_wvalid"}
					}
				},
				"/riscv_core_with_axi_0_axi_periph/m01_couplers/S_AXI": {
					"interface": "xilinx.com:interface:aximm:1.0",
					"ports": {
						"ACLK": { "actual": "S_ACLK"},
						"ARADDR": { "actual": "S_AXI_araddr[63:32]"},
						"ARESETN": { "actual": "S_ARESETN"},
						"ARPROT": { "actual": "S_AXI_arprot[5:3]"},
						"ARREADY": { "actual": "S_AXI_arready"},
						"ARVALID": { "actual": "S_AXI_arvalid"},
						"AWADDR": { "actual": "S_AXI_awaddr[63:32]"},
						"AWPROT": { "actual": "S_AXI_awprot[5:3]"},
						"AWREADY": { "actual": "S_AXI_awready"},
						"AWVALID": { "actual": "S_AXI_awvalid"},
						"BREADY": { "actual": "S_AXI_bready"},
						"BRESP": { "actual": "S_AXI_bresp[3:2]"},
						"BVALID": { "actual": "S_AXI_bvalid"},
						"RDATA": { "actual": "S_AXI_rdata[63:32]"},
						"RREADY": { "actual": "S_AXI_rready"},
						"RRESP": { "actual": "S_AXI_rresp[3:2]"},
						"RVALID": { "actual": "S_AXI_rvalid"},
						"WDATA": { "actual": "S_AXI_wdata[63:32]"},
						"WREADY": { "actual": "S_AXI_wready"},
						"WSTRB": { "actual": "S_AXI_wstrb[7:4]"},
						"WVALID": { "actual": "S_AXI_wvalid"}
					}
				},
				"/riscv_core_with_axi_0_axi_periph/s00_couplers/M_AXI": {
					"interface": "xilinx.com:interface:aximm:1.0",
					"ports": {
						"ACLK": { "actual": "M_ACLK"},
						"ARADDR": { "actual": "M_AXI_araddr[31:0]"},
						"ARESETN": { "actual": "M_ARESETN"},
						"ARPROT": { "actual": "M_AXI_arprot[2:0]"},
						"ARREADY": { "actual": "M_AXI_arready"},
						"ARVALID": { "actual": "M_AXI_arvalid"},
						"AWADDR": { "actual": "M_AXI_awaddr[31:0]"},
						"AWPROT": { "actual": "M_AXI_awprot[2:0]"},
						"AWREADY": { "actual": "M_AXI_awready"},
						"AWVALID": { "actual": "M_AXI_awvalid"},
						"BREADY": { "actual": "M_AXI_bready"},
						"BRESP": { "actual": "M_AXI_bresp[1:0]"},
						"BVALID": { "actual": "M_AXI_bvalid"},
						"RDATA": { "actual": "M_AXI_rdata[31:0]"},
						"RREADY": { "actual": "M_AXI_rready"},
						"RRESP": { "actual": "M_AXI_rresp[1:0]"},
						"RVALID": { "actual": "M_AXI_rvalid"},
						"WDATA": { "actual": "M_AXI_wdata[31:0]"},
						"WREADY": { "actual": "M_AXI_wready"},
						"WSTRB": { "actual": "M_AXI_wstrb[3:0]"},
						"WVALID": { "actual": "M_AXI_wvalid"}
					}
				},
				"/riscv_core_with_axi_0_axi_periph/s00_couplers/S_AXI": {
					"interface": "xilinx.com:interface:aximm:1.0",
					"ports": {
						"ACLK": { "actual": "S_ACLK"},
						"ARADDR": { "actual": "S_AXI_araddr[31:0]"},
						"ARESETN": { "actual": "S_ARESETN"},
						"ARPROT": { "actual": "S_AXI_arprot[2:0]"},
						"ARREADY": { "actual": "S_AXI_arready"},
						"ARVALID": { "actual": "S_AXI_arvalid"},
						"AWADDR": { "actual": "S_AXI_awaddr[31:0]"},
						"AWPROT": { "actual": "S_AXI_awprot[2:0]"},
						"AWREADY": { "actual": "S_AXI_awready"},
						"AWVALID": { "actual": "S_AXI_awvalid"},
						"BREADY": { "actual": "S_AXI_bready"},
						"BRESP": { "actual": "S_AXI_bresp[1:0]"},
						"BVALID": { "actual": "S_AXI_bvalid"},
						"RDATA": { "actual": "S_AXI_rdata[31:0]"},
						"RREADY": { "actual": "S_AXI_rready"},
						"RRESP": { "actual": "S_AXI_rresp[1:0]"},
						"RVALID": { "actual": "S_AXI_rvalid"},
						"WDATA": { "actual": "S_AXI_wdata[31:0]"},
						"WREADY": { "actual": "S_AXI_wready"},
						"WSTRB": { "actual": "S_AXI_wstrb[3:0]"},
						"WVALID": { "actual": "S_AXI_wvalid"}
					}
				},
				"/riscv_core_with_axi_0_axi_periph/xbar/M00_AXI": {
					"interface": "xilinx.com:interface:aximm:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARADDR": { "actual": "m_axi_araddr[31:0]"},
						"ARESETN": { "actual": "aresetn"},
						"ARPROT": { "actual": "m_axi_arprot[2:0]"},
						"ARREADY": { "actual": "m_axi_arready[0:0]"},
						"ARVALID": { "actual": "m_axi_arvalid[0:0]"},
						"AWADDR": { "actual": "m_axi_awaddr[31:0]"},
						"AWPROT": { "actual": "m_axi_awprot[2:0]"},
						"AWREADY": { "actual": "m_axi_awready[0:0]"},
						"AWVALID": { "actual": "m_axi_awvalid[0:0]"},
						"BREADY": { "actual": "m_axi_bready[0:0]"},
						"BRESP": { "actual": "m_axi_bresp[1:0]"},
						"BVALID": { "actual": "m_axi_bvalid[0:0]"},
						"RDATA": { "actual": "m_axi_rdata[31:0]"},
						"RREADY": { "actual": "m_axi_rready[0:0]"},
						"RRESP": { "actual": "m_axi_rresp[1:0]"},
						"RVALID": { "actual": "m_axi_rvalid[0:0]"},
						"WDATA": { "actual": "m_axi_wdata[31:0]"},
						"WREADY": { "actual": "m_axi_wready[0:0]"},
						"WSTRB": { "actual": "m_axi_wstrb[3:0]"},
						"WVALID": { "actual": "m_axi_wvalid[0:0]"}
					}
				},
				"/riscv_core_with_axi_0_axi_periph/xbar/M01_AXI": {
					"interface": "xilinx.com:interface:aximm:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARADDR": { "actual": "m_axi_araddr[63:32]"},
						"ARESETN": { "actual": "aresetn"},
						"ARPROT": { "actual": "m_axi_arprot[5:3]"},
						"ARREADY": { "actual": "m_axi_arready[1:1]"},
						"ARVALID": { "actual": "m_axi_arvalid[1:1]"},
						"AWADDR": { "actual": "m_axi_awaddr[63:32]"},
						"AWPROT": { "actual": "m_axi_awprot[5:3]"},
						"AWREADY": { "actual": "m_axi_awready[1:1]"},
						"AWVALID": { "actual": "m_axi_awvalid[1:1]"},
						"BREADY": { "actual": "m_axi_bready[1:1]"},
						"BRESP": { "actual": "m_axi_bresp[3:2]"},
						"BVALID": { "actual": "m_axi_bvalid[1:1]"},
						"RDATA": { "actual": "m_axi_rdata[63:32]"},
						"RREADY": { "actual": "m_axi_rready[1:1]"},
						"RRESP": { "actual": "m_axi_rresp[3:2]"},
						"RVALID": { "actual": "m_axi_rvalid[1:1]"},
						"WDATA": { "actual": "m_axi_wdata[63:32]"},
						"WREADY": { "actual": "m_axi_wready[1:1]"},
						"WSTRB": { "actual": "m_axi_wstrb[7:4]"},
						"WVALID": { "actual": "m_axi_wvalid[1:1]"}
					}
				},
				"/riscv_core_with_axi_0_axi_periph/xbar/S00_AXI": {
					"interface": "xilinx.com:interface:aximm:1.0",
					"ports": {
						"ACLK": { "actual": "aclk"},
						"ARADDR": { "actual": "s_axi_araddr[31:0]"},
						"ARESETN": { "actual": "aresetn"},
						"ARPROT": { "actual": "s_axi_arprot[2:0]"},
						"ARREADY": { "actual": "s_axi_arready[0:0]"},
						"ARVALID": { "actual": "s_axi_arvalid[0:0]"},
						"AWADDR": { "actual": "s_axi_awaddr[31:0]"},
						"AWPROT": { "actual": "s_axi_awprot[2:0]"},
						"AWREADY": { "actual": "s_axi_awready[0:0]"},
						"AWVALID": { "actual": "s_axi_awvalid[0:0]"},
						"BREADY": { "actual": "s_axi_bready[0:0]"},
						"BRESP": { "actual": "s_axi_bresp[1:0]"},
						"BVALID": { "actual": "s_axi_bvalid[0:0]"},
						"RDATA": { "actual": "s_axi_rdata[31:0]"},
						"RREADY": { "actual": "s_axi_rready[0:0]"},
						"RRESP": { "actual": "s_axi_rresp[1:0]"},
						"RVALID": { "actual": "s_axi_rvalid[0:0]"},
						"WDATA": { "actual": "s_axi_wdata[31:0]"},
						"WREADY": { "actual": "s_axi_wready[0:0]"},
						"WSTRB": { "actual": "s_axi_wstrb[3:0]"},
						"WVALID": { "actual": "s_axi_wvalid[0:0]"}
					}
				}
			}
		}
	}
}