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提交 b526a473 编写于 作者: 饶先宏's avatar 饶先宏
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202109122009

上级 507eee25
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Showing with 9891 addition and 565 deletion
.gitignore
浏览文件 @ b526a473
......@@ -365,107 +365,10 @@ MigrationBackup/
# Fody - auto-generated XML schema
FodyWeavers.xsd
#########
#Exclude all
#########
*
!*/
!.gitignore
###########################################################################
## VIVADO
###########################################################################
#########
#Source files:
#########
#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files.
!*.vhd
!*.v
!*.bd
!*.edif
#########
#IP files
#########
#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products
#.xci + .dcp: implementation possible but not re-synthesis
#*.xci(www.spiritconsortium.org)
!*.xci
#*.dcp(checkpoint files)
!*.dcp
!*.vds
!*.pb
#All bd comments and layout coordinates are stored within .ui
!*.ui
!*.ooc
#########
#System Generator
#########
!*.mdl
!*.slx
!*.bxml
#########
#Simulation logic analyzer
#########
!*.wcfg
!*.coe
#########
#MIG
#########
!*.prj
!*.mem
#########
#Project files
#########
#XPR + *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version)
#Do NOT ignore *.xpr files
!*.xpr
#Include *.xml files for 2013.4 or earlier version
!*.xml
#########
#Constraint files
#########
#Do NOT ignore *.xdc files
!*.xdc
#########
#TCL - files
#########
!*.tcl
#########
#Journal - files
#########
!*.jou
#########
#Reports
#########
!*.rpt
!*.txt
!*.vdi
#########
#C-files
#########
!*.c
!*.cc
!*.cpp
!*.hh
!*.h
!*.elf
!*.bmm
!*.xmp
!*.xlsx
!*.caffemodel
!*.coeff
!*.coe
!*.cod
!*.mif
!*.hex
!*.doc
!*.docx
!*.pdf
!*.ppt
!*.pptx
!*.txt
!*.zip
!*.html
!*.htm
!*.proto
##VIVADO
*.cache/
*.gen/
*.runs/
*.sim/
*.hw/
sim_scripts/
\ No newline at end of file
examples/hdl4se_riscv/z7/ip_repo/myip_1.0/drivers/myip_v1_0/data/myip.mdd 0 → 100644
浏览文件 @ b526a473
OPTION psf_version = 2.1;
BEGIN DRIVER myip
OPTION supported_peripherals = (myip);
OPTION copyfiles = all;
OPTION VERSION = 1.0;
OPTION NAME = myip;
END DRIVER
examples/hdl4se_riscv/z7/ip_repo/myip_1.0/drivers/myip_v1_0/src/Makefile 0 → 100644
浏览文件 @ b526a473
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
INCLUDEFILES=*.h
LIBSOURCES=*.c
OUTS = *.o
libs:
echo "Compiling myip..."
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
make clean
include:
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
clean:
rm -rf ${OUTS}
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.ip_user_files/bd/risc_axi_v5_top/sim/risc_axi_v5_top.protoinst 0 → 100644
浏览文件 @ b526a473
{
"version": "1.0",
"modules": {
"risc_axi_v5_top": {
"proto_instances": {
"/axi_uartlite_0/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "s_axi_aclk"},
"ARADDR": { "actual": "s_axi_araddr"},
"ARESETN": { "actual": "s_axi_aresetn"},
"ARREADY": { "actual": "s_axi_arready"},
"ARVALID": { "actual": "s_axi_arvalid"},
"AWADDR": { "actual": "s_axi_awaddr"},
"AWREADY": { "actual": "s_axi_awready"},
"AWVALID": { "actual": "s_axi_awvalid"},
"BREADY": { "actual": "s_axi_bready"},
"BRESP": { "actual": "s_axi_bresp"},
"BVALID": { "actual": "s_axi_bvalid"},
"RDATA": { "actual": "s_axi_rdata"},
"RREADY": { "actual": "s_axi_rready"},
"RRESP": { "actual": "s_axi_rresp"},
"RVALID": { "actual": "s_axi_rvalid"},
"WDATA": { "actual": "s_axi_wdata"},
"WREADY": { "actual": "s_axi_wready"},
"WSTRB": { "actual": "s_axi_wstrb"},
"WVALID": { "actual": "s_axi_wvalid"}
}
},
"/led_key_0/s00_axi": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "s00_axi_aclk"},
"ARADDR": { "actual": "s00_axi_araddr"},
"ARESETN": { "actual": "s00_axi_aresetn"},
"ARPROT": { "actual": "s00_axi_arprot"},
"ARREADY": { "actual": "s00_axi_arready"},
"ARVALID": { "actual": "s00_axi_arvalid"},
"AWADDR": { "actual": "s00_axi_awaddr"},
"AWPROT": { "actual": "s00_axi_awprot"},
"AWREADY": { "actual": "s00_axi_awready"},
"AWVALID": { "actual": "s00_axi_awvalid"},
"BREADY": { "actual": "s00_axi_bready"},
"BRESP": { "actual": "s00_axi_bresp"},
"BVALID": { "actual": "s00_axi_bvalid"},
"RDATA": { "actual": "s00_axi_rdata"},
"RREADY": { "actual": "s00_axi_rready"},
"RRESP": { "actual": "s00_axi_rresp"},
"RVALID": { "actual": "s00_axi_rvalid"},
"WDATA": { "actual": "s00_axi_wdata"},
"WREADY": { "actual": "s00_axi_wready"},
"WSTRB": { "actual": "s00_axi_wstrb"},
"WVALID": { "actual": "s00_axi_wvalid"}
}
},
"/riscv_core_with_axi_0/m00_axi": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "m00_axi_aclk"},
"ARADDR": { "actual": "m00_axi_araddr"},
"ARESETN": { "actual": "m00_axi_aresetn"},
"ARPROT": { "actual": "m00_axi_arprot"},
"ARREADY": { "actual": "m00_axi_arready"},
"ARVALID": { "actual": "m00_axi_arvalid"},
"AWADDR": { "actual": "m00_axi_awaddr"},
"AWPROT": { "actual": "m00_axi_awprot"},
"AWREADY": { "actual": "m00_axi_awready"},
"AWVALID": { "actual": "m00_axi_awvalid"},
"BREADY": { "actual": "m00_axi_bready"},
"BRESP": { "actual": "m00_axi_bresp"},
"BVALID": { "actual": "m00_axi_bvalid"},
"RDATA": { "actual": "m00_axi_rdata"},
"RREADY": { "actual": "m00_axi_rready"},
"RRESP": { "actual": "m00_axi_rresp"},
"RVALID": { "actual": "m00_axi_rvalid"},
"WDATA": { "actual": "m00_axi_wdata"},
"WREADY": { "actual": "m00_axi_wready"},
"WSTRB": { "actual": "m00_axi_wstrb"},
"WVALID": { "actual": "m00_axi_wvalid"}
}
},
"/riscv_core_with_axi_0_axi_periph/M00_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "M00_ACLK"},
"ARADDR": { "actual": "M00_AXI_araddr[31:0]"},
"ARESETN": { "actual": "ARESETN"},
"ARREADY": { "actual": "M00_AXI_arready[0:0]"},
"ARVALID": { "actual": "M00_AXI_arvalid[0:0]"},
"AWADDR": { "actual": "M00_AXI_awaddr[31:0]"},
"AWREADY": { "actual": "M00_AXI_awready[0:0]"},
"AWVALID": { "actual": "M00_AXI_awvalid[0:0]"},
"BREADY": { "actual": "M00_AXI_bready[0:0]"},
"BRESP": { "actual": "M00_AXI_bresp[1:0]"},
"BVALID": { "actual": "M00_AXI_bvalid[0:0]"},
"RDATA": { "actual": "M00_AXI_rdata[31:0]"},
"RREADY": { "actual": "M00_AXI_rready[0:0]"},
"RRESP": { "actual": "M00_AXI_rresp[1:0]"},
"RVALID": { "actual": "M00_AXI_rvalid[0:0]"},
"WDATA": { "actual": "M00_AXI_wdata[31:0]"},
"WREADY": { "actual": "M00_AXI_wready[0:0]"},
"WSTRB": { "actual": "M00_AXI_wstrb[3:0]"},
"WVALID": { "actual": "M00_AXI_wvalid[0:0]"}
}
},
"/riscv_core_with_axi_0_axi_periph/M01_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "M01_ACLK"},
"ARADDR": { "actual": "M01_AXI_araddr[63:32]"},
"ARESETN": { "actual": "ARESETN"},
"ARPROT": { "actual": "M01_AXI_arprot[5:3]"},
"ARREADY": { "actual": "M01_AXI_arready"},
"ARVALID": { "actual": "M01_AXI_arvalid"},
"AWADDR": { "actual": "M01_AXI_awaddr[63:32]"},
"AWPROT": { "actual": "M01_AXI_awprot[5:3]"},
"AWREADY": { "actual": "M01_AXI_awready"},
"AWVALID": { "actual": "M01_AXI_awvalid"},
"BREADY": { "actual": "M01_AXI_bready"},
"BRESP": { "actual": "M01_AXI_bresp[3:2]"},
"BVALID": { "actual": "M01_AXI_bvalid"},
"RDATA": { "actual": "M01_AXI_rdata[63:32]"},
"RREADY": { "actual": "M01_AXI_rready"},
"RRESP": { "actual": "M01_AXI_rresp[3:2]"},
"RVALID": { "actual": "M01_AXI_rvalid"},
"WDATA": { "actual": "M01_AXI_wdata[63:32]"},
"WREADY": { "actual": "M01_AXI_wready"},
"WSTRB": { "actual": "M01_AXI_wstrb[7:4]"},
"WVALID": { "actual": "M01_AXI_wvalid"}
}
},
"/riscv_core_with_axi_0_axi_periph/S00_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "S00_ACLK"},
"ARADDR": { "actual": "S00_AXI_araddr[31:0]"},
"ARESETN": { "actual": "ARESETN"},
"ARPROT": { "actual": "S00_AXI_arprot[2:0]"},
"ARREADY": { "actual": "S00_AXI_arready"},
"ARVALID": { "actual": "S00_AXI_arvalid"},
"AWADDR": { "actual": "S00_AXI_awaddr[31:0]"},
"AWPROT": { "actual": "S00_AXI_awprot[2:0]"},
"AWREADY": { "actual": "S00_AXI_awready"},
"AWVALID": { "actual": "S00_AXI_awvalid"},
"BREADY": { "actual": "S00_AXI_bready"},
"BRESP": { "actual": "S00_AXI_bresp[1:0]"},
"BVALID": { "actual": "S00_AXI_bvalid"},
"RDATA": { "actual": "S00_AXI_rdata[31:0]"},
"RREADY": { "actual": "S00_AXI_rready"},
"RRESP": { "actual": "S00_AXI_rresp[1:0]"},
"RVALID": { "actual": "S00_AXI_rvalid"},
"WDATA": { "actual": "S00_AXI_wdata[31:0]"},
"WREADY": { "actual": "S00_AXI_wready"},
"WSTRB": { "actual": "S00_AXI_wstrb[3:0]"},
"WVALID": { "actual": "S00_AXI_wvalid"}
}
},
"/riscv_core_with_axi_0_axi_periph/m00_couplers/M_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "M_ACLK"},
"ARADDR": { "actual": "M_AXI_araddr[31:0]"},
"ARESETN": { "actual": "M_ARESETN"},
"ARREADY": { "actual": "M_AXI_arready[0:0]"},
"ARVALID": { "actual": "M_AXI_arvalid[0:0]"},
"AWADDR": { "actual": "M_AXI_awaddr[31:0]"},
"AWREADY": { "actual": "M_AXI_awready[0:0]"},
"AWVALID": { "actual": "M_AXI_awvalid[0:0]"},
"BREADY": { "actual": "M_AXI_bready[0:0]"},
"BRESP": { "actual": "M_AXI_bresp[1:0]"},
"BVALID": { "actual": "M_AXI_bvalid[0:0]"},
"RDATA": { "actual": "M_AXI_rdata[31:0]"},
"RREADY": { "actual": "M_AXI_rready[0:0]"},
"RRESP": { "actual": "M_AXI_rresp[1:0]"},
"RVALID": { "actual": "M_AXI_rvalid[0:0]"},
"WDATA": { "actual": "M_AXI_wdata[31:0]"},
"WREADY": { "actual": "M_AXI_wready[0:0]"},
"WSTRB": { "actual": "M_AXI_wstrb[3:0]"},
"WVALID": { "actual": "M_AXI_wvalid[0:0]"}
}
},
"/riscv_core_with_axi_0_axi_periph/m00_couplers/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "S_ACLK"},
"ARADDR": { "actual": "S_AXI_araddr[31:0]"},
"ARESETN": { "actual": "S_ARESETN"},
"ARREADY": { "actual": "S_AXI_arready[0:0]"},
"ARVALID": { "actual": "S_AXI_arvalid[0:0]"},
"AWADDR": { "actual": "S_AXI_awaddr[31:0]"},
"AWREADY": { "actual": "S_AXI_awready[0:0]"},
"AWVALID": { "actual": "S_AXI_awvalid[0:0]"},
"BREADY": { "actual": "S_AXI_bready[0:0]"},
"BRESP": { "actual": "S_AXI_bresp[1:0]"},
"BVALID": { "actual": "S_AXI_bvalid[0:0]"},
"RDATA": { "actual": "S_AXI_rdata[31:0]"},
"RREADY": { "actual": "S_AXI_rready[0:0]"},
"RRESP": { "actual": "S_AXI_rresp[1:0]"},
"RVALID": { "actual": "S_AXI_rvalid[0:0]"},
"WDATA": { "actual": "S_AXI_wdata[31:0]"},
"WREADY": { "actual": "S_AXI_wready[0:0]"},
"WSTRB": { "actual": "S_AXI_wstrb[3:0]"},
"WVALID": { "actual": "S_AXI_wvalid[0:0]"}
}
},
"/riscv_core_with_axi_0_axi_periph/m01_couplers/M_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "M_ACLK"},
"ARADDR": { "actual": "M_AXI_araddr[63:32]"},
"ARESETN": { "actual": "M_ARESETN"},
"ARPROT": { "actual": "M_AXI_arprot[5:3]"},
"ARREADY": { "actual": "M_AXI_arready"},
"ARVALID": { "actual": "M_AXI_arvalid"},
"AWADDR": { "actual": "M_AXI_awaddr[63:32]"},
"AWPROT": { "actual": "M_AXI_awprot[5:3]"},
"AWREADY": { "actual": "M_AXI_awready"},
"AWVALID": { "actual": "M_AXI_awvalid"},
"BREADY": { "actual": "M_AXI_bready"},
"BRESP": { "actual": "M_AXI_bresp[3:2]"},
"BVALID": { "actual": "M_AXI_bvalid"},
"RDATA": { "actual": "M_AXI_rdata[63:32]"},
"RREADY": { "actual": "M_AXI_rready"},
"RRESP": { "actual": "M_AXI_rresp[3:2]"},
"RVALID": { "actual": "M_AXI_rvalid"},
"WDATA": { "actual": "M_AXI_wdata[63:32]"},
"WREADY": { "actual": "M_AXI_wready"},
"WSTRB": { "actual": "M_AXI_wstrb[7:4]"},
"WVALID": { "actual": "M_AXI_wvalid"}
}
},
"/riscv_core_with_axi_0_axi_periph/m01_couplers/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "S_ACLK"},
"ARADDR": { "actual": "S_AXI_araddr[63:32]"},
"ARESETN": { "actual": "S_ARESETN"},
"ARPROT": { "actual": "S_AXI_arprot[5:3]"},
"ARREADY": { "actual": "S_AXI_arready"},
"ARVALID": { "actual": "S_AXI_arvalid"},
"AWADDR": { "actual": "S_AXI_awaddr[63:32]"},
"AWPROT": { "actual": "S_AXI_awprot[5:3]"},
"AWREADY": { "actual": "S_AXI_awready"},
"AWVALID": { "actual": "S_AXI_awvalid"},
"BREADY": { "actual": "S_AXI_bready"},
"BRESP": { "actual": "S_AXI_bresp[3:2]"},
"BVALID": { "actual": "S_AXI_bvalid"},
"RDATA": { "actual": "S_AXI_rdata[63:32]"},
"RREADY": { "actual": "S_AXI_rready"},
"RRESP": { "actual": "S_AXI_rresp[3:2]"},
"RVALID": { "actual": "S_AXI_rvalid"},
"WDATA": { "actual": "S_AXI_wdata[63:32]"},
"WREADY": { "actual": "S_AXI_wready"},
"WSTRB": { "actual": "S_AXI_wstrb[7:4]"},
"WVALID": { "actual": "S_AXI_wvalid"}
}
},
"/riscv_core_with_axi_0_axi_periph/s00_couplers/M_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "M_ACLK"},
"ARADDR": { "actual": "M_AXI_araddr[31:0]"},
"ARESETN": { "actual": "M_ARESETN"},
"ARPROT": { "actual": "M_AXI_arprot[2:0]"},
"ARREADY": { "actual": "M_AXI_arready"},
"ARVALID": { "actual": "M_AXI_arvalid"},
"AWADDR": { "actual": "M_AXI_awaddr[31:0]"},
"AWPROT": { "actual": "M_AXI_awprot[2:0]"},
"AWREADY": { "actual": "M_AXI_awready"},
"AWVALID": { "actual": "M_AXI_awvalid"},
"BREADY": { "actual": "M_AXI_bready"},
"BRESP": { "actual": "M_AXI_bresp[1:0]"},
"BVALID": { "actual": "M_AXI_bvalid"},
"RDATA": { "actual": "M_AXI_rdata[31:0]"},
"RREADY": { "actual": "M_AXI_rready"},
"RRESP": { "actual": "M_AXI_rresp[1:0]"},
"RVALID": { "actual": "M_AXI_rvalid"},
"WDATA": { "actual": "M_AXI_wdata[31:0]"},
"WREADY": { "actual": "M_AXI_wready"},
"WSTRB": { "actual": "M_AXI_wstrb[3:0]"},
"WVALID": { "actual": "M_AXI_wvalid"}
}
},
"/riscv_core_with_axi_0_axi_periph/s00_couplers/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "S_ACLK"},
"ARADDR": { "actual": "S_AXI_araddr[31:0]"},
"ARESETN": { "actual": "S_ARESETN"},
"ARPROT": { "actual": "S_AXI_arprot[2:0]"},
"ARREADY": { "actual": "S_AXI_arready"},
"ARVALID": { "actual": "S_AXI_arvalid"},
"AWADDR": { "actual": "S_AXI_awaddr[31:0]"},
"AWPROT": { "actual": "S_AXI_awprot[2:0]"},
"AWREADY": { "actual": "S_AXI_awready"},
"AWVALID": { "actual": "S_AXI_awvalid"},
"BREADY": { "actual": "S_AXI_bready"},
"BRESP": { "actual": "S_AXI_bresp[1:0]"},
"BVALID": { "actual": "S_AXI_bvalid"},
"RDATA": { "actual": "S_AXI_rdata[31:0]"},
"RREADY": { "actual": "S_AXI_rready"},
"RRESP": { "actual": "S_AXI_rresp[1:0]"},
"RVALID": { "actual": "S_AXI_rvalid"},
"WDATA": { "actual": "S_AXI_wdata[31:0]"},
"WREADY": { "actual": "S_AXI_wready"},
"WSTRB": { "actual": "S_AXI_wstrb[3:0]"},
"WVALID": { "actual": "S_AXI_wvalid"}
}
},
"/riscv_core_with_axi_0_axi_periph/xbar/M00_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "m_axi_araddr[31:0]"},
"ARESETN": { "actual": "aresetn"},
"ARPROT": { "actual": "m_axi_arprot[2:0]"},
"ARREADY": { "actual": "m_axi_arready[0:0]"},
"ARVALID": { "actual": "m_axi_arvalid[0:0]"},
"AWADDR": { "actual": "m_axi_awaddr[31:0]"},
"AWPROT": { "actual": "m_axi_awprot[2:0]"},
"AWREADY": { "actual": "m_axi_awready[0:0]"},
"AWVALID": { "actual": "m_axi_awvalid[0:0]"},
"BREADY": { "actual": "m_axi_bready[0:0]"},
"BRESP": { "actual": "m_axi_bresp[1:0]"},
"BVALID": { "actual": "m_axi_bvalid[0:0]"},
"RDATA": { "actual": "m_axi_rdata[31:0]"},
"RREADY": { "actual": "m_axi_rready[0:0]"},
"RRESP": { "actual": "m_axi_rresp[1:0]"},
"RVALID": { "actual": "m_axi_rvalid[0:0]"},
"WDATA": { "actual": "m_axi_wdata[31:0]"},
"WREADY": { "actual": "m_axi_wready[0:0]"},
"WSTRB": { "actual": "m_axi_wstrb[3:0]"},
"WVALID": { "actual": "m_axi_wvalid[0:0]"}
}
},
"/riscv_core_with_axi_0_axi_periph/xbar/M01_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "m_axi_araddr[63:32]"},
"ARESETN": { "actual": "aresetn"},
"ARPROT": { "actual": "m_axi_arprot[5:3]"},
"ARREADY": { "actual": "m_axi_arready[1:1]"},
"ARVALID": { "actual": "m_axi_arvalid[1:1]"},
"AWADDR": { "actual": "m_axi_awaddr[63:32]"},
"AWPROT": { "actual": "m_axi_awprot[5:3]"},
"AWREADY": { "actual": "m_axi_awready[1:1]"},
"AWVALID": { "actual": "m_axi_awvalid[1:1]"},
"BREADY": { "actual": "m_axi_bready[1:1]"},
"BRESP": { "actual": "m_axi_bresp[3:2]"},
"BVALID": { "actual": "m_axi_bvalid[1:1]"},
"RDATA": { "actual": "m_axi_rdata[63:32]"},
"RREADY": { "actual": "m_axi_rready[1:1]"},
"RRESP": { "actual": "m_axi_rresp[3:2]"},
"RVALID": { "actual": "m_axi_rvalid[1:1]"},
"WDATA": { "actual": "m_axi_wdata[63:32]"},
"WREADY": { "actual": "m_axi_wready[1:1]"},
"WSTRB": { "actual": "m_axi_wstrb[7:4]"},
"WVALID": { "actual": "m_axi_wvalid[1:1]"}
}
},
"/riscv_core_with_axi_0_axi_periph/xbar/S00_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "s_axi_araddr[31:0]"},
"ARESETN": { "actual": "aresetn"},
"ARPROT": { "actual": "s_axi_arprot[2:0]"},
"ARREADY": { "actual": "s_axi_arready[0:0]"},
"ARVALID": { "actual": "s_axi_arvalid[0:0]"},
"AWADDR": { "actual": "s_axi_awaddr[31:0]"},
"AWPROT": { "actual": "s_axi_awprot[2:0]"},
"AWREADY": { "actual": "s_axi_awready[0:0]"},
"AWVALID": { "actual": "s_axi_awvalid[0:0]"},
"BREADY": { "actual": "s_axi_bready[0:0]"},
"BRESP": { "actual": "s_axi_bresp[1:0]"},
"BVALID": { "actual": "s_axi_bvalid[0:0]"},
"RDATA": { "actual": "s_axi_rdata[31:0]"},
"RREADY": { "actual": "s_axi_rready[0:0]"},
"RRESP": { "actual": "s_axi_rresp[1:0]"},
"RVALID": { "actual": "s_axi_rvalid[0:0]"},
"WDATA": { "actual": "s_axi_wdata[31:0]"},
"WREADY": { "actual": "s_axi_wready[0:0]"},
"WSTRB": { "actual": "s_axi_wstrb[3:0]"},
"WVALID": { "actual": "s_axi_wvalid[0:0]"}
}
}
}
}
}
}
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.ip_user_files/ip/ram4KB/ram4KB.veo 0 → 100644
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// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
// IP Revision: 4
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
ram4KB your_instance_name (
.clka(clka), // input wire clka
.ena(ena), // input wire ena
.wea(wea), // input wire [3 : 0] wea
.addra(addra), // input wire [9 : 0] addra
.dina(dina), // input wire [31 : 0] dina
.douta(douta) // output wire [31 : 0] douta
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file ram4KB.v when simulating
// the core, ram4KB. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.ip_user_files/ip/ram4KB/ram4KB.vho 0 → 100644
浏览文件 @ b526a473
-- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
-- IP Revision: 4
-- The following code must appear in the VHDL architecture header.
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT ram4KB
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : ram4KB
PORT MAP (
clka => clka,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- INST_TAG_END ------ End INSTANTIATION Template ---------
-- You must compile the wrapper file ram4KB.vhd when simulating
-- the core, ram4KB. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.ip_user_files/mem_init_files/risc_axi_v5_top.bda 0 → 100644
浏览文件 @ b526a473
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<data key="EH">2</data>
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</edge>
</graph>
</graphml>
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.srcs/sources_1/bd/risc_axi_v5_top/risc_axi_v5_top.bda 0 → 100644
浏览文件 @ b526a473
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<key attr.name="vert_name" attr.type="string" for="node" id="VM"/>
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<data key="BA">0xF0000000</data>
<data key="BP">C_BASEADDR</data>
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<data key="MX">/riscv_core_with_axi_0</data>
<data key="MI">m00_axi</data>
<data key="MS">SEG_led_key_0_reg0</data>
<data key="MV">xilinx.com:module_ref:riscv_core_with_axi_master_xilinxwrap:1.0</data>
<data key="TM">both</data>
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<data key="SI">s00_axi</data>
<data key="SS">reg0</data>
<data key="SV">xilinx.com:module_ref:led_key:1.0</data>
<data key="TU">register</data>
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<data key="VT">VR</data>
</node>
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<data key="BP">C_BASEADDR</data>
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<data key="MX">/riscv_core_with_axi_0</data>
<data key="MI">m00_axi</data>
<data key="MS">SEG_axi_uartlite_0_Reg</data>
<data key="MV">xilinx.com:module_ref:riscv_core_with_axi_master_xilinxwrap:1.0</data>
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<data key="SV">xilinx.com:ip:axi_uartlite:2.0</data>
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</graphml>
examples/hdl4se_riscv/z7/riscv_zynq_v5/riscv_zynq_v5.ip_user_files/mem_init_files/design_1.bda 0 → 100644
浏览文件 @ b526a473
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<graphml xmlns="http://graphml.graphdrawing.org/xmlns" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://graphml.graphdrawing.org/xmlns http://graphml.graphdrawing.org/xmlns/1.0/graphml.xsd">
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examples/hdl4se_riscv/z7/riscv_zynq_v5/riscv_zynq_v5.srcs/sources_1/bd/design_1/design_1.bda 0 → 100644
浏览文件 @ b526a473
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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