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202109131348

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examples/hdl4se_riscv/test_code/console.c
浏览文件 @ cbd5fc48
......@@ -567,7 +567,7 @@ void testisa()
int main(int argc, char* argv[])
{
int count = 1;
#if 1
#if 0
*(unsigned int*)0xf0000004 = (1 << 15) | (1 << 18);
do {
count = count + 1;
......
examples/hdl4se_riscv/test_code/test.cod
浏览文件 @ cbd5fc48
@00000000
37 11 00 00 EF 00 80 00 6F F0 9F FF
37 11 00 00 EF 00 10 24 6F F0 9F FF
@0000000C
13 01 01 FE 23 2E 81 00 13 04 01 02 B7 07 00 F0
93 87 07 10 23 26 F4 FE 83 27 C4 FE 93 87 87 00
83 A7 07 00 23 24 F4 FE 83 27 84 FE 93 F7 87 00
93 B7 17 00 93 F7 F7 0F 13 85 07 00 03 24 C1 01
13 01 01 02 67 80 00 00
@00000054
13 01 01 FE 23 2E 81 00 13 04 01 02 B7 07 00 F0
93 87 07 10 23 26 F4 FE 83 27 C4 FE 93 87 87 00
83 A7 07 00 23 24 F4 FE 83 27 84 FE 93 F7 17 00
93 87 F7 FF 93 B7 17 00 93 F7 F7 0F 13 85 07 00
03 24 C1 01 13 01 01 02 67 80 00 00
@000000A0
13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03
23 2E A4 FC B7 07 00 F0 93 87 07 10 23 26 F4 FE
EF F0 DF F4 93 07 05 00 63 8E 07 00 83 27 C4 FE
93 87 47 00 03 27 C4 FD 23 A0 E7 00 93 07 00 00
6F 00 80 00 93 07 F0 FF 13 85 07 00 83 20 C1 02
03 24 81 02 13 01 01 03 67 80 00 00
@000000FC
13 01 01 FE 23 2E 11 00 23 2C 81 00 13 04 01 02
B7 07 00 F0 93 87 07 10 23 26 F4 FE EF F0 DF F3
93 07 05 00 63 88 07 00 83 27 C4 FE 83 A7 07 00
6F 00 80 00 93 07 F0 FF 13 85 07 00 83 20 C1 01
03 24 81 01 13 01 01 02 67 80 00 00
@00000148
13 01 01 FE 23 2E 11 00 23 2C 81 00 13 04 01 02
23 26 A4 FE 6F 00 00 03 13 00 00 00 83 27 C4 FE
83 C7 07 00 13 85 07 00 EF F0 1F F3 13 07 05 00
93 07 F0 FF E3 04 F7 FE 83 27 C4 FE 93 87 17 00
23 26 F4 FE 83 27 C4 FE 83 C7 07 00 E3 96 07 FC
93 07 00 00 13 85 07 00 83 20 C1 01 03 24 81 01
13 01 01 02 67 80 00 00
@000001B0
13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03
23 2E A4 FC 23 2C B4 FC 23 26 04 FE 03 27 84 FD
93 07 10 00 63 C6 E7 00 93 07 00 00 6F 00 80 09
EF F0 DF F1 23 24 A4 FE 03 27 84 FE 93 07 F0 FF
E3 08 F7 FE 83 27 C4 FE 13 87 17 00 23 26 E4 FE
13 87 07 00 83 27 C4 FD B3 87 E7 00 03 27 84 FE
13 77 F7 0F 23 80 E7 00 13 00 00 00 03 25 84 FE
EF F0 1F E8 13 07 05 00 93 07 F0 FF E3 08 F7 FE
83 27 84 FD 93 87 F7 FF 03 27 C4 FE 63 50 F7 02
03 27 84 FE 93 07 A0 00 63 0C F7 00 03 27 84 FE
93 07 D0 00 63 06 F7 00 6F F0 9F F8 13 00 00 00
83 27 C4 FE 03 27 C4 FD B3 07 F7 00 23 80 07 00
83 27 C4 FE 13 85 07 00 83 20 C1 02 03 24 81 02
13 01 01 03 67 80 00 00
@00000288
13 01 01 FC 23 2E 81 02 13 04 01 04 23 26 A4 FC
23 24 B4 FC 23 24 04 FE 23 22 04 FE 83 27 84 FC
63 DA 07 00 83 27 84 FC B3 07 F0 40 23 24 F4 FC
23 22 04 FE 83 27 84 FC 63 96 07 06 83 27 84 FE
13 87 17 00 23 24 E4 FE 13 87 07 00 83 27 C4 FC
B3 87 E7 00 13 07 00 03 23 80 E7 00 6F 00 80 07
03 27 84 FC 93 07 A0 00 B3 67 F7 02 13 F7 F7 0F
83 27 84 FE 93 86 17 00 23 24 D4 FE 93 86 07 00
83 27 C4 FC B3 87 D7 00 13 07 07 03 13 77 F7 0F
23 80 E7 00 03 27 84 FC 93 07 A0 00 B3 47 F7 02
23 24 F4 FC 83 27 84 FC E3 4C F0 FA 83 27 44 FE
63 82 07 02 83 27 84 FE 13 87 17 00 23 24 E4 FE
13 87 07 00 83 27 C4 FC B3 87 E7 00 13 07 D0 02
23 80 E7 00 23 26 04 FE 6F 00 C0 06 83 27 84 FE
13 87 F7 FF 83 27 C4 FE B3 07 F7 40 23 20 F4 FE
83 27 C4 FE 03 27 C4 FC B3 07 F7 00 83 C7 07 00
A3 0F F4 FC 83 27 04 FE 03 27 C4 FC 33 07 F7 00
83 27 C4 FE 83 26 C4 FC B3 87 F6 00 03 47 07 00
23 80 E7 00 83 27 04 FE 03 27 C4 FC B3 07 F7 00
03 47 F4 FD 23 80 E7 00 83 27 C4 FE 93 87 17 00
23 26 F4 FE 83 27 84 FE 13 D7 F7 01 B3 07 F7 00
93 D7 17 40 13 87 07 00 83 27 C4 FE E3 C0 E7 F8
83 27 84 FE 03 27 C4 FC B3 07 F7 00 23 80 07 00
83 27 84 FE 13 85 07 00 03 24 C1 03 13 01 01 04
67 80 00 00
@0000040C
13 01 01 FB 23 26 81 04 13 04 01 05 23 26 A4 FC
23 20 B4 FC 23 22 C4 FC 23 24 D4 FC 93 07 07 00
A3 0F F4 FA 23 24 04 FE 6F 00 00 09 83 27 04 FC
93 F7 F7 00 23 2E F4 FC 03 27 C4 FD 93 07 90 00
63 C4 E7 02 83 27 C4 FD 13 F7 F7 0F 83 27 84 FE
83 26 C4 FC B3 87 F6 00 13 07 07 03 13 77 F7 0F
23 80 E7 00 6F 00 40 02 83 27 C4 FD 13 F7 F7 0F
83 27 84 FE 83 26 C4 FC B3 87 F6 00 13 07 77 05
13 77 F7 0F 23 80 E7 00 83 27 44 FC 93 97 C7 01
03 27 04 FC 13 58 47 00 33 E8 07 01 83 27 44 FC
93 D8 47 00 23 20 04 FD 23 22 14 FD 83 27 84 FE
93 87 17 00 23 24 F4 FE 83 27 04 FC 03 27 44 FC
B3 E7 E7 00 E3 94 07 F6 6F 00 40 02 83 27 84 FE
13 87 17 00 23 24 E4 FE 13 87 07 00 83 27 C4 FC
B3 87 E7 00 03 47 F4 FB 23 80 E7 00 03 27 84 FE
83 27 84 FC E3 4C F7 FC 23 26 04 FE 6F 00 C0 06
83 27 84 FE 13 87 F7 FF 83 27 C4 FE B3 07 F7 40
23 22 F4 FE 83 27 C4 FE 03 27 C4 FC B3 07 F7 00
83 C7 07 00 A3 01 F4 FE 83 27 44 FE 03 27 C4 FC
33 07 F7 00 83 27 C4 FE 83 26 C4 FC B3 87 F6 00
03 47 07 00 23 80 E7 00 83 27 44 FE 03 27 C4 FC
B3 07 F7 00 03 47 34 FE 23 80 E7 00 83 27 C4 FE
93 87 17 00 23 26 F4 FE 83 27 84 FE 13 D7 F7 01
B3 07 F7 00 93 D7 17 40 13 87 07 00 83 27 C4 FE
E3 C0 E7 F8 83 27 84 FE 03 27 C4 FC B3 07 F7 00
23 80 07 00 83 27 84 FE 13 85 07 00 03 24 C1 04
13 01 01 05 67 80 00 00
@000005B4
13 01 01 FD 23 26 81 02 13 04 01 03 23 2E A4 FC
23 2C B4 FC 93 07 10 00 23 26 F4 FE B7 07 00 F0
93 87 47 00 37 87 04 00 23 A0 E7 00 83 27 C4 FE
93 87 17 00 23 26 F4 FE B7 07 00 F0 93 87 47 00
03 27 C4 FE 23 A0 E7 00 6F F0 5F FE
23 2C B4 FC 23 26 04 FE 23 24 04 FE 93 07 10 00
23 22 F4 FE 6F 00 C0 08 83 27 C4 FD 83 C7 07 00
23 20 F4 FE 03 27 04 FE 93 07 F0 02 63 D2 E7 04
03 27 04 FE 93 07 90 03 63 CC E7 02 03 27 84 FE
93 07 07 00 93 97 27 00 B3 87 E7 00 93 97 17 00
13 87 07 00 83 27 04 FE B3 07 F7 00 93 87 07 FD
23 24 F4 FE 93 07 10 00 23 26 F4 FE 6F 00 80 02
83 27 C4 FE 63 9E 07 02 03 27 04 FE 93 07 D0 02
63 1A F7 00 93 07 F0 FF 23 22 F4 FE 93 07 10 00
23 26 F4 FE 83 27 C4 FD 93 87 17 00 23 2E F4 FC
83 27 C4 FD 83 C7 07 00 E3 98 07 F6 6F 00 80 00
13 00 00 00 03 27 84 FE 83 27 44 FE B3 07 F7 02
23 24 F4 FE 83 27 84 FD 63 88 07 00 83 27 84 FD
03 27 C4 FD 23 A0 E7 00 83 27 84 FE 13 85 07 00
03 24 C1 02 13 01 01 03 67 80 00 00
@000006B0
13 01 01 FD 23 26 81 02 13 04 01 03 23 2E A4 FC
23 2C B4 FC 23 26 04 FE 23 24 04 FE 6F 00 00 0E
83 27 C4 FD 83 C7 07 00 23 22 F4 FE 03 27 44 FE
93 07 F0 02 63 DA E7 02 03 27 44 FE 93 07 90 03
63 C4 E7 02 93 07 10 00 23 26 F4 FE 83 27 84 FE
13 97 47 00 83 27 44 FE B3 07 F7 00 93 87 07 FD
23 24 F4 FE 6F 00 C0 08 03 27 44 FE 93 07 00 06
63 DA E7 02 03 27 44 FE 93 07 60 06 63 C4 E7 02
93 07 10 00 23 26 F4 FE 83 27 84 FE 13 97 47 00
83 27 44 FE B3 07 F7 00 93 87 97 FA 23 24 F4 FE
6F 00 00 05 03 27 44 FE 93 07 00 04 63 DA E7 02
03 27 44 FE 93 07 60 04 63 C4 E7 02 93 07 10 00
23 26 F4 FE 83 27 84 FE 13 97 47 00 83 27 44 FE
B3 07 F7 00 93 87 97 FC 23 24 F4 FE 6F 00 40 01
83 27 C4 FE 63 94 07 02 93 07 10 00 23 26 F4 FE
83 27 C4 FD 93 87 17 00 23 2E F4 FC 83 27 C4 FD
83 C7 07 00 E3 9E 07 F0 6F 00 80 00 13 00 00 00
83 27 84 FD 63 88 07 00 83 27 84 FD 03 27 C4 FD
23 A0 E7 00 83 27 84 FE 13 85 07 00 03 24 C1 02
13 01 01 03 67 80 00 00
@000007E8
13 01 01 FB 23 26 11 04 23 24 81 04 23 22 21 05
23 20 31 05 23 2E 41 03 23 2C 51 03 13 04 01 05
B7 17 00 00 83 A7 87 E8 93 F7 07 FF 23 2A F4 FC
23 2C 04 FC 6F 00 C0 1B 83 27 44 FD 13 89 07 00
93 09 00 00 93 07 C4 FB 13 07 00 03 93 06 80 00
93 05 09 00 13 86 09 00 13 85 07 00 EF F0 9F BC
93 07 C4 FB 13 85 07 00 EF F0 9F 8F B7 17 00 00
13 85 07 E4 EF F0 DF 8E 23 2E 04 FC 6F 00 40 0A
83 27 44 FD 23 26 F4 FC 03 27 C4 FD 83 27 44 FD
33 07 F7 00 B7 17 00 00 83 A7 87 E8 63 7A F7 00
B7 17 00 00 13 85 47 E4 EF F0 9F 8B 6F 00 00 05
83 27 C4 FD 03 27 C4 FC B3 07 F7 00 83 C7 07 00
13 8A 07 00 93 0A 00 00 93 07 C4 FB 13 07 00 03
93 06 20 00 93 05 0A 00 13 86 0A 00 13 85 07 00
EF F0 5F B4 93 07 C4 FB 13 85 07 00 EF F0 5F 87
B7 17 00 00 13 85 87 E4 EF F0 9F 86 03 27 C4 FD
93 07 70 00 63 18 F7 00 B7 17 00 00 13 85 C7 E4
EF F0 1F 85 83 27 C4 FD 93 87 17 00 23 2E F4 FC
03 27 C4 FD 93 07 F0 00 E3 DC E7 F4 B7 17 00 00
13 85 07 E5 EF F0 DF 82 23 2E 04 FC 6F 00 80 07
83 27 44 FD 23 28 F4 FC 83 27 C4 FD 03 27 04 FD
B3 07 F7 00 03 C7 07 00 93 07 F0 01 63 FA E7 02
83 27 C4 FD 03 27 04 FD B3 07 F7 00 03 C7 07 00
93 07 E0 07 63 EE E7 00 83 27 C4 FD 03 27 04 FD
B3 07 F7 00 83 C7 07 00 23 0E F4 FA 6F 00 C0 00
93 07 E0 02 23 0E F4 FA A3 0E 04 FA 93 07 C4 FB
13 85 07 00 EF F0 CF FB 83 27 C4 FD 93 87 17 00
23 2E F4 FC 03 27 C4 FD 93 07 F0 00 E3 D2 E7 F8
B7 17 00 00 13 85 47 E5 EF F0 8F F9 83 27 44 FD
93 87 07 01 23 2A F4 FC 83 27 44 FD 93 F7 F7 0F
63 80 07 02 83 27 84 FD 93 87 17 00 23 2C F4 FC
03 27 84 FD 93 07 F0 00 E3 D0 E7 E4 6F 00 80 00
13 00 00 00 B7 17 00 00 13 85 87 E5 EF F0 4F F5
B7 17 00 00 03 27 44 FD 23 A4 E7 E8 13 00 00 00
83 20 C1 04 03 24 81 04 03 29 41 04 83 29 01 04
03 2A C1 03 83 2A 81 03 13 01 01 05 67 80 00 00
@00000A28
13 01 01 FF 23 26 81 00 13 04 01 01 13 00 00 00
03 24 C1 00 13 01 01 01 67 80 00 00
@00000A44
13 01 01 F7 23 26 11 08 23 24 81 08 23 22 21 09
23 20 31 09 23 2E 41 07 23 2C 51 07 13 04 01 09
23 2E A4 F6 23 2C B4 F6 93 07 10 00 23 2E F4 FC
B7 07 00 F0 93 87 07 10 23 2A F4 FC 83 27 44 FD
93 87 C7 00 13 07 20 1B 23 A0 E7 00 EF F0 CF D7
93 07 05 00 63 88 07 00 B7 17 00 00 13 85 C7 E5
EF F0 4F EA 83 27 C4 FD 93 87 17 00 23 2E F4 FC
B7 07 00 F0 93 87 47 00 03 27 C4 FD 23 A0 E7 00
EF F0 0F D9 93 07 05 00 63 86 07 04 93 07 44 F8
93 05 70 02 13 85 07 00 EF F0 4F ED 13 00 00 00
B7 17 00 00 13 85 07 E6 EF F0 CF E5 93 07 44 F8
13 85 07 00 EF F0 0F E5 B7 17 00 00 13 85 87 E5
EF F0 4F E4 03 47 44 F8 93 07 20 06 63 1E F7 06
6F 00 40 02 83 27 C4 FD 93 87 17 00 23 2E F4 FC
B7 07 00 F0 93 87 47 00 03 27 C4 FD 23 A0 E7 00
6F F0 1F F9 93 07 44 F8 93 87 27 00 93 05 00 00
13 85 07 00 EF F0 DF A6 23 2C A4 FA 83 27 84 FB
63 58 F0 02 B7 07 00 F0 93 87 07 10 23 2A F4 FA
B7 F7 FA 02 13 87 07 08 83 27 84 FB 33 47 F7 02
83 27 44 FB 93 87 C7 00 23 A0 E7 00 6F 00 C0 2A
EF F0 5F EA 6F 00 40 2A 03 47 44 F8 93 07 40 06
63 1C F7 02 93 07 44 F8 93 87 27 00 93 05 00 00
13 85 07 00 EF F0 9F B0 23 2E A4 FA 83 27 C4 FB
63 58 F0 00 03 27 C4 FB B7 17 00 00 23 A4 E7 E8
EF F0 5F C2 6F 00 40 26 03 47 44 F8 93 07 70 07
63 1C F7 0A 93 07 44 F8 93 87 27 00 13 07 04 FB
93 05 07 00 13 85 07 00 EF F0 5F AC 23 24 A4 FC
83 27 04 FB 13 07 04 FB 93 05 07 00 13 85 07 00
EF F0 DF AA 23 22 A4 FC 83 27 04 FB 13 07 04 FB
93 05 07 00 13 85 07 00 EF F0 5F A9 23 20 A4 FC
03 27 04 FC 93 07 10 00 63 1C F7 00 83 27 84 FC
03 27 44 FC 13 77 F7 0F 23 80 E7 00 6F 00 C0 1E
03 27 04 FC 93 07 20 00 63 1E F7 00 83 27 84 FC
03 27 44 FC 13 17 07 01 13 57 07 41 23 90 E7 00
6F 00 80 1C 03 27 04 FC 93 07 40 00 63 1A F7 00
83 27 84 FC 03 27 44 FC 23 A0 E7 00 6F 00 C0 1A
EF F0 5F DA 6F 00 40 1A 03 47 44 F8 93 07 20 07
63 1A F7 18 23 2C 04 FC 93 07 44 F8 93 87 27 00
13 07 C4 FA 93 05 07 00 13 85 07 00 EF F0 1F A0
23 28 A4 FC 83 27 C4 FA 13 07 C4 FA 93 05 07 00
13 85 07 00 EF F0 9F 9E 23 26 A4 FC 03 27 C4 FC
93 07 10 00 63 10 F7 02 83 27 04 FD 83 C7 07 00
23 2C F4 FC B7 17 00 00 13 85 47 E6 EF F0 8F C5
6F 00 80 05 03 27 C4 FC 93 07 20 00 63 10 F7 02
83 27 04 FD 83 97 07 00 23 2C F4 FC B7 17 00 00
13 85 C7 E6 EF F0 0F C3 6F 00 00 03 03 27 C4 FC
93 07 40 00 63 10 F7 02 83 27 04 FD 83 A7 07 00
23 2C F4 FC B7 17 00 00 13 85 47 E7 EF F0 8F C0
6F 00 80 00 EF F0 1F CE 03 27 C4 FC 93 07 10 00
63 0E F7 00 03 27 C4 FC 93 07 20 00 63 08 F7 00
03 27 C4 FC 93 07 40 00 63 10 F7 0C 83 27 04 FD
13 89 07 00 93 D7 F7 41 93 89 07 00 93 07 44 F8
13 07 00 03 93 06 80 00 93 05 09 00 13 86 09 00
13 85 07 00 EF F0 4F E7 93 07 44 F8 13 85 07 00
EF F0 4F BA B7 17 00 00 13 85 C7 E7 EF F0 8F B9
93 07 44 F8 83 25 84 FD 13 85 07 00 EF F0 8F CC
93 07 44 F8 13 85 07 00 EF F0 CF B7 B7 17 00 00
13 85 07 E8 EF F0 0F B7 83 27 84 FD 13 8A 07 00
93 D7 F7 41 93 8A 07 00 83 27 C4 FC 93 96 17 00
93 07 44 F8 13 07 00 03 93 05 0A 00 13 86 0A 00
13 85 07 00 EF F0 4F E0 93 07 44 F8 13 85 07 00
EF F0 4F B3 B7 17 00 00 13 85 47 E8 EF F0 8F B2
6F 00 80 00 EF F0 1F C0 13 00 00 00 EF F0 CF 9D
93 07 05 00 E3 8C 07 FE 6F F0 5F C5
@00000E40
20 20 00 00 20 20 20 00 20 00 00 00 2D 20 00 00
20 20 7C 00 7C 0A 00 00 0A 0D 00 00 3E 3E 00 00
0A 0D 3A 00 63 68 61 72 20 40 00 00 73 68 6F 72
74 20 40 00 69 6E 74 20 40 00 00 00 20 3D 20 00
28 00 00 00 29 0A 0D 00
@00000E88
01 00 00 00
examples/hdl4se_riscv/test_code/test.coe
浏览文件 @ cbd5fc48
memory_initialization_radix = 16;
memory_initialization_vector =
1137,
8000EF,
241000EF,
FF9FF06F,
FE010113,
812E23,
2010413,
F00007B7,
10078793,
FEF42623,
FEC42783,
878793,
7A783,
FEF42423,
FE842783,
87F793,
17B793,
FF7F793,
78513,
1C12403,
2010113,
8067,
FE010113,
812E23,
2010413,
F00007B7,
10078793,
FEF42623,
FEC42783,
878793,
7A783,
FEF42423,
FE842783,
17F793,
FFF78793,
17B793,
FF7F793,
78513,
1C12403,
2010113,
8067,
FD010113,
2112623,
2812423,
3010413,
FCA42E23,
F00007B7,
10078793,
FEF42623,
F4DFF0EF,
50793,
78E63,
FEC42783,
478793,
FDC42703,
E7A023,
793,
80006F,
FFF00793,
78513,
2C12083,
2812403,
3010113,
8067,
FE010113,
112E23,
812C23,
2010413,
F00007B7,
10078793,
FEF42623,
F3DFF0EF,
50793,
78863,
FEC42783,
7A783,
80006F,
FFF00793,
78513,
1C12083,
1812403,
2010113,
8067,
FE010113,
112E23,
812C23,
2010413,
FEA42623,
300006F,
13,
FEC42783,
7C783,
78513,
F31FF0EF,
50713,
FFF00793,
FEF704E3,
FEC42783,
178793,
FEF42623,
FEC42783,
7C783,
FC0796E3,
793,
78513,
1C12083,
1812403,
2010113,
8067,
FD010113,
2112623,
2812423,
3010413,
FCA42E23,
FCB42C23,
FE042623,
FD842703,
100793,
E7C663,
793,
980006F,
F1DFF0EF,
FEA42423,
FE842703,
FFF00793,
FEF708E3,
FEC42783,
178713,
FEE42623,
78713,
FDC42783,
E787B3,
FE842703,
FF77713,
E78023,
13,
FE842503,
E81FF0EF,
50713,
FFF00793,
FEF708E3,
FD842783,
FFF78793,
FEC42703,
2F75063,
FE842703,
A00793,
F70C63,
FE842703,
D00793,
F70663,
F89FF06F,
13,
FEC42783,
FDC42703,
F707B3,
78023,
FEC42783,
78513,
2C12083,
2812403,
3010113,
8067,
FC010113,
2812E23,
4010413,
FCA42623,
FCB42423,
FE042423,
FE042223,
FC842783,
7DA63,
FC842783,
40F007B3,
FCF42423,
FE042223,
FC842783,
6079663,
FE842783,
178713,
FEE42423,
78713,
FCC42783,
E787B3,
3000713,
E78023,
780006F,
FC842703,
A00793,
2F767B3,
FF7F713,
FE842783,
178693,
FED42423,
78693,
FCC42783,
D787B3,
3070713,
FF77713,
E78023,
FC842703,
A00793,
2F747B3,
FCF42423,
FC842783,
FAF04CE3,
FE442783,
2078263,
FE842783,
178713,
FEE42423,
78713,
FCC42783,
E787B3,
2D00713,
E78023,
FE042623,
6C0006F,
FE842783,
FFF78713,
FEC42783,
40F707B3,
FEF42023,
FEC42783,
FCC42703,
F707B3,
7C783,
FCF40FA3,
FE042783,
FCC42703,
F70733,
FEC42783,
FCC42683,
F687B3,
74703,
E78023,
FE042783,
FCC42703,
F707B3,
FDF44703,
E78023,
FEC42783,
178793,
FEF42623,
FE842783,
1F7D713,
F707B3,
4017D793,
78713,
FEC42783,
F8E7C0E3,
FE842783,
FCC42703,
F707B3,
78023,
FE842783,
78513,
3C12403,
4010113,
8067,
FB010113,
4812623,
5010413,
FCA42623,
FCB42023,
FCC42223,
FCD42423,
70793,
FAF40FA3,
FE042423,
900006F,
FC042783,
F7F793,
FCF42E23,
FDC42703,
900793,
2E7C463,
FDC42783,
FF7F713,
FE842783,
FCC42683,
F687B3,
3070713,
FF77713,
E78023,
240006F,
FDC42783,
FF7F713,
FE842783,
FCC42683,
F687B3,
5770713,
FF77713,
E78023,
FC442783,
1C79793,
FC042703,
475813,
107E833,
FC442783,
47D893,
FD042023,
FD142223,
FE842783,
178793,
FEF42423,
FC042783,
FC442703,
E7E7B3,
F60794E3,
240006F,
FE842783,
178713,
FEE42423,
78713,
FCC42783,
E787B3,
FBF44703,
E78023,
FE842703,
FC842783,
FCF74CE3,
FE042623,
6C0006F,
FE842783,
FFF78713,
FEC42783,
40F707B3,
FEF42223,
FEC42783,
FCC42703,
F707B3,
7C783,
FEF401A3,
FE442783,
FCC42703,
F70733,
FEC42783,
FCC42683,
F687B3,
74703,
E78023,
FE442783,
FCC42703,
F707B3,
FE344703,
E78023,
FEC42783,
178793,
FEF42623,
FE842783,
1F7D713,
F707B3,
4017D793,
78713,
FEC42783,
F8E7C0E3,
FE842783,
FCC42703,
F707B3,
78023,
FE842783,
78513,
4C12403,
5010113,
8067,
FD010113,
2812623,
3010413,
FCA42E23,
FCB42C23,
FE042623,
FE042423,
100793,
FEF42223,
8C0006F,
FDC42783,
7C783,
FEF42023,
FE042703,
2F00793,
4E7D263,
FE042703,
3900793,
2E7CC63,
FE842703,
70793,
279793,
E787B3,
179793,
78713,
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CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
2AC0006F,
EA5FF0EF,
2A40006F,
F8444703,
6400793,
2F71C63,
F8440793,
278793,
593,
78513,
B09FF0EF,
FAA42E23,
FBC42783,
F05863,
FBC42703,
17B7,
E8E7A423,
C25FF0EF,
2640006F,
F8444703,
7700793,
AF71C63,
F8440793,
278793,
FB040713,
70593,
78513,
AC5FF0EF,
FCA42423,
FB042783,
FB040713,
70593,
78513,
AADFF0EF,
FCA42223,
FB042783,
FB040713,
70593,
78513,
A95FF0EF,
FCA42023,
FC042703,
100793,
F71C63,
FC842783,
FC442703,
FF77713,
E78023,
1EC0006F,
FC042703,
200793,
F71E63,
FC842783,
FC442703,
1071713,
41075713,
E79023,
1C80006F,
FC042703,
400793,
F71A63,
FC842783,
FC442703,
E7A023,
1AC0006F,
DA5FF0EF,
1A40006F,
F8444703,
7200793,
18F71A63,
FC042C23,
F8440793,
278793,
FAC40713,
70593,
78513,
A01FF0EF,
FCA42823,
FAC42783,
FAC40713,
70593,
78513,
9E9FF0EF,
FCA42623,
FCC42703,
100793,
2F71063,
FD042783,
7C783,
FCF42C23,
17B7,
E6478513,
C58FF0EF,
580006F,
FCC42703,
200793,
2F71063,
FD042783,
79783,
FCF42C23,
17B7,
E6C78513,
C30FF0EF,
300006F,
FCC42703,
400793,
2F71063,
FD042783,
7A783,
FCF42C23,
17B7,
E7478513,
C08FF0EF,
80006F,
CE1FF0EF,
FCC42703,
100793,
F70E63,
FCC42703,
200793,
F70863,
FCC42703,
400793,
CF71063,
FD042783,
78913,
41F7D793,
78993,
F8440793,
3000713,
800693,
90593,
98613,
78513,
E74FF0EF,
F8440793,
78513,
BA4FF0EF,
17B7,
E7C78513,
B98FF0EF,
F8440793,
FD842583,
78513,
CC8FF0EF,
F8440793,
78513,
B7CFF0EF,
17B7,
E8078513,
B70FF0EF,
FD842783,
78A13,
41F7D793,
78A93,
FCC42783,
179693,
F8440793,
3000713,
A0593,
A8613,
78513,
E04FF0EF,
F8440793,
78513,
B34FF0EF,
17B7,
E8478513,
B28FF0EF,
80006F,
C01FF0EF,
13,
9DCFF0EF,
50793,
FE078CE3,
C55FF06F,
2020,
202020,
20,
202D,
7C2020,
A7C,
D0A,
3E3E,
3A0D0A,
72616863,
4020,
726F6873,
402074,
20746E69,
40,
203D20,
28,
D0A29,
1,
1,
CDCDCDCD,
CDCDCDCD,
CDCDCDCD,
......
examples/hdl4se_riscv/test_code/test.hex
浏览文件 @ cbd5fc48
:0C00000037110000EF0080006FF09FFF40
:10000C00130101FD2326810213040103232EA4FCFA
:10001C00232CB4FC930710002326F4FEB70700F042
:10002C00938747003787040023A0E7008327C4FE8B
:10003C00938717002326F4FEB70700F09387470039
:0C004C000327C4FE23A0E7006FF05FFE56
:0C00000037110000EF0010246FF09FFF8C
:10000C00130101FE232E810013040102B70700F037
:10001C00938707102326F4FE8327C4FE938787005B
:10002C0083A707002324F4FE832784FE93F787001D
:10003C0093B7170093F7F70F138507000324C1013B
:08004C001301010267800000AE
:10005400130101FE232E810013040102B70700F0EF
:10006400938707102326F4FE8327C4FE9387870013
:1000740083A707002324F4FE832784FE93F7170045
:100084009387F7FF93B7170093F7F70F13850700CC
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:1000A000130101FD232611022324810213040103FD
:1000B000232EA4FCB70700F0938707102326F4FE35
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:1003B8000347F4FD2380E7008327C4FE93871700D3
:1003C8002326F4FE832784FE13D7F701B307F7002B
:1003D80093D71740138707008327C4FEE3C0E7F8C5
:1003E800832784FE0327C4FCB307F7002380070094
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:040408006780000009
:10040C00130101FB23268104130401052326A4FCFC
:10041C002320B4FC2322C4FC2324D4FC9307070020
:10042C00A30FF4FA232404FE6F000009832704FCB5
:10043C0093F7F700232EF4FC0327C4FD93079000D9
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:10048C001377F70F2380E700832744FC9397C7016A
:10049C00032704FC1358470033E80701832744FC67
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:10059C0023800700832784FE138507000324C104EE
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:1005B400130101FD2326810213040103232EA4FC4D
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:100604009307070093972700B387E7009397170092
:1006140013870700832704FEB307F700938707FDBA
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:1006740013000000032784FE832744FEB307F70218
:100684002324F4FE832784FD63880700832784FDE5
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:1006F00063C4E702930710002326F4FE832784FED9
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:10074000832744FEB307F700938797FA2324F4FE28
:100750006F000005032744FE9307000463DAE702F5
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:10078000B307F700938797FC2324F4FE6F00400122
:100790008327C4FE63940702930710002326F4FE08
:1007A0008327C4FD93871700232EF4FC8327C4FD01
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:100A1800032AC103832A81031301010567800000AB
:100A2800130101FF232681001304010113000000B4
:0C0A38000324C1001301010167800000CD
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:100E040013850700EFF04FE0930744F813850700BC
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:0C0E340093070500E38C07FE6FF05FC51C
:100E40002020000020202000200000002D20000095
:100E500020207C007C0A00000A0D00003E3E0000BD
:100E60000A0D3A00636861722040000073686F7277
:100E700074204000696E742040000000203D200076
:080E800028000000290A0D0002
:040E88000100000065
:00000001FF
examples/hdl4se_riscv/test_code/test.info
浏览文件 @ cbd5fc48
......@@ -10,25 +10,39 @@ ELF Header:
Version: 0x1
Entry point address: 0x0
Start of program headers: 52 (bytes into file)
Start of section headers: 4480 (bytes into file)
Start of section headers: 8840 (bytes into file)
Flags: 0x0
Size of this header: 52 (bytes)
Size of program headers: 32 (bytes)
Number of program headers: 1
Size of section headers: 40 (bytes)
Number of section headers: 8
Section header string table index: 7
Number of section headers: 22
Section header string table index: 21
Section Headers:
[Nr] Name Type Addr Off Size ES Flg Lk Inf Al
[ 0] NULL 00000000 000000 000000 00 0 0 0
[ 1] .text PROGBITS 00000000 001000 00000c 00 AX 0 0 4
[ 2] .text.main PROGBITS 0000000c 00100c 00004c 00 AX 0 0 4
[ 3] .comment PROGBITS 00000000 001058 000012 01 MS 0 0 1
[ 4] .riscv.attributes RISCV_ATTRIBUTE 00000000 00106a 000021 00 0 0 1
[ 5] .symtab SYMTAB 00000000 00108c 000090 10 6 6 4
[ 6] .strtab STRTAB 00000000 00111c 00001d 00 0 0 1
[ 7] .shstrtab STRTAB 00000000 001139 000047 00 0 0 1
[ 2] .text._canputchar PROGBITS 0000000c 00100c 000048 00 AX 0 0 4
[ 3] .text._haschar PROGBITS 00000054 001054 00004c 00 AX 0 0 4
[ 4] .text._putchar PROGBITS 000000a0 0010a0 00005c 00 AX 0 0 4
[ 5] .text._getchar PROGBITS 000000fc 0010fc 00004c 00 AX 0 0 4
[ 6] .text._puts PROGBITS 00000148 001148 000068 00 AX 0 0 4
[ 7] .text._gets PROGBITS 000001b0 0011b0 0000d8 00 AX 0 0 4
[ 8] .text._i2s PROGBITS 00000288 001288 000184 00 AX 0 0 4
[ 9] .text._h2s PROGBITS 0000040c 00140c 0001a8 00 AX 0 0 4
[10] .text._s2d PROGBITS 000005b4 0015b4 0000fc 00 AX 0 0 4
[11] .text._s2h PROGBITS 000006b0 0016b0 000138 00 AX 0 0 4
[12] .text.dispmem PROGBITS 000007e8 0017e8 000240 00 AX 0 0 4
[13] .text.printhelp PROGBITS 00000a28 001a28 00001c 00 AX 0 0 4
[14] .text.main PROGBITS 00000a44 001a44 0003fc 00 AX 0 0 4
[15] .rodata PROGBITS 00000e40 001e40 000048 00 A 0 0 4
[16] .sdata.displ[...] PROGBITS 00000e88 001e88 000004 00 WA 0 0 4
[17] .comment PROGBITS 00000000 001e8c 000012 01 MS 0 0 1
[18] .riscv.attributes RISCV_ATTRIBUTE 00000000 001e9e 000021 00 0 0 1
[19] .symtab SYMTAB 00000000 001ec0 000240 10 20 33 4
[20] .strtab STRTAB 00000000 002100 000082 00 0 0 1
[21] .shstrtab STRTAB 00000000 002182 000103 00 0 0 1
Key to Flags:
W (write), A (alloc), X (execute), M (merge), S (strings), I (info),
L (link order), O (extra OS processing required), G (group), T (TLS),
......@@ -39,11 +53,11 @@ There are no section groups in this file.
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD 0x001000 0x00000000 0x00000000 0x00058 0x00058 R E 0x1000
LOAD 0x001000 0x00000000 0x00000000 0x00e8c 0x00e8c RWE 0x1000
Section to Segment mapping:
Segment Sections...
00 .text .text.main
00 .text .text._canputchar .text._haschar .text._putchar .text._getchar .text._puts .text._gets .text._i2s .text._h2s .text._s2d .text._s2h .text.dispmem .text.printhelp .text.main .rodata .sdata.displayaddr
There is no dynamic section in this file.
......@@ -51,17 +65,44 @@ There are no relocations in this file.
The decoding of unwind sections for machine type RISC-V is not currently supported.
Symbol table '.symtab' contains 9 entries:
Symbol table '.symtab' contains 36 entries:
Num: Value Size Type Bind Vis Ndx Name
0: 00000000 0 NOTYPE LOCAL DEFAULT UND
1: 00000000 0 SECTION LOCAL DEFAULT 1 .text
2: 0000000c 0 SECTION LOCAL DEFAULT 2 .text.main
3: 00000000 0 SECTION LOCAL DEFAULT 3 .comment
4: 00000000 0 SECTION LOCAL DEFAULT 4 .riscv.attributes
5: 00000000 0 FILE LOCAL DEFAULT ABS console.c
6: 00000000 12 FUNC GLOBAL DEFAULT 1 __start
7: 0000000c 76 FUNC GLOBAL DEFAULT 2 main
8: 00000058 0 NOTYPE GLOBAL DEFAULT 2 _end
2: 0000000c 0 SECTION LOCAL DEFAULT 2 .text._canputchar
3: 00000054 0 SECTION LOCAL DEFAULT 3 .text._haschar
4: 000000a0 0 SECTION LOCAL DEFAULT 4 .text._putchar
5: 000000fc 0 SECTION LOCAL DEFAULT 5 .text._getchar
6: 00000148 0 SECTION LOCAL DEFAULT 6 .text._puts
7: 000001b0 0 SECTION LOCAL DEFAULT 7 .text._gets
8: 00000288 0 SECTION LOCAL DEFAULT 8 .text._i2s
9: 0000040c 0 SECTION LOCAL DEFAULT 9 .text._h2s
10: 000005b4 0 SECTION LOCAL DEFAULT 10 .text._s2d
11: 000006b0 0 SECTION LOCAL DEFAULT 11 .text._s2h
12: 000007e8 0 SECTION LOCAL DEFAULT 12 .text.dispmem
13: 00000a28 0 SECTION LOCAL DEFAULT 13 .text.printhelp
14: 00000a44 0 SECTION LOCAL DEFAULT 14 .text.main
15: 00000e40 0 SECTION LOCAL DEFAULT 15 .rodata
16: 00000e88 0 SECTION LOCAL DEFAULT 16 .sdata.displayaddr
17: 00000000 0 SECTION LOCAL DEFAULT 17 .comment
18: 00000000 0 SECTION LOCAL DEFAULT 18 .riscv.attributes
19: 00000000 0 FILE LOCAL DEFAULT ABS console.c
20: 0000000c 72 FUNC LOCAL DEFAULT 2 _canputchar
21: 00000054 76 FUNC LOCAL DEFAULT 3 _haschar
22: 000000a0 92 FUNC LOCAL DEFAULT 4 _putchar
23: 000000fc 76 FUNC LOCAL DEFAULT 5 _getchar
24: 00000148 104 FUNC LOCAL DEFAULT 6 _puts
25: 000001b0 216 FUNC LOCAL DEFAULT 7 _gets
26: 00000288 388 FUNC LOCAL DEFAULT 8 _i2s
27: 0000040c 424 FUNC LOCAL DEFAULT 9 _h2s
28: 000005b4 252 FUNC LOCAL DEFAULT 10 _s2d
29: 000006b0 312 FUNC LOCAL DEFAULT 11 _s2h
30: 00000e88 4 OBJECT LOCAL DEFAULT 16 displayaddr
31: 000007e8 576 FUNC LOCAL DEFAULT 12 dispmem
32: 00000a28 28 FUNC LOCAL DEFAULT 13 printhelp
33: 00000000 12 FUNC GLOBAL DEFAULT 1 __start
34: 00000a44 1020 FUNC GLOBAL DEFAULT 14 main
35: 00000e8c 0 NOTYPE GLOBAL DEFAULT 16 _end
No version information found in this file.
Attribute Section: riscv
......
examples/hdl4se_riscv/verilog/riscv_axi/riscv_core_with_axi_master.v
浏览文件 @ cbd5fc48
......@@ -103,7 +103,7 @@ module riscv_core_with_axi_master (
regfile regs(regno, regena, wClk, regwrdata, regwren, regrddata);
regfile regs2(regno2, regena2, wClk, regwrdata2, regwren2, regrddata2);
`define ALTERA
`define ALTERA_
`ifdef ALTERA
ram4kB ram(.clock(wClk), .address(ramaddr), .byteena(~bWriteMask), .data(bWriteData), .wren(((bWriteAddr & 32'hff000000) == 0)?wWrite:1'b0), .q(bReadDataRam));
......
examples/hdl4se_riscv/z7/ip_repo/myipmaster_1.0/bd/bd.tcl 0 → 100644
浏览文件 @ cbd5fc48
proc init { cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
set full_sbusif_list [list ]
foreach busif $all_busif {
if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
set busif_param_list [list]
set busif_name [get_property NAME $busif]
if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
continue
}
foreach tparam $axi_standard_param_list {
lappend busif_param_list "C_${busif_name}_${tparam}"
}
bd::mark_propagate_only $cell_handle $busif_param_list
}
}
}
proc pre_propagate {cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
foreach busif $all_busif {
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
continue
}
if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
continue
}
set busif_name [get_property NAME $busif]
foreach tparam $axi_standard_param_list {
set busif_param_name "C_${busif_name}_${tparam}"
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
if { $val_on_cell != "" } {
set_property CONFIG.${tparam} $val_on_cell $busif
}
}
}
}
}
proc propagate {cellpath otherInfo } {
set cell_handle [get_bd_cells $cellpath]
set all_busif [get_bd_intf_pins $cellpath/*]
set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
foreach busif $all_busif {
if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
continue
}
if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
continue
}
set busif_name [get_property NAME $busif]
foreach tparam $axi_standard_param_list {
set busif_param_name "C_${busif_name}_${tparam}"
set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
#override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
if { $val_on_cell_intf_pin != "" } {
set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
}
}
}
}
}
examples/hdl4se_riscv/z7/ip_repo/myipmaster_1.0/example_designs/bfm_design/design.tcl 0 → 100644
浏览文件 @ cbd5fc48
proc create_ipi_design { offsetfile design_name } {
create_bd_design $design_name
open_bd_design $design_name
# Create Clock and Reset Ports
set ACLK [ create_bd_port -dir I -type clk ACLK ]
set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK
set ARESETN [ create_bd_port -dir I -type rst ARESETN ]
set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $ARESETN
set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK
# Create instance: myipmaster_0, and set properties
set myipmaster_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:myipmaster:1.0 myipmaster_0]
# Create External ports
set M00_AXI_INIT_AXI_TXN [ create_bd_port -dir I M00_AXI_INIT_AXI_TXN ]
set M00_AXI_ERROR [ create_bd_port -dir O M00_AXI_ERROR ]
set M00_AXI_TXN_DONE [ create_bd_port -dir O M00_AXI_TXN_DONE ]
# Create instance: slave_0, and set properties
set slave_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vip slave_0]
set_property -dict [ list CONFIG.PROTOCOL {AXI4LITE} CONFIG.INTERFACE_MODE {SLAVE} ] $slave_0
connect_bd_intf_net [get_bd_intf_pins slave_0/S_AXI ] [get_bd_intf_pins myipmaster_0/M00_AXI]
# Create port connections
connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins slave_0/ACLK] [get_bd_pins myipmaster_0/M00_AXI_ACLK]
connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins slave_0/ARESETN] [get_bd_pins myipmaster_0/M00_AXI_ARESETN]
connect_bd_net -net init_axi_txn_00 [get_bd_ports M00_AXI_INIT_AXI_TXN] [get_bd_pins myipmaster_0/M00_AXI_INIT_AXI_TXN]
connect_bd_net -net error_00 [get_bd_ports M00_AXI_ERROR] [get_bd_pins myipmaster_0/M00_AXI_ERROR]
connect_bd_net -net txn_done_00 [get_bd_ports M00_AXI_TXN_DONE] [get_bd_pins myipmaster_0/M00_AXI_TXN_DONE]
set_property target_simulator XSim [current_project]
set_property -name {xsim.simulate.runtime} -value {100ms} -objects [get_filesets sim_1]
# Auto assign address
assign_bd_address
# Copy all address to interface_address.vh file
set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]]
upvar 1 $offsetfile offset_file
set offset_file "${bd_path}/myipmaster_v1_0_tb_include.svh"
set fp [open $offset_file "w"]
puts $fp "`ifndef myipmaster_v1_0_tb_include_vh_"
puts $fp "`define myipmaster_v1_0_tb_include_vh_\n"
puts $fp "//Configuration current bd names"
puts $fp "`define BD_NAME ${design_name}"
puts $fp "`define BD_INST_NAME ${design_name}_i"
puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n"
puts $fp "//Configuration address parameters"
puts $fp "`endif"
close $fp
}
set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores xilinx.com:user:myipmaster:1.0]]]]
set test_bench_file ${ip_path}/example_designs/bfm_design/myipmaster_v1_0_tb.sv
set interface_address_vh_file ""
# Set IP Repository and Update IP Catalogue
set repo_paths [get_property ip_repo_paths [current_fileset]]
if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
update_ip_catalog
}
set design_name ""
set all_bd {}
set all_bd_files [get_files *.bd -quiet]
foreach file $all_bd_files {
set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
lappend all_bd $bd_name
}
for { set i 1 } { 1 } { incr i } {
set design_name "myipmaster_v1_0_bfm_${i}"
if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
break
}
}
create_ipi_design interface_address_vh_file ${design_name}
validate_bd_design
set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
import_files -force -norecurse $wrapper_file
set_property SOURCE_SET sources_1 [get_filesets sim_1]
import_files -fileset sim_1 -norecurse -force $test_bench_file
remove_files -quiet -fileset sim_1 myipmaster_v1_0_tb_include.vh
import_files -fileset sim_1 -norecurse -force $interface_address_vh_file
set_property top myipmaster_v1_0_tb [get_filesets sim_1]
set_property top_lib {} [get_filesets sim_1]
set_property top_file {} [get_filesets sim_1]
launch_simulation -simset sim_1 -mode behavioral
examples/hdl4se_riscv/z7/ip_repo/myipmaster_1.0/example_designs/bfm_design/myipmaster_v1_0_tb.sv 0 → 100644
浏览文件 @ cbd5fc48
`timescale 1ns / 1ps
`include "myipmaster_v1_0_tb_include.svh"
import axi_vip_pkg::*;
import myipmaster_v1_0_bfm_1_slave_0_0_pkg::*;
module myipmaster_v1_0_tb();
xil_axi_uint error_cnt = 0;
xil_axi_uint comparison_cnt = 0;
axi_transaction wr_transaction;
axi_transaction rd_transaction;
axi_monitor_transaction mst_monitor_transaction;
axi_monitor_transaction master_moniter_transaction_queue[$];
xil_axi_uint master_moniter_transaction_queue_size =0;
axi_monitor_transaction mst_scb_transaction;
axi_monitor_transaction passthrough_monitor_transaction;
axi_monitor_transaction passthrough_master_moniter_transaction_queue[$];
xil_axi_uint passthrough_master_moniter_transaction_queue_size =0;
axi_monitor_transaction passthrough_mst_scb_transaction;
axi_monitor_transaction passthrough_slave_moniter_transaction_queue[$];
xil_axi_uint passthrough_slave_moniter_transaction_queue_size =0;
axi_monitor_transaction passthrough_slv_scb_transaction;
axi_monitor_transaction slv_monitor_transaction;
axi_monitor_transaction slave_moniter_transaction_queue[$];
xil_axi_uint slave_moniter_transaction_queue_size =0;
axi_monitor_transaction slv_scb_transaction;
xil_axi_uint mst_agent_verbosity = 0;
xil_axi_uint slv_agent_verbosity = 0;
xil_axi_uint passthrough_agent_verbosity = 0;
bit clock;
bit reset;
xil_axi_ulong mem_rd_addr;
xil_axi_ulong mem_wr_addr;
bit[32-1:0] write_data;
bit write_strb[];
bit[32-1:0] read_data;
myipmaster_v1_0_bfm_1_slave_0_0_slv_mem_t slv_agent_0;
bit error_0;
bit done_0;
bit init_0;
`BD_WRAPPER DUT(
.ARESETN(reset),
.M00_AXI_INIT_AXI_TXN(init_0),
.M00_AXI_TXN_DONE(done_0),
.M00_AXI_ERROR(error_0),
.ACLK(clock)
);
initial begin
slv_agent_0 = new("slave vip agent",DUT.`BD_INST_NAME.slave_0.inst.IF);
slv_agent_0.vif_proxy.set_dummy_drive_type(XIL_AXI_VIF_DRIVE_NONE);
slv_agent_0.set_agent_tag("Slave VIP");
slv_agent_0.set_verbosity(slv_agent_verbosity);
slv_agent_0.start_slave();
$timeformat (-12, 1, " ps", 1);
end
initial begin
reset <= 1'b0;
#200ns;
reset <= 1'b1;
repeat (5) @(negedge clock);
end
always #5 clock <= ~clock;
initial begin
init_0 = 0;
#200ns;
init_0 =1'b1;
#20ns;
init_0 = 1'b0;
$display("EXAMPLE TEST M00_AXI:");
wait( done_0 == 1'b1);
$display("M00_AXI: PTGEN_TEST_FINISHED!");
if ( error_0 ) begin
$display("PTGEN_TEST: FAILED!");
end else begin
$display("PTGEN_TEST: PASSED!");
end
#1ns;
$finish;
end
initial begin
#1;
forever begin
slv_agent_0.monitor.item_collected_port.get(slv_monitor_transaction);
slave_moniter_transaction_queue.push_back(slv_monitor_transaction);
slave_moniter_transaction_queue_size++;
end
end
endmodule
examples/hdl4se_riscv/z7/ip_repo/myipmaster_1.0/example_designs/debug_hw_design/design.tcl 0 → 100644
浏览文件 @ cbd5fc48
proc create_ipi_design { offsetfile design_name } {
create_bd_design $design_name
open_bd_design $design_name
# Create and configure Clock/Reset
create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0
create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0
#Constraints will be provided manually while pin planning.
create_bd_port -dir I -type rst reset_rtl
set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl]
connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl]
connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset]
set external_reset_port reset_rtl
create_bd_port -dir I -type clk clock_rtl
connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl]
set external_clock_port clock_rtl
#Avoid IPI DRC, make clock port synchronous to reset
if { $external_clock_port ne "" && $external_reset_port ne "" } {
set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port]
}
# Connect other sys_reset pins
connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked]
# Create instance: myipmaster_0, and set properties
set myipmaster_0 [ create_bd_cell -type ip -vlnv xilinx.com:user:myipmaster:1.0 myipmaster_0 ]
# Create instance: jtag_axi_0, and set properties
set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ]
set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0]
connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
# Create instance: axi_peri_interconnect, and set properties
set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ]
connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn]
set_property -dict [ list CONFIG.NUM_SI {1} ] $axi_peri_interconnect
connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI]
set_property -dict [ list CONFIG.NUM_MI {3} ] $axi_peri_interconnect
connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
connect_bd_net [get_bd_pins axi_peri_interconnect/M01_ACLK] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_peri_interconnect/M01_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
connect_bd_net [get_bd_pins axi_peri_interconnect/M02_ACLK] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_peri_interconnect/M02_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
# Create instance: axi_mem_interconnect, and set properties
set axi_mem_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_mem_interconnect ]
connect_bd_net [get_bd_pins axi_mem_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_mem_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn]
set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_mem_interconnect
connect_bd_net [get_bd_pins axi_mem_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_mem_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
set_property -dict [ list CONFIG.NUM_SI {2} ] $axi_mem_interconnect
connect_bd_net [get_bd_pins axi_mem_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_mem_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
connect_bd_net [get_bd_pins axi_mem_interconnect/S01_ACLK] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_mem_interconnect/S01_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn]
connect_bd_intf_net [get_bd_intf_pins axi_mem_interconnect/S01_AXI] [get_bd_intf_pins axi_peri_interconnect/M00_AXI]
# Create instance: axi_bram_ctrl_0, and set properties
set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl axi_bram_ctrl_0 ]
connect_bd_intf_net [get_bd_intf_pins axi_mem_interconnect/M00_AXI] [get_bd_intf_pins axi_bram_ctrl_0/S_AXI]
connect_bd_net [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
# Create instance: axi_bram_0, and set properties
set axi_bram_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen axi_bram_0 ]
set_property -dict [ list CONFIG.Memory_Type {True_Dual_Port_RAM} ] $axi_bram_0
connect_bd_intf_net [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins axi_bram_0/BRAM_PORTA]
connect_bd_intf_net [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTB] [get_bd_intf_pins axi_bram_0/BRAM_PORTB]
# Create instance: axi_gpio_out, and set properties
set axi_gpio_out [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio axi_gpio_out ]
set_property -dict [ list CONFIG.C_ALL_OUTPUTS {1} CONFIG.C_GPIO_WIDTH {1} ] $axi_gpio_out
connect_bd_net [get_bd_pins axi_gpio_out/s_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_gpio_out/s_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
connect_bd_intf_net [get_bd_intf_pins axi_gpio_out/S_AXI] [get_bd_intf_pins axi_peri_interconnect/M01_AXI]
# Create instance: axi_gpio_in, and set properties
set axi_gpio_in [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio axi_gpio_in ]
set_property -dict [ list CONFIG.C_ALL_INPUTS {1} CONFIG.C_GPIO_WIDTH {2} ] $axi_gpio_in
connect_bd_net [get_bd_pins axi_gpio_in/s_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins axi_gpio_in/s_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
connect_bd_intf_net [get_bd_intf_pins axi_gpio_in/S_AXI] [get_bd_intf_pins axi_peri_interconnect/M02_AXI]
# Create instance: xlconcat_0, and set properties
set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat xlconcat_0 ]
set_property -dict [ list CONFIG.NUM_PORTS {2} ] $xlconcat_0
connect_bd_net [get_bd_pins xlconcat_0/dout] [get_bd_pins axi_gpio_in/gpio_io_i]
# Connect all clock, reset & status pins of myipmaster_0 master interfaces..
connect_bd_intf_net [get_bd_intf_pins axi_mem_interconnect/S00_AXI] [get_bd_intf_pins myipmaster_0/M00_AXI]
connect_bd_net [get_bd_pins myipmaster_0/m00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1]
connect_bd_net [get_bd_pins myipmaster_0/m00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn]
connect_bd_net [get_bd_pins myipmaster_0/m00_axi_txn_done] [get_bd_pins xlconcat_0/In0]
connect_bd_net [get_bd_pins myipmaster_0/m00_axi_error] [get_bd_pins xlconcat_0/In1]
connect_bd_net [get_bd_pins myipmaster_0/m00_axi_init_axi_txn] [ get_bd_pins axi_gpio_out/gpio_io_o ]
# Auto assign address
assign_bd_address
# Configure address param & range of myipmaster_0 master interfaces..
set_property range 16K [get_bd_addr_segs {jtag_axi_0/Data/SEG_axi_bram_ctrl_0_Mem0}]
set_property range 16K [get_bd_addr_segs {myipmaster_0/M00_AXI/SEG_axi_bram_ctrl_0_Mem0}]
set_property -dict [list CONFIG.C_M00_AXI_TARGET_SLAVE_BASE_ADDR {0xC0000000} ] [get_bd_cells myipmaster_0]
# Copy all address to myipmaster_v1_0_include.tcl file
set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
upvar 1 $offsetfile offset_file
set offset_file "${bd_path}/myipmaster_v1_0_include.tcl"
set fp [open $offset_file "w"]
puts $fp "# Configuration address parameters"
set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_axi_gpio_in_Reg ]]
puts $fp "set axi_gpio_in_addr ${offset}"
set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_axi_gpio_out_Reg ]]
puts $fp "set axi_gpio_out_addr ${offset}"
close $fp
}
# Set IP Repository and Update IP Catalogue
set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores xilinx.com:user:myipmaster:1.0]]]]
set hw_test_file ${ip_path}/example_designs/debug_hw_design/myipmaster_v1_0_hw_test.tcl
set repo_paths [get_property ip_repo_paths [current_fileset]]
if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } {
set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset]
update_ip_catalog
}
set design_name ""
set all_bd {}
set all_bd_files [get_files *.bd -quiet]
foreach file $all_bd_files {
set file_name [string range $file [expr {[string last "/" $file] + 1}] end]
set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]]
lappend all_bd $bd_name
}
for { set i 1 } { 1 } { incr i } {
set design_name "myipmaster_v1_0_hw_${i}"
if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } {
break
}
}
set intf_address_include_file ""
create_ipi_design intf_address_include_file ${design_name}
save_bd_design
validate_bd_design
set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force]
import_files -force -norecurse $wrapper_file
puts "-------------------------------------------------------------------------------------------------"
puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, "
puts " please perform following steps to test design in targeted board."
puts "1. Generate bitstream"
puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target"
puts "3. Download generated bitstream"
puts "4. Run generated hardware test using below command, this invokes basic read/write operation"
puts " to every interface present in the peripheral : xilinx.com:user:myip:1.0"
puts " : source -notrace ${hw_test_file}"
puts "-------------------------------------------------------------------------------------------------"
examples/hdl4se_riscv/z7/ip_repo/myipmaster_1.0/example_designs/debug_hw_design/myipmaster_v1_0_hw_test.tcl 0 → 100644
浏览文件 @ cbd5fc48
# Runtime Tcl commands to interact with - myipmaster_v1_0
# Sourcing design address info tcl
set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd
source ${bd_path}/myipmaster_v1_0_include.tcl
# jtag axi master interface hardware name, change as per your design.
set jtag_axi_master hw_axi_1
set ec 0
# hw test script
# Delete all previous axis transactions
if { [llength [get_hw_axi_txns -quiet]] } {
delete_hw_axi_txn [get_hw_axi_txns -quiet]
}
# Master Tests..
# CIP Master performs write and read transaction followed by data comparison.
# To initiate the master "init_axi_txn" port needs to be asserted high. The same assertion is done by axi_gpio_out driven by jtag_axi_lite master.
# Writing 32'b1 to axi_gpio_out reg will initiate the first master. Subsequent masters will take following gpio bits.
# Master 0 init_axi_txn is controlled by bit_0 of axi_gpio_out while bit_1 initiates Master 1.
# To monitor the result of the data comparison by Master 0, error and done flags are being monitored by axi_gpio_in.
# Reading bit 0 of gpio_1_reg gives the done status of the master transaction while bit 1 gives the error
# status of the transaction initiated by the master. bit_0 being '1' means the transaction is complete
# while bit_1 being 1 means the transaction is completed with error. The status of subsequent masters
# will take up higher order bits in the same order. Master 1 has bit_2 as done bit, bit_3 as error bit.
# Utility procs
proc get_done_and_error_bit { rdata totmaster position } {
# position can be 0 1 2 3 ...
# Always Done is at sequence of bit 0 & error is at bit 1 position.
set hexdata [string range $rdata 0 7 ]
# In case of 64 bit data width
#set hexdata [string range $rdata 8 15 ]
binary scan [binary format H* $hexdata] B* bindata
set bindata [string range $bindata [expr 32 - $totmaster * 2] 31 ]
set DE [string range $bindata [ expr ($totmaster - ($position + 1) ) * 2 ] [expr ($totmaster - ($position + 1) ) * 2 + 1] ]
return $DE
}
proc bin2hex {bin} {
set result ""
set prepend [string repeat 0 [expr (4-[string length $bin]%4)%4]]
foreach g [regexp -all -inline {[01]{4}} $prepend$bin] {
foreach {b3 b2 b1 b0} [split $g ""] {
append result [format %X [expr {$b3*8+$b2*4+$b1*2+$b0}]]
}
}
return $result
}
proc get_init_data { position } {
# position can be 0, 1, 2, 3, 4...15
set initbit 00000000000000000000000000000000
set position [ expr 31 - $position ]
set newinitbit [string replace $initbit $position $position 1]
set hexdata [bin2hex $newinitbit]
return $hexdata
}
# Test: M00_AXI
set wdata_m00_axi [get_init_data 0]
create_hw_axi_txn w_m00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $axi_gpio_out_addr -data ${wdata_m00_axi}
create_hw_axi_txn r_m00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $axi_gpio_in_addr
# Initiate transactions
run_hw_axi r_m00_axi_addr
run_hw_axi w_m00_axi_addr
run_hw_axi r_m00_axi_addr
set rdata_tmp [get_property DATA [get_hw_axi_txn r_m00_axi_addr]]
set DE [ get_done_and_error_bit $rdata_tmp 1 0 ]
# Compare read data
if { $DE == 01 } {
puts "Data comparison test pass for - M00_AXI"
} else {
puts "Data comparison test fail for - M00_AXI, rdata-$rdata_tmp expected-01 actual-$DE"
inc ec
}
# Check error flag
if { $ec == 0 } {
puts "PTGEN_TEST: PASSED!"
} else {
puts "PTGEN_TEST: FAILED!"
}
examples/hdl4se_riscv/z7/ip_repo/myipmaster_1.0/hdl/myipmaster_v1_0.v 0 → 100644
浏览文件 @ cbd5fc48
`timescale 1 ns / 1 ps
module myipmaster_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Master Bus Interface M00_AXI
parameter C_M00_AXI_START_DATA_VALUE = 32'hAA000000,
parameter C_M00_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
parameter integer C_M00_AXI_ADDR_WIDTH = 32,
parameter integer C_M00_AXI_DATA_WIDTH = 32,
parameter integer C_M00_AXI_TRANSACTIONS_NUM = 4
)
(
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Master Bus Interface M00_AXI
input wire m00_axi_init_axi_txn,
output wire m00_axi_error,
output wire m00_axi_txn_done,
input wire m00_axi_aclk,
input wire m00_axi_aresetn,
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_awaddr,
output wire [2 : 0] m00_axi_awprot,
output wire m00_axi_awvalid,
input wire m00_axi_awready,
output wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_wdata,
output wire [C_M00_AXI_DATA_WIDTH/8-1 : 0] m00_axi_wstrb,
output wire m00_axi_wvalid,
input wire m00_axi_wready,
input wire [1 : 0] m00_axi_bresp,
input wire m00_axi_bvalid,
output wire m00_axi_bready,
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_araddr,
output wire [2 : 0] m00_axi_arprot,
output wire m00_axi_arvalid,
input wire m00_axi_arready,
input wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_rdata,
input wire [1 : 0] m00_axi_rresp,
input wire m00_axi_rvalid,
output wire m00_axi_rready
);
// Instantiation of Axi Bus Interface M00_AXI
myipmaster_v1_0_M00_AXI # (
.C_M_START_DATA_VALUE(C_M00_AXI_START_DATA_VALUE),
.C_M_TARGET_SLAVE_BASE_ADDR(C_M00_AXI_TARGET_SLAVE_BASE_ADDR),
.C_M_AXI_ADDR_WIDTH(C_M00_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M00_AXI_DATA_WIDTH),
.C_M_TRANSACTIONS_NUM(C_M00_AXI_TRANSACTIONS_NUM)
) myipmaster_v1_0_M00_AXI_inst (
.INIT_AXI_TXN(m00_axi_init_axi_txn),
.ERROR(m00_axi_error),
.TXN_DONE(m00_axi_txn_done),
.M_AXI_ACLK(m00_axi_aclk),
.M_AXI_ARESETN(m00_axi_aresetn),
.M_AXI_AWADDR(m00_axi_awaddr),
.M_AXI_AWPROT(m00_axi_awprot),
.M_AXI_AWVALID(m00_axi_awvalid),
.M_AXI_AWREADY(m00_axi_awready),
.M_AXI_WDATA(m00_axi_wdata),
.M_AXI_WSTRB(m00_axi_wstrb),
.M_AXI_WVALID(m00_axi_wvalid),
.M_AXI_WREADY(m00_axi_wready),
.M_AXI_BRESP(m00_axi_bresp),
.M_AXI_BVALID(m00_axi_bvalid),
.M_AXI_BREADY(m00_axi_bready),
.M_AXI_ARADDR(m00_axi_araddr),
.M_AXI_ARPROT(m00_axi_arprot),
.M_AXI_ARVALID(m00_axi_arvalid),
.M_AXI_ARREADY(m00_axi_arready),
.M_AXI_RDATA(m00_axi_rdata),
.M_AXI_RRESP(m00_axi_rresp),
.M_AXI_RVALID(m00_axi_rvalid),
.M_AXI_RREADY(m00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
examples/hdl4se_riscv/z7/riscv_axi_v5/riscv_axi_v5.gen/sources_1/bd/risc_axi_v5_top/hdl/risc_axi_v5_top_wrapper.v
浏览文件 @ cbd5fc48
//Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
//Date : Sun Sep 12 19:05:02 2021
//Date : Mon Sep 13 12:39:03 2021
//Host : DESKTOP-I91JIJO running 64-bit major release (build 9200)
//Command : generate_target risc_axi_v5_top_wrapper.bd
//Design : risc_axi_v5_top_wrapper
......
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