- 20 1月, 2021 2 次提交
- 19 1月, 2021 16 次提交
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由 jinyue110 提交于
s2_hit use s3_valid :)
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由 jinyue110 提交于
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由 Fa_wang 提交于
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由 Fa_wang 提交于
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由 Fa_wang 提交于
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由 LinJiawei 提交于
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由 Fa_wang 提交于
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由 Fa_wang 提交于
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由 William Wang 提交于
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由 jinyue110 提交于
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由 William Wang 提交于
When sbuffer checks if it is empty, it needs to check if sq is also empty so there is no pending store. Errors will emerge rarely if we do not check sq.
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由 jinyue110 提交于
Previously, we only give the first instrcution to backend when the packet causes a page fault. It will be stuck if not because waymask is 0 because no hit but hit includes ipf. So we seperates them.
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由 jinyue110 提交于
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由 jinyue110 提交于
exception and mmio judgement is done in tlb according to paddr. icache send mmio request to Instruction uncache module. It send TileLink GET to peripherals like flash and receive instructions per beat.
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由 William Wang 提交于
* Gen selectMask in 2nd cycle, in parallel with DeqMask
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由 jinyue110 提交于
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- 18 1月, 2021 2 次提交
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由 Yinan Xu 提交于
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由 William Wang 提交于
We used to select writeback inst and update writebacked bit at the same cycle. However, it is too long to finish in one cycle. Now we select writeback inst and gen wbSelectedMask in cycle 1, then we use RegNext(wbSelectedMask) and writeback bit to select inst in the next cycle.
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- 17 1月, 2021 11 次提交
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由 ZhangZifei 提交于
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由 Yinan Xu 提交于
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由 zoujr 提交于
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由 zhanglinjuan 提交于
XSCore: Enable icache prefetch
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由 jinyue110 提交于
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由 LinJiawei 提交于
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由 LinJiawei 提交于
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由 LinJiawei 提交于
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由 William Wang 提交于
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由 William Wang 提交于
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由 Lingrui98 提交于
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- 16 1月, 2021 9 次提交
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由 Lingrui98 提交于
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由 Lingrui98 提交于
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由 LinJiawei 提交于
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由 Lingrui98 提交于
this commit has two motivations: 1. fix the bug of not sending valid instruction when ipf && !icahce_hit 2. save the delay of adding a mux of huge width before sending instr to predecode
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由 zoujr 提交于
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由 Yinan Xu 提交于
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由 William Wang 提交于
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由 Fa_wang 提交于
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由 LinJiawei 提交于
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