ICache-uncache add MMIO perf register

src/main/scala/xiangshan/backend/fu/CSR.scala

@@ -742,8 +742,8 @@ class CSR extends FunctionUnit with HasCSRConst
     "PtwCycleCnt" -> (0x1026, "perfCntPtwCycleCnt"  ),
     "PtwL2TlbHit" -> (0x1027, "perfCntPtwL2TlbHit"  ),
     "ICacheReq"   -> (0x1028, "perfCntIcacheReqCnt" ),
-    "ICacheMiss"  -> (0x1029, "perfCntIcacheMissCnt")
-    // "FetchFromICache" -> (0x102a, "CntFetchFromICache"),
+    "ICacheMiss"  -> (0x1029, "perfCntIcacheMissCnt"),
+    "ICacheMMIO" -> (0x102a, "perfCntIcacheMMIOCnt")
     // "FetchFromLoopBuffer" -> (0x102b, "CntFetchFromLoopBuffer"),
     // "ExitLoop1" -> (0x102c, "CntExitLoop1"),
     // "ExitLoop2" -> (0x102d, "CntExitLoop2"),

src/main/scala/xiangshan/cache/InstrUncache.scala

@@ -103,6 +103,10 @@ class InstrMMIOEntry(edge: TLEdgeOut) extends XSModule with HasICacheParameters
     when (io.mmio_grant.fire()) {
       respDataReg(beatCounter.value) := io.mmio_grant.bits.data
       assert(refill_done, "MMIO response should be one beat only!")
+      println(mmioBusWidth)
+      println(mmioBusBytes)
+      println(mmioBeats)
+      println(mmioBeats - 1)
       state := Mux(needFlush || io.flush, s_invalid,Mux(beatCounter.value === (mmioBeats - 1).U,s_send_resp,s_refill_req))
       beatCounter.inc()
     }

src/main/scala/xiangshan/cache/icache.scala

@@ -59,13 +59,11 @@ trait HasFrontEndExceptionNo {
 
 abstract class ICacheBundle extends XSBundle
   with HasICacheParameters
-  with HasInstrMMIOConst
 
 abstract class ICacheModule extends XSModule
   with HasICacheParameters
   with ICacheBase
   with HasFrontEndExceptionNo
-  with HasInstrMMIOConst
 
 abstract class ICacheArray extends XSModule
   with HasICacheParameters
@@ -373,10 +371,10 @@ class ICache extends ICacheModule
   val s3_hit = RegEnable(next=s2_hit,init=false.B,enable=s2_fire)
   val s3_mmio = RegEnable(next=s2_mmio,init=false.B,enable=s2_fire)
   val s3_wayMask = RegEnable(next=waymask,init=0.U,enable=s2_fire)
-  val s3_miss = s3_valid && !s3_hit && !s3_mmio
   val s3_idx = get_idx(s3_req_pc)
   val s3_exception_vec = RegEnable(next= icacheExceptionVec,init=0.U.asTypeOf(Vec(8,Bool())), enable=s2_fire)
   val s3_has_exception = s3_exception_vec.asUInt.orR
+  val s3_miss = s3_valid && !s3_hit && !s3_mmio && !s3_has_exception
   when(s3_flush)                  { s3_valid := false.B }
   .elsewhen(s2_fire && !s2_flush) { s3_valid := true.B }
   .elsewhen(io.resp.fire())       { s3_valid := false.B }
@@ -547,6 +545,7 @@ class ICache extends ICacheModule
   if (!env.FPGAPlatform ) {
     ExcitingUtils.addSource( s3_valid && !blocking, "perfCntIcacheReqCnt", Perf)
     ExcitingUtils.addSource( s3_miss && blocking && io.resp.fire(), "perfCntIcacheMissCnt", Perf)
+    ExcitingUtils.addSource( s3_mmio && blocking && io.resp.fire(), "perfCntIcacheMMIOCnt", Perf)
   }
 }
 

src/main/scala/xiangshan/frontend/IFU.scala

@@ -12,7 +12,7 @@ import freechips.rocketchip.tile.HasLazyRoCC
 trait HasInstrMMIOConst extends HasXSParameter{
   def mmioBusWidth = 64
   def mmioBusBytes = mmioBusWidth /8
-  def mmioBeats = FetchWidth * 4 / mmioBusWidth
+  def mmioBeats = FetchWidth * 4 * 8 / mmioBusWidth
   def mmioMask  = VecInit(List.fill(PredictWidth)(true.B)).asUInt
 }