clean up arbiter

src/main/scala/xiangshan/backend/exu/Exu.scala

@@ -120,13 +120,21 @@ abstract class Exu(val config: ExuConfig) extends XSModule {
 
   def writebackArb(in: Seq[DecoupledIO[FuOutput]], out: DecoupledIO[ExuOutput]): Arbiter[FuOutput] = {
     if (needArbiter) {
-      val arb = Module(new Arbiter(new FuOutput(in.head.bits.len), in.size))
-      arb.io.in <> in
-      arb.io.out.ready := out.ready
-      out.bits.data := arb.io.out.bits.data
-      out.bits.uop := arb.io.out.bits.uop
-      out.valid := arb.io.out.valid
-      arb
+      if(in.size == 1){
+        in.head.ready := out.ready
+        out.bits.data := in.head.bits.data
+        out.bits.uop := in.head.bits.uop
+        out.valid := in.head.valid
+        null
+      } else {
+        val arb = Module(new Arbiter(new FuOutput(in.head.bits.len), in.size))
+        arb.io.in <> in
+        arb.io.out.ready := out.ready
+        out.bits.data := arb.io.out.bits.data
+        out.bits.uop := arb.io.out.bits.uop
+        out.valid := arb.io.out.valid
+        arb
+      }
     } else {
       in.foreach(_.ready := out.ready)
       val sel = Mux1H(in.map(x => x.valid -> x))

src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala

@@ -14,8 +14,8 @@ class FmiscExeUnit extends Exu(fmiscExeUnitCfg) {
   val toFpUnits = Seq(f2f, fdivSqrt)
   val toIntUnits = Seq(f2i)
 
-  assert(fpArb.io.in.length == toFpUnits.size)
-  assert(intArb.io.in.length == toIntUnits.size)
+  assert(toFpUnits.size == 1 || fpArb.io.in.length == toFpUnits.size)
+  assert(toIntUnits.size == 1 || intArb.io.in.length == toIntUnits.size)
 
   val input = io.fromFp
   val isRVF = input.bits.uop.ctrl.isRVF

src/main/scala/xiangshan/backend/exu/Wb.scala

@@ -56,15 +56,20 @@ class Wb(cfgs: Seq[ExuConfig], numOut: Int, isFp: Boolean) extends XSModule {
     mulReq.size
   )
 
-  val arbiters = for(i <- mulReq.indices) yield {
-    val other = arbReq(i).getOrElse(Seq())
-    val arb = Module(new Arbiter(new ExuOutput, 1+other.size))
-    arb.io.in <> mulReq(i) +: other
+  for(i <- mulReq.indices) {
     val out = io.out(directConnect.size + i)
-    out.valid := arb.io.out.valid
-    out.bits := arb.io.out.bits
-    arb.io.out.ready := true.B
-    arb
+    val other = arbReq(i).getOrElse(Seq())
+    if(other.isEmpty){
+      out.valid := mulReq(i).valid
+      out.bits := mulReq(i).bits
+      mulReq(i).ready := true.B
+    } else {
+      val arb = Module(new Arbiter(new ExuOutput, 1+other.size))
+      arb.io.in <> mulReq(i) +: other
+      out.valid := arb.io.out.valid
+      out.bits := arb.io.out.bits
+      arb.io.out.ready := true.B
+    }
   }
 
   if(portUsed < numOut){
@@ -78,10 +83,11 @@ class Wb(cfgs: Seq[ExuConfig], numOut: Int, isFp: Boolean) extends XSModule {
   }
   for(i <- mulReq.indices){
     sb.append(s"[ ${cfgs(io.in.indexOf(mulReq(i))).name} ")
+    val useArb = arbReq(i).nonEmpty
     for(req <- arbReq(i).getOrElse(Nil)){
       sb.append(s"${cfgs(io.in.indexOf(req)).name} ")
     }
-    sb.append(s"] -> arb -> out #${directConnect.size + i}\n")
+    sb.append(s"] -> ${if(useArb) "arb ->" else ""} out #${directConnect.size + i}\n")
   }
   println(sb)