remove the old hard-wired pma and turn to pmp-like csr registers. the pma config is writen in pma register.
1. pma are m-priv csr, so only m-mode csrrw can change pma
2. even in m-mode, pma should be always checked, no matter lock or not
3. so carefully write pma, make sure not to "suicide"

* pma: add pmp-like pma, just module/bundle added, not to circuit

use reserved 2 bits as atomic and cached

* pma: add pmp-like pma into pmp module

pma have two more attribute than pmp
1. atmoic;
2. c/cache, if false, go to mmio.

pma uses 16+4 machine-level custom ready write csr.
pma will always be checked even in m-mode.

* pma: remove the old MemMap in tlb, mmio arrives next cycle

* pma: ptw raise af when mmio

* pma: fix bug of match's zip with last entry

* pma: fix bug of pass reset signal through method's parameter

strange bug, want to reset, pass reset signal to a method, does not
work.
import chisel3.Module.reset, the method can access reset it's self.

* pma: move some method to trait and fix bug of pma_init value

* pma: fix bug of pma init value assign way

* tlb: fix stupid bug that pf.ld not & fault_valid

* loadunit: fix bug that uop is flushed, pmp's dcache kill failed also

* ifu: mmio access needs f2_valid now

* loadunit: if mmio and have sent fastUop, flush pipe when commit

* storeunit: stu->lsq at stage1 and re-in lsq at stage2 to update mmio

* Add perf counters
* add reg from hpm counter source
* add print perfcounter enable

* mem: support ld-ld violation check
* mem: do not fast wakeup if ld vio check failed
* mem: disable ld-ld vio check after core reset

add mmu's asid support.
1. put asid inside sram (if the entry is sram), or it will take too many sources.
2. when sfence, just flush it all, don't care asid.
3. when hit check, check asid.
4. when asid changed, flush all the inflight ptw req for safety
5. simple asid unit test:
asid 1 write, asid 2 read and check, asid 2 write, asid 1 read and check. same va, different pa

* ASID: make satp's asid bits configurable to RW
* use AsidLength to control it

* ASID: implement asid refilling and hit checking
* TODO: sfence flush with asid

* ASID: implement sfence with asid
* TODO: extract asid from SRAMTemplate

* ASID: extract asid from SRAMTemplate
* all is down
* TODO: test

* fix write to asid

* Sfence: support rs2 of sfence and fix Fence Unit
* rs2 of Sfence should be Reg and pass it to Fence Unit
* judge the value of reg instead of the index in Fence Unit

* mmu: re-write asid

now, asid is stored inside sram, so sfence just flush it
it's a complex job to handle the problem that asid is changed but
no sfence.vma is executed. when asid is changed, all the inflight
mmu reqs are flushed but entries in storage is not influenced.
so the inflight reqs do not need to record asid, just use satp.asid

* tlb: fix bug of refill mask

* ci: add asid unit test
Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>

* L1D: provide independent meta array for load pipe

* misc: reorg files in cache dir

* chore: reorg l1d related files

* bump difftest: use clang to compile verialted files

* dcache: add BankedDataArray

* dcache: fix data read way_en

* dcache: fix banked data wmask

* dcache: replay conflict correctly

 When conflict is detected:
* Report replay
* Disable fast wakeup

* dcache: fix bank addr match logic

* dcache: add bank conflict perf counter

* dcache: fix miss perf counters

* chore: make lsq data print perttier

* dcache: enable banked ecc array

* dcache: set dcache size to 128KB

* dcache: read mainpipe data from banked data array

* dcache: add independent mainpipe data read port

* dcache: revert size change

* Size will be changed after main pipe refactor

* Merge remote-tracking branch 'origin/master' into l1-size

* dcache: reduce banked data load conflict

* MainPipe: ReleaseData for all replacement even if it's clean

* dcache: set dcache size to 128KB

BREAKING CHANGE: l2 needed to provide right vaddr index to probe l1,
and it has to help l1 to avoid addr alias problem

* chore: fix merge conflict

* Change L2 to non-inclusive / Add alias bits in L1D

* debug: hard coded dup data array for debuging

* dcache: fix ptag width

* dcache: fix amo main pipe req

* dcache: when probe, use vaddr for main pipe req

* dcache: include vaddr in atomic unit req

* dcache: fix get_tag() function

* dcache: fix writeback paddr

* huancun: bump version

* dcache: erase block offset bits in release addr

* dcache: do not require probe vaddr != 0

* dcache: opt banked data read timing

* bump huancun

* dcache: fix atom unit pipe req vaddr

* dcache: simplify main pipe writeback_vaddr

* bump huancun

* dcache: remove debug data array

* Turn on all usr bits in L1

* Bump huancun

* Bump huancun

* enable L2 prefetcher

* bump huancun

* set non-inclusive L2/L3 + 128KB L1 as default config

* Use data in TLBundleB to hint ProbeAck beeds data

* mmu.l2tlb: mem_resp now fills multi mq pte buffer

mq entries can just deq without accessing l2tlb cache

* dcache: handle dirty userbit

* bump huancun

* chore: l1 cache code clean up

* Remove l1plus cache
* Remove HasBankedDataArrayParameters

* Add bus pmu between L3 and Mem

* bump huncun

* IFU: add performance counters and mmio af

* icache replacement policy moniter

* ifu miss situation moniter

* icache miss rate

* raise access fault when found mmio req

* Add framework for seperated main pipe and reg meta array

* Rewrite miss queue for seperated pipes

* Add RefillPipe

* chore: rename NewSbuffer.scala

* cache: add CacheInstruction opcode and reg list

* CSR: add cache control registers

* Add Replace Pipe

* CacheInstruction: add CSRs for cache instruction

* mem: remove store replay unit

* Perf counter to be added
* Timing opt to be done

* mem: update sbuffer to support new dcache

* sbuffer: fix missqueue time out logic

* Merge remote-tracking branch 'origin/master' into dcache-rm-sru

* chore: fix merge conflict, remove nStoreReplayEntries

* Temporarily disable TLMonitor

* Bump huancun (L2/L3 MSHR bug fix)

* Rewrite main pipe

* ReplacePipe: read meta to decide whether data should be read

* RefillPipe: add a store resp port

* MissQueue: new req should be rejected according to set+way

* Add replacement policy interface

* sbuffer: give missq replay the highest priority

Now we give missqReplayHasTimeOut the highest priority, as eviction
has already happened
Besides, it will fix the problem that fix dcache eviction generate logic
gives the wrong sbuffer id

* Finish DCache framework

* Split meta & tag and use regs to build meta array

* sbuffer: use new dcache io

* dcache: update dcache resp in memblock and fake d$

* Add atomics processing flow

* Refactor Top

* Bump huancun

* DCacheWrapper: disable ld fast wakeup only when bank conflict

* sbuffer: update dcache_resp difftest io

* MainPipe: fix combinational loop

* Sbuffer: fix bug in assert

* RefillPipe: fix bug of getting tag from addr

* dcache: ~0.U should restrict bit-width

* LoadPipe: fix bug in assert

* ReplacePipe: addr to be replaced should be block-aligned

* MainPipe: fix bug in required coh sending to miss queue

* DCacheWrapper: tag write in refill pipe should always be ready

* MainPipe: use replacement way_en when the req is from miss queue

* MissQueue: refill data should be passed on to main pipe

* MainPipe: do not use replacement way when tag match

* CSR: clean up cache op regs

* chore: remove outdated comments

* ReplacePipe: fix stupid bug

* dcache: replace checkOneHot with assert

* alu: fix bug of rev8 & orc.b instruction

* MissQueue: fix bug in the condition of mshr accepting a req

* MissQueue: add perf counters

* chore: delete out-dated code

* chore: add license

* WritebackQueue: distinguish id from miss queue

* AsynchronousMetaArray: fix bug

* Sbuffer: fix difftest io

* DCacheWrapper: duplicate one more tag copy for main pipe

* Add perf cnt to verify whether replacing is too early

* dcache: Release needs to wait for refill pipe

* WritebackQueue: fix accept condition

* MissQueue: remove unnecessary assert

* difftest: let refill check ingore illegal mem access

* Parameters: enlarge WritebackQueue to break dead-lock

* DCacheWrapper: store hit wirte should not be interrupted by refill

* Config: set nReleaseEntries to twice of nMissEntries

* DCacheWrapper: main pipe read should block refill pipe by set
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
Co-authored-by: NLinJiawei <linjiav@outlook.com>
Co-authored-by: NTangDan <tangdan@ict.ac.cn>
Co-authored-by: NLinJiawei <linjiawei20s@ict.ac.cn>
Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>
Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn>
Co-authored-by: NJinYue <jinyue20s@ict.ac.cn>
Co-authored-by: Zhangfw <471348957@qq.com>

This commit optimizes the move elimination implementation.

Reference counting for every physical register is recorded. Originally
0-31 registers have counters of ones. Every time the physical register
is allocated or deallocated, the counter is increased or decreased by
one. When the counter becomes zero from a non-zero value, the register
is freed and released to freelist.

frontendBundle: add chiselName annotation for bundles, code clean ups and timing optimization (hopefully)

* [WIP] PMP: add pmp to tlb & csr(ptw part is not added)

* pmp: add pmp, unified

* pmp: add pmp, distributed but same cycle

* pmp: pmp resp next cycle

* [WIP] PMP: add l2tlb missqueue pmp support

* pmp: add pmp to ptw and regnext pmp for frontend

* pmp: fix bug of napot-match

* pmp: fix bug of method aligned

* pmp: when write cfg, update mask

* pmp: fix bug of store af getting in store unit

* tlb: fix bug, add af check(access fault from ptw)

* tlb: af may have higher priority than pf when ptw has af

* ptw: fix bug of sending paddr to pmp and recv af

* ci: add pmp unit test

* pmp: change PMPPlatformGrain to 6 (512bits)

* pmp: fix bug of read_addr

* ci: re-add pmp unit test

* l2tlb: lazymodule couldn't use @chiselName

* l2tlb: fix bug of l2tlb missqueue duplicate req's logic

filt the duplicate req:
old: when enq, change enq state to different state
new: enq + mem.req.fire, more robust

* pmp: pmp checker now supports samecycle & regenable

This commit optimizes RenameTable's timing.

Read addresses come from instruction buffer directly and has best
timing. So we let data read at decode stage and bypass write data
from this clock cycle to the read data at next cycle.

For write, we latch the write request and process it at the next cycle.

This commit moves load/store reservation stations into the first
ExuBlock (or calling it IntegerBlock). The unnecessary dispatch module
is also removed from CtrlBlock.

Now the module organization becomes:
* ExuBlock: Int RS, Load/Store RS, Int RF, Int FUs
* ExuBlock_1: Fp RS, Fp RF, Fp FUs
* MemBlock: Load/Store FUs

Besides, load queue has 80 entries and store queue has 64 entries now.

* Refactor cache params

* L2: support multi-bank

* fix l2 size

* remove 'IgnoreNode'

* bump difftest and huancun

* change ROB to 256 entries
* change physical register file to 192 entries
* re-organize reservation stations, function units and regfile

* rename Roq to Rob

* remove trailing whitespaces

* remove unused parameters

* L1D: provide independent meta array for load pipe

* misc: reorg files in cache dir

* chore: reorg l1d related files

* bump difftest: use clang to compile verialted files

* dcache: add BankedDataArray

* dcache: fix data read way_en

* dcache: fix banked data wmask

* dcache: replay conflict correctly

 When conflict is detected:
* Report replay
* Disable fast wakeup

* dcache: fix bank addr match logic

* dcache: add bank conflict perf counter

* dcache: fix miss perf counters

* chore: make lsq data print perttier

* dcache: enable banked ecc array

* dcache: set dcache size to 128KB

* dcache: read mainpipe data from banked data array

* dcache: add independent mainpipe data read port

* dcache: revert size change

* Size will be changed after main pipe refactor

* Merge remote-tracking branch 'origin/master' into l1-size

* dcache: reduce banked data load conflict

* MainPipe: ReleaseData for all replacement even if it's clean

* dcache: set dcache size to 128KB

BREAKING CHANGE: l2 needed to provide right vaddr index to probe l1,
and it has to help l1 to avoid addr alias problem

* chore: fix merge conflict

* Change L2 to non-inclusive / Add alias bits in L1D

* debug: hard coded dup data array for debuging

* dcache: fix ptag width

* dcache: fix amo main pipe req

* dcache: when probe, use vaddr for main pipe req

* dcache: include vaddr in atomic unit req

* dcache: fix get_tag() function

* dcache: fix writeback paddr

* huancun: bump version

* dcache: erase block offset bits in release addr

* dcache: do not require probe vaddr != 0

* dcache: opt banked data read timing

* bump huancun

* dcache: fix atom unit pipe req vaddr

* dcache: simplify main pipe writeback_vaddr

* bump huancun

* dcache: remove debug data array

* Turn on all usr bits in L1

* Bump huancun

* Bump huancun

* enable L2 prefetcher

* bump huancun

* set non-inclusive L2/L3 + 128KB L1 as default config

* Use data in TLBundleB to hint ProbeAck beeds data

* mmu.l2tlb: mem_resp now fills multi mq pte buffer

mq entries can just deq without accessing l2tlb cache

* dcache: handle dirty userbit

* bump huancun

* chore: l1 cache code clean up

* Remove l1plus cache
* Remove HasBankedDataArrayParameters

* Add bus pmu between L3 and Mem

* bump huncun

* dcache: fix l1 probe index generate logic

* Now right probe index will be used according to the len of alias bits

* dcache: clean up amo pipeline

* DCacheParameter rowBits will be removed in the future, now we set it to 128
to make dcache work

* dcache: fix amo word index

* bump huancun
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>
Co-authored-by: Nzhanglinjuan <zhanglinjuan20s@ict.ac.cn>
Co-authored-by: NTangDan <tangdan@ict.ac.cn>
Co-authored-by: NZhangZifei <zhangzifei20z@ict.ac.cn>
Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn>

nothing changed but add one parameter to control if ldtlb and sttlb are the same
now there two similar parameters:

outReplace: when this is true, two ldtlb are 'same', two sttlb are 'same'
refillBothTlb: when this is true, the four tlb are same(require outReplace to be true)

* mmu.tlb: add param refillBothTlb to refill both ld & st tlb

* mmu.tlb: set param refillBothTlb to false

* misc: add submodule huancun

* huancun: integrate huancun to SoC as L3

* remove l2prefetcher

* update huancun

* Bump HuanCun

* Use HuanCun instead old L2/L3

* bump huancun

* bump huancun

* Set L3NBanks to 4

* Update rocketchip

* Bump huancun

* Bump HuanCun

* Optimize debug configs

* Configs: fix L3 bug

* Add TLLogger

* TLLogger: fix release ack address

* Support write prefix into database

* Recoding more tilelink info

* Add a database output format converter

* missqueue: add difftest port for memory difftest during refill

* misc: bump difftest

* misc: bump difftest & huancun

* missqueue: do not check refill data when get Grant

* Add directory debug tool

* config: increase client dir size for non-inclusive cache

* Bump difftest and huancun

* Update l2/l3 cache configs

* Remove deprecated fpga/*

* Remove cache test

* Remove L2 preftecher

* bump huancun

* Params: turn on l2 prefetch by default

* misc: remove duplicate chisel-tester2

* misc: remove sifive inclusive cache

* bump difftest

* bump huancun

* config: use 4MB L3 cache

* bump huancun

* bump difftest

* bump difftest
Co-authored-by: Nwangkaifan <wangkaifan@ict.ac.cn>
Co-authored-by: NTangDan <tangdan@ict.ac.cn>

* mmu.tlb: l2tlb's l3 now 128 sets and 4 ways

* mmu.tlb: set itlb default size

* backend, rename: support elimination of mv inst whose lsrc=0
[known bug] instr page fault not properly raised after sfence.vma

* backend, roq: [bug fix] won't label me with exception as writebacked

* Revert "Revert "l0tlb: add a new level tlb to each mem pipeline (#936)" (#945)"

This reverts commit b052b972.

* fu: remove unused import

* mmu.tlb: 2 load/store pipeline has 1 dtlb

* mmu: remove btlb, the l1-tlb

* mmu: set split-tlb to 32 to check perf effect

* mmu: wrap tlb's param with TLBParameters

* mmu: add params 'useBTlb'

dtlb size is small: normal 8, super 2

* mmu.tlb: add Bundle TlbEntry, simplify tlb hit logic(coding)

* mmu.tlb: seperate tlb's storage, relative hit/sfence logic

tlb now supports full-associate, set-associate, directive-associate.
more: change tlb's parameter usage, change util.Random to support
case that mod is 1.

* mmu.tlb: support normalAsVictim, super(fa) -> normal(sa/da)

be carefull to use tlb's parameter, only a part of param combination
is supported

* mmu.tlb: fix bug of hit method and victim write

* mmu.tlb: add tlb storage's perf counter

* mmu.tlb: rewrite replace part, support set or non-set

* mmu.tlb: add param outReplace to receive out replace index

* mmu.tlb: change param superSize to superNWays

add param superNSets, which should always be 1

* mmu.tlb: change some perf counter's name and change some params

* mmu.tlb: fix bug of replace io bundle

* mmu.tlb: remove unused signal wayIdx in tlbstorageio

* mmu.tlb: separate tlb_ld/st into two 'same' tlb

* mmu.tlb: when nWays is 1, replace returns 0.U

before, replace will return 1.U, no influence for refill but bad
for perf counter

* mmu.tlb: give tlb_ld and tlb_st a name (in waveform)

* mmu: wrap l2tlb's param withL2TLBParameters

* mmu.l2tlb: add param blockBytes: 64, 8 ptes

* mmu.l2tlb: set l2tlb cache size to l2:256, l3:4096

* mmu.l2tlb: add config print

* mmu.l2tlb: fix bug of resp data indices choosen and opt coding style

This reverts commit 5aae5b8d.

        "trait" was used to improve code style
parameters: use EnableIntMoveElim to control code generation
[WIP] EnableIntMoveElim=false hasn't been tested

FreeList: same as above
Parameters: add 2 core param and 2 derived param
[TODO] use EnableIntMoveElim to control ME function

* Miniconfig: change dtlb size to 32 at minimal config

* mmu.dtlb: change tlb's replacement access code style

dtlb now can support plru (functionaly).
plru with multi-access is chained, so there will be long latency
  for dtlb to use plru.

* mmu.tlb: add tlb at new level named btlb

bridge tlb:
one l0-tlb in each mem pipeline
all the l0-tlb connect to bridge tlb
btlb connects to l2tlb, so btlb is also l1-tlb
itlb remains the same

* mmu.tlb: set tlb size: l0-8, l1-64

* mmu.btlb: add sfence logic

* mmu.tlb: fix bug of sfence logic of g bit

* mmu.btlb: add some perf counter

* mmu.btlb: fix bug of random replace

* mmu.filter: add port vector to record which ports the reqs come from

* mmu.btlb: add some perf counter && add refill mask

* mmu.filter: add check for flushed req

This commit separates store address and store data in backend, including both reservation stations and function units. This commit also changes how stIssuePtr is updated. stIssuePtr should only be updated when both store data and address issue. 

* Miniconfig: change dtlb size to 32 at minimal config

* mmu.dtlb: change tlb's replacement access code style

dtlb now can support plru (functionaly).
plru with multi-access is chained, so there will be long latency
  for dtlb to use plru.

* mmu.l2tlb: cut down l2tlb.l2 to 256 and set l3.way to 8

* mmu.l2tlb: cut down l2tlb.l3 to 2048 from 4096

* Revert "mmu.l2tlb: cut down l2tlb.l3 to 2048 from 4096"

This reverts commit efbb077ef4be1d4e585a49537ba9be3144423b52.

New option `EnableFastForward` is added to config list.
EnableFastForward will reduce L1D$ miss but make timing worse.

* `forwardMaskFast` is generated at load_s1, it is used to generate
fastUop for fast wakeup
* `forwardMask` is generated at load_s2, it will be used to check if
forward result is correct

Basic features of debug mode are implemented.

* Rewrite CSR for debug mode
* Peripheral work for implementing debug module
* Added single step support
* Use difftest with JTAG support

tage: fix phist support