- 14 1月, 2022 2 次提交
- 13 1月, 2022 2 次提交
- 07 1月, 2022 1 次提交
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由 Lingrui98 提交于
* split entries into by numBr and use bits in pc to hash between them * use shorter tags for each table * make perfEvents a general interface for branch predictor components in order to remove casting operation in composer
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- 04 1月, 2022 1 次提交
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由 Lingrui98 提交于
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- 01 1月, 2022 1 次提交
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由 Lingrui98 提交于
* move statisical corrector to stage 3 * add recover path in stage 3 for ras in case stage 2 falsely push or pop * let stage 2 has the highest physical priority in bpu * left ras broken for the next commit to fix
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- 30 12月, 2021 1 次提交
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由 Lingrui98 提交于
* reduce number of tables to 4, meanwhile quadrupling number of entries per table, improving area efficiency * use per bank wrbypass * invalidate read response when writing to SRAM * move validArray and useful bit into SRAMs, thus reducing area * use an optimized history config for such table sizes
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- 24 12月, 2021 2 次提交
- 23 12月, 2021 1 次提交
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由 Lingrui98 提交于
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- 17 12月, 2021 1 次提交
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由 Lingrui98 提交于
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- 14 12月, 2021 1 次提交
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由 Lingrui98 提交于
* use parallel mux to select provider and altprovider for TAGE and ITTAGE * reduce logics on SC prediction * calculate higher bits of targets at stage 1 for ftb * reduce logics for RAS and ITTAGE prediction assignment
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- 10 12月, 2021 2 次提交
- 08 12月, 2021 1 次提交
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由 Lingrui98 提交于
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- 07 12月, 2021 1 次提交
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由 Lingrui98 提交于
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- 02 12月, 2021 2 次提交
- 16 11月, 2021 1 次提交
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由 Lingrui98 提交于
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- 15 11月, 2021 1 次提交
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由 zoujr 提交于
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- 13 11月, 2021 2 次提交
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由 Lingrui98 提交于
* fix a bug of wrongly discarding some new bits to be xored * ghr should be longer in default config to avoid falsely overriding * move TageBanks to top, and fix SC folded history config
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由 Lingrui98 提交于
* fix a bug of wrongly discarding some new bits to be xored * ghr should be longer in default config to avoid falsely overriding * move TageBanks to top, and fix SC folded history config
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- 12 11月, 2021 3 次提交
- 11 11月, 2021 1 次提交
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由 Lingrui98 提交于
* use compressed info to do redirects * implement folded history class
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- 20 10月, 2021 1 次提交
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由 Lingrui98 提交于
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- 18 10月, 2021 1 次提交
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由 Lingrui98 提交于
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- 17 10月, 2021 1 次提交
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由 Lingrui98 提交于
previously we may use random data from ftq meta sram, and now we fixed this issue
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- 28 9月, 2021 1 次提交
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由 Yinan Xu 提交于
* rename Roq to Rob * remove trailing whitespaces * remove unused parameters
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- 01 9月, 2021 1 次提交
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由 Lingrui98 提交于
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- 30 8月, 2021 1 次提交
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由 rvcoesjw 提交于
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- 28 8月, 2021 1 次提交
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由 Lingrui98 提交于
* modify UBitPeriod to one-eights of the previous value to adapt to nRows enlarged by eight times * fix a bug assigning sc update mask
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- 26 8月, 2021 1 次提交
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由 Lingrui98 提交于
* fix a bug when establishing new ftb entry with a jalr * use ftb hit signal instead of ubtb to assign entry_hit_status * move always taken logic to ftb
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- 24 8月, 2021 1 次提交
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由 Lingrui98 提交于
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- 22 8月, 2021 1 次提交
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由 Lingrui98 提交于
table configs for each bank
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- 20 8月, 2021 1 次提交
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由 Lingrui98 提交于
[WIP] BPU: Modify BPU and Ftq interfaces fix bug calc backendRedirectCfi.shift ftq: update interface [WIP] BPU: Add lastStage function in BranchPredictionResp [WIP] BPU: Move Tage to s2 [WIP] BPU: Fix some bugs ftq: add fast enq logic [WIP] BPU: Move RAS to s2 bpu: s2 and s3 valid should consider corresponding flush signal [WIP] BPU: When s1_valid and s2_valid all false, s3 target need compare with s0_pc_reg, s3_predicted_ghit as well [WIP] BPU: Move resp.s3 assignment from Tage to RAS [WIP] BPU: Fix bug that Tage send meta in s2 [WIP] BPU: Add brOffset and jmpOffset in ubtb tage-sc: fix typos
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- 18 8月, 2021 1 次提交
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由 Lingrui98 提交于
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- 16 8月, 2021 1 次提交
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由 Lingrui98 提交于
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