* remove base table and use ftb results as base pred
* add corrsponding redirect logic in bpu

* split entries into by numBr and use bits in pc to hash between them
* use shorter tags for each table
* make perfEvents a general interface for branch predictor components
  in order to remove casting operation in composer

ecc tag error should not be reported if we do not read tag

Previously the stepie bit won't take effect

* l2/l3: Report ecc error to beu or plic

* Bump huancun

* Connect l3 ecc error to plic

* SoC: Use TLBuffer instead TLEdgeBuffer

* Buffer adjustment

CSRs are updated later after instructions commit from ROB. Thus, we
need to delay difftest commit for several cycles.

* Reduce trigger hit wires that goes into exceptiongen
* Fix frontend triggers rewriting hit wire
* Retrieved some accidentally dropped changes in branch dm-debug (mainly fixes to debug mode)
* Fix dmode in tdata1
* Fix ebreaks not causing exception in debug mode
* Fix dcsr field bugs
* Fix faulty distributed tEnable
* Fix store triggers not using vaddr
* Fix store trigger rewriting hit vector
* Initialize distributed tdata registers in MemBlock and Frontend to zero
* Fix load trigger select bit in mcontrol
* Fix singlestep bit valid in debug mode
* Mask all interrupts in debug mode

* mem: fix error csr update

* dcache: l2 error will now trigger atom error

* chore: fix cache error debug decoder

* mem: split L1CacheErrorInfo and L1BusErrorUnitInfo

XiangShan has registered an marchid of 25: https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md .
This value should be returned from CSR `marchid`.

* move statisical corrector to stage 3
* add recover path in stage 3 for ras in case stage 2 falsely push or pop
* let stage 2 has the highest physical priority in bpu
* left ras broken for the next commit to fix

* reduce number of tables to 4, meanwhile quadrupling number of entries per table, improving area efficiency
* use per bank wrbypass
* invalidate read response when writing to SRAM
* move validArray and useful bit into SRAMs, thus reducing area
* use an optimized history config for such table sizes

* timing: use single ported SRAMs, invalidating read responses on write
* performance:
-- shortening history length to accelerate training
-- use a predictor to reduce s2_redirects on FTB not hit

* fix performance counter in ICacheMainpipe

* IPrefetch: add prefetch address merge and counter

* Add Prefetch and Parity enable register for ICache

* Add ICache parity enable control for pipe

* IFU: fix mmio RVC bug

* IFU: add resend address check for mmio

When a mmio fetch an RVI instruction which cross 64 bits,
IFU must send paddr + 2.U to fetch the higher 16 bits.
But the paddr + 2.U is not checked by TLB or PMP. This may cause
some unexpected fetch stuck problem.

This commit adds blocking logic for instructions when they enter
dispatch queues. If previous instructions have exceptions, any
following instructions should be enter dispatch queue.

Consider the following case. If uop(0) has an exception and is a load.
If uop(1) does not have an exception and is a load as well. Then the
allocation logic in dispatch queue will allocate an entry for both
uop(0) and uop(1). However, uop(0) will not set enq.valid and leave
the entry in dispatch queue empty. uop(1) will be allocated in dpq.
In dispatch queue, pointers are updated according to the real number
of instruction enqueue, which is one. While the second is actually
allocated. This causes errors.

* dcache: add source info in L1CacheErrorInfo

* ICache: fix valid signal and add source/opType

* dcache: fix bug in ecc error

* mem,csr: send full L1CacheErrorInfo to CSR

* icache: provide cache error info for CSR

* dcache: force resp hit if tag ecc error happens

* mem: reorg l1 cache error report path

Now dcache tag error will force trigger a hit

* dcache: fix readline ecc check error

* dcache: mainpipe will not be influenced by tag error

* dcache: fix data ecc check error

* dcache: if coh state is Nothing, do not raise error
Co-authored-by: Nzhanglinjuan <zhanglinjuan20s@ict.ac.cn>
Co-authored-by: NJinYue <jinyue20s@ict.ac.cn>

For 0:x and 1:x, 1:x should be after 0:x.

Valid should be set to true after atomic.exception.valid and cleared
after redirect is valid.