Fix l1plus double hit problem and random replace bug

It used to be changed only when hit

Instead of using io.req.bits as a index to search in valid array, we use
s1_addr register to keep the valid read from valid register array.

roq,exceptionGen: enq_valid should not set when io.flush is valid

roq: block commits when exception.roqIdx === deqPtrVec.last

utils,log: fix PerfDebug conditions

soc: set the number of external interrupts to 150 and dontTouch it

RS: add param srcLen which decides the src data len stored in rs

roq,exceptionGen: don't allow wb or enq after flush

But this would not work(for syntax bug) until other modules change

dispatch2Fp: regfile read port 11 should use psrc3

PTW: refactor ptw. ptw uses multi-way cache and vpn as tag

dispatch2: optimize arbitration logic for better timing

rs: fix roqIdx sent to bypassQueue

Opt jump/alu timing

roq: only store one exceptionVec or flushPipe