Merge pull request #545 from RISCVERS/fix-rs-bypass

rs: fix roqIdx sent to bypassQueue

Merge pull request #545 from RISCVERS/fix-rs-bypass
rs: fix roqIdx sent to bypassQueue
0bdc2a26 · Yinan Xu · GitHub · e84eefe2 · ab385c6c · 0bdc2a26
隐藏空白更改
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src/main/scala/xiangshan/backend/issue/ReservationStation.scala ...in/scala/xiangshan/backend/issue/ReservationStation.scala +1 -1

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--- a/src/main/scala/xiangshan/backend/issue/ReservationStation.scala
+++ b/src/main/scala/xiangshan/backend/issue/ReservationStation.scala
@@ -489,7 +489,7 @@ class ReservationStationCtrl
    val asynIdxUop = (0 until iqSize).map(i => asynUop(io.indexVec(i)) )
    val readyIdxVec = (0 until iqSize).map(i => io.validVec(i) && Cat(srcQueue(io.indexVec(i))).andR )
    val fastAsynUop = ParallelPriorityMux(readyIdxVec zip asynIdxUop)
-    val fastRoqIdx = ParallelPriorityMux(readyIdxVec zip roqIdx)
+    val fastRoqIdx = ParallelPriorityMux(readyIdxVec zip (0 until iqSize).map(i => roqIdx(io.indexVec(i))))
    val fastSentUop = Wire(new MicroOp)
    fastSentUop := DontCare
    fastSentUop.pdest := fastAsynUop.pdest