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体验新版 GitCode,发现更多精彩内容 >>
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daa4676c
编写于
2月 04, 2021
作者:
Y
Yinan Xu
浏览文件
操作
浏览文件
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差异文件
Merge remote-tracking branch 'origin/master' into fix-dispatch2-fp
上级
016af88d
18933059
变更
9
展开全部
隐藏空白更改
内联
并排
Showing
9 changed file
with
840 addition
and
748 deletion
+840
-748
src/main/scala/xiangshan/XSCore.scala
src/main/scala/xiangshan/XSCore.scala
+9
-7
src/main/scala/xiangshan/backend/fu/CSR.scala
src/main/scala/xiangshan/backend/fu/CSR.scala
+1
-1
src/main/scala/xiangshan/cache/ICache.scala
src/main/scala/xiangshan/cache/ICache.scala
+0
-0
src/main/scala/xiangshan/cache/ICacheMissQueue.scala
src/main/scala/xiangshan/cache/ICacheMissQueue.scala
+0
-0
src/main/scala/xiangshan/cache/PTW.scala
src/main/scala/xiangshan/cache/PTW.scala
+766
-0
src/main/scala/xiangshan/cache/TLB.scala
src/main/scala/xiangshan/cache/TLB.scala
+58
-23
src/main/scala/xiangshan/cache/Uncache.scala
src/main/scala/xiangshan/cache/Uncache.scala
+0
-0
src/main/scala/xiangshan/cache/ptw.scala
src/main/scala/xiangshan/cache/ptw.scala
+0
-711
src/main/scala/xiangshan/frontend/IFU.scala
src/main/scala/xiangshan/frontend/IFU.scala
+6
-6
未找到文件。
src/main/scala/xiangshan/XSCore.scala
浏览文件 @
daa4676c
...
...
@@ -50,6 +50,7 @@ case class XSCoreParameters
EnableLB
:
Boolean
=
false
,
EnableLoop
:
Boolean
=
false
,
EnableSC
:
Boolean
=
false
,
EnbaleTlbDebug
:
Boolean
=
false
,
EnableJal
:
Boolean
=
false
,
EnableUBTB
:
Boolean
=
true
,
HistoryLength
:
Int
=
64
,
...
...
@@ -102,10 +103,10 @@ case class XSCoreParameters
RefillSize
:
Int
=
512
,
TlbEntrySize
:
Int
=
32
,
TlbSPEntrySize
:
Int
=
4
,
TlbL2EntrySize
:
Int
=
256
,
//
or 512
TlbL2
SPEntrySize
:
Int
=
16
,
PtwL3EntrySize
:
Int
=
4096
,
//(256 * 16)
or 512
Ptw
SPEntrySize
:
Int
=
16
,
PtwL1EntrySize
:
Int
=
16
,
PtwL2EntrySize
:
Int
=
2
56
,
PtwL2EntrySize
:
Int
=
2
048
,
//(256 * 8)
NumPerfCounters
:
Int
=
16
,
NrExtIntr
:
Int
=
1
)
...
...
@@ -140,6 +141,7 @@ trait HasXSParameter {
val
EnableLB
=
core
.
EnableLB
val
EnableLoop
=
core
.
EnableLoop
val
EnableSC
=
core
.
EnableSC
val
EnbaleTlbDebug
=
core
.
EnbaleTlbDebug
val
HistoryLength
=
core
.
HistoryLength
val
BtbSize
=
core
.
BtbSize
// val BtbWays = 4
...
...
@@ -181,8 +183,8 @@ trait HasXSParameter {
val
DTLBWidth
=
core
.
LoadPipelineWidth
+
core
.
StorePipelineWidth
val
TlbEntrySize
=
core
.
TlbEntrySize
val
TlbSPEntrySize
=
core
.
TlbSPEntrySize
val
TlbL2EntrySize
=
core
.
TlbL2
EntrySize
val
TlbL2SPEntrySize
=
core
.
TlbL2
SPEntrySize
val
PtwL3EntrySize
=
core
.
PtwL3
EntrySize
val
PtwSPEntrySize
=
core
.
Ptw
SPEntrySize
val
PtwL1EntrySize
=
core
.
PtwL1EntrySize
val
PtwL2EntrySize
=
core
.
PtwL2EntrySize
val
NumPerfCounters
=
core
.
NumPerfCounters
...
...
@@ -414,7 +416,7 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
frontend
.
io
.
backend
<>
ctrlBlock
.
io
.
frontend
frontend
.
io
.
sfence
<>
integerBlock
.
io
.
fenceio
.
sfence
frontend
.
io
.
tlbCsr
:=
integerBlock
.
io
.
csrio
.
tlb
frontend
.
io
.
tlbCsr
<>
integerBlock
.
io
.
csrio
.
tlb
frontend
.
io
.
icacheMemAcq
<>
l1pluscache
.
io
.
req
l1pluscache
.
io
.
resp
<>
frontend
.
io
.
icacheMemGrant
...
...
@@ -471,7 +473,7 @@ class XSCoreImp(outer: XSCore) extends LazyModuleImp(outer)
integerBlock
.
io
.
csrio
.
perfinfo
<>
ctrlBlock
.
io
.
roqio
.
toCSR
.
perfinfo
integerBlock
.
io
.
fenceio
.
sfence
<>
memBlock
.
io
.
sfence
integerBlock
.
io
.
fenceio
.
sbuffer
<>
memBlock
.
io
.
fenceToSbuffer
memBlock
.
io
.
tlbCsr
:=
RegNext
(
integerBlock
.
io
.
csrio
.
tlb
)
memBlock
.
io
.
tlbCsr
<>
integerBlock
.
io
.
csrio
.
tlb
floatBlock
.
io
.
frm
<>
integerBlock
.
io
.
csrio
.
frm
...
...
src/main/scala/xiangshan/backend/fu/CSR.scala
浏览文件 @
daa4676c
...
...
@@ -322,7 +322,7 @@ class CSR extends FunctionUnit with HasCSRConst
// val sie = RegInit(0.U(XLEN.W))
val
sieMask
=
"h222"
.
U
&
mideleg
val
sipMask
=
"h222"
.
U
&
mideleg
val
satp
=
RegInit
(
0.
U
(
XLEN
.
W
))
val
satp
=
if
(
EnbaleTlbDebug
)
RegInit
(
UInt
(
XLEN
.
W
),
"h8000000000087fbe"
.
U
)
else
RegInit
(
0.
U
(
XLEN
.
W
))
// val satp = RegInit(UInt(XLEN.W), "h8000000000087fbe".U) // only use for tlb naive debug
val
satpMask
=
"h80000fffffffffff"
.
U
// disable asid, mode can only be 8 / 0
val
sepc
=
RegInit
(
UInt
(
XLEN
.
W
),
0.
U
)
...
...
src/main/scala/xiangshan/cache/
ic
ache.scala
→
src/main/scala/xiangshan/cache/
IC
ache.scala
浏览文件 @
daa4676c
文件已移动
src/main/scala/xiangshan/cache/
ic
acheMissQueue.scala
→
src/main/scala/xiangshan/cache/
IC
acheMissQueue.scala
浏览文件 @
daa4676c
文件已移动
src/main/scala/xiangshan/cache/PTW.scala
0 → 100644
浏览文件 @
daa4676c
此差异已折叠。
点击以展开。
src/main/scala/xiangshan/cache/
tlb
.scala
→
src/main/scala/xiangshan/cache/
TLB
.scala
浏览文件 @
daa4676c
...
...
@@ -38,6 +38,17 @@ trait HasTlbConst extends HasXSParameter {
val
v
=
Bool
()
}
}
def
replaceWrapper
(
v
:
UInt
,
lruIdx
:
UInt
)
:
UInt
=
{
val
width
=
v
.
getWidth
val
emptyIdx
=
ParallelPriorityMux
((
0
until
width
).
map
(
i
=>
(!
v
(
i
),
i
.
U
)))
val
full
=
Cat
(
v
).
andR
Mux
(
full
,
lruIdx
,
emptyIdx
)
}
def
replaceWrapper
(
v
:
Seq
[
Bool
],
lruIdx
:
UInt
)
:
UInt
=
{
replaceWrapper
(
VecInit
(
v
).
asUInt
,
lruIdx
)
}
}
abstract
class
TlbBundle
extends
XSBundle
with
HasTlbConst
...
...
@@ -275,7 +286,8 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
val
ifecth
=
if
(
isDtlb
)
false
.
B
else
true
.
B
val
mode
=
if
(
isDtlb
)
priv
.
dmode
else
priv
.
imode
// val vmEnable = satp.mode === 8.U // && (mode < ModeM) // FIXME: fix me when boot xv6/linux...
val
vmEnable
=
satp
.
mode
===
8.
U
&&
(
mode
<
ModeM
)
val
vmEnable
=
if
(
EnbaleTlbDebug
)
(
satp
.
mode
===
8.
U
)
else
(
satp
.
mode
===
8.
U
&&
(
mode
<
ModeM
))
val
reqAddr
=
req
.
map
(
_
.
bits
.
vaddr
.
asTypeOf
(
vaBundle
))
val
cmd
=
req
.
map
(
_
.
bits
.
cmd
)
...
...
@@ -297,36 +309,38 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
/**
* PTW refill
*/
val
refill
=
ptw
.
resp
.
fire
()
def
randReplace
(
v
:
UInt
)
=
{
val
width
=
v
.
getWidth
val
randIdx
=
LFSR64
()(
log2Up
(
width
)-
1
,
0
)
val
priorIdx
=
PriorityEncoder
(~(
v
)
)
val
full
=
Cat
(
v
).
andR
Mux
(
full
,
randIdx
,
priorIdx
)
}
val
refill
=
ptw
.
resp
.
fire
()
&&
!
sfence
.
valid
val
normalReplacer
=
if
(
isDtlb
)
Some
(
"random"
)
else
Some
(
"plru"
)
val
superReplacer
=
if
(
isDtlb
)
Some
(
"random"
)
else
Some
(
"plru"
)
val
nReplace
=
ReplacementPolicy
.
fromString
(
normalReplacer
,
TlbEntrySize
)
val
sReplace
=
ReplacementPolicy
.
fromString
(
superReplacer
,
TlbSPEntrySize
)
val
nRefillIdx
=
replaceWrapper
(
nv
,
nReplace
.
way
)
val
sRefillIdx
=
replaceWrapper
(
sv
,
sReplace
.
way
)
when
(
refill
)
{
val
resp
=
ptw
.
resp
.
bits
when
(
resp
.
entry
.
level
===
2.
U
)
{
val
refillIdx
=
randReplace
(
nv
.
asUInt
)
when
(
resp
.
entry
.
level
.
getOrElse
(
0.
U
)
===
2.
U
)
{
val
refillIdx
=
nRefillIdx
refillIdx
.
suggestName
(
s
"NormalRefillIdx"
)
nv
(
refillIdx
)
:=
true
.
B
nentry
(
refillIdx
).
apply
(
vpn
=
resp
.
entry
.
tag
,
ppn
=
resp
.
entry
.
ppn
,
level
=
resp
.
entry
.
level
,
perm
=
VecInit
(
resp
.
entry
.
perm
).
asUInt
,
level
=
resp
.
entry
.
level
.
getOrElse
(
0.
U
)
,
perm
=
VecInit
(
resp
.
entry
.
perm
.
getOrElse
(
0.
U
)
).
asUInt
,
pf
=
resp
.
pf
)
XSDebug
(
p
"Refill normal: idx:${refillIdx} entry:${resp.entry} pf:${resp.pf}\n"
)
}.
otherwise
{
val
refillIdx
=
randReplace
(
sv
.
asUInt
)
val
refillIdx
=
sRefillIdx
refillIdx
.
suggestName
(
s
"SuperRefillIdx"
)
sv
(
refillIdx
)
:=
true
.
B
sentry
(
refillIdx
).
apply
(
vpn
=
resp
.
entry
.
tag
,
ppn
=
resp
.
entry
.
ppn
,
level
=
resp
.
entry
.
level
,
perm
=
VecInit
(
resp
.
entry
.
perm
).
asUInt
,
level
=
resp
.
entry
.
level
.
getOrElse
(
0.
U
)
,
perm
=
VecInit
(
resp
.
entry
.
perm
.
getOrElse
(
0.
U
)
).
asUInt
,
pf
=
resp
.
pf
)
XSDebug
(
p
"Refill superpage: idx:${refillIdx} entry:${resp.entry} pf:${resp.pf}\n"
)
...
...
@@ -336,11 +350,12 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
/**
* L1 TLB read
*/
// val tlb_read_mask = Mux(refill, ((1<<(TlbEntrySize+TlbSPEntrySize))-1).U, 0.U((TlbEntrySize+TlbSPEntrySize).W))
val
nRefillMask
=
Mux
(
refill
,
UIntToOH
(
nRefillIdx
)(
TlbEntrySize
-
1
,
0
),
0.
U
).
asBools
val
sRefillMask
=
Mux
(
refill
,
UIntToOH
(
sRefillIdx
)(
TlbSPEntrySize
-
1
,
0
),
0.
U
).
asBools
def
TLBNormalRead
(
i
:
Int
)
=
{
val
entryHitVec
=
(
if
(
isDtlb
)
VecInit
(
entry
.
map
{
e
=>
~
refill
&&
e
.
hit
(
reqAddr
(
i
).
vpn
/*, satp.asid*/
)})
VecInit
(
entry
.
zip
(
nRefillMask
++
sRefillMask
).
map
{
case
(
e
,
m
)
=>
~
m
&&
e
.
hit
(
reqAddr
(
i
).
vpn
)})
else
VecInit
(
entry
.
map
(
_
.
hit
(
reqAddr
(
i
).
vpn
/*, satp.asid*/
)))
)
...
...
@@ -349,17 +364,38 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
val
cmdReg
=
if
(
isDtlb
)
RegNext
(
cmd
(
i
))
else
cmd
(
i
)
val
validReg
=
if
(
isDtlb
)
RegNext
(
valid
(
i
))
else
valid
(
i
)
val
entryHitVecReg
=
if
(
isDtlb
)
RegNext
(
entryHitVec
)
else
entryHitVec
entryHitVecReg
.
suggestName
(
s
"entryHitVecReg_${i}"
)
val
hitVec
=
(
v
zip
entryHitVecReg
).
map
{
case
(
a
,
b
)
=>
a
&
b
}
val
pfHitVec
=
(
pf
zip
entryHitVecReg
).
map
{
case
(
a
,
b
)
=>
a
&
b
}
val
hitVec
=
VecInit
((
v
zip
entryHitVecReg
).
map
{
case
(
a
,
b
)
=>
a
&
b
})
val
pfHitVec
=
VecInit
((
pf
zip
entryHitVecReg
).
map
{
case
(
a
,
b
)
=>
a
&
b
})
val
pfArray
=
ParallelOR
(
pfHitVec
).
asBool
&&
validReg
&&
vmEnable
val
hit
=
ParallelOR
(
hitVec
).
asBool
&&
validReg
&&
vmEnable
&&
~
pfArray
val
miss
=
!
hit
&&
validReg
&&
vmEnable
&&
~
pfArray
val
hitppn
=
ParallelMux
(
hitVec
zip
entry
.
map
(
_
.
ppn
(
reqAddrReg
.
vpn
)))
val
hitPerm
=
ParallelMux
(
hitVec
zip
entry
.
map
(
_
.
data
.
perm
))
hitVec
.
suggestName
(
s
"hitVec_${i}"
)
pfHitVec
.
suggestName
(
s
"pfHitVec_${i}"
)
hit
.
suggestName
(
s
"hit_${i}"
)
miss
.
suggestName
(
s
"miss_${i}"
)
hitppn
.
suggestName
(
s
"hitppn_${i}"
)
hitPerm
.
suggestName
(
s
"hitPerm_${i}"
)
if
(!
isDtlb
)
{
// NOTE: only support one access
val
hitVecUInt
=
hitVec
.
asUInt
XSDebug
(
hitVecUInt
.
orR
,
p
"HitVecUInt:${Hexadecimal(hitVecUInt)}\n"
)
when
(
Cat
(
hitVecUInt
(
TlbEntrySize
-
1
,
0
)).
orR
&&
validReg
&&
vmEnable
)
{
nReplace
.
access
(
OHToUInt
(
hitVecUInt
(
TlbEntrySize
-
1
,
0
)))
XSDebug
(
p
"Normal Page Access: ${Hexadecimal(OHToUInt(hitVecUInt(TlbEntrySize-1, 0)))}\n"
)
}
when
(
Cat
(
hitVecUInt
(
TlbEntrySize
+
TlbSPEntrySize
-
1
,
TlbEntrySize
)).
orR
&&
validReg
&&
vmEnable
)
{
sReplace
.
access
(
OHToUInt
(
hitVecUInt
(
TlbEntrySize
+
TlbSPEntrySize
-
1
,
TlbEntrySize
)))
XSDebug
(
p
"Super Page Access: ${Hexadecimal(OHToUInt(hitVecUInt(TlbEntrySize + TlbSPEntrySize - 1, TlbEntrySize)))}\n"
)
}
}
XSDebug
(
valid
(
i
),
p
"(${i.U}) entryHit:${Hexadecimal(entryHitVec.asUInt)}\n"
)
XSDebug
(
validReg
,
p
"(${i.U}) entryHitReg:${Hexadecimal(entryHitVecReg.asUInt)} hitVec:${Hexadecimal(
VecInit(hitVec).asUInt)} pfHitVec:${Hexadecimal(VecInit(pfHitVec)
.asUInt)} pfArray:${Hexadecimal(pfArray.asUInt)} hit:${hit} miss:${miss} hitppn:${Hexadecimal(hitppn)} hitPerm:${hitPerm}\n"
)
XSDebug
(
validReg
,
p
"(${i.U}) entryHitReg:${Hexadecimal(entryHitVecReg.asUInt)} hitVec:${Hexadecimal(
hitVec.asUInt)} pfHitVec:${Hexadecimal(pfHitVec
.asUInt)} pfArray:${Hexadecimal(pfArray.asUInt)} hit:${hit} miss:${miss} hitppn:${Hexadecimal(hitppn)} hitPerm:${hitPerm}\n"
)
val
multiHit
=
{
val
hitSum
=
PopCount
(
hitVec
)
...
...
@@ -409,7 +445,7 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
waiting
:=
false
.
B
}
// ptw <> DontCare // TODO: need check it
ptw
.
req
.
valid
:=
hasMissReq
&&
!
sfence
.
valid
&&
!
waiting
&&
!
RegNext
(
refill
)
ptw
.
req
.
valid
:=
hasMissReq
&&
!
waiting
&&
!
RegNext
(
refill
)
ptw
.
resp
.
ready
:=
waiting
// val ptwReqSeq = Wire(Seq.fill(Width)(new comBundle()))
...
...
@@ -429,7 +465,6 @@ class TLB(Width: Int, isDtlb: Boolean) extends TlbModule with HasCSRConst{
// sfence (flush)
when
(
sfence
.
valid
)
{
ptw
.
req
.
valid
:=
false
.
B
when
(
sfence
.
bits
.
rs1
)
{
// virtual address *.rs1 <- (rs1===0.U)
when
(
sfence
.
bits
.
rs2
)
{
// asid, but i do not want to support asid, *.rs2 <- (rs2===0.U)
// all addr and all asid
...
...
src/main/scala/xiangshan/cache/
u
ncache.scala
→
src/main/scala/xiangshan/cache/
U
ncache.scala
浏览文件 @
daa4676c
文件已移动
src/main/scala/xiangshan/cache/ptw.scala
已删除
100644 → 0
浏览文件 @
016af88d
此差异已折叠。
点击以展开。
src/main/scala/xiangshan/frontend/IFU.scala
浏览文件 @
daa4676c
...
...
@@ -151,7 +151,7 @@ class IFU extends XSModule with HasIFUConst with HasCircularQueuePtrHelper
val
npcGen
=
new
PriorityMuxGenerator
[
UInt
]
npcGen
.
register
(
true
.
B
,
RegNext
(
if1_npc
),
Some
(
"stallPC"
))
val
if2_bp
=
bpu
.
io
.
out
(
0
)
// if taken, bp_redirect should be true
// when taken on half RVI, we suppress this redirect signal
...
...
@@ -294,7 +294,7 @@ class IFU extends XSModule with HasIFUConst with HasCircularQueuePtrHelper
def
br_offset
(
inst
:
UInt
,
rvc
:
Bool
)
:
SInt
=
{
Mux
(
rvc
,
Cat
(
inst
(
12
),
inst
(
6
,
5
),
inst
(
2
),
inst
(
11
,
10
),
inst
(
4
,
3
),
0.
U
(
1.
W
)).
asSInt
,
Cat
(
inst
(
31
),
inst
(
7
),
inst
(
30
,
25
),
inst
(
11
,
8
),
0.
U
(
1.
W
)).
asSInt
()
Cat
(
inst
(
31
),
inst
(
7
),
inst
(
30
,
25
),
inst
(
11
,
8
),
0.
U
(
1.
W
)).
asSInt
()
)
}
val
if4_instrs
=
if4_pd
.
instrs
...
...
@@ -331,7 +331,7 @@ class IFU extends XSModule with HasIFUConst with HasCircularQueuePtrHelper
}
prevHalfInstrReq
.
valid
:=
if4_fire
&&
if4_bp
.
saveHalfRVI
&&
HasCExtension
.
B
// // this is result of the last half RVI
prevHalfInstrReq
.
bits
.
pc
:=
if4_pd
.
pc
(
PredictWidth
-
1
)
prevHalfInstrReq
.
bits
.
npc
:=
snpc
(
if4_pc
)
...
...
@@ -406,7 +406,7 @@ class IFU extends XSModule with HasIFUConst with HasCircularQueuePtrHelper
io
.
toFtq
.
valid
:=
ftqEnqBuf_valid
io
.
toFtq
.
bits
:=
ftqEnqBuf
toFtqBuf
:=
DontCare
toFtqBuf
.
ftqPC
:=
if4_pc
toFtqBuf
.
lastPacketPC
.
valid
:=
if4_pendingPrevHalfInstr
...
...
@@ -584,7 +584,7 @@ class IFU extends XSModule with HasIFUConst with HasCircularQueuePtrHelper
XSDebug
(
"[IF3][if3_prevHalfInstr] v=%d pc=%x npc=%x instr=%x ipf=%d\n\n"
,
if3_prevHalfInstr
.
valid
,
if3_prevHalfInstr
.
bits
.
pc
,
if3_prevHalfInstr
.
bits
.
npc
,
if3_prevHalfInstr
.
bits
.
instr
,
if3_prevHalfInstr
.
bits
.
ipf
)
if3_gh
.
debug
(
"if3"
)
XSDebug
(
"[IF4][predecode] mask=%b\n"
,
if4_pd
.
mask
)
XSDebug
(
"[IF4][snpc]: %x, realMask=%b\n"
,
if4_snpc
,
if4_mask
)
XSDebug
(
"[IF4][bp] taken=%d jmpIdx=%d hasNTBrs=%d target=%x saveHalfRVI=%d\n"
,
if4_bp
.
taken
,
if4_bp
.
jmpIdx
,
if4_bp
.
hasNotTakenBrs
,
if4_bp
.
target
,
if4_bp
.
saveHalfRVI
)
...
...
@@ -613,7 +613,7 @@ class IFU extends XSModule with HasIFUConst with HasCircularQueuePtrHelper
ftqEnqBuf_valid
,
ftqEnqBuf_ready
,
b
.
ftqPC
,
b
.
cfiIndex
.
valid
,
b
.
cfiIndex
.
bits
,
b
.
cfiIsCall
,
b
.
cfiIsRet
,
b
.
cfiIsRVC
)
XSDebug
(
"[FtqEnqBuf] valids=%b br_mask=%b rvc_mask=%b hist=%x predHist=%x rasSp=%d rasTopAddr=%x rasTopCtr=%d\n"
,
b
.
valids
.
asUInt
,
b
.
br_mask
.
asUInt
,
b
.
rvc_mask
.
asUInt
,
b
.
hist
.
asUInt
,
b
.
predHist
.
asUInt
,
b
.
rasSp
,
b
.
rasTop
.
retAddr
,
b
.
rasTop
.
ctr
)
XSDebug
(
"[ToFTQ] v=%d r=%d leftOne=%d ptr=%d\n"
,
io
.
toFtq
.
valid
,
io
.
toFtq
.
ready
,
io
.
ftqLeftOne
,
io
.
ftqEnqPtr
.
value
)
XSDebug
(
"[ToFTQ] v=%d r=%d leftOne=%d ptr=%d\n"
,
io
.
toFtq
.
valid
,
io
.
toFtq
.
ready
,
io
.
ftqLeftOne
,
io
.
ftqEnqPtr
.
value
)
}
}
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