bpu: try to avoid making some invalid predictions that occupy cache bandwidth

* block reads when ittage writes
* reset ras on reset so that it would not provide random addresses

src/main/scala/xiangshan/frontend/ITTAGE.scala

@@ -259,7 +259,7 @@ class ITTageTable
   }
 
   val bank_conflict = (0 until nBanks).map(b => table_banks(b).io.w.req.valid && s0_bank_req_1h(b)).reduce(_||_)
-  io.req.ready := true.B
+  io.req.ready := !io.update.valid
   // io.req.ready := !bank_conflict
   XSPerfAccumulate(f"ittage_table_bank_conflict", bank_conflict)
 

src/main/scala/xiangshan/frontend/RAS.scala

@@ -120,6 +120,7 @@ class RAS(implicit p: Parameters) extends BasePredictor {
       }
     }
 
+    
     update(io.recover_valid)(
       Mux(io.recover_valid, io.recover_push,     io.push_valid),
       Mux(io.recover_valid, io.recover_pop,      io.pop_valid),
@@ -128,9 +129,19 @@ class RAS(implicit p: Parameters) extends BasePredictor {
       Mux(io.recover_valid, io.recover_sp - 1.U, topPtr),
       Mux(io.recover_valid, io.recover_new_addr, io.spec_new_addr),
       Mux(io.recover_valid, io.recover_top,      top))
-
+      
     io.sp := sp
     io.top := top
+    
+    val resetIdx = RegInit(0.U(log2Ceil(RasSize).W))
+    val do_reset = RegInit(true.B)
+    when (do_reset) {
+      stack.write(resetIdx, RASEntry(0x80000000L.U, 0.U))
+    }
+    resetIdx := resetIdx + do_reset
+    when (resetIdx === (RasSize-1).U) {
+      do_reset := false.B
+    }
 
     debugIO.push_entry := RASEntry(io.spec_new_addr, Mux(alloc_new, 1.U, top.ctr + 1.U))
     debugIO.alloc_new := alloc_new