* perf: set acc arg of XSPerf as false by default

* perf: add write-port competition counter for intBlock & floatBlock

* perf: remove prefix of perf signal

* perf: add perf-cnt for interface between frontend & backend

* perf: modify perf-cnt for prefetchers

* Ftq: bypass 'commit state' to fix dequeue bug

* perf: uptimize perf-cnt in ctrlblock & ftq

* perf: fix compilation problem in ftq

* perf: remove duplicate perf-cnt

* perf: calcu extra walk cycle exceeding frontend flush bubble

* Revert "perf: calcu extra walk cycle exceeding frontend flush bubble"

This reverts commit 2c30e9896b6af93a34e2d8d78055d810ebd0ac70.

* perf: add perf-cnt for ifu

* perf: add perf-cnt for rs

* RS: optimize numExist signal

* RS: fix some typo

* perf: add QueuePerf util to monitor usage info of queues

* perf: remove some duprecate perfcnt

Update SoC and emu configurations

Add bus error unit and connect ecc errors to beu

* MissQueue: add perf cnt for inflight entries in maximum

* MissQueue: max_inflight ignores cycles when missQueue is empty

This allows the software to determine whether an address
can be read or written.

* add perf counters for btb and ubtb
* update btb only on not hit or jalr mispredicts to reduce write stalls

just record the tlb result(access and miss) of first issue by add
signal isFirstIssue (isFirstIssue = cntCountQueue(i) === 0.U)

* DCacheWrapper: MainPipe use read port 1 to ease congestion

* MainPipe: do not consider congestion with ldu0 read when disabling fast wakeup

Previously we use numactl to specify both nodes and cpus for emu.
However, when other processes are using the same cpu, verilated emu
suffers from huge performance degradation. To avoid these scenarios,
we only specify the numa node to achieve a more stable performance.

In this commit, we add support for a simpler version of move elimination.

The original instruction sequences are:
move r1, r0
add r2, r1, r3

The optimized sequnces are:
move pr1, pr0
add pr2, pr0, pr3 # instead of add pr2, pr1, pr3

In this way, add can be issued once r0 is ready and move seems to be eliminated.

* MainPipe/LoadPipe: disable fast wakeup when data sram is to be written

* RS: set EnableLoadFastWakeUp true

* LoadPipe: add perf cnt for disabling ld fast wakeup speculatively

* MainPipe: disable ld fast wakeup when s1 read data in MainPipe
Co-authored-by: Nzhanglinjuan <zhanglinjuan16@mails.ucas.ac.cn>

* DCache: fix bug in failing to update access info of plru replacement

* DCache: add performance counters