- 22 9月, 2019 14 次提交
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
* Flushing ICache will cost cycles equal to the number of cache sets, which is 512 now. Before finishing the flush, instruction fetch will be stalled. * Now we really pass nexum-am/tests/cachetest/test/loader.c.
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由 Zihao Yu 提交于
* When executing fence.i, the pipeline and ICache will be flushed. New instructions will be fetched from memory, or DCache with coherence support. * With fence.i, we should pass nexus-am/tests/cachetest/test/loader.c.
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由 Zihao Yu 提交于
Rv64 fpga See merge request projectn/noop!13
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
* AXI requires araddr to be aligned with arsize
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由 Zihao Yu 提交于
* 64-bit multiplier consumes more DSPs on FPGA than 32-bit multiplier. Cascaded DSPs lead to poor timing, and must improve by more registers.
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
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- 21 9月, 2019 9 次提交
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由 Zihao Yu 提交于
debug,Makefile: add more rules See merge request projectn/noop!12
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
Fix mdu See merge request projectn/noop!11
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由 Zihao Yu 提交于
* This will increase the latency of word operations: IPC: 0.544714 -> 0.528246 * Should perform more optimization on earlyFinish.
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
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由 Zihao Yu 提交于
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由 William Wang 提交于
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由 William Wang 提交于
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- 20 9月, 2019 6 次提交
- 19 9月, 2019 8 次提交
- 18 9月, 2019 1 次提交
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由 Zihao Yu 提交于
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- 17 9月, 2019 2 次提交