noop,MDU: merge mulw into XLEN-bit multiplier

src/main/scala/noop/fu/MDU.scala

@@ -148,7 +148,6 @@ class MDU extends NOOPModule {
 
   val mul = Module(new Multiplier(XLEN + 1))
   val div = Module(new Divider(64))
-  val mul32 = Module(new Multiplier(32))
   val div32 = Module(new Divider(32))
   List(mul.io, div.io).map { case x =>
     x.in.bits(0) := src1
@@ -168,7 +167,7 @@ class MDU extends NOOPModule {
   mul.io.in.bits(0) := LookupTree(func(1,0), mulInputFuncTable.map(p => (p._1(1,0), p._2._1(src1))))
   mul.io.in.bits(1) := LookupTree(func(1,0), mulInputFuncTable.map(p => (p._1(1,0), p._2._2(src2))))
 
-  List(mul32.io, div32.io).map { case x =>
+  List(div32.io).map { case x =>
     x.in.bits(0) := src1(31,0)
     x.in.bits(1) := src2(31,0)
     x.sign := MDUOpType.isSign(func)
@@ -176,31 +175,28 @@ class MDU extends NOOPModule {
   }
   val isDiv = MDUOpType.isDiv(func)
   val isW   = MDUOpType.isW(func)
-  mul.io.in.valid := io.in.valid && !isDiv && !isW
+  mul.io.in.valid := io.in.valid && !isDiv
   div.io.in.valid := io.in.valid && isDiv && !isW
-  mul32.io.in.valid := io.in.valid && !isDiv && isW
   div32.io.in.valid := io.in.valid && isDiv && isW
 
-  io.out.bits := LookupTree(func, List(
-    MDUOpType.mul  -> mul.io.out.bits(XLEN-1,0),
-    MDUOpType.mulh -> mul.io.out.bits(2*XLEN-1,XLEN),
-    MDUOpType.mulhu -> mul.io.out.bits(2*XLEN-1,XLEN),
-    MDUOpType.mulhsu -> mul.io.out.bits(2*XLEN-1,XLEN),
+  val mulRes = Mux(func(1,0) === MDUOpType.mul(1,0), mul.io.out.bits(XLEN-1,0), mul.io.out.bits(2*XLEN-1,XLEN))
+  val divRes = LookupTree(func, List(
     MDUOpType.div  -> div.io.out.bits(XLEN-1,0),
     MDUOpType.divu -> div.io.out.bits(XLEN-1,0),
     MDUOpType.rem  -> div.io.out.bits(2*XLEN-1,XLEN),
     MDUOpType.remu -> div.io.out.bits(2*XLEN-1,XLEN),
 
-    MDUOpType.mulw -> SignExt(mul32.io.out.bits(31,0), XLEN),
     MDUOpType.divw -> SignExt(div32.io.out.bits(31,0), XLEN),
     MDUOpType.divuw-> SignExt(div32.io.out.bits(31,0), XLEN),
     MDUOpType.remw -> SignExt(div32.io.out.bits(63,32), XLEN),
     MDUOpType.remuw-> SignExt(div32.io.out.bits(63,32), XLEN)
   ))
+  val res = Mux(isDiv, divRes, mulRes)
+  io.out.bits := Mux(isW, SignExt(res(31,0),64), res)
 
   val isDivReg = Mux(io.in.fire(), isDiv, RegNext(isDiv))
   io.in.ready := Mux(isDiv, div.io.in.ready, mul.io.in.ready)
-  io.out.valid := Mux(isDivReg, div.io.out.valid || div32.io.out.valid, mul.io.out.valid || mul32.io.out.valid)
+  io.out.valid := Mux(isDivReg, div.io.out.valid || div32.io.out.valid, mul.io.out.valid)
 
   BoringUtils.addSource(mul.io.out.fire(), "perfCntCondMmulInstr")
 }