* Now can pass compiling.

[WIP] comment out-of-date code in frontend

[WIP] move NewFtq to xiangshan.frontend and rename class to Ftq

Ibuffer: update sigal names for new IFU

[WIP] remove redundant NewFrontend

[WIP] set entry_fetch_status to f_sent once send req to buf

Fix syntax error in IFU

Fix syntax error in IFU/ICache/Ibuffer

[WIP] indent fix in ftq

BPU: Move GlobalHistory define from IFU.scala to BPU.scala

[WIP] fix some compilation errors

BPU: Remove HasIFUConst
and move some bundles from BPU.scala to frontendBundle.scala

[WIP] fix some compilation errors

[WIP] rename ftq-bpu ios

[WIP] recover some const definitions

[WIP] fix some compilation errors

[WIP]connect some IOs in frontend

BPU: fix syntax error

[WIP] fix compilation errors in predecode

BPU: fix RAS syntax error

[WIP] add some simulation perf counters back

BPU: Remove numBr redefine in ubtb and bim

* FrontendBundle.scala: change IFU-to-Ftq Bundle defination.
    delete jump and branch, instead use missOffset and cfiOffset.
* ICache.scala: fix some name error using IDEA
* IFU.scala: update bundle connection logic according to FrontendBundle
* PreDecode.scala: generate missOffset and cfiOffset

add handshake between pipeline stage

* misc: cleanup for submodules and Makefile

* misc: use ready-to-run submodule
Co-authored-by: NWilliam Wang <zeweiwang@outlook.com>

* Recover Ftq Pointer and send miss req to I$ MSHRs
* Instruction reorder is done by Ftq

* TODO: need a solution for fetch-on-miss

difftest: support --no-diff arg to emulate without difftest by nemu