[WIP]IFU: add fetch-on-miss logic.

* Recover Ftq Pointer and send miss req to I$ MSHRs
* Instruction reorder is done by Ftq

src/main/scala/xiangshan/decoupled-frontend/IFU.scala

@@ -26,7 +26,8 @@ class IFU(implicit p: Parameters) extends XSModule
   val io = IO(new IFUIO)
   val (toFtq, fromFtq)    = (io.FtqInterface.toFtq, io.FtqInterface.fromFtq)
   val (toMeta, toData, meta_resp, data_resp) =  (io.ICacheInterface.toMeta, io.ICacheInterface.toData, io.ICacheInterface.fromMeta, io.ICacheInterface.fromData)
-  
+  val (toMissQueue, fromMissQueue) = (io.ICacheInterface.toMissQueue, io.ICacheInterface.fromMissQueue)
+
   //fetch: send addr to Meta/TLB and Data simultaneously
   val fetch_req = Seq(toMeta, toData)
   fetch_req.map(channel => 
@@ -42,8 +43,17 @@ class IFU(implicit p: Parameters) extends XSModule
   io.toIbuffer.valid := fetch_valid
   (0 until FetchWidth).map(i  => io.toIbuffer.bits.instr(i) := data_resp.bits.instr(i))
 
-  //TODO: sulotion to fetch-on-miss problem
-  io.toFtq.valid := (fectch_valid) || (fetch_fail && meta_resp.bits.refill.valid)
-  io.toFtq.bits.replayIdx := RegNext(fromFtq.bits.idx)
+  //fetch miss 
+  val fetch_miss_register = RegInit(false.B)
+  fetch_miss_register.valid := fetch_fail
+
+  val fetch_miss_ftqIdx   = RegNext(fromFtq.bits.idx)
 
+  toFtq.valid := (fectch_valid) || (fetch_miss_register.valid && REFILL_VALID)
+  toFtq.entryState := Mux(fetch_valid,"fetch_resp","replay_resp")
+  toFtq.bits.replayIdx := fetch_miss_ftqIdx 
+  
+  toMissQueue.valid    :=  fetch_fail
+  toMissQueue.bits     :=  fetch_miss_ftq_idx
+  
 }