[WIP]Frontend: Done Elaborating

src/main/scala/xiangshan/Bundle.scala

@@ -140,7 +140,7 @@ class CfiUpdateInfo(implicit p: Parameters) extends XSBundle with HasBPUParamete
   val rasEntry = new RASEntry
   val hist = new GlobalHistory
   val predHist = new GlobalHistory
-  val specCnt = Vec(PredictWidth, UInt(10.W))
+  val specCnt = Vec(numBr, UInt(10.W))
   // need pipeline update
   val sawNotTakenBranch = Bool()
   val predTaken = Bool()

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -24,7 +24,7 @@ import xiangshan.backend.decode.{DecodeStage, ImmUnion}
 import xiangshan.backend.rename.{BusyTable, Rename}
 import xiangshan.backend.dispatch.Dispatch
 import xiangshan.backend.exu._
-import xiangshan.frontend.{FtqRead, FtqToCtrlIO, FtqPtr}
+import xiangshan.frontend.{FtqRead, FtqToCtrlIO, FtqPtr, CfiInfoToCtrl}
 import xiangshan.backend.roq.{Roq, RoqCSRIO, RoqLsqIO, RoqPtr}
 import xiangshan.mem.LsqEnqIO
 
@@ -79,12 +79,12 @@ class RedirectGenerator(implicit p: Parameters) extends XSModule
     val exuMispredict = Vec(numRedirect, Flipped(ValidIO(new ExuOutput)))
     val loadReplay = Flipped(ValidIO(new Redirect))
     val flush = Input(Bool())
-    val stage1PcRead = Flipped((new FtqToCtrlIO).getRedirectPcRead)
-    val stage1CfiRead = Flipped((new FtqToCtrlIO).cfi_reads)
+    val stage1PcRead = Vec(numRedirect+1, new FtqRead(UInt(VAddrBits.W)))
+    val stage1CfiRead = Vec(numRedirect+1, new FtqRead(new CfiInfoToCtrl))
     val stage2Redirect = ValidIO(new Redirect)
     val stage3Redirect = ValidIO(new Redirect)
     val memPredUpdate = Output(new MemPredUpdateReq)
-    val memPredPcRead = Flipped((new FtqToCtrlIO).getMemPredPcRead) // read req send form stage 2
+    val memPredPcRead = new FtqRead(UInt(VAddrBits.W)) // read req send form stage 2
   })
   /*
         LoadQueue  Jump  ALU0  ALU1  ALU2  ALU3   exception    Stage1

src/main/scala/xiangshan/decoupled-frontend/BPU.scala

@@ -33,7 +33,7 @@ trait HasBPUConst extends HasXSParameter with HasIFUConst {
   // val resetVector = 0x10000000L//TODO: set reset vec
 }
 
-trait HasBPUParameter extends HasXSParameter {
+trait HasBPUParameter extends HasXSParameter with HasBPUConst {
   val BPUDebug = true && !env.FPGAPlatform
   val EnableCFICommitLog = true
   val EnbaleCFIPredLog = true
@@ -228,7 +228,7 @@ class BpuToFtqIO(implicit p: Parameters) extends XSBundle {
 
 class PredictorIO(implicit p: Parameters) extends XSBundle {
   val bpu_to_ftq = new BpuToFtqIO()
-  val ftq_to_bpu = new FtqToBpuIO()
+  val ftq_to_bpu = Flipped(new FtqToBpuIO())
 }
 
 class FakeBPU(implicit p: Parameters) extends XSModule with HasBPUConst {

src/main/scala/xiangshan/decoupled-frontend/FrontendBundle.scala

@@ -10,7 +10,7 @@ class FetchRequestBundle(implicit p: Parameters) extends XSBundle {
   val startAddr    = UInt(VAddrBits.W)
   val fallThruAddr = UInt(VAddrBits.W)
   val ftqIdx       = new FtqPtr
-  val ftqOffset    = Valid(UInt(log2Ceil(32).W))
+  val ftqOffset    = ValidUndirectioned(UInt(log2Ceil(32).W))
   val target       = UInt(VAddrBits.W)
 }
 
@@ -95,7 +95,7 @@ class BranchPredictionBundle(implicit p: Parameters) extends XSBundle with HasBP
   val ghist = new GlobalHistory()
   val rasSp = UInt(log2Ceil(RasSize).W)
   val rasTop = new RASEntry
-  val specCnt = Vec(PredictWidth, UInt(10.W))
+  val specCnt = Vec(numBr, UInt(10.W))
   val meta = UInt(MaxMetaLength.W)
 
   val ftb_entry = new FTBEntry() // TODO: Send this entry to ftq

src/main/scala/xiangshan/decoupled-frontend/IFU.scala

@@ -38,7 +38,7 @@ class IfuToFtqIO(implicit p:Parameters) extends XSBundle {
 }
 
 class FtqInterface(implicit p: Parameters) extends XSBundle {
-  val fromFtq = Flipped(Decoupled(new FetchRequestBundle))
+  val fromFtq = Flipped(new FtqToIfuIO)
   val toFtq   = new IfuToFtqIO 
 }
 
@@ -89,12 +89,12 @@ class NewIFU(implicit p: Parameters) extends XSModule with Temperary with HasICa
   //  * Send req to ITLB
   //---------------------------------------------
 
-  val (f0_valid, f1_ready)                 = (fromFtq.valid, WireInit(false.B))
-  val f0_ftq_req                           = fromFtq.bits
+  val (f0_valid, f1_ready)                 = (fromFtq.req.valid, WireInit(false.B))
+  val f0_ftq_req                           = fromFtq.req.bits
   val f0_situation                         = VecInit(Seq(isCrossLineReq(f0_ftq_req.startAddr, f0_ftq_req.fallThruAddr), isLastInCacheline(f0_ftq_req.fallThruAddr)))
   val f0_doubleLine                        = f0_situation(0) || f0_situation(1)
   val f0_vSetIdx                           = VecInit(getIdx((f0_ftq_req.startAddr)), getIdx(f0_ftq_req.fallThruAddr))
-  val f0_fire                              = fromFtq.fire()
+  val f0_fire                              = fromFtq.req.fire()
 
   //fetch: send addr to Meta/TLB and Data simultaneously
   val fetch_req = List(toMeta, toData)
@@ -104,7 +104,7 @@ class NewIFU(implicit p: Parameters) extends XSModule with Temperary with HasICa
     fetch_req(i).bits.vSetIdx := f0_vSetIdx
   }
 
-  fromFtq.ready := fetch_req(0).ready && fetch_req(1).ready && f1_ready
+  fromFtq.req.ready := fetch_req(0).ready && fetch_req(1).ready && f1_ready
 
   //TODO: tlb req
   io.iTLBInter.req <> DontCare
@@ -248,7 +248,7 @@ class NewIFU(implicit p: Parameters) extends XSModule with Temperary with HasICa
   
   val f2_hit_datas    = RegEnable(next = f1_hit_data, enable = f1_fire) 
   val f2_mq_datas     = RegInit(VecInit(fromMissQueue.map(p => p.bits.data)))    //TODO: Implement miss queue response
-  val f2_datas        = Mux(f2_hit, f2_hit_datas, f2_mq_datas)
+  val f2_datas        = Mux(f2_hit, f2_hit_datas(0), f2_mq_datas) // TODO: f1_hit_datas is error
 
   def cut(cacheline: UInt, start: UInt) : Vec[UInt] ={
     val result   = Wire(Vec(17, UInt(16.W)))
@@ -270,7 +270,9 @@ class NewIFU(implicit p: Parameters) extends XSModule with Temperary with HasICa
   io.toIbuffer.bits.valid     := preDecoderOut.valid
   io.toIbuffer.bits.pd        := preDecoderOut.pd
   io.toIbuffer.bits.ftqPtr    := f2_ftq_req.ftqIdx
-  io.toIbuffer.bits.ftqOffset := preDecoderOut.pc
+  // TODO: Fix it
+  // io.toIbuffer.bits.ftqOffset := preDecoderOut.pc
+  io.toIbuffer.bits.ftqOffset.zip(preDecoderOut.pc).map{case(a, b) => a.bits := b; a.valid := true.B}
   io.toIbuffer.bits.foldpc    := preDecoderOut.pc.map(i => XORFold(i(VAddrBits-1,1), MemPredPCWidth))
 
 
@@ -278,7 +280,7 @@ class NewIFU(implicit p: Parameters) extends XSModule with Temperary with HasICa
   toFtq.pdWb.bits.pc         := preDecoderOut.pc
   toFtq.pdWb.bits.pd         := preDecoderOut.pd
   toFtq.pdWb.bits.ftqIdx     := f2_ftq_req.ftqIdx
-  toFtq.pdWb.bits.ftqOffset  := f2_ftq_req.ftqOffset
+  toFtq.pdWb.bits.ftqOffset  := f2_ftq_req.ftqOffset.bits // TODO: fix it
   toFtq.pdWb.bits.misOffset  := preDecoderOut.misOffset
   toFtq.pdWb.bits.cfiOffset  := preDecoderOut.cfiOffset
   toFtq.pdWb.bits.target     := preDecoderOut.target

src/main/scala/xiangshan/decoupled-frontend/Ibuffer.scala

@@ -44,7 +44,7 @@ class Ibuffer(implicit p: Parameters) extends XSModule with HasCircularQueuePtrH
     val pd = new PreDecodeInfo
     val pred_taken = Bool()
     val ftqPtr = new FtqPtr
-    val ftqOffset = Valid(UInt(log2Ceil(16).W))
+    val ftqOffset = UInt(log2Ceil(16).W) // TODO: fix it
   }
 
   for(out <- io.out) {

src/main/scala/xiangshan/decoupled-frontend/NewFtq.scala

@@ -144,7 +144,7 @@ class FtqToIfuIO(implicit p: Parameters) extends XSBundle {
 }
 
 class FtqToCtrlIO(implicit p: Parameters) extends XSBundle {
-  val pc_reads = Vec(1 + 6 + 1 + 1 + 1, Flipped(new FtqRead(UInt(VAddrBits.W))))
+  val pc_reads = Vec(1 + 6 + 1 + 1, Flipped(new FtqRead(UInt(VAddrBits.W))))
   val target_read = Flipped(new FtqRead(UInt(VAddrBits.W)))
   val cfi_reads = Vec(6, Flipped(new FtqRead(new CfiInfoToCtrl)))
   def getJumpPcRead = pc_reads.head
@@ -182,7 +182,7 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
   io.fromBpu.resp.ready := validEntries < FtqSize.U
   val enq_fire = io.fromBpu.resp.fire() && !flush
 
-  val ftq_pc_mem = Module(new SyncDataModuleTemplate(new Ftq_RF_Components, FtqSize, 10, 1))
+  val ftq_pc_mem = Module(new SyncDataModuleTemplate(new Ftq_RF_Components, FtqSize, 11, 1))
   ftq_pc_mem.io.wen(0) := enq_fire
   ftq_pc_mem.io.waddr(0) := bpuPtr.value
   ftq_pc_mem.io.wdata(0).startAddr := io.fromBpu.resp.bits.pc
@@ -192,16 +192,15 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
   val ftq_hist_mem = Module(new SyncDataModuleTemplate(new GlobalHistory, FtqSize, 10, 1))
   ftq_hist_mem.io.wen(0) := enq_fire
   ftq_hist_mem.io.waddr(0) := bpuPtr.value
-  ftq_pc_mem.io.wdata(0) := io.fromBpu.resp.bits.ghist
+  ftq_hist_mem.io.wdata(0) := io.fromBpu.resp.bits.ghist
   
   val ftq_redirect_sram = Module(new FtqNRSRAM(new Ftq_Redirect_SRAMEntry, 2))
-  ftq_redirect_sram.io.wen(0) := enq_fire
-  ftq_redirect_sram.io.waddr(0) := bpuPtr.value
+  ftq_redirect_sram.io.wen := enq_fire
+  ftq_redirect_sram.io.waddr := bpuPtr.value
   ftq_redirect_sram.io.wdata.rasSp := io.fromBpu.resp.bits.rasSp
   ftq_redirect_sram.io.wdata.rasEntry := io.fromBpu.resp.bits.rasTop
   ftq_redirect_sram.io.wdata.specCnt := io.fromBpu.resp.bits.specCnt
 
-  pred_target_sram.io.raddr(0) := ifuPtr.value
   val pred_target_sram = Module(new FtqNRSRAM(UInt(VAddrBits.W), 2))
   pred_target_sram.io.wen := enq_fire
   pred_target_sram.io.waddr := bpuPtr.value
@@ -257,7 +256,7 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
   ftq_pd_mem.io.waddr(0) := pdWb.bits.ftqIdx.value
   val pds = pdWb.bits.pd
   ftq_pd_mem.io.wdata(0).brMask := VecInit(pds.map(pd => pd.isBr && pd.valid))
-  ftq_pd_mem.io.wdata(0).jmpInfo.valid := VecInit(pds.map(pd => (pd.isJal || pd.isJalr) && pd.valid))
+  ftq_pd_mem.io.wdata(0).jmpInfo.valid := VecInit(pds.map(pd => (pd.isJal || pd.isJalr) && pd.valid)).asUInt.orR
   ftq_pd_mem.io.wdata(0).jmpInfo.bits := ParallelPriorityMux(pds.map(pd => (pd.isJal || pd.isJalr) && pd.valid),
                                                           pds.map(pd => VecInit(pd.isJalr, pd.isCall, pd.isRet)))
   ftq_pd_mem.io.wdata(0).jmpOffset := ParallelPriorityEncoder(pds.map(pd => (pd.isJal || pd.isJalr) && pd.valid))
@@ -280,11 +279,11 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
   ifuPtr := ifuPtr + to_buf_fire
   
   when (flush) {
-    to_buf_valid := false.B
+    ifu_req_buf.valid := false.B
   }.elsewhen (to_buf_fire) {
-    to_buf_valid := true.B
+    ifu_req_buf.valid := true.B
   }.elsewhen (io.toIfu.req.fire()) {
-    to_buf_valid := false.B
+    ifu_req_buf.valid := false.B
   }
   
   // read pc and target
@@ -293,7 +292,7 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
   pred_target_sram.io.ren(0) := to_buf_fire
   
   when (to_buf_fire) {
-    ifu_req_buf.bits.ftqIdx := ifuPtr.value
+    ifu_req_buf.bits.ftqIdx := ifuPtr
     ifu_req_buf.bits.ftqOffset := cfiIndex_vec(ifuPtr.value)
   }
   when (RegNext(to_buf_fire)) {
@@ -305,7 +304,7 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
   val last_cycle_to_buf_fire = RegNext(to_buf_fire)
   io.toIfu.req.valid := ifu_req_buf.valid
   io.toIfu.req.bits.ftqIdx := ifu_req_buf.bits.ftqIdx
-  io.toIfu.req.bits.ftqOffset := ifu_req_buf.bits.ftqIdx
+  io.toIfu.req.bits.ftqOffset := ifu_req_buf.bits.ftqOffset
   io.toIfu.req.bits.startAddr := Mux(last_cycle_to_buf_fire,
                                      ftq_pc_mem.io.rdata(10).startAddr,
                                      ifu_req_buf.bits.startAddr)
@@ -336,7 +335,7 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
   }
   // redirect read cfiInfo, couples to redirectGen s2
   ftq_redirect_sram.io.ren(0) := io.fromBackend.stage2Redirect.valid
-  ftq_redirect_sram.io.raddr(0) := io.fromBackend.stage2Redirect.bits.ftqIdx
+  ftq_redirect_sram.io.raddr(0) := io.fromBackend.stage2Redirect.bits.ftqIdx.value
   val stage3CfiInfo = ftq_redirect_sram.io.rdata(0)
   val fromBackendRedirect = WireInit(io.fromBackend.stage3Redirect)
   fromBackendRedirect.bits.cfiUpdate.rasSp := stage3CfiInfo.rasSp
@@ -388,6 +387,9 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
   def getFtqOffset(n: Int): UInt = extractWbInfo(io.fromBackend.exuWriteback(n))._2
   // FtqSize * onehot
   val wbPortSel_vec = Wire(Vec(FtqSize, Vec(nWbPorts + 1, Bool())))
+  val wbFtqOffset_vec = Wire(Vec(nWbPorts+1, UInt(4.W)))
+  for (i <- 0 until nWbPorts) { wbFtqOffset_vec(i) := getFtqOffset(i)}
+  wbFtqOffset_vec(nWbPorts) := fromIfuRedirect.bits.ftqOffset
   // in order to handle situation in which multiple cfi taken writebacks target the same ftqEntry
   for (i <- 0 until FtqSize) {
     val needToUpdateThisEntry =
@@ -413,8 +415,8 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe
     // TODO: distinguish exuWb and ifuWb
     for (n <- 0 until nWbPorts+1) {
       val hasFormerWriteBack = VecInit(
-        for (another <- 0 until nWbPorts if another != n) yield {
-          needToUpdateThisEntry(another) && getFtqOffset(another) < getFtqOffset(n)
+        for (another <- 0 until nWbPorts+1 if another != n) yield {
+          needToUpdateThisEntry(another) && wbFtqOffset_vec(another) < wbFtqOffset_vec(n)
         }
       ).asUInt.orR
       wbPortSel_vec(i)(n) := needToUpdateThisEntry(n) && !hasFormerWriteBack || !VecInit(needToUpdateThisEntry).asUInt().orR() && updateCfiValidMask(n)