提交 c30bc36c 编写于 作者: Z zoujr

[WIP]IFU: Fix some NullPointer errors

上级 47863f7e
......@@ -128,7 +128,13 @@ class NewIFU(implicit p: Parameters) extends XSModule with Temperary with HasICa
val f1_situation = RegEnable(next = f0_situation, enable=f0_fire)
val f1_doubleLine = RegEnable(next = f0_doubleLine, enable=f0_fire)
val f1_vSetIdx = RegEnable(next = f0_vSetIdx, enable=f0_fire)
val f1_fire = f1_valid && tlbHit && f2_ready
val f1_fire = f1_valid && tlbHit && f2_ready
val preDecoder = Module(new PreDecode)
val (preDecoderIn, preDecoderOut) = (preDecoder.io.in, preDecoder.io.out)
//flush generate and to Ftq
val flush = preDecoderOut.misOffset.valid
when(flush) {f1_valid := false.B}
.elsewhen(f0_fire) {f1_valid := true.B}
......@@ -152,8 +158,6 @@ class NewIFU(implicit p: Parameters) extends XSModule with Temperary with HasICa
((replacers zip touch_sets) zip touch_ways).map{case ((r, s),w) => r.access(s,w)}
f1_ready := f2_ready || !f2_valid
val f1_hit_data = VecInit(f1_datas.zipWithIndex.map { case(bank, i) =>
val bank0_hit_data = Mux1H(bank0_hit_vec.asUInt, bank)
val bank1_hit_data = Mux1H(bank1_hit_vec.asUInt, bank)
......@@ -173,6 +177,8 @@ class NewIFU(implicit p: Parameters) extends XSModule with Temperary with HasICa
val f2_doubleLine = RegEnable(next = f1_doubleLine, enable=f1_fire)
val f2_fire = io.toIbuffer.fire()
f1_ready := f2_ready || !f2_valid
when(flush) {f2_valid := false.B}
.elsewhen(f1_fire) {f2_valid := true.B }
.elsewhen(io.toIbuffer.fire()) {f2_valid := false.B}
......@@ -195,7 +201,7 @@ class NewIFU(implicit p: Parameters) extends XSModule with Temperary with HasICa
//instruction
val wait_idle :: wait_send_req :: wait_finish :: Nil = Enum(3)
val wait_state = Vec(2, RegInit(wait_idle))
val wait_state = VecInit(Seq.fill(2)(RegInit(wait_idle)))
toMissQueue <> DontCare
fromMissQueue.map{port => port.ready := true.B}
......@@ -241,12 +247,8 @@ class NewIFU(implicit p: Parameters) extends XSModule with Temperary with HasICa
}
val f2_hit_datas = RegEnable(next = f1_hit_data, enable = f1_fire)
val f2_mq_datas = Reg(VecInit(fromMissQueue.map(p => p.bits.data))) //TODO: Implement miss queue response
val f2_mq_datas = RegInit(VecInit(fromMissQueue.map(p => p.bits.data))) //TODO: Implement miss queue response
val f2_datas = Mux(f2_hit, f2_hit_datas, f2_mq_datas)
val preDecoder = Module(new PreDecode)
val (preDecoderIn, preDecoderOut) = (preDecoder.io.in, preDecoder.io.out)
def cut(cacheline: UInt, start: UInt) : Vec[UInt] ={
val result = Wire(Vec(17, UInt(16.W)))
......@@ -272,9 +274,6 @@ class NewIFU(implicit p: Parameters) extends XSModule with Temperary with HasICa
io.toIbuffer.bits.foldpc := preDecoderOut.pc.map(i => XORFold(i(VAddrBits-1,1), MemPredPCWidth))
//flush generate and to Ftq
val flush = preDecoderOut.misOffset.valid
toFtq.pdWb.valid := (f2_valid && f2_hit) || miss_all_fix
toFtq.pdWb.bits.pc := preDecoderOut.pc
toFtq.pdWb.bits.pd := preDecoderOut.pd
......
......@@ -100,7 +100,14 @@ class PreDecode(implicit p: Parameters) extends XSModule with HasPdconst with Ha
val isLastInBlock = (i == MAXINSNUM - 1).B
val currentIsRVC = isRVC(inst) && HasCExtension.B
val lastIsValidEnd = validEnd(i-1) || isFirstInBlock || !HasCExtension.B
// TODO: when i == 0
// val lastIsValidEnd = if(i == 0) true.B else validEnd(i-1)) || isFirstInBlock || !HasCExtension.B
val lastIsValidEnd = Wire(Bool())
if (i == 0) {
lastIsValidEnd := true.B || isFirstInBlock || !HasCExtension.B
} else {
lastIsValidEnd := validEnd(i-1) || isFirstInBlock || !HasCExtension.B
}
validStart(i) := lastIsValidEnd || !HasCExtension.B
validEnd(i) := validStart(i) && currentIsRVC || !validStart(i) || !HasCExtension.B
......@@ -116,7 +123,7 @@ class PreDecode(implicit p: Parameters) extends XSModule with HasPdconst with Ha
//io.out.pd(i).excType := ExcType.notExc
expander.io.in := inst
io.out.instrs(i) := expander.io.out.bits
io.out.pc(i) := pcStart + (i << 1).U(log2Ceil(MAXINSNUM).W)
io.out.pc(i) := pcStart + (i << 1).U((log2Ceil(MAXINSNUM)+1).W)
targets(i) := io.out.pc(i) + Mux(io.out.pd(i).isBr, SignExt(brOffset, XLEN), SignExt(jalOffset, XLEN))
......@@ -135,7 +142,7 @@ class PreDecode(implicit p: Parameters) extends XSModule with HasPdconst with Ha
val jalOffset = PriorityEncoder(isJumpOH)
val brOffset = PriorityEncoder(isBrOH)
io.out.valid := validStart
io.out.valid := validStart.asUInt()
io.out.misOffset.valid := misPred.asUInt().orR()
io.out.misOffset.bits := PriorityEncoder(misPred)
......
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