- 18 9月, 2020 2 次提交
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由 William Wang 提交于
* lr_valid will be copied from processor to emulator when: * sc falied && * processor's lr_valid is set to false && * emulator's lr_valid is set to true
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由 William Wang 提交于
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- 17 9月, 2020 7 次提交
- 16 9月, 2020 2 次提交
- 15 9月, 2020 1 次提交
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由 William Wang 提交于
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- 14 9月, 2020 3 次提交
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由 William Wang 提交于
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由 William Wang 提交于
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由 William Wang 提交于
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- 13 9月, 2020 2 次提交
- 12 9月, 2020 3 次提交
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由 William Wang 提交于
* It will make snapshot more precise * NEMU that includes commit d4efeb7 is needed to use difftest
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由 LinJiawei 提交于
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由 zhanglinjuan 提交于
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- 11 9月, 2020 5 次提交
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由 GouLingrui 提交于
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由 GouLingrui 提交于
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由 Allen 提交于
Now, data array write port priority: store pipe > atomics pipe > refill. When atomics runs, store are all flushed out, new stores are blocked. So there will be no store competing for data write port. But refill may compete for data write port even if atomics runs with no spec exec! This is how it happens: speculative load misses goes to miss queue but this load was later killed and atomics starts running. Miss queue gets data and starts to refill, competing for data array write port. Atomics pipe fails to get data write port, assertion fails.
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由 Allen 提交于
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由 Allen 提交于
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- 10 9月, 2020 6 次提交
- 09 9月, 2020 8 次提交
- 08 9月, 2020 1 次提交
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由 ZhangZifei 提交于
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