Atomics: deal with atomcis w and d.

src/main/scala/xiangshan/backend/decode/isa/RVA.scala

@@ -11,36 +11,54 @@ object RVAInstr extends HasInstrType {
   // Note: use instr(14,12) to distinguish D/W inst
   // def LR      = BitPat("b00010??00000_?????_???_?????_0101111")
   // def SC      = BitPat("b00011??00000_?????_???_?????_0101111")
-  def LR_D    = BitPat("b00010_??_00000_?????_011_?????_0101111")
-  def SC_D    = BitPat("b00011_??_?????_?????_011_?????_0101111")
-  def LR_W    = BitPat("b00010_??_00000_?????_010_?????_0101111")
-  def SC_W    = BitPat("b00011_??_?????_?????_010_?????_0101111")
-  def AMOSWAP = BitPat("b00001_??_?????_?????_01?_?????_0101111")
-  def AMOADD  = BitPat("b00000_??_?????_?????_01?_?????_0101111")
-  def AMOXOR  = BitPat("b00100_??_?????_?????_01?_?????_0101111")
-  def AMOAND  = BitPat("b01100_??_?????_?????_01?_?????_0101111")
-  def AMOOR   = BitPat("b01000_??_?????_?????_01?_?????_0101111")
-  def AMOMIN  = BitPat("b10000_??_?????_?????_01?_?????_0101111")
-  def AMOMAX  = BitPat("b10100_??_?????_?????_01?_?????_0101111")
-  def AMOMINU = BitPat("b11000_??_?????_?????_01?_?????_0101111")
-  def AMOMAXU = BitPat("b11100_??_?????_?????_01?_?????_0101111")
+  def LR_D      = BitPat("b00010_??_00000_?????_011_?????_0101111")
+  def SC_D      = BitPat("b00011_??_?????_?????_011_?????_0101111")
+  def AMOSWAP_D = BitPat("b00001_??_?????_?????_011_?????_0101111")
+  def AMOADD_D  = BitPat("b00000_??_?????_?????_011_?????_0101111")
+  def AMOXOR_D  = BitPat("b00100_??_?????_?????_011_?????_0101111")
+  def AMOAND_D  = BitPat("b01100_??_?????_?????_011_?????_0101111")
+  def AMOOR_D   = BitPat("b01000_??_?????_?????_011_?????_0101111")
+  def AMOMIN_D  = BitPat("b10000_??_?????_?????_011_?????_0101111")
+  def AMOMAX_D  = BitPat("b10100_??_?????_?????_011_?????_0101111")
+  def AMOMINU_D = BitPat("b11000_??_?????_?????_011_?????_0101111")
+  def AMOMAXU_D = BitPat("b11100_??_?????_?????_011_?????_0101111")
+
+  def LR_W      = BitPat("b00010_??_00000_?????_010_?????_0101111")
+  def SC_W      = BitPat("b00011_??_?????_?????_010_?????_0101111")
+  def AMOSWAP_W = BitPat("b00001_??_?????_?????_010_?????_0101111")
+  def AMOADD_W  = BitPat("b00000_??_?????_?????_010_?????_0101111")
+  def AMOXOR_W  = BitPat("b00100_??_?????_?????_010_?????_0101111")
+  def AMOAND_W  = BitPat("b01100_??_?????_?????_010_?????_0101111")
+  def AMOOR_W   = BitPat("b01000_??_?????_?????_010_?????_0101111")
+  def AMOMIN_W  = BitPat("b10000_??_?????_?????_010_?????_0101111")
+  def AMOMAX_W  = BitPat("b10100_??_?????_?????_010_?????_0101111")
+  def AMOMINU_W = BitPat("b11000_??_?????_?????_010_?????_0101111")
+  def AMOMAXU_W = BitPat("b11100_??_?????_?????_010_?????_0101111")
   // funct3 === 010 or 011
 
   val table = Array(
-    // LR          -> List(InstrI, FuType.mou, LSUOpType.lr),
-    // SC          -> List(InstrS, FuType.mou, LSUOpType.sc),
-    LR_D        -> List(InstrI, FuType.mou, LSUOpType.lr),
-    LR_W        -> List(InstrI, FuType.mou, LSUOpType.lr),
-    SC_D        -> List(InstrSA, FuType.mou, LSUOpType.sc),
-    SC_W        -> List(InstrSA, FuType.mou, LSUOpType.sc),
-    AMOSWAP     -> List(InstrR, FuType.mou, LSUOpType.amoswap),
-    AMOADD      -> List(InstrR, FuType.mou, LSUOpType.amoadd),
-    AMOXOR      -> List(InstrR, FuType.mou, LSUOpType.amoxor),
-    AMOAND      -> List(InstrR, FuType.mou, LSUOpType.amoand),
-    AMOOR       -> List(InstrR, FuType.mou, LSUOpType.amoor),
-    AMOMIN      -> List(InstrR, FuType.mou, LSUOpType.amomin),
-    AMOMAX      -> List(InstrR, FuType.mou, LSUOpType.amomax),
-    AMOMINU     -> List(InstrR, FuType.mou, LSUOpType.amominu),
-    AMOMAXU     -> List(InstrR, FuType.mou, LSUOpType.amomaxu)
+    LR_D          -> List(InstrI, FuType.mou, LSUOpType.lr_d),
+    SC_D          -> List(InstrSA, FuType.mou, LSUOpType.sc_d),
+    AMOSWAP_D     -> List(InstrR, FuType.mou, LSUOpType.amoswap_d),
+    AMOADD_D      -> List(InstrR, FuType.mou, LSUOpType.amoadd_d),
+    AMOXOR_D      -> List(InstrR, FuType.mou, LSUOpType.amoxor_d),
+    AMOAND_D      -> List(InstrR, FuType.mou, LSUOpType.amoand_d),
+    AMOOR_D       -> List(InstrR, FuType.mou, LSUOpType.amoor_d),
+    AMOMIN_D      -> List(InstrR, FuType.mou, LSUOpType.amomin_d),
+    AMOMAX_D      -> List(InstrR, FuType.mou, LSUOpType.amomax_d),
+    AMOMINU_D     -> List(InstrR, FuType.mou, LSUOpType.amominu_d),
+    AMOMAXU_D     -> List(InstrR, FuType.mou, LSUOpType.amomaxu_d),
+
+    LR_W          -> List(InstrI, FuType.mou, LSUOpType.lr_w),
+    SC_W          -> List(InstrSA, FuType.mou, LSUOpType.sc_w),
+    AMOSWAP_W     -> List(InstrR, FuType.mou, LSUOpType.amoswap_w),
+    AMOADD_W      -> List(InstrR, FuType.mou, LSUOpType.amoadd_w),
+    AMOXOR_W      -> List(InstrR, FuType.mou, LSUOpType.amoxor_w),
+    AMOAND_W      -> List(InstrR, FuType.mou, LSUOpType.amoand_w),
+    AMOOR_W       -> List(InstrR, FuType.mou, LSUOpType.amoor_w),
+    AMOMIN_W      -> List(InstrR, FuType.mou, LSUOpType.amomin_w),
+    AMOMAX_W      -> List(InstrR, FuType.mou, LSUOpType.amomax_w),
+    AMOMINU_W     -> List(InstrR, FuType.mou, LSUOpType.amominu_w),
+    AMOMAXU_W     -> List(InstrR, FuType.mou, LSUOpType.amomaxu_w),
   )
 }

src/main/scala/xiangshan/backend/package.scala

@@ -107,6 +107,8 @@ package object backend {
   }
 
   object LSUOpType {
+    // normal load/store
+    // bit(1, 0) are size
     def lb   = "b000000".U
     def lh   = "b000001".U
     def lw   = "b000010".U
@@ -114,29 +116,41 @@ package object backend {
     def lbu  = "b000100".U
     def lhu  = "b000101".U
     def lwu  = "b000110".U
-    def flw  = "b010110".U
     def sb   = "b001000".U
     def sh   = "b001001".U
     def sw   = "b001010".U
     def sd   = "b001011".U
 
-    def lr      = "b100010".U
-    def sc      = "b100011".U
-    def amoswap = "b100001".U
-    def amoadd  = "b100000".U
-    def amoxor  = "b100100".U
-    def amoand  = "b101100".U
-    def amoor   = "b101000".U
-    def amomin  = "b110000".U
-    def amomax  = "b110100".U
-    def amominu = "b111000".U
-    def amomaxu = "b111100".U
-
-    def isStore(func: UInt): Bool = func(3)
-    def isAtom(func: UInt): Bool = func(5)
-
-    def atomW = "010".U
-    def atomD = "011".U
+    // float/double load store
+    def flw  = "b010110".U
+
+    // atomics
+    // bit(1, 0) are size
+    // since atomics use a different fu type
+    // so we can safely reuse other load/store's encodings
+    def lr_w      = "b000010".U
+    def sc_w      = "b000110".U
+    def amoswap_w = "b001010".U
+    def amoadd_w  = "b001110".U
+    def amoxor_w  = "b010010".U
+    def amoand_w  = "b010110".U
+    def amoor_w   = "b011010".U
+    def amomin_w  = "b011110".U
+    def amomax_w  = "b100010".U
+    def amominu_w = "b100110".U
+    def amomaxu_w = "b101010".U
+
+    def lr_d      = "b000011".U
+    def sc_d      = "b000111".U
+    def amoswap_d = "b001011".U
+    def amoadd_d  = "b001111".U
+    def amoxor_d  = "b010011".U
+    def amoand_d  = "b010111".U
+    def amoor_d   = "b011011".U
+    def amomin_d  = "b011111".U
+    def amomax_d  = "b100011".U
+    def amominu_d = "b100111".U
+    def amomaxu_d = "b101011".U
   }
 
   object BTBtype {

src/main/scala/xiangshan/mem/AtomicsUnit.scala

@@ -58,7 +58,8 @@ class AtomicsUnit extends XSModule with MemoryOpConstants{
     io.dtlb.req.valid       := true.B
     io.dtlb.req.bits.vaddr  := in.src1
     io.dtlb.req.bits.roqIdx := in.uop.roqIdx
-    io.dtlb.req.bits.cmd    := Mux(in.uop.ctrl.fuOpType === LSUOpType.lr, TlbCmd.read, TlbCmd.write)
+    val is_lr = in.uop.ctrl.fuOpType === LSUOpType.lr_w || in.uop.ctrl.fuOpType === LSUOpType.lr_d
+    io.dtlb.req.bits.cmd    := Mux(is_lr, TlbCmd.read, TlbCmd.write)
     io.dtlb.req.bits.debug.pc := in.uop.cf.pc
     io.dtlb.req.bits.debug.lsroqIdx := in.uop.lsroqIdx
 
@@ -90,21 +91,33 @@ class AtomicsUnit extends XSModule with MemoryOpConstants{
   when (state === s_cache_req) {
     io.dcache.req.valid := true.B
     io.dcache.req.bits.cmd := LookupTree(in.uop.ctrl.fuOpType, List(
-      LSUOpType.lr -> M_XLR,
-      LSUOpType.sc -> M_XSC,
-      LSUOpType.amoswap -> M_XA_SWAP,
-      LSUOpType.amoadd -> M_XA_ADD,
-      LSUOpType.amoxor -> M_XA_XOR,
-      LSUOpType.amoand -> M_XA_AND,
-      LSUOpType.amoor -> M_XA_OR,
-      LSUOpType.amomin -> M_XA_MIN,
-      LSUOpType.amomax -> M_XA_MAX,
-      LSUOpType.amominu -> M_XA_MINU,
-      LSUOpType.amomaxu -> M_XA_MAXU
+      LSUOpType.lr_w      -> M_XLR,
+      LSUOpType.sc_w      -> M_XSC,
+      LSUOpType.amoswap_w -> M_XA_SWAP,
+      LSUOpType.amoadd_w  -> M_XA_ADD,
+      LSUOpType.amoxor_w  -> M_XA_XOR,
+      LSUOpType.amoand_w  -> M_XA_AND,
+      LSUOpType.amoor_w   -> M_XA_OR,
+      LSUOpType.amomin_w  -> M_XA_MIN,
+      LSUOpType.amomax_w  -> M_XA_MAX,
+      LSUOpType.amominu_w -> M_XA_MINU,
+      LSUOpType.amomaxu_w -> M_XA_MAXU,
+
+      LSUOpType.lr_d      -> M_XLR,
+      LSUOpType.sc_d      -> M_XSC,
+      LSUOpType.amoswap_d -> M_XA_SWAP,
+      LSUOpType.amoadd_d  -> M_XA_ADD,
+      LSUOpType.amoxor_d  -> M_XA_XOR,
+      LSUOpType.amoand_d  -> M_XA_AND,
+      LSUOpType.amoor_d   -> M_XA_OR,
+      LSUOpType.amomin_d  -> M_XA_MIN,
+      LSUOpType.amomax_d  -> M_XA_MAX,
+      LSUOpType.amominu_d -> M_XA_MINU,
+      LSUOpType.amomaxu_d -> M_XA_MAXU
     ))
 
     io.dcache.req.bits.addr := paddr 
-    io.dcache.req.bits.data := in.src2
+    io.dcache.req.bits.data := genWdata(in.src2, in.uop.ctrl.fuOpType(1,0))
     // TODO: atomics do need mask: fix mask
     io.dcache.req.bits.mask := genWmask(paddr, in.uop.ctrl.fuOpType(1,0))
     io.dcache.req.bits.meta.id       := DCacheAtomicsType.atomics

src/main/scala/xiangshan/mem/LoadUnit.scala

@@ -254,8 +254,7 @@ class LoadUnit extends XSModule {
       LSUOpType.ld   -> SignExt(rdataSel(63, 0), XLEN),
       LSUOpType.lbu  -> ZeroExt(rdataSel(7, 0) , XLEN),
       LSUOpType.lhu  -> ZeroExt(rdataSel(15, 0), XLEN),
-      LSUOpType.lwu  -> ZeroExt(rdataSel(31, 0), XLEN),
-      LSUOpType.ldu  -> ZeroExt(rdataSel(63, 0), XLEN)
+      LSUOpType.lwu  -> ZeroExt(rdataSel(31, 0), XLEN)
   ))
 
   // ecc check

src/main/scala/xiangshan/mem/Lsroq.scala

@@ -263,8 +263,7 @@ class Lsroq extends XSModule {
         LSUOpType.ld   -> SignExt(rdataSel(63, 0), XLEN),
         LSUOpType.lbu  -> ZeroExt(rdataSel(7, 0) , XLEN),
         LSUOpType.lhu  -> ZeroExt(rdataSel(15, 0), XLEN),
-        LSUOpType.lwu  -> ZeroExt(rdataSel(31, 0), XLEN),
-        LSUOpType.ldu  -> ZeroExt(rdataSel(63, 0), XLEN)
+        LSUOpType.lwu  -> ZeroExt(rdataSel(31, 0), XLEN)
     ))
     io.ldout(i).bits.uop := uop(loadWbSel(i))
     io.ldout(i).bits.data := rdataPartialLoad

src/main/scala/xiangshan/mem/Memend.scala

@@ -11,36 +11,50 @@ import xiangshan.cache._
 import bus.tilelink.{TLArbiter, TLCached, TLMasterUtilities, TLParameters}
 
 object LSUOpType {
-  def lb   = "b000000".U
-  def lh   = "b000001".U
-  def lw   = "b000010".U
-  def ld   = "b000011".U
-  def lbu  = "b000100".U
-  def lhu  = "b000101".U
-  def lwu  = "b000110".U
-  def ldu  = "b000111".U
-  def sb   = "b001000".U
-  def sh   = "b001001".U
-  def sw   = "b001010".U
-  def sd   = "b001011".U
-  
-  def lr      = "b100010".U
-  def sc      = "b100011".U
-  def amoswap = "b100001".U
-  def amoadd  = "b100000".U
-  def amoxor  = "b100100".U
-  def amoand  = "b101100".U
-  def amoor   = "b101000".U
-  def amomin  = "b110000".U
-  def amomax  = "b110100".U
-  def amominu = "b111000".U
-  def amomaxu = "b111100".U
-  
-  def isStore(func: UInt): Bool = func(3)
-  def isAtom(func: UInt): Bool = func(5)
-  
-  def atomW = "010".U
-  def atomD = "011".U
+    // normal load/store
+    // bit(1, 0) are size
+    def lb   = "b000000".U
+    def lh   = "b000001".U
+    def lw   = "b000010".U
+    def ld   = "b000011".U
+    def lbu  = "b000100".U
+    def lhu  = "b000101".U
+    def lwu  = "b000110".U
+    def sb   = "b001000".U
+    def sh   = "b001001".U
+    def sw   = "b001010".U
+    def sd   = "b001011".U
+
+    // float/double load store
+    def flw  = "b010110".U
+
+    // atomics
+    // bit(1, 0) are size
+    // since atomics use a different fu type
+    // so we can safely reuse other load/store's encodings
+    def lr_w      = "b000010".U
+    def sc_w      = "b000110".U
+    def amoswap_w = "b001010".U
+    def amoadd_w  = "b001110".U
+    def amoxor_w  = "b010010".U
+    def amoand_w  = "b010110".U
+    def amoor_w   = "b011010".U
+    def amomin_w  = "b011110".U
+    def amomax_w  = "b100010".U
+    def amominu_w = "b100110".U
+    def amomaxu_w = "b101010".U
+
+    def lr_d      = "b000011".U
+    def sc_d      = "b000111".U
+    def amoswap_d = "b001011".U
+    def amoadd_d  = "b001111".U
+    def amoxor_d  = "b010011".U
+    def amoand_d  = "b010111".U
+    def amoor_d   = "b011011".U
+    def amomin_d  = "b011111".U
+    def amomax_d  = "b100011".U
+    def amominu_d = "b100111".U
+    def amomaxu_d = "b101011".U
 }
 
 object DCacheAtomicsType {