- 29 3月, 2023 2 次提交
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由 Ziyue-Zhang 提交于
bump ready-to-run
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由 Ziyue Zhang 提交于
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- 28 3月, 2023 1 次提交
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由 czw 提交于
1. func(VPERM): fix tail process, optimize vcompress, change vslide module name 2. func(VPERM): change to 2-stage 3. test(VPERM): add golden model and test: vslidedown 4. test(VPERM): set vxsat=0 for vperm 5. test(VFADD): support vector-scalar operations func(VFADD): support vector-scalar operations 6. test: include 7. func(VFMA): add input:op_code,frs1,is_frs1; support vfmul.vv 8. func(VFMA):add vfmul.vf vfnmacc.vv vfnmacc.vf and their test supports 9. func(IALU):add IALU V3 * fix(decode): fix decode bug of selImm 1. fix decode bug of selImm 2. change VipuType to VpermType * func(yunsuan): add VIAlu code v3 1. add VIAlu code v3 2. Update the IO of VFPU * pom(yunsuan): add IALU V3 1. func(VPERM): fix tail process, optimize vcompress, change vslide module name 2. func(VPERM): change to 2-stage 3. test(VPERM): add golden model and test: vslidedown 4. test(VPERM): set vxsat=0 for vperm 5. test(VFADD): support vector-scalar operations func(VFADD): support vector-scalar operations 6. test: include <algorithm> 7. func(VFMA): add input:op_code,frs1,is_frs1; support vfmul.vv 8. func(VFMA):add vfmul.vf vfnmacc.vv vfnmacc.vf and their test supports 9. func(IALU):add IALU V3
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- 24 3月, 2023 3 次提交
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由 czw 提交于
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由 czw 提交于
1. pom(build.sbt):Update the version of scala in sbt 2. func(VIntFixpAlu):add test for VIntFixpAlu 3. fix(vand): fix vand OPType 4. fix(VIntAdder64b):fix a bug that mask inst result should be 1 when !vm && !vmask(i)
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由 zhanglyGit 提交于
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- 23 3月, 2023 3 次提交
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由 bugGenerator 提交于
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由 zhanglyGit 提交于
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由 zhanglyGit 提交于
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- 22 3月, 2023 2 次提交
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由 zhanglyGit 提交于
* func(decode+VIPU): support vslide1up instruction * bump(yunsuan): func(VFADD) & VIPU type & test(VPERM)
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由 zhanglyGit 提交于
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- 20 3月, 2023 7 次提交
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由 bugGenerator 提交于
refactor(VIPU): optimize decoding logic of VIPU
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由 czw 提交于
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由 czw 提交于
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由 czw 提交于
1. Some logic moves from VIPU.scala to VPUSubModule.scala 2. add VIAluFix
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由 czw 提交于
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由 zhanglyGit 提交于
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由 zhanglyGit 提交于
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- 19 3月, 2023 2 次提交
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由 czw 提交于
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由 bugGenerator 提交于
merge rf-after-issue, also sync with master
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- 18 3月, 2023 2 次提交
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由 ZhangZifei 提交于
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由 bugGenerator 提交于
refactor(UopDivType): rename UopDivType & change VECTOR_TMP_REG_MV to FP_TMP_REG_MV
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- 17 3月, 2023 6 次提交
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由 czw 提交于
1. rename UopDivType 2. change VECTOR_TMP_REG_MV to FP_TMP_REG_MV 3. add UopDivType.VEC_MMM for decode of VMAND_MM VMANDN_MM ... VMXOR_MM
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由 czw 提交于
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由 zhanglyGit 提交于
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由 ZhangZifei 提交于
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由 ZhangZifei 提交于
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由 zhanglyGit 提交于
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- 16 3月, 2023 6 次提交
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由 zhanglyGit 提交于
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由 ZhangZifei 提交于
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由 happy-lx 提交于
Add a custom arbiter. In the case of multiple sources with the same cache block address, the arbiter will assign only one entry in misssqueue but ready for all same cache block address requests. This will reduce the number of replays of the load instruction which cannot enter the missqueue
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由 bugGenerator 提交于
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由 bugGenerator 提交于
func(vfmin vfmax): pass vfmin & vfmax in VectorFloatAdder func(vstart): add vstart from CSR to VIPU func(VipuType): add VipuType of vwsubu.vv vwsubu.wv vwsub.vx vwsub.wx pom(yunsuan): support vfmin vfmax func(vfmin vfmax): pass vfmin & vfmax in VectorFloatAdder
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由 ZhangZifei 提交于
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- 15 3月, 2023 6 次提交