Now, it doesn't even compile.
We will start merging dev-lsu.

Now, bugs are caused by contention on meta array read/write.
I will stop debugging this pipeline and start refactoring it.

Added some debug logs.

These problems are made when migrating from chisel2 to chisel3.
In chisel2, we use UInt(value, width) to define a fixed width UInt.
In chisel3, it should be value.U(width.W).
But in TileLink.scala, I turned them into value.U(width),
which means take the width bit of value.U!!!

So, be careful when you are copy-pasting code from rocketchip or boom.

Now mshrs can end transaction and go to replay.

It still behaves unexpectedly.
So temporarily disable it for now.

Fixed the unexpected output.
But I could not fully explain the scala or chisel issues behind this.
It just worked.

to work with TL-C L1 Cache, I created a new FakeTLLLC from it.
FakeTLLLC is a TL-C to AXI converter.
But we call it FakeTLLLC since for now it plays the role of LLC.

You can pass in a dump function, and it will be executed when Log
triggers and prefix is automatically appended.

Revised the core pipeline.

2. Generate unsigned numbers to avoid UInt casting errors.

Just compiles.

* By doing this, we can use PipelineConnect to build in-modile pipeline

Optimization: when the terms in issueQueue have no rdy && enq is
rdy && first stage is empty then send the enq term directly