- 20 8月, 2020 1 次提交
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由 linjiawei 提交于
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- 19 8月, 2020 3 次提交
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由 linjiawei 提交于
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由 ZhangZifei 提交于
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由 ZhangZifei 提交于
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- 18 8月, 2020 8 次提交
- 17 8月, 2020 6 次提交
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由 Allen 提交于
array ready. Or we will make a combinational loop. I'm still considering about the correctness and forward progress of our sync scheme.
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由 Allen 提交于
Now, it can only do normal load. It will replay req on cache miss. Enough for dtlb ptw.
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由 linjiawei 提交于
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由 Allen 提交于
Making stu completely nonblocking.
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由 linjiawei 提交于
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由 linjiawei 提交于
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- 16 8月, 2020 5 次提交
- 15 8月, 2020 2 次提交
- 14 8月, 2020 15 次提交
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由 ZhangZifei 提交于
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由 ZhangZifei 提交于
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由 ZhangZifei 提交于
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由 Allen 提交于
Our missQueue design means we can not avoid these assertions. We send response before free this missQueueEntry and storeMissQueueEntry. So during this short period, sbuffer may still send down the same block, which is perfectly OK and we should not assert it. LoadMissQueue and StoreMissQueue design may need to be revised.
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由 Allen 提交于
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由 ZhangZifei 提交于
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由 William Wang 提交于
* DCacheLoadReq -> DCacheWordReq * DCacheStoreReq -> DCacheLineReq
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由 ZhangZifei 提交于
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由 Yinan Xu 提交于
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由 ZhangZifei 提交于
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由 Allen 提交于
Sbuffer may send down blocks with the same idx(but we will block it). Sbuffer should not send down the same block multiple times(this means sbuffer is buggy).
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由 Allen 提交于
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由 Allen 提交于
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由 Allen 提交于
Do not block replayed reqs. Also, let LoadMissQueue and StoreMissQueue set meta.replay correctly. Initialized replay_resp_ctr to zero in StoreMissEntry.
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由 Allen 提交于
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