Add debug info

src/main/scala/device/AXI4SlaveModule.scala

@@ -6,6 +6,7 @@ import utils._
 import freechips.rocketchip.diplomacy.{AddressSet, LazyModule, LazyModuleImp, RegionType, TransferSizes}
 import chipsalliance.rocketchip.config.Parameters
 import freechips.rocketchip.amba.axi4.{AXI4Parameters, AXI4SlaveNode, AXI4SlaveParameters, AXI4SlavePortParameters}
+import xiangshan.HasXSLog
 
 abstract class AXI4SlaveModule[T <: Data]
 (
@@ -33,7 +34,7 @@ abstract class AXI4SlaveModule[T <: Data]
 }
 
 class AXI4SlaveModuleImp[T<:Data](outer: AXI4SlaveModule[T])
-  extends LazyModuleImp(outer)
+  extends LazyModuleImp(outer) with HasXSLog
 {
   val io = IO(new Bundle {
     val extra = if(outer._extra == null) None else Some(outer._extra.cloneType)
@@ -41,27 +42,27 @@ class AXI4SlaveModuleImp[T<:Data](outer: AXI4SlaveModule[T])
 
   val (in, edge) = outer.node.in.head
 
-  val timer = GTimer()
+//  val timer = GTimer()
   when(in.ar.fire()){
-    printf(p"[$timer][ar] addr: ${Hexadecimal(in.ar.bits.addr)} " +
+    XSDebug(p"[ar] addr: ${Hexadecimal(in.ar.bits.addr)} " +
       p"arlen:${in.ar.bits.len} arsize:${in.ar.bits.size} " +
       p"id: ${in.ar.bits.id}\n"
     )
   }
   when(in.aw.fire()){
-    printf(p"[$timer][aw] addr: ${Hexadecimal(in.aw.bits.addr)} " +
+    XSDebug(p"[aw] addr: ${Hexadecimal(in.aw.bits.addr)} " +
       p"awlen:${in.aw.bits.len} awsize:${in.aw.bits.size} " +
       p"id: ${in.aw.bits.id}\n"
     )
   }
   when(in.w.fire()){
-    printf(p"[$timer][w] wmask: ${Binary(in.w.bits.strb)} last:${in.w.bits.last}\n")
+    XSDebug(p"[w] wmask: ${Binary(in.w.bits.strb)} last:${in.w.bits.last}\n")
   }
   when(in.b.fire()){
-    printf(p"[$timer][b] id: ${in.b.bits.id}\n")
+    XSDebug(p"[b] id: ${in.b.bits.id}\n")
   }
   when(in.r.fire()){
-    printf(p"[$timer][r] id: ${in.r.bits.id}\n")
+    XSDebug(p"[r] id: ${in.r.bits.id}\n")
   }
 
 

src/main/scala/device/TLTimer.scala

@@ -44,8 +44,8 @@ class TLTimer(address: Seq[AddressSet], sim: Boolean)(implicit p: Parameters) ex
       0xbff8 -> RegField.bytes(mtime)
     )
 
-    val gtime = GTimer()
-    printf(p"[$gtime][Timer] mtime=$mtime cnt=$cnt freq=$freq\n")
+//    val gtime = GTimer()
+//    printf(p"[$gtime][Timer] mtime=$mtime cnt=$cnt freq=$freq\n")
 
     mtip := RegNext(mtime >= mtimecmp)
   }

src/main/scala/utils/DebugIdentityNode.scala

@@ -4,8 +4,9 @@ import chisel3._
 import chipsalliance.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
 import freechips.rocketchip.tilelink.{TLClientNode, TLIdentityNode, TLMasterParameters, TLMasterPortParameters}
+import xiangshan.HasXSLog
 
-class DebugIdentityNode()(implicit p: Parameters) extends LazyModule {
+class DebugIdentityNode()(implicit p: Parameters) extends LazyModule  {
 
   val node = TLIdentityNode()
 
@@ -15,17 +16,16 @@ class DebugIdentityNode()(implicit p: Parameters) extends LazyModule {
     )
   )))
 
-  lazy val module = new LazyModuleImp(this){
+  lazy val module = new LazyModuleImp(this) with HasXSLog with HasTLDump{
     val (out, _) = node.out(0)
     val (in, _) = node.in(0)
-    val timer = GTimer()
     when(in.a.fire()){
-      printf(p"[$timer][A] addr: ${Hexadecimal(in.a.bits.address)} " +
-        p"opcode: ${in.a.bits.opcode} data: ${Hexadecimal(in.a.bits.data)} size: ${in.a.bits.size} source: ${in.a.bits.source}\n"
-      )
+      XSDebug(" ")
+      in.a.bits.dump
     }
     when(in.d.fire()){
-      printf(p"[$timer][D] opcode: ${in.d.bits.opcode} data: ${Hexadecimal(in.d.bits.data)} size:${in.d.bits.size} source: ${in.d.bits.source}\n")
+      XSDebug(" ")
+      in.d.bits.dump
     }
   }
 }

src/main/scala/utils/TLDump.scala

+package utils
+
+import chisel3._
+import freechips.rocketchip.tilelink.{TLBundle, TLBundleA, TLBundleB, TLBundleC, TLBundleD, TLBundleE, TLChannel}
+
+trait HasTLDump {
+
+  implicit class dumpA(a: TLBundleA) {
+    def dump =
+      printf(
+        s"${a.channelName} opcode: %x param: %x size: %x source: %d address: %x mask: %x data: %x corrupt: %b\n",
+        a.opcode, a.param, a.size, a.source, a.address, a.mask, a.data, a.corrupt
+      )
+  }
+
+  implicit class dumpB(b: TLBundleB) {
+    def dump =
+      printf(
+        s"${b.channelName} opcode: %x param: %x size: %x source: %d address: %x mask: %x data: %x corrupt: %b\n",
+        b.opcode, b.param, b.size, b.source, b.address, b.mask, b.data, b.corrupt
+      )
+  }
+
+  implicit class dumpC(c: TLBundleC) {
+    def dump =
+      printf(
+        s"${c.channelName} opcode: %x param: %x size: %x source: %d address: %x data: %x corrupt: %b\n",
+        c.opcode, c.param, c.size, c.source, c.address, c.data, c.corrupt
+      )
+  }
+
+  implicit class dumpD(d: TLBundleD) {
+    def dump =
+      printf(
+        s"${d.channelName} opcode: %x param: %x size: %x source: %d sink: %d denied: %b data: %x corrupt: %b\n",
+        d.opcode, d.param, d.size, d.source, d.sink, d.denied, d.data, d.corrupt
+      )
+  }
+
+  implicit class dumpE(e: TLBundleE) {
+    def dump =
+      printf(s"${e.channelName} sink: %d\n", e.sink)
+  }
+}

src/main/scala/xiangshan/cache/missQueue.scala

@@ -3,7 +3,7 @@ package xiangshan.cache
 import chisel3._
 import chisel3.util._
 import freechips.rocketchip.tilelink._
-import utils.XSDebug
+import utils.{HasTLDump, XSDebug}
 
 class MissReq extends DCacheBundle
 {
@@ -344,7 +344,7 @@ class MissEntry(edge: TLEdgeOut) extends DCacheModule
 }
 
 
-class MissQueue(edge: TLEdgeOut) extends DCacheModule
+class MissQueue(edge: TLEdgeOut) extends DCacheModule with HasTLDump
 {
   val io = IO(new Bundle {
     val req    = Flipped(DecoupledIO(new MissReq))
@@ -469,17 +469,16 @@ class MissQueue(edge: TLEdgeOut) extends DCacheModule
     io.wb_req.bits.way_en, io.wb_req.bits.voluntary)
 
   // print tilelink messages
-  // TODO: impl TLBundle.dump
   when (io.mem_acquire.fire()) {
     XSDebug("mem_acquire ")
-//    io.mem_acquire.bits.dump
+    io.mem_acquire.bits.dump
   }
   when (io.mem_grant.fire()) {
     XSDebug("mem_grant ")
-//    io.mem_grant.bits.dump
+    io.mem_grant.bits.dump
   }
   when (io.mem_finish.fire()) {
     XSDebug("mem_finish ")
-//    io.mem_finish.bits.dump
+    io.mem_finish.bits.dump
   }
 }

src/main/scala/xiangshan/cache/uncache.scala

@@ -2,7 +2,7 @@ package xiangshan.cache
 
 import chisel3._
 import chisel3.util._
-import utils.XSDebug
+import utils.{HasTLDump, XSDebug}
 import chipsalliance.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy.{IdRange, LazyModule, LazyModuleImp, TransferSizes}
 import freechips.rocketchip.tilelink.{TLArbiter, TLBundleA, TLBundleD, TLClientNode, TLEdgeOut, TLMasterParameters, TLMasterPortParameters}
@@ -138,6 +138,7 @@ class UncacheImp(outer: Uncache)
   extends LazyModuleImp(outer)
     with HasDCacheParameters
     with HasXSLog
+    with HasTLDump
 {
   val io = IO(new UncacheIO)
 
@@ -199,13 +200,12 @@ class UncacheImp(outer: Uncache)
   XSDebug(resp.fire(), "data: %x\n", req.bits.data)
 
   // print tilelink messages
-  // TODO: add dump info
   when (mem_acquire.fire()) {
     XSDebug("mem_acquire \n")
-//    mem_acquire.bits.dump
+    mem_acquire.bits.dump
   }
   when (mem_grant.fire()) {
     XSDebug("mem_grant \n")
-//    mem_grant.bits.dump
+    mem_grant.bits.dump
   }
 }